ON ESD7205 Esd protection diode Datasheet

ESD7205, SZESD7205
ESD Protection Diodes
Low Capacitance ESD Protection Diodes
for High Speed Data Line
The ESD7205 transient voltage suppressor is designed to protect
high speed data lines from ESD. Ultra−low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines. The small form factor,
flow−through style package allows for easy PCB layout and matched
trace lengths necessary to maintain consistent impedance between
high speed differential lines such as Ethernet and LVDS present in
automotive camera modules.
• Low Capacitance (0.4 pF Typical, I/O to GND)
• Diode capacitance matching
• Protection for the Following IEC Standards:
•
MARKING
DIAGRAMS
SOT−723
CASE 631AA
EA M
1
EA
M
Features
•
•
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= Specific Device Code
= Date Code
SC−70
CASE 419
IEC 61000−4−2 Level 4 (ESD)
Low ESD Clamping Voltage (12 V Typical, +16 A TLP, I/O to GND)
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
ECMG
G
1
EC
= Specific Device Code
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
Typical Applications
•
•
•
•
•
100BASE−T1 / OPEN Alliance BroadR−Reach Automotive Ethernet
10/100/1000BASE−T Ethernet
LVDS
Automotive USB 2.0
High Speed Differential Pairs
PIN CONFIGURATION
AND SCHEMATIC
Pin 1
Pin 2
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Operating Junction Temperature Range
TJ
−55 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
±25
±25
±30
±20
kV
IEC 61000−4−2 Contact
IEC 61000−4−2 Air
ISO 10605 330 pF / 2 kW Contact
ISO 10605 330 pF / 330 W Contact
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2016
November, 2016 − Rev. 2
1
Pin 3
=
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 6 of this data sheet.
Publication Order Number:
ESD7205/D
ESD7205, SZESD7205
ELECTRICAL CHARACTERISTICS
I
(TA = 25°C unless otherwise noted)
IF
Parameter
Symbol
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
VBR
IT
VC VBR VRWM
Working Peak Reverse Voltage
V
IR VF
IT
Maximum Reverse Leakage Current @ VRWM
Breakdown Voltage @ IT
Test Current
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
IPP
Uni−Directional TVS
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Reverse Working
Voltage
Breakdown Voltage
Symbol
Conditions
VRWM
I/O Pin to GND
Min
Max
Unit
5.0
V
VBR
IT = 1 mA, I/O Pin to GND
Reverse Leakage
Current
IR
VRWM = 5.0 V, I/O Pin to GND
Clamping Voltage
(Note 1)
VC
IEC61000−4−2, ±8 kV Contact
See Figures 3 and 4
Clamping Voltage TLP
(Note 2)
VC
IPP = 8 A
IPP = 16 A
IPP = −8 A
IPP = −16 A
10
12.5
−4.0
−8.0
Junction Capacitance
Match
DCJ
VR = 0 V, f = 1 MHz between I/O1 to GND and I/O
2 to GND
5
10
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz between I/O Pins and GND
ESD7205DT5G
ESD7205WTT1G
0.34
0.47
0.55
0.85
VR = 0 V, f = 1 MHz between I/O Pins
ESD7205DT5G
ESD7205WTT1G
0.20
0.23
0.35
0.40
3dB Bandwidth
fBW
RL = 50 W
5.2
Typ
6.0
2
V
1
mA
V
%
pF
5
1. For test procedure see Figures 5 and 6 and application note AND8307/D.
2. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
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8.0
GHz
ESD7205, SZESD7205
1.0
1.E−03
0.9
1.E−04
0.8
1.E−05
0.7
1.E−06
0.6
I (A)
C (pF)
1.E−02
1.E−07
1.E−08
0.4
1.E−09
0.3
1.E−10
0.2
1.E−11
0.1
1.E−12
−2 −1
0
1
2
3
4
5
6
7
8
9
0
0
10
2
3
5
4
V (V)
VBias (V)
Figure 2. CV Characteristics
10
80
0
70
−10
60
−20
VOLTAGE (V)
VOLTAGE (V)
1
Figure 1. IV Characteristics
90
50
40
30
20
−30
−40
−50
−60
10
−70
0
−80
−10
−20
I/O−GND
0.5
0
20
40
60
80
TIME (ns)
100
120
140
−90
−20
Figure 3. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
0
20
40
60
80
TIME (ns)
100
120
Figure 4. IEC61000−4−2 −8 kV Contact ESD
Clamping Voltage
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3
140
ESD7205, SZESD7205
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test Voltage (kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 5. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 6. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
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4
ESD7205, SZESD7205
20
10
18
8
−14
12
6
10
6
−12
−10
8
4
6
4
2
4
−8
−6
−4
2
−2
2
NOTE:
8
−16
EQUIVALENT VIEC (kV)
TLP CURRENT (A)
TLP CURRENT (A)
16
2
4
6
8
10
12
14
16
18
0
0
0
20
2
4
6
8
10
12
14
16
VOLTAGE (V)
VOLTAGE (V)
Figure 7. Positive TLP IV Curve
Figure 8. Negative TLP IV Curve
18
0
20
TLP parameter: Z0 = 50 W, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns.
Transmission Line Pulse (TLP) Measurement
L
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 9. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 10 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels.
50 W Coax
Cable
S Attenuator
÷
50 W Coax
Cable
10 MW
IM
VM
DUT
VC
Oscilloscope
Figure 9. Simplified Schematic of a Typical TLP
System
Figure 10. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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5
EQUIVALENT VIEC (kV)
−18
14
0
0
10
−20
ESD7205, SZESD7205
1
0.6
0
0.5
−1
CAPACITANCE (pF)
−2
dB
−3
−4
−5
−6
−7
−8
0.4
0.3
0.2
3.3 V
0V
0.1
−9
−10
1.E+06
1.E+07
1.E+08
1.E+09
1.E+10
0.0
0.E+00
FREQUENCY (Hz)
5.E+08 1.E+09
2.E+09
2.E+09 3.E+09 3.E+09
FREQUENCY
Figure 11. RF Insertion Loss
Figure 12. Capacitance over Frequency
ORDERING INFORMATION
Package
Shipping†
ESD7205DT5G
SOT−723
(Pb−Free)
8000 / Tape & Reel
SZESD7205DT5G*
SOT−723
(Pb−Free)
8000 / Tape & Reel
ESD7205WTT1G
SOT−323
(Pb−Free)
3000 / Tape & Reel
SZESD7205WTT1G*
SOT−323
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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6
ESD7205, SZESD7205
PACKAGE DIMENSIONS
SOT−723
CASE 631AA
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH. MINIMUM LEAD THICKNESS IS THE MINIMUM
THICKNESS OF BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
−X−
D
A
b1
−Y−
3
E
1
HE
2
2X
2X
b
e
C
0.08 X Y
SIDE VIEW
TOP VIEW
3X
DIM
A
b
b1
C
D
E
e
HE
L
L2
L
1
3X
MILLIMETERS
MIN
NOM
MAX
0.45
0.50
0.55
0.15
0.21
0.27
0.25
0.31
0.37
0.07
0.12
0.17
1.15
1.20
1.25
0.75
0.80
0.85
0.40 BSC
1.15
1.20
1.25
0.29 REF
0.15
0.20
0.25
RECOMMENDED
SOLDERING FOOTPRINT*
L2
BOTTOM VIEW
2X
0.40
2X
0.27
PACKAGE
OUTLINE
1.50
3X
0.52
0.36
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
ESD7205, SZESD7205
PACKAGE DIMENSIONS
SC−70 (SOT−323)
CASE 419−04
ISSUE N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
D
e1
DIM
A
A1
A2
b
c
D
E
e
e1
L
HE
3
E
HE
1
2
b
e
A
0.05 (0.002)
MIN
0.80
0.00
0.30
0.10
1.80
1.15
1.20
0.20
2.00
MILLIMETERS
NOM
MAX
0.90
1.00
0.05
0.10
0.70 REF
0.35
0.40
0.18
0.25
2.10
2.20
1.24
1.35
1.30
1.40
0.65 BSC
0.38
0.56
2.10
2.40
MIN
0.032
0.000
0.012
0.004
0.071
0.045
0.047
0.008
0.079
INCHES
NOM
0.035
0.002
0.028 REF
0.014
0.007
0.083
0.049
0.051
0.026 BSC
0.015
0.083
MAX
0.040
0.004
0.016
0.010
0.087
0.053
0.055
0.022
0.095
c
A2
L
A1
SOLDERING FOOTPRINT*
0.65
0.025
0.65
0.025
1.9
0.075
0.9
0.035
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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ESD7205/D