NSC CLC016 Data retiming pll with automatic rate selection Datasheet

CLC016
Data Retiming PLL with Automatic Rate Selection
General Description
Features
National’s Comlinear CLC016 is a low-cost, monolithic, data
retiming phase-locked loop (PLL) designed for high-speed
serial clock and data recovery. The CLC016 simplifies highspeed data recovery in multi-rate systems by incorporating
auto-rate select (ARS) circuitry on chip. This function allows
the user to configure the CLC016 to recognize up to four different data rates and automatically adjust to provide accurate, low-jitter clock and data recovery. A single resistor is
used to set each data rate anywhere between 40 Mbps and
400 Mbps. No potentiometers, crystals, or other external ICs
are required to set the rate.
The CLC016 has output jitter of only 130 pspp at a 270 Mbps
data rate and 0.25% fractional loop bandwidth. Low phase
detector output offset and low VCO injection combine to ensure that the CLC016 does not generate bit errors or large
phase transients in response to extreme fluctuations in data
transition density. The result is improved performance when
handling the pathological patterns inherent in the SMPTE
259M video industry standard.
The carrier detect and output mute functions may be used
together to automatically latch the outputs when no data is
present, preventing random transitions. The external loop filter allows the user to tailor the loop response to the specific
application needs. The CLC016 will operate with either +5V
or −5.2V power supplies. The serial data inputs and outputs,
as well as the recovered clock outputs, allow single- or
differential-ECL interfacing. The logic control inputs are TTLcompatible.
n
n
n
n
n
n
n
n
n
n
n
Retimed data output
Recovered clock output
Auto and manual rate select modes
Four user-configurable data rates
No potentiometers required
External loop bandwidth control
Frequency detector for lock acquisition
Carrier detect output
Output MUTE function
Single supply operation: +5V or −5.2V
Low cost
Key Specifications
n Low jitter: 130 pspp @ 270 Mbps, 0.25% fractional loop
bandwidth (0.675 MHz)
n High data rates: 40 Mbps − 400 Mbps
n Low supply current: 100 mA, including output biasing
n Flexible fractional loop bandwidth: from 0.05% to 0.5%
Applications
n SMPTE 259M serial digital interfaces: NTSC/PAL, 4:2:2
component, 360 Mbps wide screen
n Serial digital video routing and distribution
n Clock and data recovery for high-speed data
transmission
n Re-synchronization of serial data for SONET/SDH, ATM,
CAD networks, medical and industrial imaging
DS100087-1
Order Number
Temperature
Package
CLC016ACQ
0˚C to +70˚C
PLCC V28A
CLC016AJQ
–40˚C to +85˚C
PLCC V28A
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100087
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CLC016 Data Retiming PLL with Automatic Rate Selection
July 1998
Typical Application
Four-Rate Clock and Data Recovery with Automatic Rate Selection
DS100087-2
Pinout
DS100087-3
28-pin PLCC
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2
Absolute Maximum Ratings (Note 1)
Reliability Information
MTTF (based on limited life
test data)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC–VEE)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering 4 sec)
ESD Rating (Note 12)
Package Thermal Resistance
θJA 28-Pin PLCC
θJC 28-Pin PLCC
2.6 x 107 hours
Recommended Operating
Conditions
−0.3, +6.0V
+150˚C
−65˚C to +150˚C
+260˚C
2kV
Supply Voltage (VCC–VEE)
Operating Temperature
Jitter Transfer Function Fractional Loop
Bandwidth
SCO/SCO, SDO/SDO Minimum
Voltage (Note 13)
85˚C/W
35˚C/W
4.5V to 5.5V
–40˚C to +85˚C
0.05% to 0.5%
VCC – 1.6V
Electrical Characteristics
(VCC = 0V, VEE = −5V, RBW = 500Ω; CZ = 0.1 µF; CP = 82 pF; Rn = 3504, CARS = 0.1 µF; unless specified).
Parameter
Conditions
Typ
+25˚C
Min/Max
+25˚C
Min/Max
Full Temp.
Range
Units
250
300
pspp
100
100
400
400
Mbps
± 5.0/
± 13.0
± 1.2
± 2.5/
± 18.0
± 1.3
%fCLK
DYNAMIC PERFORMANCE
Residual Jitter
270 Mbps PRN sequence
(Notes 3, 4)
150
Acquisition Time
270 Mbps PRN sequence
6 x 105
Minimum Average Data Rate, fCLK
Full Temperature Range
4.5V ≤ (VCC − VEE) ≤ 5.5V
(Note 3)
0 to 70˚
4.5V ≤ (VCC − VEE) ≤ 5.5V
40
Maximum Average Data Rate, fCLK
4.5V ≤ (VCC − VEE) ≤ 5.5V
(Note 3)
Tracking and Capture Range
4.5V ≤ (VCC − VEE) ≤ 5.5V
(Notes 3, 5)
± 8.3
VCO Power Supply Sensitivity
(Note 3)
± 0.8
± 250
VCO Temperature Sensitivity
Jitter Transfer Function −3 dB bandwidth
(Fractional Loop Bandwidth), λBW
Jitter Transfer Function Peaking
bit cells
Mbps
Mbps
%V
ppm/˚C
RBW = 100Ω (Notes 6, 7)
0.05
%fCLK
RBW = 500Ω (Notes 6, 7)
0.25
%fCLK
RBW = 1000Ω (Notes 6, 7)
0.5
%fCLK
< 0.1
dB
RBW = 500Ω, 270 Mbps
(Note 6)
STATIC PERFORMANCE
Power Supply Current, IEE
(Note 3)
105
Voltage on Selected Rn Resistor
(Note 8)
VCC −2.2
V
Voltage on Unselected Rn Resistor
(Note 8)
VCC
V
VC/VC Common-Mode Voltage, VCM
(Note 8)
VCC −1.5
V
VC/VC Diff-Mode Voltage Range, VDM
(Note 8)
± 300
mV
DDI/DDI
Input Range Upper Limit, VH
Output Voltage Swing, VOUT
ACQ/WR, MUTE, RDO/RD1
Voltage Input — LOW, VIL
(Note 3)
3
mA
V
VEE +2.5
Minimum Differential Input Amplitude, V∆
Input Current
133
VCC
Input Range Lower Limit, VL
SCO/SCO, SDO/SDO
Output Current, IOUT
125
V
200
200
mV
6
6
µA
8.6/12.7
(Note 3)
11
9.3/12
Rcollector = 75Ω (Note 3)
725
625/900
mA
mV
(Note 9)
VEE + 0.8
VEE + 0.8
Voltage Input — HIGH, VIH
(Note 3)
VEE + 2.0
VEE + 2.0
V
Input Current (IIN)
(Note 3)
± 100
± 500
nA
3
V
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Electrical Characteristics
(Continued)
(VCC = 0V, VEE = −5V, RBW = 500Ω; CZ = 0.1 µF; CP = 82 pF; Rn = 3504, CARS = 0.1 µF; unless specified).
Parameter
Conditions
Typ
+25˚C
Min/Max
+25˚C
Min/Max
Full Temp.
Range
Units
STATIC PERFORMANCE
CD, UNL, RDO/RD1
(Note 9)
Current Output — LOW, IOL
VOL ≤ VEE+0.5V
800
µA
Current Output — HIGH, IOH
VOH ≥ VCC−0.5V
−700
µA
TIMING PERFORMANCE
Delay: SCO to SDO, td
200
SCO Duty Cycle
(Note 3)
50
Rise/Fall Time: SCO, SDO, tr/tf
20%–80%, Rcollector = 75Ω
(Note 10)
230
ps
44/56
44/56
%
ps
SDO Duty Cycle Distortion
35
Minimum Setup Time:
RDO/RD1 to ACQ/WR, tSU
4
20
20
ps
ns
Minimum Hold Time:
ACQ/WR to SS1/SS0, th
3
20
20
ns
Minimum Pulse Width:
ACQ/WR, tw
5
20
20
ns
8.5/15.5
ARS Oscillator Period, tOSC
(Note 3)
10.5
CD Pulse Width, tPW
(Note 11)
1
µs
5
ns
MUTE Response Time, tM
ms
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: J-level spec. is 100% tested at +25˚C.
Note 4: Peak-to-peak jitter is defined as 6 times the rms jitter.
Note 5: Tracking and capture range are specified as a percentage of the input data rate fCLK. The minimum and maximum are guaranteed so long as Rn has been
chosen according to the equation in Resistor Selection for Data Rates.
Note 6: Average data transition density of 1 transition per 2 bit cells.
Note 7: When the value of RBW changes it is necessary to also change the values of CP and CZ. See Loop Filter Design.
Note 8: This information is provided for system troubleshooting purposes only.
Note 9: RD0/RD1 are inputs when AUTO = 0 and outputs when AUTO = 1.
Note 10: Includes typical pc board capacitance.
Note 11: The CD circuit is a retriggerable one-shot which retriggers on every data transition.
Note 12: Human body model, 1.5 kΩ in series with 100 pF.
Note 13: To maintain specified performance, SCO/SCO and SDO/SDO should not drop below this level.
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Typical Performance Characteristics
DS100087-4
DS100087-5
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5
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Typical Performance Characteristics
(Continued)
DS100087-10
DS100087-11
DS100087-12
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For application assistance, refer to the list of telephone numbers on the pack page of this data sheet.
Product Description
The CLC016 Data Retiming PLL is a monolithic circuit that
recovers clock and data from a serial NRZ or NRZI data
stream. The Data Retiming PLL incorporates an Auto-Rate
Selection function which automatically selects one of four
user-configurable data rates. The following outline lists the
material covered in this data sheet:
•
•
•
•
•
•
•
•
Data Retimer Typical Connections
The CLC016 schematics provided in Figure 1 and Figure 2
show typical +5V or −5.2V connections with Auto-Rate Selection configured for SMPTE 259M standard video data
rates: 143, 177, 270 and 360 Mbps. The section Resistor
Selection for Data Rates gives tables and equations for determining Rn resistor values for any data rate from 50 Mbps
to 400 Mbps. A resistor value table is also given for SONET/
SDH data rates. The schematics in Figure 1 and Figure 2 do
not include input termination. The high impedance inputs on
the CLC016 allow the user to define the termination. The Interfaces section suggests recommended terminations for
the inputs and outputs of the CLC016.
Typical schematics for +5V or −5.2V operation
Block diagram description
Pin definitions
Design guidelines
Interface connections
Measurement
Typical applications
Printed circuit layout and evaluation boards
DS100087-13
FIGURE 1. Typical +5V Connection
DS100087-14
FIGURE 2. Typical −5.2V Connection
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Product Description
Operation Description
The CLC016 Data Retiming PLL, Figure 3, has three main
functions: Frequency Detector (FD), Phase-Locked Loop
(PLL) and Auto-Rate Select (ARS).
(Continued)
Pin Definitions
Name
DDI, DDI
Pin #
5, 6
Description
SCO,
SCO
23, 22
Differential collector (ECL,
PECL compatible) clock outputs
SDO,
SDO
25, 24
Differential collector (ECL,
PECL compatible) retimed data
outputs
RDO,
RD1
20, 21
Bi-directional (TTL, CMOS)
VCO data rate bus. See Table 3
for state table.
Rn
13, 14,
15, 17
VCO rate configuration resistors
(n = 0, 1, 2, 3).
RTN
18
Return for Rn
SER
4
Loop unlock output (TTL,
CMOS) indicator. High when
loop is unlocked or
harmonic-locked.
CD
19
Carrier detector (TTL, CMOS)
output. Low when no signal is
present.
MUTE
28
Output mute (TTL, CMOS)
control. Connect to CD to latch
outputs when no signal is
present.
AUTO
16
Auto- or manual-rate mode
control (TTL, CMOS) input.
Assert high for auto-rate mode.
ACQ/WR
8
ARS oscillator enable and rate
latch enable (TTL, CMOS)
input. Connect to SER (see
diagrams) for auto-rate mode.
CARS
2
External capacitor connections
for controlling the rate of the
ARS search.
12, 9
VCO control lines. Loop filter
connects across these and FD.
VC, VC
FD
10
Frequency detector output. CZ
must connect from FD to VC.
VCC
7, 26
Positive supply pins (ground or
+5V).
VEE
1, 3, 11,
27
Negative supply pins (−5.2V or
ground).
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The Frequency Detector detects the frequency difference
between the input data rate and the VCO frequency, and
forces a rapid change in VCO frequency to minimize that difference. As the frequency difference approaches zero, the
PLL acquires phase lock and the Frequency Detector becomes inactive. In Auto-Rate Select mode, the Frequency
Detector requests the ARS function to search for a new data
rate.
The PLL consists of a Voltage Controlled Oscillator (VCO), a
Phase Detector (PD), and an external Loop Filter (LF). The
PLL recovers a low-jitter clock for data retiming. The data is
re-synchronized (retimed) at the Data Latch. The data and
clock are buffered outputs.
The ARS block has two modes of operation: Auto-Rate Mode
(ARM) and Manual-Rate Mode (MRM). Once the ARS function is activated (ARM), it sequences through the userselected data rates until phase lock is achieved. The user
has control over the rate at which ARS steps through the
data rates (see Auto-Rate Selection section).
The Carrier Detect (CD) block detects the presence of input
data and is an input to the ARS block. When CD is connected to MUTE and no data is present, the clock and data
outputs are latched.
Differential (ECL, PECL) data
inputs.
DS100087-15
FIGURE 3. Functional Block Diagram
8
Product Description
previously-selected resistor Rn and incrementing to Rn+1,
etc. in order of R0, R1, R2, R3, R0, .... This sequence is repeated until lock is achieved. The 2-bit bidirectional bus,
comprised of RD0 and RD1, indicates the selected data rate.
The RD0, RD1 bidirectional bus is set to output mode when
AUTO is active (high). Therefore, RD0, RD1 can be monitored when AUTO is active. When no data is present at the
inputs, CD will inhibit the ARM.
In manual mode the RD0, RD1 lines are set to input mode.
Therefore, RD0, RD1 cannot be monitored when AUTO is inactive. The selection of external components for both modes
of operation is discussed in sections, Resistor Selection for
Data Rates, and Auto-Rate Selection.
(Continued)
Functional Block Descriptions
Frequency Detector (FD)
The Frequency Detector detects the difference between
VCO rate and the input data rate, then forces the frequency
(rate) difference to zero. In Auto-Rate Mode, when a difference is detected, FD requests the ARS block to start a
search to match the rate. Once the PLL acquires phase lock,
the PLL takes control and the FD goes inactive.
Phase Detector (PD)
The PD compares the phase of the VCO to the phase of the
input data. The PD output is a differential current which is
proportional to the phase error. The PD gain has units of amperes per radian and is dependent upon the data transition
density (ρ). The data transition density is defined as the average number of data transitions per clock cycle, and is
bounded by 0 ≤ ρ ≤ 1. The PD output is connected to the
VCO through the external loop filter network. This network
translates the PD output current to a voltage that controls the
VCO.
Loop Filter (LF)
The external Loop Filter shown in Figure 3 is made up of
passive components RBW, CZ, and CP. This external loop filter controls the PLL dynamics and acquisition time.
The Frequency Detector supplies its signal to the CZ capacitor, and takes control of the VCO under the condition of frequency unlock. The selection of the filter components is covered in the Loop Filter Design section.
Voltage Controlled Oscillator (VCO)
The VCO is a temperature-compensated, factory-trimmed
multivibrator that requires no external capacitors for tuning. It
is stable over temperature and power supply variations. This
eliminates the need for potentiometers to adjust each of the
VCO center frequencies to correspond with the input data
rates. Instead, an external resistor (Rn) is used to set each of
four data rates in the range of 40 Mbps to 400 Mbps.
Carrier Detector (CD)
The CD circuit is a retriggerable one-shot which retriggers on
every data transition. When data transitions occur at a rate
≥1 transition per µs, CD indicates the presence of data at the
input pins DDI and DDI. CD also inputs a signal to ARS that
inhibits any rate search from occurring in the absence of input data. When CD in connected to the MUTE pin, and no
data is present, the output clock (SCO, SCO) and data
(SDO, SDO) lines are latched.
Auto-Rate Select (ARS) and Multiplexer (MUX)
DESIGN GUIDELINES
Resistor Selection for Data Rates
The CLC016 Data Retiming PPL supports 4 different data
rates using user-selected resistors that set the VCO center
frequency. The resistors found in Figures 1, 2 are identified
by the reference designators Rn, where n is 0, 1, 2 and 3.
It is recommended that the user select resistor values with
tolerances of 1% and temperature coefficients of ≤100 ppm/
˚C. Refer to Table 1 and Table 2 for calculated resistor values for SMPTE and SONET standards. Resistors for other
data rates are determined from the following equation:
where n = 0, 1, 2, 3 and fCLK is the desired data rate.
TABLE 1. Resistor Values for SMPTE 259M Data Rates
Data Rate
(Mbps)
Ref. Des.
(in Figures
1, 2)
Rn
Calculated
Resistor
(kΩ)
1%
Resistors
(in Figures
1, 2)
(kΩ)
143
R0
6.79
6.81
177
R1
5.45
5.49
270
R2
3.50
3.48
360
R3
2.58
2.55
TABLE 2. DS-3 and SONET/SDH Resistor Values
Data Rate
(Mbps)
The ARS, in conjunction with the MUX, sequences through
the user-configured resistor values (Rn) in an unlocked condition. The ARS has two modes: Auto-Rate Mode (ARM) and
Manual-Rate Mode (MRM). It incorporates additional features and functions that are discussed in the section named
Auto-Rate Selection.
When ARS is in Auto-Rate Mode, its inputs are the FD (the
LHP control line), the Carrier Detect (CD), the VCO (CLK),
and Latched Data output. These input signals produce an
external Search (SER) signal that, when connected to the
ACQ/WR input, enables the ARM operation. A single capacitor, CARS, sets the ARM sequence time for stepping through
the different user-configured data rates.
The timing section of the ARS block controls the digital input
analog multiplexer (MUX). Under the control of ARS, the
MUX steps through each data rate starting with the
Calculated
Resistor
(kΩ)
1% Resistors
(kΩ)
44.7
22.1
22.1
51.84
19.1
19.1
155.52
6.23
6.19
311.04
3.02
3.01
Loop Filter Design
The function of the PLL is to low-pass filter the jitter of the incoming data stream. The jitter transfer function for the PLL
(or the phase transfer function) is set by the phase detector
gain, the loop filter transfer function, and the VCO gain.
These elements are shown in the small-signal block diagram, Figure 4.
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Product Description
The fractional loop bandwidth is set by the loop component
RBW:
(Continued)
where ρ is the data transition density in average number of
data transitions per bit cell, and ranges in value from 0 to 1.
For example, if a pseudo-random data stream is used, the
value of ρ is 1/2, and a data transition will occur once every
two bit cells on the average. The phase detector and VCO
gain set the constants in the equation.
If the value of RBW is 500Ω and ρ = 1/2, the fractional loop
bandwidth is:
DS100087-16
FIGURE 4. PLL Loop
The jitter transfer function is the small signal transfer function, θo/θi, and is given by:
For a data rate of 270 Mbps this corresponds to a loop bandwidth fBW = 644 kHz. The jitter at frequencies above 644 kHz
will be attenuated by the PLL.
The equation may be rearranged to obtain RBW as a function
of the desired fractional loop bandwidth:
where fBW is the PLL bandwidth and fZ is a zero in the closed
loop transfer function.
The phase detector gain and VCO gain are fixed internally.
Selection of the external loop filter components defines the
overall jitter transfer function. Additionally, the filter components control the acquisition performance of the PLL.
A Bode plot for the closed loop PLL jitter transfer function is
shown in Figure 5.
Setting the Jitter Peaking Factor (Selecting CZ)
The jitter peaking factor, δ, is set by the ratio of the critical
frequencies fZ and fBW. The ratio is defined as:
Figure 6 shows how the jitter peaking factor, δ, varies with α.
For example, if the value of α is 0.1, then the jitter peaking is
about 0.6 dB.
The approximation for the required value of α to obtain a
given amount of jitter peaking is:
α ≅ δ(0.134 + 0.058δ)
The critical frequency fZ is:
Select CZ by the following equation:
DS100087-17
FIGURE 5. Closed-Loop Transfer Function
At frequencies above fBW (the PLL bandwidth) the jitter is attenuated. At frequencies below fBW the jitter is transmitted
through the PLL. A small amount of jitter peaking (δ) occurs
at frequencies below fBW. The amount of peaking increases
when fZ moves closer to fBW.
Setting the Loop Bandwidth (Selecting RBW)
The fractional loop bandwidth, λBW, is the ratio of fBW to the
data rate. The CLC016 is specified for operation with fractional loop bandwidths ranging from 0.05% to 0.5%. For example, if the loop bandwidth is 1 MHz and the data rate is
270 Mbps, then the fractional loop bandwidth is:
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Product Description
In addition, CP can affect the ability of the PLL to acquire
lock, especially at high data rates. Because of this, it is recommended to eliminate CP entirely for the condition of high
data rate ( > 300 Mbps) combined with narrow loop bandwidth ( < 0.1%).
Multiple Rate Considerations
RBW establishes the fractional loop bandwidth. For a fixed
value of RBW, fBW will vary with the selected data rate. The
location of the critical frequencies fZ and fP, however, are independent of data rate.
To control jitter peaking for all multi-rate application choose:
(Continued)
•
the value of CZ for the smallest value of fBW (which is obtained at the lowest data rate).
•
the value of CP for the largest value of fBW (which is obtained at the highest data rate).
Loop Filter Element Summary Table
The table below summarizes the recommended loop filter element values for each of the four SMPTE 259M data rates
and a fractional loop bandwidth of 0.25%. The final row of
the table gives the recommended values for the multi-rate
case, where all four of the SMPTE rates are configured.
DS100087-18
FIGURE 6. Jitter Peaking Curve
As an example, assume that the amount of jitter peaking that
can be tolerated is 0.05 dB. From the jitter peaking design
equation (or from Figure 6) the required value of α is:
α ≅ 0.05[0.134 + (0.058)(0.05)] = 0.007
Now assuming that the loop bandwidth is 644 kHz and that
the value of RBW is 500Ω, the value of CZ is:
Data Rate
(Mbps)
fBW
(kHz)
RBW
(Ω)
CZ
(µF)
CP
(pF)
143
358
500
0.10
200
177
443
500
0.10
160
270
675
500
0.047
100
360
900
500
0.04
82
143–360
0.25% fCLK
500
0.10
82
Component Types and Tolerances
It is recommended that RBW resistors have tolerances of 1%
and temperature coefficients of ≤100 ppm/˚C. The recommended capacitors are ceramic surface mount with 5% tolerance or better.
The value of CZ also affects the acquisition performance of
the PLL. Estimate the acquisition time with the following
equation:
AUTO-RATE SELECTION
Auto Rate Mode (ARM)
This section provides more detail on the ARS sub-system
and how to use it. Figure 7 shows a detailed view of the ARS
portion of the Figure 3 block diagram
The auto-rate mode is enabled by connecting AUTO to VCC
and SER to ACQ/WR through the 1 kΩ/1 nF network. When
the VCO is not at the input data rate, SER goes high enabling the ARS oscillator and the Latch. The oscillator increments the 2-bit counter and causes the VCO to sequence
through the rates determined by resistor Rn (beginning at the
currently selected rate and advancing the index, n, upward).
The oscillator period (TARS) is determined by CARS. When
the VCO rate is at the input data rate, SER goes low and
ceases to increment the counter.
where tACQ x fCLK is the acquisition time in number of bit
cells.
Selecting CP
Capacitor CP establishes a high frequency pole in the loop
filter to remove high frequency spectral components from the
phase detector. The pole frequency fP is:
In general, the pole should be set at least a factor of 4 above
the PLL bandwidth, fBW. Therefore, select CP using:
For example, if RBW is 500Ω and fBW is 644 kHz, then an appropriate value for CP is:
Choosing a value for CP larger than the value recommended
by the selection equation will introduce jitter peaking. Reducing the value of CP below that recommended by the selection equation is acceptable, but will result in some increase
in jitter. This is most noticeable with large fractional loop
bandwidths.
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Product Description
(Continued)
DS100087-20
FIGURE 8. Data Rate Applied or Moves
within PLL Capture
DS100087-19
FIGURE 7. Auto-Rate Select
SER goes high when CD is high and either of the following
conditions is true:
• The FD is active, causing LHP to go high.
• The harmonic lock detector determines that the VCO is
running at a harmonic of the input data rate, causing
HLOCK to go high.
Timing diagrams related to locking and unlocking of the PLL
and removal of the input data are given in Figures 8, 9 and
Figure 10. The term tACQ in Figure 8 is defined in the Loop
Filter Design section. Also, tS is the settling time for the
phase error to decay to less than 90˚. It is given by the following equation:
tS = RBW x CZ x In(2) + 20 µs
DS100087-21
FIGURE 9. Data Rate Moves beyond the
PLL Tracking Range
The ARS oscillator period must be greater than the sum of
tACQ and tS:
tARS = (140 ms/µF) x CARS > tACQ + tS
The harmonic lock detector senses if the VCO is locked to a
data rate harmonic (integer multiple) by looking for the presence of bit changes across 3 consecutive periods of CLK as
shown in Case 1 of Figure 11. This event occurs on average
25% of the time in random data. HLOCK goes low if the occurrence rate is less than 12.5%. When a harmonic lock condition occurs there is at least a 2 µs delay for HLOCK to go
high. Case 2 illustrates the situation where CLK is at the 2nd
harmonic of the input data rate and each input bit cell is
double-clocked. Bit changes across three consecutive periods are never detected and HLOCK goes high.
During intervals of sparse data transitions, the harmonic lock
detector may cause SER to go high. An example of this is
the pathological pattern associated with the SMPTE 259M
video industry standard. For an interval of 50 µs, the input
data transitions can be separated by 20-bit cells; and it appears to the harmonic lock detector as though the VCO is at
a harmonic rate. So long as these intervals do not exceed
the period of the ARS oscillator, the ARS sub-system will not
increment the 2-bit counter. TARS must be the greater of
the value calculated by the above equation of the sparse
data pattern interval. Figure 12 shows a timing diagram relating to sparse data transition intervals.
DS100087-22
FIGURE 10. Input Data Removed
DS100087-23
FIGURE 11. Harmonic Lock Detector Operation
In auto-rate mode the user can monitor the RD0/1 bus to determine the automatically selected data rate. Refer to Table 3
for the correspondence between the data bus state and the
selected rate resistor.
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12
Product Description
The ACQ/WR line and bus lines RD0/1 must observe setup
and hold conditions. The minimum requirements are specified in the sub-section Timing Performance of the Electrical Characteristics page. The timing diagram in Figure 14
indicates where the measurements are made.
(Continued)
DS100087-24
DS100087-26
FIGURE 12. Response to Sparse Patterns
FIGURE 14. ACQ/WR and RD0/1 Timing Diagram
Minimum Data Rate Spacing in ARM
Fixed Rate Mode
For single data rate applications, set AUTO low, ACQ/WR
high, and tie RD0 and RD1 to the levels shown in Table 3.
Also, short CARS to VEE.
Minimum Data Rate Spacing in MRM
If it is desired that SER goes high (due to the inability of the
PLL rate) as an indication that the incoming data rate does
not correspond to the intended rate selected by RD0 and
RD1, then the minimum spacing between data rates must be
great enough to prevent the tracking and capture range of
the PLL at one rate from encompassing the adjacent rate. If
the data rates are too close, it is possible for the PLL to lock
to either rate regardless of which was selected by RD0 and
RD1. The tracking and capture range is given in the Electrical Characteristics table. In addition, the tolerance of VCO
rate configuration resistors should be added to the guaranteed tracking and capture range in computing minimum data
rate spacing.
Output Timing
The clock-to-output data timing has a small delay of clock-todata. This delay is specified in the Electrical Characteristics page under the sub-section Timing Performance. The
delay is measured from the 50% level of the CLK to the eye
pattern 50% crossing, as shown in Figure 15
RD0 and RD1 indicate which VCO rate configuration resistor
(i.e., Rn) is selected. For each resistor there is a range of
rates that the PLL will lock to. If two data rates fall within this
range, a given RD0/RD1 indication may correspond to either
rate. If it is desired that each incoming data rate be uniquely
reported by RD0 and RD1, then the minimum spacing between data rates must be great enough to prevent the tracking and capture range of the PLL for one rate configuration
resistor from encompassing the adjacent rate. The tracking
and capture range is given in the Electrical Characteristic
table. In addition, the tolerance of VCO rate configuration resistor should be added to the guaranteed tracking and capture range in computing minimum data rate spacing.
Manual Rate Mode (MRM)
The Manual Rate Mode provides the user with manual control over the data rate selection. This is done by setting the
AUTO line low and shorting the CARS capacitor to VEE. The
manual data rate is set by the 2-bit bus RD0/1 using the
ACQ/WR line to initiate a MUX update. Table 3 gives the
state table for resistor selection.
TABLE 3. Rate State Table
ACQ/WR
RD1
RD0
Resistor
1
0
0
R0
1
0
1
R1
1
1
0
R2
1
1
1
R3
0
X
X
No Change
DS100087-27
When in the MRM, the AUTO line is set low as in Figure 13.
The buffer output is TRI-STATE ® which allows the bus lines
RD0/1 to be used as inputs to the latch. The inputs RD0/1
are latched by using the ACQ/WR line.
FIGURE 15. Output Timing of Clock and Data
INPUT INTERFACES
The CLC016 provides high impedance inputs which accept
differential or single-ended input drive. The detailed electrical specifications are found in the Electrical Characteristics page. Recommended interfaces for the CLC016 follow.
Four conditions should be observed when interfacing to the
CLC016 inputs:
DS100087-25
FIGURE 13. Manual Select Mode
13
•
Keep input levels within specified common-mode input
range.
•
•
Provide a bias current path to the inputs.
Terminate cable in the proper impedance.
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Product Description
•
(Continued)
Observe the output current requirements of the driving
device.
Figure 16 and Figure 17 show DC and AC coupled interface
examples which meet these four conditions.
DS100087-30
FIGURE 18. Differential Load-Terminated
Output Interface
DS100087-28
Differential Source-Terminated Output Interface
Figure 19 is similar to Figure 18 except that the termination
is placed near the output pins.
FIGURE 16. Differential 75Ω Source
DS100087-29
FIGURE 17. AC Coupled Termination
OUTPUT INTERFACES
SDO, SDO, SCO, and SCO swing at ECL logic levels when
the correct external components are used. However, the outputs are not standard emitter-coupled logic outputs. Instead,
the signals flow from the collectors of the output transistors.
The primary advantage of this architecture is lower power
dissipation. Some example interfaces follow.
Differential Load-Terminated Output Interface
DS100087-31
FIGURE 19. Differential SourceTerminated Output Interface
Terminating Physically Separated Outputs
When the circuit design requires the outputs to be routed to
separate locations, the recommended interface is depicted
in Figure 20. Choose the resistors for an equivalent 75Ω termination of the cable impedance (or other cable characteristic impedance, as appropriate).
Figure 18 shows an interface to drive signals differentially
over a coaxial cable. The diode establishes VOH.. The dioderesistor network sets VOL. The resistors terminate the cable
in its characteristic impedance.
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14
Product Description
TYPICAL APPLICATIONS
The CLC016 was designed as one of a series of data transmission support chips. The CLC016 is recommended for a
wide variety of clock and data recovery applications that fit
within its range of data rates.
Serial Data Transmission over Cable
(Continued)
Serial data transmission is common for all types of communication channels where the data is sent over coaxial or
twisted pair cable. Figure 21 shows a typical connection using a CLC006 driver chip, CLC014 Adaptive Cable Equalizer,
and the CLC016 Data Retiming PLL. The CLC016 extracts
the clock and retimes the data from the serial bit stream.
The components recommended in Figure 21 support the
four common data rates specified in SMPTE 259M.
ESD
The CLC016 is a CMOS chip. Operators are cautioned to
use grounding straps when handling.
DS100087-32
FIGURE 20. Load Terminated Output Interface
MEASUREMENTS & EVALUATION
When evaluating the CLC016 Data Retimer, it is recommended that you solder the part to the board or use a leadless chip carrier socket. Probing with capacitive probes will
disturb the CLC016 performance. When probing the signal
levels use a 1 pF capacitance probe with a 500Ω tip.
The block diagram below shows a simple method of measuring the clock to eye pattern jitter. Use of the CLC016 evaluation board is recommended for jitter evaluation. It also provides a good reference for a user’s circuit board design. The
plot in Figure 23 shows a histogram of the jitter and where
the measurements were taken.
CONTROL LINE INTERFACES
The use of the CLC016 with +5V supplies allows the control
lines to interface to standard TTL logic signals. Operating the
CLC016 at −5.2V requires level-shifting circuits for the control line inputs. Refer to the Static Performance section of
the Electrical Characteristics page for required input voltage levels.
POWER CONSUMPTION
The power supply current given in the Electrical Characteristics table includes the current required for both the clock and
data output buffers to drive a 75Ω load to ECL swings.
DS100087-33
FIGURE 21. Typical Cable Connection
15
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Product Description
(Continued)
DS100087-34
FIGURE 22. Jitter Measurement Setup
DS100087-35
FIGURE 23. Typical Jitter Histogram
8.
PCB LAYOUT RECOMMENDATIONS
Printed circuit board layout affects the performance of the
CLC016. The following are PCB layout rules for the CLC016:
1. Use a ground plane.
2. De-couple VCC/VEE power pins with 0.01 µF ceramic capacitors placed ≤0.1” (3mm) from the power pins and
6.8 µF tantalum capacitors.
3. For long signal runs, match transmission lines to the desired characteristic impedance for the input and output
lines.
4. Remove ground plane 0.025” (0.06mm) from all pads.
5. Remove ground plane from the area around the loop filter and frequency selection resistors.
6. Keep digital and analog lines sufficiently away from loop
filter or frequency selection resistors.
7. Avoid the use of sockets in production boards.
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In proto-boards use a low-profile, low impedance, type
socket.
EVALUATION BOARD
An evaluation board layout and schematic are shown on the
following page. The art work shows the board solder masks,
trace layers, and ground plane. To order an evaluation
board, contact your local sales representative or National support center and request part number
CLC730057.
The evaluation board provides LEDs and switches to operate the PLL in various modes. The board allows the user to
select +5V or −5.2V power supplies, identified on the printed
board silk screen. Insert all tantalum capacitors as shown in
the schematic or silk screen. A complete bill of materials is
given in the following table. The components recommended
in the materials list are for SMPTE 259M standards.
16
Product Description
(Continued)
DS100087-36
Schematic for Evaluation Board CLC730057
17
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Product Description
(Continued)
CLC730057 Retimer Evaluation Board Material List
Item
Reference
Designator
1
U1
CLC016AJQ Retimer Chip
1
2
U2
74HC04 Hex Inv. 14 PIN SOIC
1
3
U3
4
VEE/VCC
5
Gnd
6
DDI, DDI, SDO,
SDO, SCO, SCO
Description
Qty
74HC00 Quad 2-Input Pos-Nand Gate
1
Banana Jack, Red, EF Johnson #108-0902-001
1
Banana Jack, Black, EF Johnson #108-0993-001
1
BNC PC Amphenol #31-5329-52RFX
6
7
C6
0.001 µF SMD Cap, Size 1206
1
8
C1, C2, C3, C4, C7,
C8, C12, C13
0.01 µF SMD Cap, Size 1206
8
4
9
C10, C11, CX, CZ
0.1 µF SMD Cap, Size 1206
10
CP
82 pF SMD Cap, Size 1206
1
11
C5, C9
6.8 µF SMD Cap, Tantalum Cap, Size 6032 Digikey #PCT3685
2
5 Position Dip Switch Grayhill #GH1216
1
12
SW1
13
D1, D2
14
DL4148-ND Switching Diode (1N4148 or equivalent)
2
RT0, RT1, RT2,
RT3
Sub-miniature PCB Mount LED Array PC084-GL5
1
15
CD, UNL
Single Sub-miniature PCB Mount LED PC080-RL5
2
16
RBW
499Ω SMD Resistor, Size 1206
1
17
R8–R12, R18, R19
10 kΩ SMD Resistor, Size 1206
7
18
R17
1 kΩ SMD Resistor, Size 1206
1
19
R13–R16
75Ω SMD Resistor, Size 1206
4
20
R3
2550Ω SMD 1% Resistor, Size 1206
1
21
R2
3480Ω SMD 1% Resistor, Size 1206
1
22
R1
5490Ω SMD 1% Resistor, Size 1206
1
23
R0
6810Ω SMD 1% Resistor, Size 1206
1
24
R4, R5, R6, R7
25
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Choose for input termination
4
Socket Digikey #A2141-ND
1
18
Product Description
(Continued)
The PC board plots consist of 4-layers depicting signal traces, power planes and ground planes for the CLC730057 evaluation
board. Layers not to scale.
DS100087-37
DS100087-38
DS100087-39
DS100087-40
DS100087-42
DS100087-41
19
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CLC016 Data Retiming PLL with Automatic Rate Selection
Physical Dimensions
inches (millimeters) unless otherwise noted
Order Number CLC016ACQ or CLC016AJQ
NS Package Number V28A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into
sonably expected to cause the failure of the life support
the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness.
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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