Altera CLK13P Stratix ii device handbook, volume 1 Datasheet

Stratix II Device Handbook, Volume 1
101 Innovation Drive
San Jose, CA 95134
www.altera.com
SII5V1-4.5
Copyright © 2011 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as
expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
ii
Altera Corporation
Contents
Chapter Revision Dates .......................................................................... vii
About this Handbook ................................................................................ i
How to Contact Altera ............................................................................................................................... i
Typographic Conventions ......................................................................................................................... i
Section I. Stratix II Device Family Data Sheet
Revision History ....................................................................................................................... Section I–1
Chapter 1. Introduction
Introduction ............................................................................................................................................ 1–1
Features ................................................................................................................................................... 1–1
Document Revision History ................................................................................................................. 1–6
Chapter 2. Stratix II Architecture
Functional Description .......................................................................................................................... 2–1
Logic Array Blocks ................................................................................................................................ 2–3
LAB Interconnects ............................................................................................................................ 2–4
LAB Control Signals ......................................................................................................................... 2–5
Adaptive Logic Modules ...................................................................................................................... 2–6
ALM Operating Modes ................................................................................................................... 2–9
Register Chain ................................................................................................................................. 2–20
Clear & Preset Logic Control ........................................................................................................ 2–22
MultiTrack Interconnect ..................................................................................................................... 2–22
TriMatrix Memory ............................................................................................................................... 2–28
Memory Block Size ......................................................................................................................... 2–29
Digital Signal Processing Block ......................................................................................................... 2–40
Modes of Operation ....................................................................................................................... 2–44
DSP Block Interface ........................................................................................................................ 2–44
PLLs & Clock Networks ..................................................................................................................... 2–48
Global & Hierarchical Clocking ................................................................................................... 2–48
Enhanced & Fast PLLs ................................................................................................................... 2–57
Enhanced PLLs ............................................................................................................................... 2–68
Fast PLLs .......................................................................................................................................... 2–69
I/O Structure ........................................................................................................................................ 2–69
Double Data Rate I/O Pins ........................................................................................................... 2–77
External RAM Interfacing ............................................................................................................. 2–81
Programmable Drive Strength ..................................................................................................... 2–83
Altera Corporation
iii
Contents
Stratix II Device Handbook, Volume 1
Open-Drain Output ........................................................................................................................ 2–84
Bus Hold .......................................................................................................................................... 2–84
Programmable Pull-Up Resistor .................................................................................................. 2–85
Advanced I/O Standard Support ................................................................................................ 2–85
On-Chip Termination .................................................................................................................... 2–89
MultiVolt I/O Interface ................................................................................................................. 2–93
High-Speed Differential I/O with DPA Support ............................................................................ 2–96
Dedicated Circuitry with DPA Support .................................................................................... 2–100
Fast PLL & Channel Layout ........................................................................................................ 2–102
Document Revision History ............................................................................................................. 2–104
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 JTAG Boundary-Scan Support ............................................................................... 3–1
SignalTap II Embedded Logic Analyzer ............................................................................................ 3–4
Configuration ......................................................................................................................................... 3–4
Operating Modes .............................................................................................................................. 3–5
Configuration Schemes ................................................................................................................... 3–7
Configuring Stratix II FPGAs with JRunner ............................................................................... 3–10
Programming Serial Configuration Devices with SRunner ..................................................... 3–10
Configuring Stratix II FPGAs with the MicroBlaster Driver ................................................... 3–11
PLL Reconfiguration ...................................................................................................................... 3–11
Temperature Sensing Diode (TSD) ................................................................................................... 3–11
Automated Single Event Upset (SEU) Detection ............................................................................ 3–13
Custom-Built Circuitry .................................................................................................................. 3–14
Software Interface ........................................................................................................................... 3–14
Document Revision History ............................................................................................................... 3–14
Chapter 4. Hot Socketing & Power-On Reset
Stratix II
Hot-Socketing Specifications ...............................................................................................................
Devices Can Be Driven Before Power-Up ....................................................................................
I/O Pins Remain Tri-Stated During Power-Up ...........................................................................
Signal Pins Do Not Drive the VCCIO, VCCINT or VCCPD Power Supplies ....................................
Hot Socketing Feature Implementation in Stratix II Devices ..........................................................
Power-On Reset Circuitry ....................................................................................................................
Document Revision History .................................................................................................................
4–1
4–2
4–2
4–2
4–3
4–5
4–6
Chapter 5. DC & Switching Characteristics
Operating Conditions ........................................................................................................................... 5–1
Absolute Maximum Ratings ........................................................................................................... 5–1
Recommended Operating Conditions .......................................................................................... 5–2
DC Electrical Characteristics .......................................................................................................... 5–3
I/O Standard Specifications ........................................................................................................... 5–4
Bus Hold Specifications ................................................................................................................. 5–17
On-Chip Termination Specifications ........................................................................................... 5–17
Pin Capacitance .............................................................................................................................. 5–19
Power Consumption ........................................................................................................................... 5–20
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Altera Corporation
Contents
Contents
Timing Model ....................................................................................................................................... 5–20
Preliminary & Final Timing .......................................................................................................... 5–20
I/O Timing Measurement Methodology .................................................................................... 5–21
Performance .................................................................................................................................... 5–27
Internal Timing Parameters .......................................................................................................... 5–34
Stratix II Clock Timing Parameters .............................................................................................. 5–41
Clock Network Skew Adders ....................................................................................................... 5–50
IOE Programmable Delay ............................................................................................................. 5–51
Default Capacitive Loading of Different I/O Standards .......................................................... 5–52
I/O Delays ....................................................................................................................................... 5–54
Maximum Input & Output Clock Toggle Rate .......................................................................... 5–66
Duty Cycle Distortion ......................................................................................................................... 5–77
DCD Measurement Techniques ................................................................................................... 5–78
High-Speed I/O Specifications .......................................................................................................... 5–87
PLL Timing Specifications .................................................................................................................. 5–91
External Memory Interface Specifications ....................................................................................... 5–94
JTAG Timing Specifications ............................................................................................................... 5–96
Document Revision History ............................................................................................................... 5–97
Chapter 6. Reference & Ordering Information
Software ..................................................................................................................................................
Device Pin-Outs .....................................................................................................................................
Ordering Information ...........................................................................................................................
Document Revision History .................................................................................................................
Altera Corporation
6–1
6–1
6–1
6–2
v
Contents
vi
Stratix II Device Handbook, Volume 1
Altera Corporation
Chapter Revision Dates
The chapters in this book, Stratix II Device Handbook, Volume 1, were revised on the following dates.
Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. Introduction
Revised:
Part number:
May 2007
SII51001-4.2
Chapter 2. Stratix II Architecture
Revised:
May 2007
Part number: SII51002-4.3
Chapter 3. Configuration & Testing
Revised:
May 2007
Part number: SII51003-4.2
Chapter 4. Hot Socketing & Power-On Reset
Revised:
May 2007
Part number: SII51004-3.2
Chapter 5. DC & Switching Characteristics
Revised:
April 2011
Part number: SII51005-4.5
Chapter 6. Reference & Ordering Information
Revised:
April 2011
Part number: SII51006-2.2
Altera Corporation
vii
Chapter Revision Dates
viii
Stratix II Device Handbook, Volume 1
Altera Corporation
About this Handbook
This handbook provides comprehensive information about the Altera®
Stratix® II family of devices.
How to Contact
Altera
For the most up-to-date information about Altera products, refer to the
following table.
Contact (1)
Contact
Method
Address
Technical support
Website
www.altera.com/support
Technical training
Website
www.altera.com/training
Email
[email protected]
Product literature
Email
www.altera.com/literature
Altera literature services
Website
[email protected]
Non-technical support (General) Email
(Software Licensing)
Email
[email protected]
[email protected]
Note to table:
(1)
Typographic
Conventions
Visual Cue
You can also contact your local Altera sales office or sales representative.
This document uses the typographic conventions shown below.
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold
type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial Capital
Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Altera Corporation
i
Preliminary
Typographic Conventions
Visual Cue
Italic type
Stratix II Device Handbook, Volume 1
Meaning
Internal timing parameters and variables are shown in italic type.
Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and
a., b., c., etc.
Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
●
•
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
c
The caution indicates required information that needs special consideration and
understanding and should be read prior to starting or continuing with the
procedure or process.
w
The warning indicates information that should be read prior to starting or
continuing the procedure or processes
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
ii
Preliminary
Altera Corporation
Section I. Stratix II Device
Family Data Sheet
This section provides the data sheet specifications for Stratix® II devices.
This section contains feature definitions of the internal architecture,
configuration and JTAG boundary-scan testing information, DC
operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix II devices.
This section contains the following chapters:
Revision History
Altera Corporation
■
Chapter 1, Introduction
■
Chapter 2, Stratix II Architecture
■
Chapter 3, Configuration & Testing
■
Chapter 4, Hot Socketing & Power-On Reset
■
Chapter 5, DC & Switching Characteristics
■
Chapter 6, Reference & Ordering Information
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section I–1
Stratix II Device Family Data Sheet
Section I–2
Stratix II Device Handbook, Volume 1
Altera Corporation
1. Introduction
SII51001-4.2
Introduction
The Stratix® II FPGA family is based on a 1.2-V, 90-nm, all-layer copper
SRAM process and features a new logic structure that maximizes
performance, and enables device densities approaching 180,000
equivalent logic elements (LEs). Stratix II devices offer up to 9 Mbits of
on-chip, TriMatrix™ memory for demanding, memory intensive
applications and has up to 96 DSP blocks with up to 384 (18-bit × 18-bit)
multipliers for efficient implementation of high performance filters and
other DSP functions. Various high-speed external memory interfaces are
supported, including double data rate (DDR) SDRAM and DDR2
SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data
rate (SDR) SDRAM. Stratix II devices support various I/O standards
along with support for 1-gigabit per second (Gbps) source synchronous
signaling with DPA circuitry. Stratix II devices offer a complete clock
management solution with internal clock frequency of up to 550 MHz
and up to 12 phase-locked loops (PLLs). Stratix II devices are also the
industry’s first FPGAs with the ability to decrypt a configuration
bitstream using the Advanced Encryption Standard (AES) algorithm to
protect designs.
Features
The Stratix II family offers the following features:
■
■
■
■
■
■
■
■
Altera Corporation
May 2007
15,600 to 179,400 equivalent LEs; see Table 1–1
New and innovative adaptive logic module (ALM), the basic
building block of the Stratix II architecture, maximizes performance
and resource usage efficiency
Up to 9,383,040 RAM bits (1,172,880 bytes) available without
reducing logic resources
TriMatrix memory consisting of three RAM block sizes to implement
true dual-port memory and first-in first-out (FIFO) buffers
High-speed DSP blocks provide dedicated implementation of
multipliers (at up to 450 MHz), multiply-accumulate functions, and
finite impulse response (FIR) filters
Up to 16 global clocks with 24 clocking resources per device region
Clock control blocks support dynamic clock network enable/disable,
which allows clock networks to power down to reduce power
consumption in user mode
Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device
provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication
and phase shifting
1–1
Features
■
■
■
■
■
■
■
Support for numerous single-ended and differential I/O standards
High-speed differential I/O support with DPA circuitry for 1-Gbps
performance
Support for high-speed networking and communications bus
standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY
Level 4), HyperTransport™ technology, and SFI-4
Support for high-speed external memory, including DDR and DDR2
SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM
Support for multiple intellectual property megafunctions from
Altera MegaCore® functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
Support for design security using configuration bitstream
encryption
Support for remote configuration updates
Table 1–1. Stratix II FPGA Family Features
Feature
EP2S15
EP2S30
EP2S60
EP2S90
EP2S130
EP2S180
ALMs
6,240
13,552
24,176
36,384
53,016
71,760
Adaptive look-up tables (ALUTs) (1)
12,480
27,104
48,352
72,768
106,032
143,520
Equivalent LEs (2)
15,600
33,880
60,440
90,960
132,540
179,400
M512 RAM blocks
104
202
329
488
699
930
M4K RAM blocks
78
144
255
408
609
768
M-RAM blocks
0
1
2
4
6
9
Total RAM bits
419,328
1,369,728
2,544,192
4,520,488
6,747,840
9,383,040
DSP blocks
12
16
36
48
63
96
18-bit × 18-bit multipliers (3)
48
64
144
192
252
384
Enhanced PLLs
2
2
4
4
4
4
Fast PLLs
Maximum user I/O pins
4
4
8
8
8
8
366
500
718
902
1,126
1,170
Notes to Table 1–1:
(1)
(2)
(3)
One ALM contains two ALUTs. The ALUT is the cell used in the Quartus® II software for logic synthesis.
This is the equivalent number of LEs in a Stratix device (four-input LUT-based architecture).
These multipliers are implemented using the DSP blocks.
1–2
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Introduction
Stratix II devices are available in space-saving FineLine BGA® packages
(see Tables 1–2 and 1–3).
Table 1–2. Stratix II Package Options & I/O Pin Counts
Device
484-Pin
FineLine BGA
484-Pin
Hybrid
FineLine
BGA
672-Pin
FineLine
BGA
EP2S15
342
366
EP2S30
342
500
EP2S60 (3)
334
EP2S90 (3)
Notes (1), (2)
780-Pin
FineLine
BGA
492
308
EP2S130 (3)
1,020-Pin
FineLine BGA
1,508-Pin
FineLine BGA
718
534
758
902
534
742
1,126
742
1,170
EP2S180 (3)
Notes to Table 1–2:
(1)
(2)
(3)
All I/O pin counts include eight dedicated clock input pins (clk1p, clk1n, clk3p, clk3n, clk9p, clk9n,
clk11p, and clk11n) that can be used for data inputs.
The Quartus II software I/O pin counts include one additional pin, PLL_ENA, which is not available as generalpurpose I/O pins. The PLL_ENA pin can only be used to enable the PLLs within the device.
The I/O pin counts for the EP2S60, EP2S90, EP2S130, and EP2S180 devices in the 1020-pin and 1508-pin packages
include eight dedicated fast PLL clock inputs (FPLL7CLKp/n, FPLL8CLKp/n, FPLL9CLKp/n, and
FPLL10CLKp/n) that can be used for data inputs.
Table 1–3. Stratix II FineLine BGA Package Sizes
Dimension
Pitch (mm)
Area (mm2)
Length × width
(mm × mm)
484 Pin
484-Pin
Hybrid
672 Pin
780 Pin
1,020 Pin
1,508 Pin
1.00
1.00
1.00
1.00
1.00
1.00
529
729
729
841
1,089
1,600
23 × 23
27 × 27
27 × 27
29 × 29
33 × 33
40 × 40
All Stratix II devices support vertical migration within the same package
(for example, you can migrate between the EP2S15, EP2S30, and EP2S60
devices in the 672-pin FineLine BGA package). Vertical migration means
that you can migrate to devices whose dedicated pins, configuration pins,
and power pins are the same for a given package across device densities.
To ensure that a board layout supports migratable densities within one
package offering, enable the applicable vertical migration path within the
Quartus II software (Assignments menu > Device > Migration Devices).
Altera Corporation
May 2007
1–3
Stratix II Device Handbook, Volume 1
Features
After compilation, check the information messages for a full list of I/O,
DQ, LVDS, and other pins that are not available because of the selected
migration path.
Table 1–4 lists the Stratix II device package offerings and shows the total
number of non-migratable user I/O pins when migrating from one
density device to a larger density device. Additional I/O pins may not be
migratable if migrating from the larger device to the smaller density
device.
1
When moving from one density to a larger density, the larger
density device may have fewer user I/O pins. The larger device
requires more power and ground pins to support the additional
logic within the device. Use the Quartus II Pin Planner to
determine which user I/O pins are migratable between the two
devices.
Table 1–4. Total Number of Non-Migratable I/O Pins for Stratix II Vertical Migration Paths
Vertical Migration
Path
484-Pin
FineLine BGA
672-Pin
FineLine BGA
EP2S15 to EP2S30
0 (1)
0
EP2S15 to EP2S60
8 (1)
0
EP2S30 to EP2S60
8 (1)
8
780-Pin
FineLine BGA
1020-Pin
FineLine BGA
EP2S60 to EP2S90
0
EP2S60 to EP2S130
0
EP2S60 to EP2S180
0
0 (1)
EP2S90 to EP2S130
1508-Pin
FineLine BGA
16
17
EP2S90 to EP2S180
16
0
EP2S130 to EP2S180
0
0
Note to Table 1–4:
(1)
Some of the DQ/DQS pins are not migratable. Refer to the Quartus II software information messages for more
detailed information.
1
f
To determine if your user I/O assignments are correct, run the
I/O Assignment Analysis command in the Quartus II software
(Processing > Start > Start I/O Assignment Analysis).
Refer to the I/O Management chapter in volume 2 of the Quartus II
Handbook for more information on pin migration.
1–4
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Introduction
Stratix II devices are available in up to three speed grades, -3, -4, and -5,
with -3 being the fastest. Table 1–5 shows Stratix II device speed-grade
offerings.
Table 1–5. Stratix II Device Speed Grades
484-Pin
Hybrid
FineLine
BGA
Device
Temperature
Grade
484-Pin
FineLine
BGA
EP2S15
Commercial
-3, -4, -5
Industrial
-4
-4
EP2S30
Commercial
-3, -4, -5
-3, -4, -5
Industrial
-4
-4
EP2S60
Commercial
-3, -4, -5
-3, -4, -5
Industrial
-4
EP2S90
Commercial
EP2S130
Commercial
Industrial
-4
-4
EP2S180
Commercial
-3, -4, -5
-3, -4, -5
Industrial
-4
-4
672-Pin
FineLine
BGA
780-Pin
FineLine
BGA
1,508-Pin
FineLine
BGA
-3, -4, -5
-3, -4, -5
-4
-4, -5
-4
-4, -5
-3, -4, -5
-4
-4
-4, -5
-3, -4, -5
-3, -4, -5
Industrial
Altera Corporation
May 2007
1,020-Pin
FineLine
BGA
-3, -4, -5
1–5
Stratix II Device Handbook, Volume 1
Document Revision History
Document
Revision History
Table 1–6 shows the revision history for this chapter.
Table 1–6. Document Revision History
Date and
Document
Version
Changes Made
May 2007, v4.2
Moved Document Revision History to the end of the
chapter.
April 2006, v4.1
●
●
●
December 2005,
v4.0
●
July 2005, v3.1
●
●
●
May 2005, v3.0
●
●
Summary of Changes
—
Updated “Features” section.
Removed Note 4 from Table 1–2.
Updated Table 1–4.
—
Updated Tables 1–2, 1–4, and 1–5.
Updated Figure 2–43.
—
Added vertical migration information, including
Table 1–4.
Updated Table 1–5.
—
Updated “Features” section.
Updated Table 1–2.
—
March 2005,
v2.1
Updated “Introduction” and “Features” sections.
—
January 2005,
v2.0
Added note to Table 1–2.
—
October 2004,
v1.2
Updated Tables 1–2, 1–3, and 1–5.
—
July 2004, v1.1
●
Updated Tables 1–1 and 1–2.
Updated “Features” section.
—
●
February 2004,
v1.0
Added document to the Stratix II Device Handbook.
1–6
Stratix II Device Handbook, Volume 1
—
Altera Corporation
May 2007
2. Stratix II Architecture
SII51002-4.3
Functional
Description
Stratix® II devices contain a two-dimensional row- and column-based
architecture to implement custom logic. A series of column and row
interconnects of varying length and speed provides signal interconnects
between logic array blocks (LABs), memory block structures (M512 RAM,
M4K RAM, and M-RAM blocks), and digital signal processing (DSP)
blocks.
Each LAB consists of eight adaptive logic modules (ALMs). An ALM is
the Stratix II device family’s basic building block of logic providing
efficient implementation of user logic functions. LABs are grouped into
rows and columns across the device.
M512 RAM blocks are simple dual-port memory blocks with 512 bits plus
parity (576 bits). These blocks provide dedicated simple dual-port or
single-port memory up to 18-bits wide at up to 500 MHz. M512 blocks are
grouped into columns across the device in between certain LABs.
M4K RAM blocks are true dual-port memory blocks with 4K bits plus
parity (4,608 bits). These blocks provide dedicated true dual-port, simple
dual-port, or single-port memory up to 36-bits wide at up to 550 MHz.
These blocks are grouped into columns across the device in between
certain LABs.
M-RAM blocks are true dual-port memory blocks with 512K bits plus
parity (589,824 bits). These blocks provide dedicated true dual-port,
simple dual-port, or single-port memory up to 144-bits wide at up to
420 MHz. Several M-RAM blocks are located individually in the device's
logic array.
DSP blocks can implement up to either eight full-precision 9 × 9-bit
multipliers, four full-precision 18 × 18-bit multipliers, or one
full-precision 36 × 36-bit multiplier with add or subtract features. The
DSP blocks support Q1.15 format rounding and saturation in the
multiplier and accumulator stages. These blocks also contain shift
registers for digital signal processing applications, including finite
impulse response (FIR) and infinite impulse response (IIR) filters. DSP
blocks are grouped into columns across the device and operate at up to
450 MHz.
Altera Corporation
May 2007
2–1
Functional Description
Each Stratix II device I/O pin is fed by an I/O element (IOE) located at
the end of LAB rows and columns around the periphery of the device.
I/O pins support numerous single-ended and differential I/O standards.
Each IOE contains a bidirectional I/O buffer and six registers for
registering input, output, and output-enable signals. When used with
dedicated clocks, these registers provide exceptional performance and
interface support with external memory devices such as DDR and DDR2
SDRAM, RLDRAM II, and QDR II SRAM devices. High-speed serial
interface channels with dynamic phase alignment (DPA) support data
transfer at up to 1 Gbps using LVDS or HyperTransportTM technology I/O
standards.
Figure 2–1 shows an overview of the Stratix II device.
Figure 2–1. Stratix II Block Diagram
M4K RAM Blocks
DSP Blocks for
for True Dual-Port
Multiplication and Full
Memory & Other Embedded
Implementation of FIR Filters Memory Functions
M512 RAM Blocks for
Dual-Port Memory, Shift
Registers, & FIFO Buffers
IOEs Support DDR, PCI, PCI-X,
SSTL-3, SSTL-2, HSTL-1, HSTL-2,
LVDS, HyperTransport & other
I/O Standards
IOEs
IOEs
IOEs
IOEs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
IOEs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
LABs
M-RAM Block
DSP
Block
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
The number of M512 RAM, M4K RAM, and DSP blocks varies by device
along with row and column numbers and M-RAM blocks. Table 2–1 lists
the resources available in Stratix II devices.
Table 2–1. Stratix II Device Resources
Device
M512 RAM
Columns/Blocks
M4K RAM
Columns/Blocks
M-RAM
Blocks
DSP Block
Columns/Blocks
LAB
Columns
LAB Rows
EP2S15
4 / 104
3 / 78
0
2 / 12
30
26
EP2S30
6 / 202
4 / 144
1
2 / 16
49
36
EP2S60
7 / 329
5 / 255
2
3 / 36
62
51
EP2S90
8 / 488
6 / 408
4
3 / 48
71
68
EP2S130
9 / 699
7 / 609
6
3 / 63
81
87
EP2S180
11 / 930
8 / 768
9
4 / 96
100
96
Logic Array
Blocks
Altera Corporation
May 2007
Each LAB consists of eight ALMs, carry chains, shared arithmetic chains,
LAB control signals, local interconnect, and register chain connection
lines. The local interconnect transfers signals between ALMs in the same
LAB. Register chain connections transfer the output of an ALM register to
the adjacent ALM register in an LAB. The Quartus® II Compiler places
associated logic in an LAB or adjacent LABs, allowing the use of local,
shared arithmetic chain, and register chain connections for performance
and area efficiency. Figure 2–2 shows the Stratix II LAB structure.
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Stratix II Device Handbook, Volume 1
Logic Array Blocks
Figure 2–2. Stratix II LAB Structure
Row Interconnects of
Variable Speed & Length
ALMs
Direct link
interconnect from
adjacent block
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Direct link
interconnect to
adjacent block
Local Interconnect
LAB
Local Interconnect is Driven
from Either Side by Columns & LABs,
& from Above by Rows
Column Interconnects of
Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive ALMs in the same LAB. It is driven
by column and row interconnects and ALM outputs in the same LAB.
Neighboring LABs, M512 RAM blocks, M4K RAM blocks, M-RAM
blocks, or DSP blocks from the left and right can also drive an LAB's local
interconnect through the direct link connection. The direct link
connection feature minimizes the use of row and column interconnects,
providing higher performance and flexibility. Each ALM can drive
24 ALMs through fast local and direct link interconnects. Figure 2–3
shows the direct link connection.
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–3. Direct Link Connection
Direct link interconnect from
left LAB, TriMatrix memory
block, DSP block, or IOE output
Direct link interconnect from
right LAB, TriMatrix memory
block, DSP block, or IOE output
ALMs
Direct link
interconnect
to right
Direct link
interconnect
to left
Local
Interconnect
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its ALMs.
The control signals include three clocks, three clock enables, two
asynchronous clears, synchronous clear, asynchronous preset/load, and
synchronous load control signals. This gives a maximum of 11 control
signals at a time. Although synchronous load and clear signals are
generally used when implementing counters, they can also be used with
other functions.
Each LAB can use three clocks and three clock enable signals. However,
there can only be up to two unique clocks per LAB, as shown in the LAB
control signal generation circuit in Figure 2–4. Each LAB's clock and clock
enable signals are linked. For example, any ALM in a particular LAB
using the labclk1 signal also uses labclkena1. If the LAB uses both
the rising and falling edges of a clock, it also uses two LAB-wide clock
signals. De-asserting the clock enable signal turns off the corresponding
LAB-wide clock.
Each LAB can use two asynchronous clear signals and an asynchronous
load/preset signal. By default, the Quartus II software uses a NOT gate
push-back technique to achieve preset. If you disable the NOT gate
push-up option or assign a given register to power up high using the
Quartus II software, the preset is achieved using the asynchronous load
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
signal with asynchronous load data input tied high. When the
asynchronous load/preset signal is used, the labclkena0 signal is no
longer available.
The LAB row clocks [5..0] and LAB local interconnect generate the
LAB-wide control signals. The MultiTrackTM interconnect's inherent low
skew allows clock and control signal distribution in addition to data.
Figure 2–4 shows the LAB control signal generation circuit.
Figure 2–4. LAB-Wide Control Signals
There are two unique
clock signals per LAB.
6
Dedicated Row LAB Clocks
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0
labclk1
labclkena0
or asyncload
or labpreset
Adaptive Logic
Modules
labclk2
labclkena1
labclkena2
labclr1
syncload
labclr0
synclr
The basic building block of logic in the Stratix II architecture, the adaptive
logic module (ALM), provides advanced features with efficient logic
utilization. Each ALM contains a variety of look-up table (LUT)-based
resources that can be divided between two adaptive LUTs (ALUTs). With
up to eight inputs to the two ALUTs, one ALM can implement various
combinations of two functions. This adaptability allows the ALM to be
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Stratix II Device Handbook, Volume 1
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May 2007
Stratix II Architecture
completely backward-compatible with four-input LUT architectures. One
ALM can also implement any function of up to six inputs and certain
seven-input functions.
In addition to the adaptive LUT-based resources, each ALM contains two
programmable registers, two dedicated full adders, a carry chain, a
shared arithmetic chain, and a register chain. Through these dedicated
resources, the ALM can efficiently implement various arithmetic
functions and shift registers. Each ALM drives all types of interconnects:
local, row, column, carry chain, shared arithmetic chain, register chain,
and direct link interconnects. Figure 2–5 shows a high-level block
diagram of the Stratix II ALM while Figure 2–6 shows a detailed view of
all the connections in the ALM.
Figure 2–5. High-Level Block Diagram of the Stratix II ALM
carry_in
shared_arith_in
reg_chain_in
To general or
local routing
dataf0
adder0
datae0
D
dataa
datab
datac
datad
Q
To general or
local routing
reg0
Combinational
Logic
adder1
D
Q
datae1
To general or
local routing
reg1
dataf1
To general or
local routing
carry_out
shared_arith_out
Altera Corporation
May 2007
reg_chain_out
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Stratix II Device Handbook, Volume 1
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Stratix II Device Handbook, Volume 1
datae0
datac
Local
Interconnect
Local
datad
datae1
Local
Interconnect
Local
Interconnect
dataf1
datab
Local
Interconnect
Local
Interconnect
dataa
Local
Interconnect
Interconnect
dataf0
Local
Interconnect
3-Input
LUT
3-Input
LUT
4-Input
LUT
3-Input
LUT
3-Input
LUT
4-Input
LUT
shared_arith_out
shared_arith_in
carry_out
carry_in
VCC
sclr
syncload
reg_chain_out
reg_chain_in
clk[2..0]
aclr[1..0]
ENA
CLRN
PRN/ALD
D
Q
ADATA
ENA
CLRN
PRN/ALD
D
Q
ADATA
asyncload
ena[2..0]
Local
Interconnect
Row, column &
direct link routing
Row, column &
direct link routing
Local
Interconnect
Row, column &
direct link routing
Row, column &
direct link routing
Adaptive Logic Modules
Figure 2–6. Stratix II ALM Details
Altera Corporation
May 2007
Stratix II Architecture
One ALM contains two programmable registers. Each register has data,
clock, clock enable, synchronous and asynchronous clear, asynchronous
load data, and synchronous and asynchronous load/preset inputs.
Global signals, general-purpose I/O pins, or any internal logic can drive
the register's clock and clear control signals. Either general-purpose I/O
pins or internal logic can drive the clock enable, preset, asynchronous
load, and asynchronous load data. The asynchronous load data input
comes from the datae or dataf input of the ALM, which are the same
inputs that can be used for register packing. For combinational functions,
the register is bypassed and the output of the LUT drives directly to the
outputs of the ALM.
Each ALM has two sets of outputs that drive the local, row, and column
routing resources. The LUT, adder, or register output can drive these
output drivers independently (see Figure 2–6). For each set of output
drivers, two ALM outputs can drive column, row, or direct link routing
connections, and one of these ALM outputs can also drive local
interconnect resources. This allows the LUT or adder to drive one output
while the register drives another output. This feature, called register
packing, improves device utilization because the device can use the
register and the combinational logic for unrelated functions. Another
special packing mode allows the register output to feed back into the LUT
of the same ALM so that the register is packed with its own fan-out LUT.
This provides another mechanism for improved fitting. The ALM can also
drive out registered and unregistered versions of the LUT or adder
output.
f
See the Performance & Logic Efficiency Analysis of Stratix II Devices White
Paper for more information on the efficiencies of the Stratix II ALM and
comparisons with previous architectures.
ALM Operating Modes
The Stratix II ALM can operate in one of the following modes:
■
■
■
■
Normal mode
Extended LUT mode
Arithmetic mode
Shared arithmetic mode
Each mode uses ALM resources differently. In each mode, eleven
available inputs to the ALM--the eight data inputs from the LAB local
interconnect; carry-in from the previous ALM or LAB; the shared
arithmetic chain connection from the previous ALM or LAB; and the
register chain connection--are directed to different destinations to
implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, asynchronous preset/load, synchronous clear,
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
synchronous load, and clock enable control for the register. These LABwide signals are available in all ALM modes. See the “LAB Control
Signals” section for more information on the LAB-wide control signals.
The Quartus II software and supported third-party synthesis tools, in
conjunction with parameterized functions such as library of
parameterized modules (LPM) functions, automatically choose the
appropriate mode for common functions such as counters, adders,
subtractors, and arithmetic functions. If required, you can also create
special-purpose functions that specify which ALM operating mode to use
for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and
combinational functions. In this mode, up to eight data inputs from the
LAB local interconnect are inputs to the combinational logic. The normal
mode allows two functions to be implemented in one Stratix II ALM, or
an ALM to implement a single function of up to six inputs. The ALM can
support certain combinations of completely independent functions and
various combinations of functions which have common inputs.
Figure 2–7 shows the supported LUT combinations in normal mode.
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–7. ALM in Normal Mode Note (1)
dataf0
datae0
datac
dataa
4-Input
LUT
combout0
datab
datad
datae1
dataf1
4-Input
LUT
combout1
dataf0
datae0
datac
dataa
datab
5-Input
LUT
combout0
datad
datae1
dataf1
dataf0
datae0
datac
dataa
datab
datad
datae1
dataf1
3-Input
LUT
5-Input
LUT
combout0
5-Input
LUT
combout1
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
combout0
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
combout0
6-Input
LUT
combout1
datad
datae1
dataf1
combout1
5-Input
LUT
4-Input
LUT
dataf0
datae0
datac
dataa
datab
combout0
combout1
datae1
dataf1
Note to Figure 2–7:
(1)
Combinations of functions with fewer inputs than those shown are also supported. For example, combinations of
functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, etc.
The normal mode provides complete backward compatibility with fourinput LUT architectures. Two independent functions of four inputs or less
can be implemented in one Stratix II ALM. In addition, a five-input
function and an independent three-input function can be implemented
without sharing inputs.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
For the packing of two five-input functions into one ALM, the functions
must have at least two common inputs. The common inputs are dataa
and datab. The combination of a four-input function with a five-input
function requires one common input (either dataa or datab).
In the case of implementing two six-input functions in one ALM, four
inputs must be shared and the combinational function must be the same.
For example, a 4 × 2 crossbar switch (two 4-to-1 multiplexers with
common inputs and unique select lines) can be implemented in one ALM,
as shown in Figure 2–8. The shared inputs are dataa, datab, datac, and
datad, while the unique select lines are datae0 and dataf0 for
function0, and datae1 and dataf1 for function1. This crossbar
switch consumes four LUTs in a four-input LUT-based architecture.
Figure 2–8. 4 × 2 Crossbar Switch Example
4 × 2 Crossbar Switch
sel0[1..0]
inputa
inputb
out0
inputc
inputd
Implementation in 1 ALM
dataf0
datae0
dataa
datab
datac
datad
Six-Input
LUT
(Function0)
combout0
Six-Input
LUT
(Function1)
combout1
out1
sel1[1..0]
datae1
dataf1
In a sparsely used device, functions that could be placed into one ALM
may be implemented in separate ALMs. The Quartus II Compiler spreads
a design out to achieve the best possible performance. As a device begins
to fill up, the Quartus II software automatically utilizes the full potential
of the Stratix II ALM. The Quartus II Compiler automatically searches for
functions of common inputs or completely independent functions to be
placed into one ALM and to make efficient use of the device resources. In
addition, you can manually control resource usage by setting location
assignments.
Any six-input function can be implemented utilizing inputs dataa,
datab, datac, datad, and either datae0 and dataf0 or datae1 and
dataf1. If datae0 and dataf0 are utilized, the output is driven to
register0, and/or register0 is bypassed and the data drives out to
the interconnect using the top set of output drivers (see Figure 2–9). If
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
datae1 and dataf1 are utilized, the output drives to register1
and/or bypasses register1 and drives to the interconnect using the
bottom set of output drivers. The Quartus II Compiler automatically
selects the inputs to the LUT. Asynchronous load data for the register
comes from the datae or dataf input of the ALM. ALMs in normal
mode support register packing.
Figure 2–9. 6-Input Function in Normal Mode Notes (1), (2)
dataf0
datae0
dataa
datab
datac
datad
To general or
local routing
6-Input
LUT
D
Q
To general or
local routing
reg0
datae1
dataf1
(2)
D
These inputs are available for register packing.
Q
To general or
local routing
reg1
Notes to Figure 2–9:
(1)
(2)
If datae1 and dataf1 are used as inputs to the six-input function, then datae0
and dataf0 are available for register packing.
The dataf1 input is available for register packing only if the six-input function is
un-registered.
Extended LUT Mode
The extended LUT mode is used to implement a specific set of
seven-input functions. The set must be a 2-to-1 multiplexer fed by two
arbitrary five-input functions sharing four inputs. Figure 2–10 shows the
template of supported seven-input functions utilizing extended LUT
mode. In this mode, if the seven-input function is unregistered, the
unused eighth input is available for register packing.
Functions that fit into the template shown in Figure 2–10 occur naturally
in designs. These functions often appear in designs as “if-else” statements
in Verilog HDL or VHDL code.
Altera Corporation
May 2007
2–13
Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
Figure 2–10. Template for Supported Seven-Input Functions in Extended LUT Mode
datae0
datac
dataa
datab
datad
dataf0
5-Input
LUT
To general or
local routing
combout0
D
5-Input
LUT
Q
To general or
local routing
reg0
datae1
dataf1
(1)
This input is available
for register packing.
Note to Figure 2–10:
(1)
If the seven-input function is unregistered, the unused eighth input is available for register packing. The second
register, reg1, is not available.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, counters,
accumulators, wide parity functions, and comparators. An ALM in
arithmetic mode uses two sets of two four-input LUTs along with two
dedicated full adders. The dedicated adders allow the LUTs to be
available to perform pre-adder logic; therefore, each adder can add the
output of two four-input functions. The four LUTs share the dataa and
datab inputs. As shown in Figure 2–11, the carry-in signal feeds to
adder0, and the carry-out from adder0 feeds to carry-in of adder1. The
carry-out from adder1 drives to adder0 of the next ALM in the LAB.
ALMs in arithmetic mode can drive out registered and/or unregistered
versions of the adder outputs.
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–11. ALM in Arithmetic Mode
carry_in
adder0
datae0
4-Input
LUT
To general or
local routing
D
dataf0
datac
datab
dataa
Q
To general or
local routing
reg0
4-Input
LUT
adder1
datad
datae1
4-Input
LUT
To general or
local routing
D
4-Input
LUT
Q
To general or
local routing
reg1
dataf1
carry_out
While operating in arithmetic mode, the ALM can support simultaneous
use of the adder's carry output along with combinational logic outputs. In
this operation, the adder output is ignored. This usage of the adder with
the combinational logic output provides resource savings of up to 50% for
functions that can use this ability. An example of such functionality is a
conditional operation, such as the one shown in Figure 2–12. The
equation for this example is:
R = (X < Y) ? Y : X
To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If
‘X’ is less than ‘Y,’ the carry_out signal is ‘1.’ The carry_out signal is
fed to an adder where it drives out to the LAB local interconnect. It then
feeds to the LAB-wide syncload signal. When asserted, syncload
selects the syncdata input. In this case, the data ‘Y’ drives the
syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the
syncload signal is de-asserted and ‘X’ drives the data port of the
registers.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
Figure 2–12. Conditional Operation Example
Adder output
is not used.
ALM 1
X[0]
Comb &
Adder
Logic
Y[0]
X[0]
D
R[0]
To general or
local routing
R[1]
To general or
local routing
R[2]
To general or
local routing
Q
reg0
syncdata
syncload
X[1]
Comb &
Adder
Logic
Y[1]
X[1]
D
Q
reg1
syncload
Carry Chain
ALM 2
X[2]
Y[2]
Comb &
Adder
Logic
X[2]
D
Q
reg0
syncload
Comb &
Adder
Logic
carry_out
To local routing &
then to LAB-wide
syncload
The arithmetic mode also offers clock enable, counter enable,
synchronous up/down control, add/subtract control, synchronous clear,
synchronous load. The LAB local interconnect data inputs generate the
clock enable, counter enable, synchronous up/down and add/subtract
control signals. These control signals are good candidates for the inputs
that are shared between the four LUTs in the ALM. The synchronous clear
and synchronous load options are LAB-wide signals that affect all
registers in the LAB. The Quartus II software automatically places any
registers that are not used by the counter into other LABs.
Carry Chain
The carry chain provides a fast carry function between the dedicated
adders in arithmetic or shared arithmetic mode. Carry chains can begin in
either the first ALM or the fifth ALM in an LAB. The final carry-out signal
is routed to an ALM, where it is fed to local, row, or column interconnects.
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May 2007
Stratix II Architecture
The Quartus II Compiler automatically creates carry chain logic during
design processing, or you can create it manually during design entry.
Parameterized functions such as LPM functions automatically take
advantage of carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 16 (8 ALMs in
arithmetic or shared arithmetic mode) by linking LABs together
automatically. For enhanced fitting, a long carry chain runs vertically
allowing fast horizontal connections to TriMatrix memory and DSP
blocks. A carry chain can continue as far as a full column.
To avoid routing congestion in one small area of the device when a high
fan-in arithmetic function is implemented, the LAB can support carry
chains that only utilize either the top half or the bottom half of the LAB
before connecting to the next LAB. This leaves the other half of the ALMs
in the LAB available for implementing narrower fan-in functions in
normal mode. Carry chains that use the top four ALMs in the first LAB
carry into the top half of the ALMs in the next LAB within the column.
Carry chains that use the bottom four ALMs in the first LAB carry into the
bottom half of the ALMs in the next LAB within the column. Every other
column of LABs is top-half bypassable, while the other LAB columns are
bottom-half bypassable.
See the “MultiTrack Interconnect” on page 2–22 section for more
information on carry chain interconnect.
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a three-input add. In
this mode, the ALM is configured with four 4-input LUTs. Each LUT
either computes the sum of three inputs or the carry of three inputs. The
output of the carry computation is fed to the next adder (either to adder1
in the same ALM or to adder0 of the next ALM in the LAB) via a
dedicated connection called the shared arithmetic chain. This shared
arithmetic chain can significantly improve the performance of an adder
tree by reducing the number of summation stages required to implement
an adder tree. Figure 2–13 shows the ALM in shared arithmetic mode.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
Figure 2–13. ALM in Shared Arithmetic Mode
shared_arith_in
carry_in
4-Input
LUT
To general or
local routing
D
datae0
datac
datab
dataa
datad
datae1
Q
To general or
local routing
reg0
4-Input
LUT
4-Input
LUT
To general or
local routing
D
4-Input
LUT
Q
To general or
local routing
reg1
carry_out
shared_arith_out
Note to Figure 2–13:
(1)
Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
Adder trees can be found in many different applications. For example, the
summation of the partial products in a logic-based multiplier can be
implemented in a tree structure. Another example is a correlator function
that can use a large adder tree to sum filtered data samples in a given time
frame to recover or to de-spread data which was transmitted utilizing
spread spectrum technology.
An example of a three-bit add operation utilizing the shared arithmetic
mode is shown in Figure 2–14. The partial sum (S[2..0]) and the
partial carry (C[2..0]) is obtained using the LUTs, while the result
(R[2..0]) is computed using the dedicated adders.
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May 2007
Stratix II Architecture
Figure 2–14. Example of a 3-bit Add Utilizing Shared Arithmetic Mode
shared_arith_in = '0'
carry_in = '0'
3-Bit Add Example
ALM Implementation
ALM 1
1st stage add is
implemented in LUTs.
X2 X1 X0
Y2 Y1 Y0
+ Z2 Z1 Z0
2nd stage add is
implemented in adders.
S2 S1 S0
+ C2 C1 C0
R3 R2 R1 R0
Binary Add
Decimal
Equivalents
1 1 0
1 0 1
+ 0 1 0
6
5
+ 2
0 0 1
+ 1 1 0
1
+ 2x6
1 1 0 1
13
3-Input
LUT
S0
R0
X0
Y0
Z0
3-Input
LUT
C0
X1
Y1
Z1
3-Input
LUT
S1
R1
3-Input
LUT
C1
3-Input
LUT
S2
ALM 2
R2
X2
Y2
Z2
3-Input
LUT
C2
3-Input
LUT
'0'
R3
3-Input
LUT
Shared Arithmetic Chain
In addition to the dedicated carry chain routing, the shared arithmetic
chain available in shared arithmetic mode allows the ALM to implement
a three-input add. This significantly reduces the resources necessary to
implement large adder trees or correlator functions.
The shared arithmetic chains can begin in either the first or fifth ALM in
an LAB. The Quartus II Compiler creates shared arithmetic chains longer
than 16 (8 ALMs in arithmetic or shared arithmetic mode) by linking
LABs together automatically. For enhanced fitting, a long shared
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Adaptive Logic Modules
arithmetic chain runs vertically allowing fast horizontal connections to
TriMatrix memory and DSP blocks. A shared arithmetic chain can
continue as far as a full column.
Similar to the carry chains, the shared arithmetic chains are also top- or
bottom-half bypassable. This capability allows the shared arithmetic
chain to cascade through half of the ALMs in a LAB while leaving the
other half available for narrower fan-in functionality. Every other LAB
column is top-half bypassable, while the other LAB columns are bottomhalf bypassable.
See the “MultiTrack Interconnect” on page 2–22 section for more
information on shared arithmetic chain interconnect.
Register Chain
In addition to the general routing outputs, the ALMs in an LAB have
register chain outputs. The register chain routing allows registers in the
same LAB to be cascaded together. The register chain interconnect allows
an LAB to use LUTs for a single combinational function and the registers
to be used for an unrelated shift register implementation. These resources
speed up connections between ALMs while saving local interconnect
resources (see Figure 2–15). The Quartus II Compiler automatically takes
advantage of these resources to improve utilization and performance.
2–20
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–15. Register Chain within an LAB Note (1)
From Previous ALM
Within The LAB
reg_chain_in
To general or
local routing
adder0
D
Q
To general or
local routing
reg0
Combinational
Logic
adder1
D
Q
To general or
local routing
reg1
To general or
local routing
To general or
local routing
adder0
D
Q
To general or
local routing
reg0
Combinational
Logic
adder1
D
Q
To general or
local routing
reg1
To general or
local routing
reg_chain_out
To Next ALM
within the LAB
Note to Figure 2–15:
(1)
The combinational or adder logic can be utilized to implement an unrelated, un-registered function.
See the “MultiTrack Interconnect” on page 2–22 section for more
information on register chain interconnect.
Altera Corporation
May 2007
2–21
Stratix II Device Handbook, Volume 1
MultiTrack Interconnect
Clear & Preset Logic Control
LAB-wide signals control the logic for the register's clear and load/preset
signals. The ALM directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. The direct asynchronous preset does not require a NOTgate push-back technique. Stratix II devices support simultaneous
asynchronous load/preset, and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each
LAB supports up to two clears and one load/preset signal.
In addition to the clear and load/preset ports, Stratix II devices provide a
device-wide reset pin (DEV_CLRn) that resets all registers in the device.
An option set before compilation in the Quartus II software controls this
pin. This device-wide reset overrides all other control signals.
MultiTrack
Interconnect
In the Stratix II architecture, connections between ALMs, TriMatrix
memory, DSP blocks, and device I/O pins are provided by the MultiTrack
interconnect structure with DirectDriveTM technology. The MultiTrack
interconnect consists of continuous, performance-optimized routing lines
of different lengths and speeds used for inter- and intra-design block
connectivity. The Quartus II Compiler automatically places critical design
paths on faster interconnects to improve design performance.
DirectDrive technology is a deterministic routing technology that ensures
identical routing resource usage for any function regardless of placement
in the device. The MultiTrack interconnect and DirectDrive technology
simplify the integration stage of block-based designing by eliminating the
re-optimization cycles that typically follow design changes and
additions.
The MultiTrack interconnect consists of row and column interconnects
that span fixed distances. A routing structure with fixed length resources
for all devices allows predictable and repeatable performance when
migrating through different device densities. Dedicated row
interconnects route signals to and from LABs, DSP blocks, and TriMatrix
memory in the same row. These row resources include:
■
■
■
Direct link interconnects between LABs and adjacent blocks
R4 interconnects traversing four blocks to the right or left
R24 row interconnects for high-speed access across the length of the
device
2–22
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
The direct link interconnect allows an LAB, DSP block, or TriMatrix
memory block to drive into the local interconnect of its left and right
neighbors and then back into itself. This provides fast communication
between adjacent LABs and/or blocks without using row interconnect
resources.
The R4 interconnects span four LABs, three LABs and one M512 RAM
block, two LABs and one M4K RAM block, or two LABs and one DSP
block to the right or left of a source LAB. These resources are used for fast
row connections in a four-LAB region. Every LAB has its own set of R4
interconnects to drive either left or right. Figure 2–16 shows R4
interconnect connections from an LAB. R4 interconnects can drive and be
driven by DSP blocks and RAM blocks and row IOEs. For LAB
interfacing, a primary LAB or LAB neighbor can drive a given R4
interconnect. For R4 interconnects that drive to the right, the primary
LAB and right neighbor can drive on to the interconnect. For R4
interconnects that drive to the left, the primary LAB and its left neighbor
can drive on to the interconnect. R4 interconnects can drive other R4
interconnects to extend the range of LABs they can drive. R4
interconnects can also drive C4 and C16 interconnects for connections
from one row to another. Additionally, R4 interconnects can drive R24
interconnects.
Figure 2–16. R4 Interconnect Connections
Notes (1), (2), (3)
Adjacent LAB can
Drive onto Another
LAB's R4 Interconnect
C4 and C16
Column Interconnects (1)
R4 Interconnect
Driving Right
R4 Interconnect
Driving Left
LAB
Neighbor
Primary
LAB (2)
LAB
Neighbor
Notes to Figure 2–16:
(1)
(2)
(3)
C4 and C16 interconnects can drive R4 interconnects.
This pattern is repeated for every LAB in the LAB row.
The LABs in Figure 2–16 show the 16 possible logical outputs per LAB.
Altera Corporation
May 2007
2–23
Stratix II Device Handbook, Volume 1
MultiTrack Interconnect
R24 row interconnects span 24 LABs and provide the fastest resource for
long row connections between LABs, TriMatrix memory, DSP blocks, and
Row IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row
interconnects drive to other row or column interconnects at every fourth
LAB and do not drive directly to LAB local interconnects. R24 row
interconnects drive LAB local interconnects via R4 and C4 interconnects.
R24 interconnects can drive R24, R4, C16, and C4 interconnects.
The column interconnect operates similarly to the row interconnect and
vertically routes signals to and from LABs, TriMatrix memory, DSP
blocks, and IOEs. Each column of LABs is served by a dedicated column
interconnect. These column resources include:
■
■
■
■
■
Shared arithmetic chain interconnects in an LAB
Carry chain interconnects in an LAB and from LAB to LAB
Register chain interconnects in an LAB
C4 interconnects traversing a distance of four blocks in up and down
direction
C16 column interconnects for high-speed vertical routing through
the device
Stratix II devices include an enhanced interconnect structure in LABs for
routing shared arithmetic chains and carry chains for efficient arithmetic
functions. The register chain connection allows the register output of one
ALM to connect directly to the register input of the next ALM in the LAB
for fast shift registers. These ALM to ALM connections bypass the local
interconnect. The Quartus II Compiler automatically takes advantage of
these resources to improve utilization and performance. Figure 2–17
shows the shared arithmetic chain, carry chain and register chain
interconnects.
2–24
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–17. Shared Arithmetic Chain, Carry Chain & Register Chain
Interconnects
Local Interconnect
Routing Among ALMs
in the LAB
Carry Chain & Shared
Arithmetic Chain
Routing to Adjacent ALM
ALM 1
ALM 2
Local
Interconnect
Register Chain
Routing to Adjacent
ALM's Register Inpu
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
The C4 interconnects span four LABs, M512, or M4K blocks up or down
from a source LAB. Every LAB has its own set of C4 interconnects to drive
either up or down. Figure 2–18 shows the C4 interconnect connections
from an LAB in a column. The C4 interconnects can drive and be driven
by all types of architecture blocks, including DSP blocks, TriMatrix
memory blocks, and column and row IOEs. For LAB interconnection, a
primary LAB or its LAB neighbor can drive a given C4 interconnect. C4
interconnects can drive each other to extend their range as well as drive
row interconnects for column-to-column connections.
Altera Corporation
May 2007
2–25
Stratix II Device Handbook, Volume 1
MultiTrack Interconnect
Figure 2–18. C4 Interconnect Connections Note (1)
C4 Interconnect
Drives Local and R4
Interconnects
up to Four Rows
C4 Interconnect
Driving Up
LAB
Row
Interconnect
Adjacent LAB can
drive onto neighboring
LAB's C4 interconnect
Local
Interconnect
C4 Interconnect
Driving Down
Note to Figure 2–18:
(1)
Each C4 interconnect can drive either up or down four rows.
2–26
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
C16 column interconnects span a length of 16 LABs and provide the
fastest resource for long column connections between LABs, TriMatrix
memory blocks, DSP blocks, and IOEs. C16 interconnects can cross
M-RAM blocks and also drive to row and column interconnects at every
fourth LAB. C16 interconnects drive LAB local interconnects via C4 and
R4 interconnects and do not drive LAB local interconnects directly.
All embedded blocks communicate with the logic array similar to LABto-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks)
connects to row and column interconnects and has local interconnect
regions driven by row and column interconnects. These blocks also have
direct link interconnects for fast connections to and from a neighboring
LAB. All blocks are fed by the row LAB clocks, labclk[5..0].
Table 2–2 shows the Stratix II device’s routing scheme.
Table 2–2. Stratix II Device Routing Scheme (Part 1 of 2)
Row IOE
Column IOE
DSP Blocks
M-RAM Block
M4K RAM Block
M512 RAM Block
ALM
C16 Interconnect
C4 Interconnect
R24 Interconnect
R4 Interconnect
Direct Link Interconnect
Local Interconnect
Register Chain
Carry Chain
Source
Shared Arithmetic Chain
Destination
Shared arithmetic chain
v
Carry chain
v
Register chain
v
Local interconnect
v v v v v v v
Direct link interconnect
v
R4 interconnect
v
v v v v
R24 interconnect
C4 interconnect
C16 interconnect
v v v v
v
v
v
v v v v
v v v v v v
v
M512 RAM block
v v v
v
M4K RAM block
v v v
v
ALM
M-RAM block
v v v v
DSP blocks
v v
Altera Corporation
May 2007
v
2–27
Stratix II Device Handbook, Volume 1
TriMatrix Memory
Table 2–2. Stratix II Device Routing Scheme (Part 2 of 2)
Column IOE
v
Row IOE
v v v v
TriMatrix
Memory
Row IOE
Column IOE
DSP Blocks
M-RAM Block
M4K RAM Block
M512 RAM Block
ALM
C16 Interconnect
C4 Interconnect
R24 Interconnect
R4 Interconnect
Direct Link Interconnect
Local Interconnect
Register Chain
Carry Chain
Source
Shared Arithmetic Chain
Destination
v v
TriMatrix memory consists of three types of RAM blocks: M512, M4K,
and M-RAM. Although these memory blocks are different, they can all
implement various types of memory with or without parity, including
true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO
buffers. Table 2–3 shows the size and features of the different RAM
blocks.
Table 2–3. TriMatrix Memory Features (Part 1 of 2)
Memory Feature
M512 RAM Block
(32 × 18 Bits)
M4K RAM Block
(128 × 36 Bits)
M-RAM Block
(4K × 144 Bits)
500 MHz
550 MHz
420 MHz
v
v
Maximum performance
True dual-port memory
Simple dual-port memory
v
v
v
Single-port memory
v
v
v
Shift register
v
v
ROM
v
v
(1)
FIFO buffer
v
v
v
v
v
Pack mode
Byte enable
v
Address clock enable
v
v
v
v
Parity bits
v
v
v
Mixed clock mode
v
v
v
Memory initialization (.mif)
v
v
2–28
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Table 2–3. TriMatrix Memory Features (Part 2 of 2)
Memory Feature
M512 RAM Block
(32 × 18 Bits)
M4K RAM Block
(128 × 36 Bits)
M-RAM Block
(4K × 144 Bits)
v
v
v
v
v
Simple dual-port memory
mixed width support
True dual-port memory
mixed width support
Power-up conditions
Outputs cleared
Outputs cleared
Outputs unknown
Register clears
Output registers
Output registers
Output registers
Mixed-port read-during-write Unknown output/old data Unknown output/old data Unknown output
Configurations
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
Notes to Table 2–3:
(1)
The M-RAM block does not support memory initializations. However, the M-RAM block can emulate a ROM
function using a dual-port RAM bock. The Stratix II device must write to the dual-port memory once and then
disable the write-enable ports afterwards.
Memory Block Size
TriMatrix memory provides three different memory sizes for efficient
application support. The Quartus II software automatically partitions the
user-defined memory into the embedded memory blocks using the most
efficient size combinations. You can also manually assign the memory to
a specific block size or a mixture of block sizes.
When applied to input registers, the asynchronous clear signal for the
TriMatrix embedded memory immediately clears the input registers.
However, the output of the memory block does not show the effects until
the next clock edge. When applied to output registers, the asynchronous
clear signal clears the output registers and the effects are seen
immediately.
Altera Corporation
May 2007
2–29
Stratix II Device Handbook, Volume 1
TriMatrix Memory
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful
for implementing small FIFO buffers, DSP, and clock domain transfer
applications. Each block contains 576 RAM bits (including parity bits).
M512 RAM blocks can be configured in the following modes:
■
■
■
■
■
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
1
Violating the setup or hold time on the memory block address
registers could corrupt memory contents. This applies to both
read and write operations.
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
M512 RAM blocks can have different clocks on its inputs and outputs.
The wren, datain, and write address registers are all clocked together
from one of the two clocks feeding the block. The read address, rden, and
output registers can be clocked by either of the two clocks driving the
block. This allows the RAM block to operate in read/write or
input/output clock modes. Only the output register can be bypassed. The
six labclk signals or local interconnect can drive the inclock,
outclock, wren, rden, and outclr signals. Because of the advanced
interconnect between the LAB and M512 RAM blocks, ALMs can also
control the wren and rden signals and the RAM clock, clock enable, and
asynchronous clear signals. Figure 2–19 shows the M512 RAM block
control signal generation logic.
The RAM blocks in Stratix II devices have local interconnects to allow
ALMs and interconnects to drive into RAM blocks. The M512 RAM block
local interconnect is driven by the R4, C4, and direct link interconnects
from adjacent LABs. The M512 RAM blocks can communicate with LABs
on either the left or right side through these row interconnects or with
LAB columns on the left or right side with the column interconnects. The
M512 RAM block has up to 16 direct link input connections from the left
adjacent LABs and another 16 from the right adjacent LAB. M512 RAM
outputs can also connect to left and right LABs through direct link
interconnect. The M512 RAM block has equal opportunity for access and
performance to and from LABs on either its left or right side. Figure 2–20
shows the M512 RAM block to logic array interface.
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–19. M512 RAM Block Control Signals
Dedicated
Row LAB
Clocks
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Altera Corporation
May 2007
outclocken
inclocken
inclock
outclock
wren
rden
outclr
2–31
Stratix II Device Handbook, Volume 1
TriMatrix Memory
Figure 2–20. M512 RAM Block LAB Row Interface
C4 Interconnect
R4 Interconnect
16
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
to adjacent LAB
dataout
Direct link
interconnect
from adjacent LAB
M512 RAM
Block
Direct link
interconnect
from adjacent LAB
clocks
datain
control
signals
address
2
6
M512 RAM Block Local
Interconnect Region
LAB Row Clocks
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K
RAM block is used to implement buffers for a wide variety of applications
such as storing processor code, implementing lookup schemes, and
implementing larger memory applications. Each block contains 4,608
RAM bits (including parity bits). M4K RAM blocks can be configured in
the following modes:
■
■
■
■
■
■
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
The M4K RAM blocks allow for different clocks on their inputs and
outputs. Either of the two clocks feeding the block can clock M4K RAM
block registers (renwe, address, byte enable, datain, and output registers).
Only the output register can be bypassed. The six labclk signals or local
interconnects can drive the control signals for the A and B ports of the
M4K RAM block. ALMs can also control the clock_a, clock_b,
renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b
signals, as shown in Figure 2–21.
The R4, C4, and direct link interconnects from adjacent LABs drive the
M4K RAM block local interconnect. The M4K RAM blocks can
communicate with LABs on either the left or right side through these row
resources or with LAB columns on either the right or left with the column
resources. Up to 16 direct link input connections to the M4K RAM Block
are possible from the left adjacent LABs and another 16 possible from the
right adjacent LAB. M4K RAM block outputs can also connect to left and
right LABs through direct link interconnect. Figure 2–22 shows the M4K
RAM block to logic array interface.
Figure 2–21. M4K RAM Block Control Signals
Dedicated
Row LAB
Clocks
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Altera Corporation
May 2007
clocken_b
clock_b
clock_a
clocken_a
renwe_b
renwe_a
aclr_b
aclr_a
2–33
Stratix II Device Handbook, Volume 1
TriMatrix Memory
Figure 2–22. M4K RAM Block LAB Row Interface
C4 Interconnect
Direct link
interconnect
to adjacent LAB
R4 Interconnect
16
Direct link
interconnect
to adjacent LAB
36
dataout
M4K RAM
Block
Direct link
interconnect
from adjacent LAB
Direct link
interconnect
from adjacent LAB
datain
control
signals
byte
enable
clocks
address
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
■
■
■
■
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
You cannot use an initialization file to initialize the contents of an M-RAM
block. All M-RAM block contents power up to an undefined value. Only
synchronous operation is supported in the M-RAM block, so all inputs
are registered. Output registers can be bypassed.
2–34
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Similar to all RAM blocks, M-RAM blocks can have different clocks on
their inputs and outputs. Either of the two clocks feeding the block can
clock M-RAM block registers (renwe, address, byte enable, datain, and
output registers). The output register can be bypassed. The six labclk
signals or local interconnect can drive the control signals for the A and B
ports of the M-RAM block. ALMs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_b signals as shown in Figure 2–23.
Figure 2–23. M-RAM Block Control Signals
Dedicated
Row LAB
Clocks
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
clocken_a
Local
Interconnect
clock_a
renwe_a
aclr_a
clock_b
aclr_b
renwe_b
Local
Interconnect
clocken_b
The R4, R24, C4, and direct link interconnects from adjacent LABs on
either the right or left side drive the M-RAM block local interconnect. Up
to 16 direct link input connections to the M-RAM block are possible from
the left adjacent LABs and another 16 possible from the right adjacent
LAB. M-RAM block outputs can also connect to left and right LABs
through direct link interconnect. Figure 2–24 shows an example floorplan
for the EP2S130 device and the location of the M-RAM interfaces.
Figures 2–25 and 2–26 show the interface between the M-RAM block and
the logic array.
Altera Corporation
May 2007
2–35
Stratix II Device Handbook, Volume 1
TriMatrix Memory
Figure 2–24. EP2S130 Device with M-RAM Interface Locations Note (1)
M-RAM blocks interface to
LABs on right and left sides for
easy access to horizontal I/O pins
M4K
Blocks
M-RAM
Block
M-RAM
Block
M-RAM
Block
M-RAM
Block
M-RAM
Block
M-RAM
Block
M512
Blocks
DSP
Blocks
LABs
DSP
Blocks
Note to Figure 2–24:
(1)
The device shown is an EP2S130 device. The number and position of M-RAM blocks varies in other devices.
2–36
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–25. M-RAM Block LAB Row Interface Note (1)
Row Unit Interface Allows LAB
Rows to Drive Port A Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
Row Unit Interface Allows LAB
Rows to Drive Port B Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
L0
R0
L1
R1
M-RAM Block
L2
Port A
Port B R2
L3
R3
L4
R4
L5
R5
LAB Interface
Blocks
LABs in Row
M-RAM Boundary
LABs in Row
M-RAM Boundary
Note to Figure 2–25:
(1)
Only R24 and C16 interconnects cross the M-RAM block boundaries.
Altera Corporation
May 2007
2–37
Stratix II Device Handbook, Volume 1
TriMatrix Memory
Figure 2–26. M-RAM Row Unit Interface to Interconnect
C4 Interconnect
R4 and R24 Interconnects
M-RAM Block
LAB
Up to 16
dataout_a[ ]
16
Up to 28
Direct Link
Interconnects
datain_a[ ]
addressa[ ]
addr_ena_a
renwe_a
byteenaA[ ]
clocken_a
clock_a
aclr_a
Row Interface Block
M-RAM Block to
LAB Row Interface
Block Interconnect Region
Table 2–4 shows the input and output data signal connections along with
the address and control signal input connections to the row unit interfaces
(L0 to L5 and R0 to R5).
2–38
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Table 2–4. M-RAM Row Interface Unit Signals
Unit Interface Block
f
Altera Corporation
May 2007
Input Signals
Output Signals
L0
datain_a[14..0]
byteena_a[1..0]
dataout_a[11..0]
L1
datain_a[29..15]
byteena_a[3..2]
dataout_a[23..12]
L2
datain_a[35..30]
addressa[4..0]
addr_ena_a
clock_a
clocken_a
renwe_a
aclr_a
dataout_a[35..24]
L3
addressa[15..5]
datain_a[41..36]
dataout_a[47..36]
L4
datain_a[56..42]
byteena_a[5..4]
dataout_a[59..48]
L5
datain_a[71..57]
byteena_a[7..6]
dataout_a[71..60]
R0
datain_b[14..0]
byteena_b[1..0]
dataout_b[11..0]
R1
datain_b[29..15]
byteena_b[3..2]
dataout_b[23..12]
R2
datain_b[35..30]
addressb[4..0]
addr_ena_b
clock_b
clocken_b
renwe_b
aclr_b
dataout_b[35..24]
R3
addressb[15..5]
datain_b[41..36]
dataout_b[47..36]
R4
datain_b[56..42]
byteena_b[5..4]
dataout_b[59..48]
R5
datain_b[71..57]
byteena_b[7..6]
dataout_b[71..60]
See the TriMatrix Embedded Memory Blocks in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook for more information on TriMatrix
memory.
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Stratix II Device Handbook, Volume 1
Digital Signal Processing Block
Digital Signal
Processing
Block
The most commonly used DSP functions are FIR filters, complex FIR
filters, IIR filters, fast Fourier transform (FFT) functions, direct cosine
transform (DCT) functions, and correlators. All of these use the multiplier
as the fundamental building block. Additionally, some applications need
specialized operations such as multiply-add and multiply-accumulate
operations. Stratix II devices provide DSP blocks to meet the arithmetic
requirements of these functions.
Each Stratix II device has from two to four columns of DSP blocks to
efficiently implement DSP functions faster than ALM-based
implementations. Stratix II devices have up to 24 DSP blocks per column
(see Table 2–5). Each DSP block can be configured to support up to:
■
■
■
Eight 9 × 9-bit multipliers
Four 18 × 18-bit multipliers
One 36 × 36-bit multiplier
As indicated, the Stratix II DSP block can support one 36 × 36-bit
multiplier in a single DSP block. This is true for any combination of
signed, unsigned, or mixed sign multiplications.
1
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Stratix II Device Handbook, Volume 1
This list only shows functions that can fit into a single DSP block.
Multiple DSP blocks can support larger multiplication
functions.
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–27 shows one of the columns with surrounding LAB rows.
Figure 2–27. DSP Blocks Arranged in Columns
DSP Block
Column
4 LAB
Rows
Altera Corporation
May 2007
DSP Block
2–41
Stratix II Device Handbook, Volume 1
Digital Signal Processing Block
Table 2–5 shows the number of DSP blocks in each Stratix II device.
Table 2–5. DSP Blocks in Stratix II Devices Note (1)
Device
DSP Blocks
Total 9 × 9
Multipliers
Total 18 × 18
Multipliers
Total 36 × 36
Multipliers
12
96
48
12
EP2S15
EP2S30
16
128
64
16
EP2S60
36
288
144
36
EP2S90
48
384
192
48
EP2S130
63
504
252
63
EP2S180
96
768
384
96
Note to Table 2–5:
(1)
Each device has either the numbers of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.
DSP block multipliers can optionally feed an adder/subtractor or
accumulator in the block depending on the configuration. This makes
routing to ALMs easier, saves ALM routing resources, and increases
performance, because all connections and blocks are in the DSP block.
Additionally, the DSP block input registers can efficiently implement shift
registers for FIR filter applications, and DSP blocks support Q1.15 format
rounding and saturation.
Figure 2–28 shows the top-level diagram of the DSP block configured for
18 × 18-bit multiplier mode.
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Altera Corporation
May 2007
Stratix II Architecture
Figure 2–28. DSP Block Diagram for 18 × 18-Bit Configuration
Optional Serial Shift
Register Inputs from
Previous DSP Block
Output
Selection
Multiplexer
Adder Output Block
PRN
D
Multiplier Block
Q
ENA
CLRN
From the row
interface block
D
PRN
Q1.15
Round/
Saturate
PRN
Q
D
Q
ENA
CLRN
ENA
CLRN
D
Adder/
Subtractor/
Accumulator
1
Q1.15
Round/
Saturate
PRN
Q
ENA
CLRN
D
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
PRN
Q1.15
Round/
Saturate
PRN
Q
D
Q
ENA
CLRN
Summation
Block
ENA
CLRN
Adder
D
Q
ENA
CLRN
D
PRN
Q
ENA
CLRN
PRN
Q1.15
Round/
Saturate
PRN
D
Q
D
Q
ENA
CLRN
D
D
Adder/
Subtractor/
Accumulator
2
Q1.15
Round/
Saturate
PRN
Q
ENA
CLRN
Optional Serial Shift
Register Outputs to
Next DSP Block
in the Column
Summation Stage
for Adding Four
Multipliers Together
ENA
CLRN
PRN
Q1.15
Round/
Saturate
PRN
Q
ENA
CLRN
D
Q
ENA
CLRN
Optional Pipline
Register Stage
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
to MultiTrack
Interconnect
Altera Corporation
May 2007
2–43
Stratix II Device Handbook, Volume 1
Digital Signal Processing Block
Modes of Operation
The adder, subtractor, and accumulate functions of a DSP block have four
modes of operation:
■
■
■
■
Simple multiplier
Multiply-accumulator
Two-multipliers adder
Four-multipliers adder
Table 2–6 shows the different number of multipliers possible in each DSP
block mode according to size. These modes allow the DSP blocks to
implement numerous applications for DSP including FFTs, complex FIR,
FIR, and 2D FIR filters, equalizers, IIR, correlators, matrix multiplication
and many other functions. The DSP blocks also support mixed modes
and mixed multiplier sizes in the same block. For example, half of one
DSP block can implement one 18 × 18-bit multiplier in multiplyaccumulator mode, while the other half of the DSP block implements four
9 × 9-bit multipliers in simple multiplier mode.
Table 2–6. Multiplier Size & Configurations per DSP Block
DSP Block Mode
Multiplier
9×9
Eight multipliers with
eight product outputs
Multiply-accumulator
-
Two-multipliers adder
Four-multipliers adder
18 × 18
Four multipliers with four
product outputs
36 × 36
One multiplier with one
product output
Two 52-bit multiplyaccumulate blocks
-
Four two-multiplier adder
(two 9 × 9 complex
multiply)
Two two-multiplier adder
(one 18 × 18 complex
multiply)
-
Two four-multiplier adder
One four-multiplier adder
-
DSP Block Interface
Stratix II device DSP block input registers can generate a shift register that
can cascade down in the same DSP block column. Dedicated connections
between DSP blocks provide fast connections between the shift register
inputs to cascade the shift register chains. You can cascade registers
within multiple DSP blocks for 9 × 9- or 18 × 18-bit FIR filters larger than
four taps, with additional adder stages implemented in ALMs. If the DSP
block is configured as 36 × 36 bits, the adder, subtractor, or accumulator
stages are implemented in ALMs. Each DSP block can route the shift
register chain out of the block to cascade multiple columns of DSP blocks.
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May 2007
Stratix II Architecture
The DSP block is divided into four block units that interface with four
LAB rows on the left and right. Each block unit can be considered one
complete 18 × 18-bit multiplier with 36 inputs and 36 outputs. A local
interconnect region is associated with each DSP block. Like an LAB, this
interconnect region can be fed with 16 direct link interconnects from the
LAB to the left or right of the DSP block in the same row. R4 and C4
routing resources can access the DSP block's local interconnect region.
The outputs also work similarly to LAB outputs as well. Eighteen outputs
from the DSP block can drive to the left LAB through direct link
interconnects and eighteen can drive to the right LAB though direct link
interconnects. All 36 outputs can drive to R4 and C4 routing
interconnects. Outputs can drive right- or left-column routing.
Figures 2–29 and 2–30 show the DSP block interfaces to LAB rows.
Figure 2–29. DSP Block Interconnect Interface
DSP Block
R4, C4 & Direct
Link Interconnects
OA[17..0]
OB[17..0]
R4, C4 & Direct
Link Interconnects
A1[17..0]
B1[17..0]
OC[17..0]
OD[17..0]
A2[17..0]
B2[17..0]
OE[17..0]
OF[17..0]
A3[17..0]
B3[17..0]
OG[17..0]
OH[17..0]
A4[17..0]
B4[17..0]
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Digital Signal Processing Block
Figure 2–30. DSP Block Interface to Interconnect
Direct Link Interconnect
from Adjacent LAB
C4 Interconnect
R4 Interconnect
Direct Link Outputs
to Adjacent LABs
Direct Link Interconnect
from Adjacent LAB
36
DSP Block
Row Structure
36
LAB
LAB
18
16
16
12
Control
36
A[17..0]
B[17..0]
OA[17..0]
OB[17..0]
36
Row Interface
Block
DSP Block to
LAB Row Interface
Block Interconnect Region
36 Inputs per Row
36 Outputs per Row
A bus of 44 control signals feeds the entire DSP block. These signals
include clocks, asynchronous clears, clock enables, signed/unsigned
control signals, addition and subtraction control signals, rounding and
saturation control signals, and accumulator synchronous loads. The clock
signals are routed from LAB row clocks and are generated from specific
LAB rows at the DSP block interface.
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May 2007
Stratix II Architecture
The LAB row source for control signals, data inputs, and outputs is
shown in Table 2–7.
Table 2–7. DSP Block Signal Sources & Destinations
LAB Row at
Interface
f
Altera Corporation
May 2007
Control Signals Generated
Data Inputs
Data Outputs
0
clock0
aclr0
ena0
mult01_saturate
addnsub1_round/ accum_round
addnsub1
signa
sourcea
sourceb
A1[17..0]
B1[17..0]
OA[17..0]
OB[17..0]
1
clock1
aclr1
ena1
accum_saturate
mult01_round
accum_sload
sourcea
sourceb
mode0
A2[17..0]
B2[17..0]
OC[17..0]
OD[17..0]
2
clock2
aclr2
ena2
mult23_saturate
addnsub3_round/ accum_round
addnsub3
sign_b
sourcea
sourceb
A3[17..0]
B3[17..0]
OE[17..0]
OF[17..0]
3
clock3
aclr3
ena3
accum_saturate
mult23_round
accum_sload
sourcea
sourceb
mode1
A4[17..0]
B4[17..0]
OG[17..0]
OH[17..0]
See the DSP Blocks in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II Device Handbook or the Stratix II GX Device
Handbook, for more information on DSP blocks.
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Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
PLLs & Clock
Networks
Stratix II devices provide a hierarchical clock structure and multiple PLLs
with advanced features. The large number of clocking resources in
combination with the clock synthesis precision provided by enhanced
and fast PLLs provides a complete clock management solution.
Global & Hierarchical Clocking
Stratix II devices provide 16 dedicated global clock networks and
32 regional clock networks (eight per device quadrant). These clocks are
organized into a hierarchical clock structure that allows for up to
24 clocks per device region with low skew and delay. This hierarchical
clocking scheme provides up to 48 unique clock domains in Stratix II
devices.
There are 16 dedicated clock pins (CLK[15..0]) to drive either the global
or regional clock networks. Four clock pins drive each side of the device,
as shown in Figures 2–31 and 2–32. Internal logic and enhanced and fast
PLL outputs can also drive the global and regional clock networks. Each
global and regional clock has a clock control block, which controls the
selection of the clock source and dynamically enables/disables the clock
to reduce power consumption. Table 2–8 shows global and regional clock
features.
Table 2–8. Global & Regional Clock Features
Feature
Global Clocks
Regional Clocks
Number per device
16
32
Number available per
quadrant
16
8
Sources
Dynamic clock source
selection
Dynamic enable/disable
CLK pins, PLL outputs,
or internal logic
CLK pins, PLL outputs,
or internal logic
v (1)
v
v
Note to Table 2–8:
(1)
Dynamic source clock selection is supported for selecting between CLKp pins and
PLL outputs only.
Global Clock Network
These clocks drive throughout the entire device, feeding all device
quadrants. The global clock networks can be used as clock sources for all
resources in the device-IOEs, ALMs, DSP blocks, and all memory blocks.
These resources can also be used for control signals, such as clock enables
and synchronous or asynchronous clears fed from the external pin. The
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May 2007
Stratix II Architecture
global clock networks can also be driven by internal logic for internally
generated global clocks and asynchronous clears, clock enables, or other
control signals with large fanout. Figure 2–31 shows the 16 dedicated CLK
pins driving global clock networks.
Figure 2–31. Global Clocking
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
Global Clock [15..0]
CLK[11..8]
CLK[7..4]
Regional Clock Network
There are eight regional clock networks RCLK[7..0] in each quadrant of
the Stratix II device that are driven by the dedicated CLK[15..0] input
pins, by PLL outputs, or by internal logic. The regional clock networks
provide the lowest clock delay and skew for logic contained in a single
quadrant. The CLK clock pins symmetrically drive the RCLK networks in
a particular quadrant, as shown in Figure 2–32.
Altera Corporation
May 2007
2–49
Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
Figure 2–32. Regional Clocks
RCLK[31..28]
RCLK[27..24]
CLK[15..12]
RCLK[23..20]
RCLK[3..0]
CLK[3..0]
CLK[11..8]
RCLK[19..16]
RCLK[7..4]
CLK[7..4]
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins,
PLLs or Core Logic within that Quadrant
RCLK[11..8]
RCLK[15..12]
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-regional
clock by driving two regional clock network lines in adjacent quadrants
(one from each quadrant). This allows logic that spans multiple
quadrants to utilize the same low skew clock. The routing of this clock
signal on an entire side has approximately the same speed but slightly
higher clock skew when compared with a clock signal that drives a single
quadrant. Internal logic-array routing can also drive a dual-regional
clock. Clock pins and enhanced PLL outputs on the top and bottom can
drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on
the left and right can drive vertical dual-regional clocks, as shown in
Figure 2–33. Corner PLLs cannot drive dual-regional clocks.
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May 2007
Stratix II Architecture
Figure 2–33. Dual-Regional Clocks
Clock Pins or PLL Clock Outputs
Can Drive Dual-Regional Network
CLK[15..12]
CLK[3..0]
Clock Pins or PLL Clock
Outputs Can Drive
Dual-Regional Network
CLK[3..0]
CLK[11..8]
PLLs
CLK[15..12]
CLK[11..8]
PLLs
CLK[7..4]
CLK[7..4]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources
consisting of 16 global clock lines and eight regional clock lines.
Multiplexers are used with these clocks to form busses to drive LAB row
clocks, column IOE clocks, or row IOE clocks. Another multiplexer is
used at the LAB level to select three of the six row clocks to feed the ALM
registers in the LAB (see Figure 2–34).
Figure 2–34. Hierarchical Clock Networks Per Quadrant
Clocks Available
to a Quadrant
or Half-Quadrant
Column I/O Cell
IO_CLK[7..0]
Global Clock Network [15..0]
Clock [23..0]
Lab Row Clock [5..0]
Regional Clock Network [7..0]
Row I/O Cell
IO_CLK[7..0]
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
IOE clocks have row and column block regions that are clocked by eight
I/O clock signals chosen from the 24 quadrant clock resources.
Figures 2–35 and 2–36 show the quadrant relationship to the I/O clock
regions.
Figure 2–35. EP2S15 & EP2S30 Device I/O Clock Groups
IO_CLKA[7:0]
IO_CLKB[7:0]
8
8
I/O Clock Regions
8
24 Clocks in
the Quadrant
24 Clocks in
the Quadrant
IO_CLKH[7:0]
IO_CLKC[7:0]
8
8
IO_CLKG[7:0]
IO_CLKD[7:0]
24 Clocks in
the Quadrant
24 Clocks in
the Quadrant
8
8
8
IO_CLKF[7:0]
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IO_CLKE[7:0]
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–36. EP2S60, EP2S90, EP2S130 & EP2S180 Device I/O Clock Groups
IO_CLKA[7:0]
IO_CLKB[7:0]
8
IO_CLKC[7:0]
8
IO_CLKD[7:0]
8
8
I/O Clock Regions
8
8
IO_CLKE[7:0]
IO_CLKP[7:0]
24 Clocks in the
Quadrant
24 Clocks in the
Quadrant
8
8
IO_CLKF[7:0]
IO_CLKO[7:0]
8
8
IO_CLKN[7:0]
IO_CLKG[7:0]
24 Clocks in the
Quadrant
24 Clocks in the
Quadrant
8
8
IO_CLKH[7:0]
IO_CLKM[7:0]
8
8
IO_CLKL[7:0]
8
IO_CLKK[7:0]
8
IO_CLKJ[7:0]
IO_CLKI[7:0]
You can use the Quartus II software to control whether a clock input pin
drives either a global, regional, or dual-regional clock network. The
Quartus II software automatically selects the clocking resources if not
specified.
Clock Control Block
Each global clock, regional clock, and PLL external clock output has its
own clock control block. The control block has two functions:
■
■
Altera Corporation
May 2007
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable/disable)
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Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
1
When using the global or regional clock control blocks in
Stratix II devices to select between multiple clocks or to enable
and disable clock networks, be aware of possible narrow pulses
or glitches when switching from one clock signal to another. A
glitch or runt pulse has a width that is less than the width of the
highest frequency input clock signal. To prevent logic errors
within the FPGA, Altera recommends that you build circuits
that filter out glitches and runt pulses.
Figures 2–37 through 2–39 show the clock control block for the global
clock, regional clock, and PLL external clock output, respectively.
Figure 2–37. Global Clock Control Blocks
CLKp
Pins
PLL Counter
Outputs
CLKSELECT[1..0]
(1)
2
2
CLKn
Pin
2
This multiplexer supports
User-Controllable
Dynamic Switching
Internal
Logic
Static Clock Select (2)
Enable/
Disable
Internal
Logic
GCLK
Notes to Figure 2–37:
(1)
(2)
These clock select signals can be dynamically controlled through internal logic
when the device is operating in user mode.
These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
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May 2007
Stratix II Architecture
Figure 2–38. Regional Clock Control Blocks
CLKp
Pin
PLL Counter
Outputs (3)
CLKn
Pin (2)
2
Internal
Logic
Static Clock Select (1)
Enable/
Disable
Internal
Logic
RCLK
Notes to Figure 2–38:
(1)
(2)
(3)
Altera Corporation
May 2007
These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
Only the CLKn pins on the top and bottom of the device feed to regional clock select
blocks.The clock outputs from corner PLLs cannot be dynamically selected
through the global clock control block.
The clock outputs from corner PLLs cannot be dynamically selected through the
global clock control block.
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PLLs & Clock Networks
Figure 2–39. External PLL Output Clock Control Blocks
PLL Counter
Outputs (c[5..0])
6
Static Clock Select (1)
Enable/
Disable
Internal
Logic
IOE (2)
Internal
Logic
Static Clock
Select (1)
PLL_OUT
Pin
Notes to Figure 2–39:
(1)
(2)
These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The
PLL_OUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an
internal signal or the output of the clock control block.
For the global clock control block, the clock source selection can be
controlled either statically or dynamically. The user has the option of
statically selecting the clock source by using the Quartus II software to set
specific configuration bits in the configuration file (.sof or .pof) or the
user can control the selection dynamically by using internal logic to drive
the multiplexor select inputs. When selecting statically, the clock source
can be set to any of the inputs to the select multiplexor. When selecting
the clock source dynamically, you can either select between two PLL
outputs (such as the C0 or C1 outputs from one PLL), between two PLLs
(such as the C0/C1 clock output of one PLL or the C0/C1 c1ock output of
the other PLL), between two clock pins (such as CLK0 or CLK1), or
between a combination of clock pins or PLL outputs. The clock outputs
from corner PLLs cannot be dynamically selected through the global
control block.
For the regional and PLL_OUT clock control block, the clock source
selection can only be controlled statically using configuration bits. Any of
the inputs to the clock select multiplexor can be set as the clock source.
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Stratix II Architecture
The Stratix II clock networks can be disabled (powered down) by both
static and dynamic approaches. When a clock net is powered down, all
the logic fed by the clock net is in an off-state thereby reducing the overall
power consumption of the device.
The global and regional clock networks can be powered down statically
through a setting in the configuration (.sof or .pof) file. Clock networks
that are not used are automatically powered down through configuration
bit settings in the configuration file generated by the Quartus II software.
The dynamic clock enable/disable feature allows the internal logic to
control power up/down synchronously on GCLK and RCLK nets and
PLL_OUT pins. This function is independent of the PLL and is applied
directly on the clock network or PLL_OUT pin, as shown in Figures 2–37
through 2–39.
1
The following restrictions for the input clock pins apply:
•
•
•
•
CLK0
CLK1
CLK2
CLK3
pin
pin
pin
pin
->
->
->
->
inclk[0]
inclk[1]
inclk[0]
inclk[1]
of
of
of
of
CLKCTRL
CLKCTRL
CLKCTRL
CLKCTRL
In general, even CLK numbers connect to the inclk[0] port of
CLKCTRL, and odd CLK numbers connect to the inclk[1] port
of CLKCTRL.
Failure to comply with these restrictions will result in a no-fit
error.
Enhanced & Fast PLLs
Stratix II devices provide robust clock management and synthesis using
up to four enhanced PLLs and eight fast PLLs. These PLLs increase
performance and provide advanced clock interfacing and clockfrequency synthesis. With features such as clock switchover,
spread-spectrum clocking, reconfigurable bandwidth, phase control, and
reconfigurable phase shifting, the Stratix II device’s enhanced PLLs
provide you with complete control of clocks and system timing. The fast
PLLs provide general purpose clocking with multiplication and phase
shifting as well as high-speed outputs for high-speed differential I/O
support. Enhanced and fast PLLs work together with the Stratix II
high-speed I/O and advanced clock architecture to provide significant
improvements in system performance and bandwidth.
Altera Corporation
May 2007
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PLLs & Clock Networks
The Quartus II software enables the PLLs and their features without
requiring any external devices. Table 2–9 shows the PLLs available for
each Stratix II device and their type.
Table 2–9. Stratix II Device PLL Availability
Fast PLLs
Enhanced PLLs
Device
1
2
3
4
7
8
9
10
5
6
11
12
EP2S15
v
v
v
v
EP2S30
v
v
v
v
v
v
v
v
EP2S60 (1)
v
v
v
v
v
v
v
v
v
v
v
v
EP2S90 (2)
v
v
v
v
v
v
v
v
v
v
v
v
EP2S130 (3)
v
v
v
v
v
v
v
EP2S180
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Notes to Table 2–9:
(1)
(2)
(3)
EP2S60 devices in the 1020-pin package contain 12 PLLs. EP2S60 devices in the 484-pin and 672-pin packages
contain fast PLLs 1–4 and enhanced PLLs 5 and 6.
EP2S90 devices in the 1020-pin and 1508-pin packages contain 12 PLLs. EP2S90 devices in the 484-pin and 780-pin
packages contain fast PLLS 1–4 and enhanced PLLs 5 and 6.
EP2S130 devices in the 1020-pin and 1508-pin packages contain 12PLLs. The EP2S130 device in the 780-pin package
contains fast PLLs 1–4 and enhanced PLLs 5 and 6.
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Stratix II Architecture
Table 2–10 shows the enhanced PLL and fast PLL features in Stratix II
devices.
Table 2–10. Stratix II PLL Features
Feature
Enhanced PLL
Fast PLL
Clock multiplication and division
m/(n × post-scale counter) (1)
m/(n × post-scale counter) (2)
Down to 125-ps increments (3), (4)
Down to 125-ps increments (3), (4)
Clock switchover
v
v (5)
PLL reconfiguration
v
v
Reconfigurable bandwidth
v
v
Spread spectrum clocking
v
Programmable duty cycle
v
v
Number of internal clock outputs
6
4
Number of external clock outputs
Three differential/six single-ended
(6)
Number of feedback clock inputs
One single-ended or differential
(7), (8)
Phase shift
Notes to Table 2–10:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
For enhanced PLLs, m ranges from 1 to 256, while n and post-scale counters range from 1 to 512 with 50% duty
cycle.
For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4.
The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8.
For degree increments, Stratix II devices can shift all output frequencies in increments of at least 45. Smaller degree
increments are possible depending on the frequency and divide parameters.
Stratix II fast PLLs only support manual clock switchover.
Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data
channel to generate txclkout.
If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin.
Every Stratix II device has at least two enhanced PLLs with one single-ended or differential external feedback input
per PLL.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
Figure 2–40 shows a top-level diagram of the Stratix II device and PLL
floorplan.
Figure 2–40. PLL Locations
CLK[15..12]
11
5
FPLL7CLK
7
10
FPLL10CLK
CLK[3..0]
1
2
4
3
CLK[8..11]
8
9
FPLL9CLK
PLLs
FPLL8CLK
12
6
CLK[7..4]
Figures 2–41 and 2–42 shows the global and regional clocking from the
fast PLL outputs and the side clock pins.
2–60
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
CLK8
C2
C2
RCK19
RCK17
RCK22
C3
CLK3
Fast
PLL 2
CLK2
CLK1
CLK0
Fast
PLL 1
RCK0
RCK1
RCK2
RCK3
RCK4
RCK5
RCK6
RCK7
GCK0
GCK1
GCK2
GCK3
Logic Array
Signal Input
To Clock
Network
GCK8
GCK9
GCK10
GCK11
RCK16
RCK18
RCK20
RCK21
RCK23
C1
C1
C3
C0
C0
Fast
PLL 3
CLK9
CLK10
C3
C3
C1
C2
C0
C1
C2
C0
Fast
PLL 4
CLK11
Figure 2–41. Global & Regional Clock Connections from Center Clock Pins &
Fast PLL Outputs
Note (1)
Notes to Figure 2–41:
(1)
(2)
Altera Corporation
May 2007
EP2S15 and EP2S30 devices only have four fast PLLs (1, 2, 3, and 4), but the
connectivity from these four PLLs to the global and regional clock networks
remains the same as shown.
The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input.
The global or regional clock input can be driven by an output from another PLL, a
pin-driven dedicated global or regional clock, or through a clock control block,
provided the clock control block is fed by an output from another PLL or a
pin-driven dedicated global or regional clock. An internally generated global
signal cannot drive the PLL.
2–61
Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
FPLL9CLK
C1
C1
RCK19
RCK17
Fast
PLL 8
FPLL8CLK
FPLL7CLK
Fast
PLL 7
RCK0
RCK4
RCK1
RCK5
RCK2
RCK6
RCK3
RCK7
GCK0
GCK1
GCK2
GCK3
GCK8
GCK9
GCK10
GCK11
RCK16
RCK18
C0
C0
C3
C3
C3
C3
C2
C2
C1
C2
C2
C0
C1
RCK21
RCK20
RCK22
RCK23
C0
Fast
PLL 9
Fast
PLL 10
FPLL10CLK
Figure 2–42. Global & Regional Clock Connections from Corner Clock Pins &
Fast PLL Outputs
Note (1)
Note to Figure 2–42:
(1)
The corner fast PLLs can also be driven through the global or regional clock
networks. The global or regional clock input can be driven by an output from
another PLL, a pin-driven dedicated global or regional clock, or through a clock
control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated
global signal cannot drive the PLL.
2–62
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–43 shows the global and regional clocking from enhanced PLL
outputs and top and bottom CLK pins. The connections to the global and
regional clocks from the top clock pins and enhanced PLL outputs is
shown in Table 2–11. The connections to the clocks from the bottom clock
pins is shown in Table 2–12.
Altera Corporation
May 2007
2–63
Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
Figure 2–43. Global & Regional Clock Connections from Top & Bottom Clock Pins & Enhanced PLL Outputs
Notes (1), (2), and (3)
CLK15
CLK13
CLK12
CLK14
PLL5_FB
PLL11_FB
PLL 11
PLL 5
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL5_OUT[2..0]p
PLL5_OUT[2..0]n
RCLK31
RCLK30
RCLK29
RCLK28
PLL11_OUT[2..0]p
PLL11_OUT[2..0]n
Regional
Clocks
RCLK27
RCLK26
RCLK25
RCLK24
G15
G14
G13
G12
Global
Clocks
Regional
Clocks
G4
G5
G6
G7
RCLK8
RCLK9
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
PLL6_OUT[2..0]p
PLL6_OUT[2..0]n
PLL12_OUT[2..0]p
PLL12_OUT[2..0]n
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL 12
PLL 6
PLL12_FB
PLL6_FB
CLK4
CLK6
CLK5
CLK7
Notes to Figure 2–43:
(1)
(2)
(3)
EP2S15 and EP2S30 devices only have two enhanced PLLs (5 and 6), but the connectivity from these two PLLs to
the global and regional clock networks remains the same as shown.
If the design uses the feedback input, you lose one (or two, if FBIN is differential) external clock output pin.
The enhanced PLLs can also be driven through the global or regional clock netowrks. The global or regional clock
input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a
clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
global or regional clock. An internally generated global signal cannot drive the PLL.
2–64
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
CLK15p
v
v
v
RCLK31
v
(Part 1
RCLK30
v
RCLK29
v
RCLK28
v
v
RCLK27
v
CLK14p
RCLK26
v
RCLK25
v
RCLK24
CLK13
v
CLK13p
CLK15
CLK12
CLK12p
Top Side Global & Regional
Clock Network Connectivity
CLK14
DLLCLK
Table 2–11. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs
of 2)
Clock pins
v
v
v
CLK12n
v
v
v
v
v
v
CLK13n
v
v
v
v
CLK14n
v
v
v
v
CLK15n
v
v
v
Drivers from internal logic
v
GCLKDRV0
v
GCLKDRV1
v
GCLKDRV2
v
GCLKDRV3
v
RCLKDRV0
v
v
RCLKDRV1
v
v
RCLKDRV2
v
v
RCLKDRV3
v
RCLKDRV4
v
v
v
RCLKDRV5
v
v
RCLKDRV6
v
v
RCLKDRV7
v
Enhanced PLL 5 outputs
c0
v
v
v
c1
v
v
v
c2
v
v
v
c3
v
v
v
Altera Corporation
May 2007
v
v
v
v
v
v
v
v
2–65
Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
v
v
v
v
v
RCLK31
(Part 2
RCLK30
RCLK29
RCLK28
RCLK27
RCLK26
RCLK25
RCLK24
CLK15
v
CLK14
v
c5
CLK13
c4
CLK12
Top Side Global & Regional
Clock Network Connectivity
DLLCLK
Table 2–11. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs
of 2)
v
v
v
Enhanced PLL 11 outputs
c0
v
v
c1
v
v
v
v
v
c2
v
v
c3
v
v
v
v
v
v
c4
v
v
v
c5
v
v
v
v
v
v
v
v
v
v
v
RCLK15
v
CLK7p
RCLK14
v
RCLK13
v
RCLK12
v
CLK6p
RCLK11
v
RCLK10
v
RCLK9
CLK5
v
CLK5p
CLK7
CLK4
CLK4p
CLK6
DLLCLK
Bottom Side Global &
Regional Clock Network
Connectivity
RCLK8
Table 2–12. Global & Regional Clock Connections from Bottom Clock Pins & Enhanced PLL
Outputs
(Part 1 of 2)
Clock pins
CLK4n
v
v
v
v
v
v
v
v
v
CLK5n
v
v
v
v
CLK6n
v
v
v
CLK7n
v
v
v
v
Drivers from internal logic
GCLKDRV0
v
GCLKDRV1
GCLKDRV2
2–66
Stratix II Device Handbook, Volume 1
v
v
Altera Corporation
May 2007
Stratix II Architecture
RCLK15
RCLK14
RCLK13
RCLK12
RCLK11
RCLK10
RCLK9
RCLK8
CLK7
CLK6
CLK5
CLK4
Bottom Side Global &
Regional Clock Network
Connectivity
DLLCLK
Table 2–12. Global & Regional Clock Connections from Bottom Clock Pins & Enhanced PLL
Outputs
(Part 2 of 2)
v
GCLKDRV3
v
RCLKDRV0
v
v
RCLKDRV1
v
v
RCLKDRV2
v
v
RCLKDRV3
v
RCLKDRV4
v
v
v
RCLKDRV5
v
v
RCLKDRV6
v
v
RCLKDRV7
v
Enhanced PLL 6 outputs
c0
v
v
v
c1
v
v
v
v
c2
v
v
v
c3
v
v
v
c4
v
c5
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Enhanced PLL 12 outputs
c0
v
v
c1
v
v
v
v
c2
v
v
c3
v
v
c4
c5
Altera Corporation
May 2007
v
v
v
v
v
v
v
v
v
v
v
v
v
v
2–67
Stratix II Device Handbook, Volume 1
PLLs & Clock Networks
Enhanced PLLs
Stratix II devices contain up to four enhanced PLLs with advanced clock
management features. Figure 2–44 shows a diagram of the enhanced PLL.
Figure 2–44. Stratix II Enhanced PLL Note (1)
From Adjacent PLL
VCO Phase Selection
Selectable at Each
PLL Output Port
Clock
Switchover
Circuitry
Post-Scale
Counters
Spread
Spectrum
Phase Frequency
Detector
/c0
INCLK[3..0]
/c1
4
/n
PFD
Charge
Pump
Loop
Filter
8
VCO
Global or
Regional
Clock (4)
4
Global
Clocks
8
Regional
Clocks
/c2
6
/c3
6
/m
I/O Buffers (3)
/c4
(2)
/c5
FBIN
Shaded Portions of the
PLL are Reconfigurable
Lock Detect
& Filter
to I/O or general
routing
VCO Phase Selection
Affecting All Outputs
Notes to Figure 2–44:
(1)
(2)
(3)
(4)
Each clock source can come from any of the four clock pins that are physically located on the same side of the device
as the PLL.
If the feedback input is used, you lose one (or two, if FBIN is differential) external clock output pin.
Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
2–68
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Fast PLLs
Stratix II devices contain up to eight fast PLLs with high-speed serial
interfacing ability. Figure 2–45 shows a diagram of the fast PLL.
Figure 2–45. Stratix II Device Fast PLL
Clock
Switchover
Circuitry (4)
Global or
regional clock (1)
Notes (1), (2), (3)
VCO Phase Selection
Selectable at each PLL
Output Port
Phase
Frequency
Detector
Post-Scale
Counters
diffioclk0 (2)
load_en0 (3)
÷c0
(5)
Clock
Input
÷n
4
PFD
Charge
Pump
Loop
Filter
VCO
÷k
8
load_en1 (3)
÷c1
diffioclk1 (2)
4
Global clocks
÷c2
4
Global or
regional clock (1)
8
Regional clocks
÷c3
÷m
8
to DPA block
Shaded Portions of the
PLL are Reconfigurable
Notes to Figure 2–45:
(1)
(2)
(3)
(4)
(5)
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES circuitry. Stratix II
devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a differential I/O SERDES control signal.
Stratix II fast PLLs only support manual clock switchover.
If the design enables this ÷2 counter, then the device can use a VCO frequency range of 150 to 520 MHz.
f
I/O Structure
See the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of
the Stratix II Device Handbook or the Stratix II GX Device Handbook for
more information on enhanced and fast PLLs. See “High-Speed
Differential I/O with DPA Support” on page 2–96 for more information
on high-speed differential I/O support.
The Stratix II IOEs provide many features, including:
■
■
■
■
■
■
■
■
Altera Corporation
May 2007
Dedicated differential and single-ended I/O buffers
3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
On-chip driver series termination
On-chip parallel termination
On-chip termination for differential standards
Programmable pull-up during configuration
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Stratix II Device Handbook, Volume 1
I/O Structure
■
■
■
■
■
■
■
■
Output drive strength control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
Double data rate (DDR) registers
The IOE in Stratix II devices contains a bidirectional I/O buffer, six
registers, and a latch for a complete embedded bidirectional single data
rate or DDR transfer. Figure 2–46 shows the Stratix II IOE structure. The
IOE contains two input registers (plus a latch), two output registers, and
two output enable registers. The design can use both input registers and
the latch to capture DDR input and both output registers to drive DDR
outputs. Additionally, the design can use the output enable (OE) register
for fast clock-to-output enable timing. The negative edge-clocked OE
register is used for DDR SDRAM interfacing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins.
2–70
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–46. Stratix II IOE Structure
Logic Array
OE Register
OE
D
Q
OE Register
D
Q
Output Register
Output A
D
Q
CLK
Output Register
Output B
D
Q
Input Register
D
Q
Input A
Input B
Input Register
D
Q
Input Latch
D
Q
ENA
The IOEs are located in I/O blocks around the periphery of the Stratix II
device. There are up to four IOEs per row I/O block and four IOEs per
column I/O block. The row I/O blocks drive row, column, or direct link
interconnects. The column I/O blocks drive column interconnects.
Figure 2–47 shows how a row I/O block connects to the logic array.
Figure 2–48 shows how a column I/O block connects to the logic array.
Altera Corporation
May 2007
2–71
Stratix II Device Handbook, Volume 1
I/O Structure
Figure 2–47. Row I/O Block Connection to the Interconnect Note (1)
R4 & R24
Interconnects
C4 Interconnect
I/O Block Local
Interconnect
32 Data & Control
Signals from
Logic Array (1)
32
LAB
Horizontal
I/O Block
io_dataina[3..0]
io_datainb[3..0]
Direct Link
Interconnect
to Adjacent LAB
Direct Link
Interconnect
to Adjacent LAB
io_clk[7:0]
LAB Local
Interconnect
Horizontal I/O
Block Contains
up to Four IOEs
Note to Figure 2–47:
(1)
The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
2–72
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–48. Column I/O Block Connection to the Interconnect Note (1)
32 Data &
Control Signals
from Logic Array (1)
Vertical I/O
Block Contains
up to Four IOEs
Vertical I/O Block
32
IO_dataina[3:0]
IO_datainb[3:0]
io_clk[7..0]
I/O Block
Local Interconnect
R4 & R24
Interconnects
LAB
LAB Local
Interconnect
LAB
LAB
C4 & C16
Interconnects
Note to Figure 2–48:
(1)
The 32 data and control signals consist of eight data out lines: four lines each for DDR applications
io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables
io_ce_in[3..0], four output clock enables io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous
clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals
io_sclr/spreset[3..0].
Altera Corporation
May 2007
2–73
Stratix II Device Handbook, Volume 1
I/O Structure
There are 32 control and data signals that feed each row or column I/O
block. These control and data signals are driven from the logic array. The
row or column IOE clocks, io_clk[7..0], provide a dedicated routing
resource for low-skew, high-speed clocks. I/O clocks are generated from
global or regional clocks (see the “PLLs & Clock Networks” section).
Figure 2–49 illustrates the signal paths through the I/O block.
Figure 2–49. Signal Path through the I/O Block
Row or Column
io_clk[7..0]
To Logic
Array
To Other
IOEs
io_dataina
io_datainb
oe
ce_in
io_oe
ce_out
io_ce_in
io_ce_out
Control
Signal
Selection
aclr/apreset
IOE
sclr/spreset
io_aclr
From Logic
Array
clk_in
io_sclr
clk_out
io_clk
io_dataouta
io_dataoutb
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/apreset, sclr/spreset,
clk_in, and clk_out. Figure 2–50 illustrates the control signal
selection.
2–74
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–50. Control Signal Selection per IOE
Dedicated I/O
Clock [7..0]
Local
Interconnect
io_oe
Local
Interconnect
io_sclr
Local
Interconnect
io_aclr
Local
Interconnect
io_ce_out
Local
Interconnect
io_ce_in
Local
Interconnect
io_clk
ce_out
clk_out
clk_in
ce_in
sclr/spreset
aclr/apreset
oe
Notes to Figure 2–50:
(1)
Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their
control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive
the I/O local interconnect, which then drives the control selection multiplexers.
In normal bidirectional operation, the input register can be used for input
data requiring fast setup times. The input register can have its own clock
input and clock enable separate from the OE and output registers. The
output register can be used for data requiring fast clock-to-output
performance. The OE register can be used for fast clock-to-output enable
timing. The OE and output register share the same clock source and the
same clock enable source from local interconnect in the associated LAB,
dedicated I/O clocks, and the column and row interconnects.
Altera Corporation
May 2007
2–75
Stratix II Device Handbook, Volume 1
I/O Structure
Figure 2–51 shows the IOE in bidirectional configuration.
Figure 2–51. Stratix II IOE in Bidirectional I/O Configuration Note (1)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
oe
OE Register
D
Q
clkout
ce_out
ENA
CLRN/PRN
OE Register
tCO Delay
VCCIO
PCI Clamp (2)
VCCIO
Programmable
Pull-Up
Resistor
aclr/apreset
Chip-Wide Reset
Output Register
D
sclr/spreset
Q
Output
Pin Delay
On-Chip
Termination
Drive Strength Control
ENA
Open-Drain Output
CLRN/PRN
Input Pin to
Logic Array Delay
Input Register
clkin
ce_in
D
Input Pin to
Input Register Delay
Bus-Hold
Circuit
Q
ENA
CLRN/PRN
Notes to Figure 2–51:
(1)
(2)
All input signals to the IOE can be inverted at the IOE.
The optional PCI clamp is only available on column I/O pins.
2–76
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
The Stratix II device IOE includes programmable delays that can be
activated to ensure input IOE register-to-logic array register transfers,
input pin-to-logic array register transfers, or output IOE register-to-pin
transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinational logic may not require the delay. Programmable
delays exist for decreasing input-pin-to-logic-array and IOE input
register delays. The Quartus II Compiler can program these delays to
automatically minimize setup time while providing a zero hold time.
Programmable delays can increase the register-to-pin delays for output
and/or output enable registers. Programmable delays are no longer
required to ensure zero hold times for logic array register-to-IOE register
transfers. The Quartus II Compiler can create the zero hold time for these
transfers. Table 2–13 shows the programmable delays for Stratix II
devices.
Table 2–13. Stratix II Programmable Delay Chain
Programmable Delays
Quartus II Logic Option
Input pin to logic array delay
Input delay from pin to internal cells
Input pin to input register delay
Input delay from pin to input register
Output pin delay
Delay from output register to output pin
Output enable register tCO delay
Delay to output enable pin
The IOE registers in Stratix II devices share the same source for clear or
preset. You can program preset or clear for each individual IOE. You can
also program the registers to power up high or low after configuration is
complete. If programmed to power up low, an asynchronous clear can
control the registers. If programmed to power up high, an asynchronous
preset can control the registers. This feature prevents the inadvertent
activation of another device's active-low input upon power-up. If one
register in an IOE uses a preset or clear signal then all registers in the IOE
must use that same signal if they require preset or clear. Additionally, a
synchronous reset signal is available for the IOE registers.
Double Data Rate I/O Pins
Stratix II devices have six registers in the IOE, which support DDR
interfacing by clocking data on both positive and negative clock edges.
The IOEs in Stratix II devices support DDR inputs, DDR outputs, and
bidirectional DDR modes.
Altera Corporation
May 2007
2–77
Stratix II Device Handbook, Volume 1
I/O Structure
When using the IOE for DDR inputs, the two input registers clock double
rate input data on alternating edges. An input latch is also used in the IOE
for DDR input acquisition. The latch holds the data that is present during
the clock high times. This allows both bits of data to be synchronous with
the same clock edge (either rising or falling). Figure 2–52 shows an IOE
configured for DDR input. Figure 2–53 shows the DDR input timing
diagram.
Figure 2–52. Stratix II IOE in DDR Input I/O Configuration Notes (1), (2), (3)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
VCCIO
To DQS Logic
Block (3)
DQS Local
Bus (2)
PCI Clamp (4)
VCCIO
Programmable
Pull-Up
Resistor
On-Chip
Termination
Input Pin to
Input RegisterDelay
sclr/spreset
Input Register
D
Q
clkin
ce_in
ENA
CLRN/PRN
Bus-Hold
Circuit
aclr/apreset
Chip-Wide Reset
Latch
Input Register
D
Q
ENA
CLRN/PRN
D
Q
ENA
CLRN/PRN
Notes to Figure 2–52:
(1)
(2)
(3)
(4)
All input signals to the IOE can be inverted at the IOE.
This signal connection is only allowed on dedicated DQ function pins.
This signal is for dedicated DQS function pins only.
The optional PCI clamp is only available on column I/O pins.
2–78
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–53. Input Timing Diagram in DDR Mode
Data at
input pin
B0
A0
B1
A1
B2
A2
B3
A3
B4
CLK
A0
A1
A2
A3
B0
B1
B2
B3
Input To
Logic Array
When using the IOE for DDR outputs, the two output registers are
configured to clock two data paths from ALMs on rising clock edges.
These output registers are multiplexed by the clock to drive the output
pin at a ×2 rate. One output register clocks the first bit out on the clock
high time, while the other output register clocks the second bit out on the
clock low time. Figure 2–54 shows the IOE configured for DDR output.
Figure 2–55 shows the DDR output timing diagram.
Altera Corporation
May 2007
2–79
Stratix II Device Handbook, Volume 1
I/O Structure
Figure 2–54. Stratix II IOE in DDR Output I/O Configuration Notes (1), (2)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
oe
OE Register
D
Q
clkout
ENA
CLRN/PRN
OE Register
tCO Delay
ce_out
aclr/apreset
VCCIO
PCI Clamp (3)
Chip-Wide Reset
OE Register
D
VCCIO
Q
sclr/spreset
ENA
CLRN/PRN
Used for
DDR, DDR2
SDRAM
Programmable
Pull-Up
Resistor
Output Register
D
Q
ENA
CLRN/PRN
Output Register
D
Output
Pin Delay
On-Chip
Termination
clk
Drive Strength
Control
Open-Drain Output
Q
ENA
CLRN/PRN
Bus-Hold
Circuit
Notes to Figure 2–54:
(1)
(2)
(3)
All input signals to the IOE can be inverted at the IOE.
The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an
inverter at the OE register data port. Similarly, the aclr and apreset signals are also active-high at the input ports
of the DDIO megafunction.
The optional PCI clamp is only available on column I/O pins.
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–55. Output TIming Diagram in DDR Mode
CLK
A1
A2
A3
A4
B1
B2
B3
B4
From Internal
Registers
B1
DDR output
A1
B2
A2
B3
A3
B4
A4
The Stratix II IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations. The negative-edge-clocked
OE register holds the OE signal inactive until the falling edge of the clock.
This is done to meet DDR SDRAM timing requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, Stratix II devices also have
dedicated phase-shift circuitry for interfacing with external memory
interfaces. Stratix II devices support DDR and DDR2 SDRAM, QDR II
SRAM, RLDRAM II, and SDR SDRAM memory interfaces. In every
Stratix II device, the I/O banks at the top (banks 3 and 4) and bottom
(banks 7 and 8) of the device support DQ and DQS signals with DQ bus
modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table 2–14 shows the number
of DQ and DQS buses that are supported per device.
Table 2–14. DQS & DQ Bus Mode Support (Part 1 of 2)
Number of
×4 Groups
Number of
×8/×9 Groups
484-pin FineLine BGA
8
4
0
0
672-pin FineLine BGA
18
8
4
0
484-pin FineLine BGA
8
4
0
0
672-pin FineLine BGA
18
8
4
0
484-pin FineLine BGA
8
4
0
0
672-pin FineLine BGA
18
8
4
0
1,020-pin FineLine BGA
36
18
8
4
Device
EP2S15
EP2S30
EP2S60
Note (1)
Package
Altera Corporation
May 2007
Number of
Number of
×16/×18 Groups ×32/×36 Groups
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Stratix II Device Handbook, Volume 1
I/O Structure
Table 2–14. DQS & DQ Bus Mode Support (Part 2 of 2)
Note (1)
Device
Package
Number of
×4 Groups
Number of
×8/×9 Groups
EP2S90
484-pin Hybrid FineLine BGA
8
4
Number of
Number of
×16/×18 Groups ×32/×36 Groups
0
0
780-pin FineLine BGA
18
8
4
0
1,020-pin FineLine BGA
36
18
8
4
1,508-pin FineLine BGA
36
18
8
4
18
8
4
0
1,020-pin FineLine BGA
36
18
8
4
1,508-pin FineLine BGA
36
18
8
4
EP2S180 1,020-pin FineLine BGA
36
18
8
4
1,508-pin FineLine BGA
36
18
8
4
EP2S130 780-pin FineLine BGA
Notes to Table 2–14:
(1)
Check the pin table for each DQS/DQ group in the different modes.
A compensated delay element on each DQS pin automatically aligns
input DQS synchronization signals with the data window of their
corresponding DQ data signals. The DQS signals drive a local DQS bus in
the top and bottom I/O banks. This DQS bus is an additional resource to
the I/O clocks and is used to clock DQ input registers with the DQS
signal.
The Stratix II device has two phase-shifting reference circuits, one on the
top and one on the bottom of the device. The circuit on the top controls
the compensated delay elements for all DQS pins on the top. The circuit
on the bottom controls the compensated delay elements for all DQS pins
on the bottom.
Each phase-shifting reference circuit is driven by a system reference clock,
which must have the same frequency as the DQS signal. Clock pins
CLK[15..12]p feed the phase circuitry on the top of the device and
clock pins CLK[7..4]p feed the phase circuitry on the bottom of the
device. In addition, PLL clock outputs can also feed the phase-shifting
reference circuits.
Figure 2–56 illustrates the phase-shift reference circuit control of each
DQS delay shift on the top of the device. This same circuit is duplicated
on the bottom of the device.
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–56. DQS Phase-Shift Circuitry Notes (1), (2), (3), (4)
From PLL 5 (3)
DQSn
Pin
DQS
Pin
DQSn
Pin
DQS
Pin
Δt
Δt
Δt
Δt
to IOE
to IOE
to IOE
to IOE
CLK[15..12]p (2)
DQS
Phase-Shift
Circuitry
DQS
Pin
DQSn
Pin
DQS
Pin
DQSn
Pin
Δt
Δt
Δt
Δt
to IOE
to IOE
to IOE
to IOE
DQS Logic
Blocks
Notes to Figure 2–56:
(1)
(2)
(3)
(4)
There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II device. There are
up to 10 pairs on the right side and 8 pairs on the left side of the DQS phase-shift circuitry.
The Δt module represents the DQS logic block.
Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed
the phase circuitry on the bottom of the device. You can also use a PLL clock output as a reference clock to the phaseshift circuitry.
You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS
phase-shift circuitry on the bottom of the device.
These dedicated circuits combined with enhanced PLL clocking and
phase-shift ability provide a complete hardware solution for interfacing
to high-speed memory.
f
For more information on external memory interfaces, refer to the
External Memory Interfaces in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II Device Handbook or the Stratix II GX Device
Handbook.
Programmable Drive Strength
The output buffer for each Stratix II device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL, LVCMOS,
SSTL, and HSTL standards have several levels of drive strength that the
user can control. The default setting used in the Quartus II software is the
maximum current strength setting that is used to achieve maximum I/O
performance. For all I/O standards, the minimum setting is the lowest
drive strength that guarantees the IOH/IOL of the standard. Using
minimum settings provides signal slew rate control to reduce system
noise and signal overshoot.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
I/O Structure
Table 2–15 shows the possible settings for the I/O standards with drive
strength control.
Table 2–15. Programmable Drive Strength Note (1)
IOH / IOL Current Strength
Setting (mA) for Column
I/O Pins
IOH / IOL Current Strength
Setting (mA) for Row I/O
Pins
3.3-V LVTTL
24, 20, 16, 12, 8, 4
12, 8, 4
3.3-V LVCMOS
I/O Standard
24, 20, 16, 12, 8, 4
8, 4
2.5-V LVTTL/LVCMOS
16, 12, 8, 4
12, 8, 4
1.8-V LVTTL/LVCMOS
12, 10, 8, 6, 4, 2
8, 6, 4, 2
8, 6, 4, 2
4, 2
SSTL-2 Class I
12, 8
12, 8
SSTL-2 Class II
24, 20, 16
16
SSTL-18 Class I
12, 10, 8, 6, 4
10, 8, 6, 4
SSTL-18 Class II
20, 18, 16, 8
-
HSTL-18 Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
HSTL-18 Class II
20, 18, 16
-
HSTL-15 Class I
12, 10, 8, 6, 4
8, 6, 4
HSTL-15 Class II
20, 18, 16
-
1.5-V LVCMOS
Note to Table 2–15:
(1)
The Quartus II software default current setting is the maximum setting for each
I/O standard.
Open-Drain Output
Stratix II devices provide an optional open-drain (equivalent to an opencollector) output for each I/O pin. This open-drain output enables the
device to provide system-level control signals (e.g., interrupt and writeenable signals) that can be asserted by any of several devices.
Bus Hold
Each Stratix II device I/O pin provides an optional bus-hold feature. The
bus-hold circuitry can weakly hold the signal on an I/O pin at its
last-driven state. Since the bus-hold feature holds the last-driven state of
the pin until the next input signal is present, you do not need an external
pull-up or pull-down resistor to hold a signal level when the bus is
tri-stated.
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Altera Corporation
May 2007
Stratix II Architecture
The bus-hold circuitry also pulls undriven pins away from the input
threshold voltage where noise can cause unintended high-frequency
switching. You can select this feature individually for each I/O pin. The
bus-hold output drives no higher than VCCIO to prevent overdriving
signals. If the bus-hold feature is enabled, the programmable pull-up
option cannot be used. Disable the bus-hold feature when the I/O pin has
been configured for differential signals.
The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of
approximately 7 kΩ to weakly pull the signal level to the last-driven state.
See the DC & Switching Characteristics chapter in the Stratix II Device
Handbook, Volume 1, for the specific sustaining current driven through this
resistor and overdrive current used to identify the next-driven input
level. This information is provided for each VCCIO voltage level.
The bus-hold circuitry is active only after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Programmable Pull-Up Resistor
Each Stratix II device I/O pin provides an optional programmable
pull-up resistor during user mode. If you enable this feature for an I/O
pin, the pull-up resistor (typically 25 kΩ) weakly holds the output to the
VCCIO level of the output pin’s bank.
Programmable pull-up resistors are only supported on user I/O pins, and
are not supported on dedicated configuration pins, JTAG pins or
dedicated clock pins.
Advanced I/O Standard Support
Stratix II device IOEs support the following I/O standards:
■
■
■
■
■
■
■
■
■
■
■
■
■
Altera Corporation
May 2007
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
3.3-V PCI-X mode 1
LVDS
LVPECL (on input and output clocks only)
HyperTransport technology
Differential 1.5-V HSTL Class I and II
Differential 1.8-V HSTL Class I and II
Differential SSTL-18 Class I and II
Differential SSTL-2 Class I and II
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Stratix II Device Handbook, Volume 1
I/O Structure
■
■
■
■
■
1.5-V HSTL Class I and II
1.8-V HSTL Class I and II
1.2-V HSTL
SSTL-2 Class I and II
SSTL-18 Class I and II
Table 2–16 describes the I/O standards supported by Stratix II devices.
Table 2–16. Stratix II Supported I/O Standards (Part 1 of 2)
I/O Standard
Type
Input Reference
Output Supply
Board Termination
Voltage (VREF) (V) Voltage (VCCIO) (V) Voltage (VTT) (V)
LVTTL
Single-ended
-
3.3
-
LVCMOS
Single-ended
-
3.3
-
2.5 V
Single-ended
-
2.5
-
1.8 V
Single-ended
-
1.8
-
1.5-V LVCMOS
Single-ended
-
1.5
-
3.3-V PCI
Single-ended
-
3.3
-
3.3-V PCI-X mode 1
Single-ended
-
3.3
-
LVDS
Differential
-
2.5 (3)
-
LVPECL (1)
Differential
-
3.3
-
HyperTransport technology Differential
-
2.5
-
Differential 1.5-V HSTL
Class I and II (2)
Differential
0.75
1.5
0.75
Differential 1.8-V HSTL
Class I and II (2)
Differential
0.90
1.8
0.90
Differential SSTL-18 Class
I and II (2)
Differential
0.90
1.8
0.90
Differential SSTL-2 Class I
and II (2)
Differential
1.25
2.5
1.25
1.2-V HSTL(4)
Voltage-referenced
0.6
1.2
0.6
1.5-V HSTL Class I and II
Voltage-referenced
0.75
1.5
0.75
1.8-V HSTL Class I and II
Voltage-referenced
0.9
1.8
0.9
SSTL-18 Class I and II
Voltage-referenced
0.90
1.8
0.90
2–86
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Table 2–16. Stratix II Supported I/O Standards (Part 2 of 2)
I/O Standard
SSTL-2 Class I and II
Type
Voltage-referenced
Input Reference
Output Supply
Board Termination
Voltage (VREF) (V) Voltage (VCCIO) (V) Voltage (VTT) (V)
1.25
2.5
1.25
Notes to Table 2–16:
(1)
(2)
(3)
(4)
This I/O standard is only available on input and output column clock pins.
This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clock
pins in I/O banks 9,10, 11, and 12.
VCCIO is 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 9, 10, 11, and 12).
The clock input pins supporting LVDS on banks 3, 4, 7, and 8 use VCCINT for LVDS input operations and have no
dependency on the VCCIO level of the bank.
1.2-V HSTL is only supported in I/O banks 4,7, and 8.
f
For more information on I/O standards supported by Stratix II I/O
banks, refer to the Selectable I/O Standards in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook.
Stratix II devices contain eight I/O banks and four enhanced PLL external
clock output banks, as shown in Figure 2–57. The four I/O banks on the
right and left of the device contain circuitry to support high-speed
differential I/O for LVDS and HyperTransport inputs and outputs. These
banks support all Stratix II I/O standards except PCI or PCI-X I/O pins,
and SSTL-18 Class II and HSTL outputs. The top and bottom I/O banks
support all single-ended I/O standards. Additionally, enhanced PLL
external clock output banks allow clock output capabilities such as
differential support for SSTL and HSTL.
Altera Corporation
May 2007
2–87
Stratix II Device Handbook, Volume 1
I/O Structure
Figure 2–57. Stratix II I/O Banks Notes (1), (2), (3), (4)
DQS8T
VREF0B3
DQS7T
VREF1B3
DQS6T
VREF2B3
VREF3B3
DQS5T
VREF4B3
PLL11
PLL5
Bank 11
Bank 9
DQS4T
DQS3T
DQS2T
DQS1T
DQS0T
VREF0B4
VREF1B4
VREF2B4
VREF3B4
VREF4B4
PLL7
PLL10
VR EF1B 5
VREF 4B5
VREF 0B2
I/O banks 1, 2, 5 & 6 support LVTTL, LVCMOS,
2.5-V, 1.8-V, 1.5-V, SSTL-2, SSTL-18 Class I,
HSTL-18 Class I, HSTL-15 Class I, LVDS, and
HyperTransport standards for input and output
operations. HSTL-18 Class II, HSTL-15-Class II,
SSTL-18 Class II standards are only supported
for input operations.
PLL1
PLL4
VR EF1B6
VREF 2B6
Bank 6
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
VREF 4B6
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
VREF 3B6
I/O banks 7, 8, 10 & 12 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
VREF 0B1
VREF 1B1
Bank 1
VR EF3B1
VR EF0B6
PLL3
VR EF4B1
PLL2
VREF 2B1
VR EF2B5
I/O banks 3, 4, 9 & 11 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
Bank 5
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
VR EF3B5
Bank 2
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
VR EF1B2
VR EF2B2
VR EF3B 2
VREF 0B5
Bank 4
VREF 4B2
Bank 3
Bank 8
Bank 12
Bank 10
PLL12
PLL6
Bank 7
PLL8
PLL9
VREF4B8
DQS8B
VREF3B8
VREF2B8
DQS7B
VREF1B8
DQS6B
VREF0B8
DQS5B
VREF4B7
VREF3B7
VREF2B7
VREF1B7
VREF0B7
DQS4B
DQS3B
DQS2B
DQS1B
DQS0B
Notes to Figure 2–57:
(1)
(2)
(3)
(4)
Figure 2–57 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical
representation only.
Depending on the size of the device, different device members have different numbers of VREF groups. Refer to the
pin list and the Quartus II software for exact locations.
Banks 9 through 12 are enhanced PLL external clock output banks. These PLL banks utilize the adjacent VREF group
when voltage-referenced standards are implemented. For example, if an SSTL input is implemented in PLL bank
10, the voltage level at VREFB7 is the reference voltage level for the SSTL input.
Horizontal I/O banks feature SERDES and DPA circuitry for high speed differential I/O standards. See the High
Speed Differential I/O Interfaces in Stratix II & Stratix II GX Devices chapter of the Stratix II Device Handbook, Volume 2
or the Stratix II GX Device Handbook, Volume 2 for more information on differential I/O standards.
2–88
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Altera Corporation
May 2007
Stratix II Architecture
Each I/O bank has its own VCCIO pins. A single device can support
1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different
VCCIO level independently. Each bank also has dedicated VREF pins to
support the voltage-referenced standards (such as SSTL-2). The PLL
banks utilize the adjacent VREF group when voltage-referenced
standards are implemented. For example, if an SSTL input is
implemented in PLL bank 10, the voltage level at VREFB7 is the reference
voltage level for the SSTL input.
I/O pins that reside in PLL banks 9 through 12 are powered by the
VCC_PLL<5, 6, 11, or 12>_OUT pins, respectively. The EP2S60F484,
EP2S60F780, EP2S90H484, EP2S90F780, and EP2S130F780 devices do not
support PLLs 11 and 12. Therefore, any I/O pins that reside in bank 11 are
powered by the VCCIO3 pin, and any I/O pins that reside in bank 12 are
powered by the VCCIO8 pin.
Each I/O bank can support multiple standards with the same VCCIO for
input and output pins. Each bank can support one VREF voltage level. For
example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, and
3.3-V PCI for inputs and outputs.
On-Chip Termination
Stratix II devices provide differential (for the LVDS or HyperTransport
technology I/O standard), series, and parallel on-chip termination to
reduce reflections and maintain signal integrity. On-chip termination
simplifies board design by minimizing the number of external
termination resistors required. Termination can be placed inside the
package, eliminating small stubs that can still lead to reflections.
Stratix II devices provide four types of termination:
■
■
■
■
Altera Corporation
May 2007
Differential termination (RD)
Series termination (RS) without calibration
Series termination (RS) with calibration
Parallel termination (RT) with calibration
2–89
Stratix II Device Handbook, Volume 1
I/O Structure
Table 2–17 shows the Stratix II on-chip termination support per I/O bank.
Table 2–17. On-Chip Termination Support by I/O Banks (Part 1 of 2)
On-Chip Termination Support
Series termination without
calibration
I/O Standard Support
Top & Bottom Banks
Left & Right Banks
3.3-V LVTTL
v
v
3.3-V LVCMOS
v
v
2.5-V LVTTL
v
v
2.5-V LVCMOS
v
v
1.8-V LVTTL
v
v
1.8-V LVCMOS
v
v
1.5-V LVTTL
v
v
1.5-V LVCMOS
v
v
SSTL-2 Class I and II
v
v
SSTL-18 Class I
v
v
SSTL-18 Class II
v
1.8-V HSTL Class I
v
1.8-V HSTL Class II
v
1.5-V HSTL Class I
v
1.2-V HSTL
v
2–90
Stratix II Device Handbook, Volume 1
v
v
Altera Corporation
May 2007
Stratix II Architecture
Table 2–17. On-Chip Termination Support by I/O Banks (Part 2 of 2)
On-Chip Termination Support
Series termination with
calibration
Parallel termination with
calibration
Differential termination (1)
I/O Standard Support
Top & Bottom Banks
3.3-V LVTTL
v
3.3-V LVCMOS
v
2.5-V LVTTL
v
2.5-V LVCMOS
v
1.8-V LVTTL
v
1.8-V LVCMOS
v
1.5-V LVTTL
v
1.5-V LVCMOS
v
SSTL-2 Class I and II
v
SSTL-18 Class I and II
v
1.8-V HSTL Class I
v
1.8-V HSTL Class II
v
1.5-V HSTL Class I
v
1.2-V HSTL
v
SSTL-2 Class I and II
v
SSTL-18 Class I and II
v
1.8-V HSTL Class I
v
1.8-V HSTL Class II
v
1.5-V HSTL Class I and II
v
1.2-V HSTL
v
Left & Right Banks
LVDS
v
HyperTransport technology
v
Note to Table 2–17:
(1)
Clock pins CLK1, CLK3, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential on-chip
termination. Clock pins CLK0, CLK2, CLK8, and CLK10 do support differential on-chip termination. Clock pins in
the top and bottom banks (CLK[4..7, 12..15]) do not support differential on-chip termination.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
I/O Structure
Differential On-Chip Termination
Stratix II devices support internal differential termination with a nominal
resistance value of 100 Ω for LVDS or HyperTransport technology input
receiver buffers. LVPECL input signals (supported on clock pins only)
require an external termination resistor. Differential on-chip termination
is supported across the full range of supported differential data rates as
shown in the DC & Switching Characteristics chapter in volume 1 of the
Stratix II Device Handbook.
f
For more information on differential on-chip termination, refer to the
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook.
f
For more information on tolerance specifications for differential on-chip
termination, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook.
On-Chip Series Termination Without Calibration
Stratix II devices support driver impedance matching to provide the I/O
driver with controlled output impedance that closely matches the
impedance of the transmission line. As a result, reflections can be
significantly reduced. Stratix II devices support on-chip series
termination for single-ended I/O standards with typical RS values of 25
and 50 Ω. Once matching impedance is selected, current drive strength is
no longer selectable. Table 2–17 shows the list of output standards that
support on-chip series termination without calibration.
On-Chip Series Termination with Calibration
Stratix II devices support on-chip series termination with calibration in
column I/O pins in top and bottom banks. There is one calibration circuit
for the top I/O banks and one circuit for the bottom I/O banks. Each
on-chip series termination calibration circuit compares the total
impedance of each I/O buffer to the external 25- or 50-Ω resistors
connected to the RUP and RDN pins, and dynamically enables or disables
the transistors until they match. Calibration occurs at the end of device
configuration. Once the calibration circuit finds the correct impedance, it
powers down and stops changing the characteristics of the drivers.
f
For more information on series on-chip termination supported by
Stratix II devices, refer to the Selectable I/O Standards in Stratix II &
Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook
or the Stratix II GX Device Handbook.
2–92
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
f
For more information on tolerance specifications for on-chip termination
with calibration, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook.
On-Chip Parallel Termination with Calibration
Stratix II devices support on-chip parallel termination with calibration for
column I/O pins only. There is one calibration circuit for the top I/O
banks and one circuit for the bottom I/O banks. Each on-chip parallel
termination calibration circuit compares the total impedance of each I/O
buffer to the external 50-Ω resistors connected to the RUP and RDN pins
and dynamically enables or disables the transistors until they match.
Calibration occurs at the end of device configuration. Once the calibration
circuit finds the correct impedance, it powers down and stops changing
the characteristics of the drivers.
1
On-chip parallel termination with calibration is only supported
for input pins.
f
For more information on on-chip termination supported by Stratix II
devices, refer to the Selectable I/O Standards in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
Stratix II GX Device Handbook.
f
For more information on tolerance specifications for on-chip termination
with calibration, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook.
MultiVolt I/O Interface
The Stratix II architecture supports the MultiVolt I/O interface feature
that allows Stratix II devices in all packages to interface with systems of
different supply voltages.
The Stratix II VCCINT pins must always be connected to a 1.2-V power
supply. With a 1.2-V VCCINT level, input pins are 1.5-, 1.8-, 2.5-, and 3.3-V
tolerant. The VCCIO pins can be connected to either a 1.5-, 1.8-, 2.5-, or
3.3-V power supply, depending on the output requirements. The output
levels are compatible with systems of the same voltage as the power
supply (for example, when VCCIO pins are connected to a 1.5-V power
supply, the output levels are compatible with 1.5-V systems).
The Stratix II VCCPD power pins must be connected to a 3.3-V power
supply. These power pins are used to supply the pre-driver power to the
output buffers, which increases the performance of the output pins. The
VCCPD pins also power configuration input pins and JTAG input pins.
Altera Corporation
May 2007
2–93
Stratix II Device Handbook, Volume 1
I/O Structure
Table 2–18 summarizes Stratix II MultiVolt I/O support.
Table 2–18. Stratix II MultiVolt I/O Support Note (1)
Input Signal (V)
VCCIO (V)
1.2
Output Signal (V)
1.2
1.5
1.8
2.5
3.3
1.2
(4)
v (2)
v (2)
v (2)
v (2)
v (4)
1.5
1.8
1.5
(4)
v
v
v (2)
v (2)
v (3)
v
1.8
(4)
v
v
v (2)
v (2)
v (3)
v (3)
v
2.5
2.5
(4)
v
v
v (3)
v (3)
v (3)
v
3.3
(4)
v
v
v (3)
v (3)
v (3)
v (3)
3.3
5.0
v
v
Notes to Table 2–18:
(1)
(2)
(3)
(4)
To drive inputs higher than VCCIO but less than 4.0 V, disable the PCI clamping diode and select the Allow LVTTL
and LVCMOS input levels to overdrive input buffer option in the Quartus II software.
The pin current may be slightly higher than the default value. You must verify that the driving device’s VO L
maximum and VO H minimum voltages do not violate the applicable Stratix II VI L maximum and VI H minimum
voltage specifications.
Although VCCIO specifies the voltage necessary for the Stratix II device to drive out, a receiving device powered at
a different level can still interface with the Stratix II device if it has inputs that tolerate the VCCIO value.
Stratix II devices do not support 1.2-V LVTTL and 1.2-V LVCMOS. Stratix II devices support 1.2-V HSTL.
The TDO and nCEO pins are powered by VCCIO of the bank that they reside
in. TDO is in I/O bank 4 and nCEO is in I/O bank 7.
Ideally, the VCC supplies for the I/O buffers of any two connected pins are
at the same voltage level. This may not always be possible depending on
the VCCIO level of TDO and nCEO pins on master devices and the
configuration voltage level chosen by VCCSEL on slave devices. Master
and slave devices can be in any position in the chain. Master indicates that
it is driving out TDO or nCEO to a slave device.
For multi-device passive configuration schemes, the nCEO pin of the
master device drives the nCE pin of the slave device. The VCCSEL pin on
the slave device selects which input buffer is used for nCE. When VCCSEL
is logic high, it selects the 1.8-V/1.5-V buffer powered by VCCIO. When
VCCSEL is logic low it selects the 3.3-V/2.5-V input buffer powered by
VCCPD. The ideal case is to have the VCCIO of the nCEO bank in a master
device match the VCCSEL settings for the nCE input buffer of the slave
device it is connected to, but that may not be possible depending on the
application. Table 2–19 contains board design recommendations to
ensure that nCEO can successfully drive nCE for all power supply
combinations.
2–94
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Table 2–19. Board Design Recommendations for nCEO
Stratix II nCEO VCCIO Voltage Level in I/O Bank 7
nCE Input Buffer Power in I/O
Bank 3
VC C I O =
3.3 V
VC C I O =
2.5 V
VC C I O =
1.8 V
VC C I O =
1.5 V
VC C I O =
1.2 V
VCCSEL high
(VC C I O Bank 3 = 1.5 V)
v(1), (2)
v (3), (4)
v (5)
v
v
VCCSEL high
(VC C I O Bank 3 = 1.8 V)
v (1), (2)
v (3), (4)
v
v
Level shifter
required
v
v (4)
v (6)
Level shifter
required
Level shifter
required
VCCSEL low
(nCE Powered by VC C P D = 3.3V)
Notes to Table 2–19:
(1)
(2)
(3)
(4)
(5)
(6)
Input buffer is 3.3-V tolerant.
The nCEO output buffer meets VO H (MIN) = 2.4 V.
Input buffer is 2.5-V tolerant.
The nCEO output buffer meets VOH (MIN) = 2.0 V.
Input buffer is 1.8-V tolerant.
An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
For JTAG chains, the TDO pin of the first device drives the TDI pin of the
second device in the chain. The VCCSEL input on JTAG input I/O cells
(TCK, TMS, TDI, and TRST) is internally hardwired to GND selecting the
3.3-V/2.5-V input buffer powered by VCCPD. The ideal case is to have the
VCCIO of the TDO bank from the first device to match the VCCSEL settings
for TDI on the second device, but that may not be possible depending on
the application. Table 2–20 contains board design recommendations to
ensure proper JTAG chain operation.
Table 2–20. Supported TDO/TDI Voltage Combinations (Part 1 of 2)
Device
Stratix II
Stratix II TDO VC C I O Voltage Level in I/O Bank 4
TDI Input
Buffer Power V
C C I O = 3.3 V VC C I O = 2.5 V VC C I O = 1.8 V VC C I O = 1.5 V VC C I O = 1.2 V
Always
VC C P D (3.3V)
Altera Corporation
May 2007
v (1)
v (2)
v (3)
Level shifter
required
Level shifter
required
2–95
Stratix II Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
Table 2–20. Supported TDO/TDI Voltage Combinations (Part 2 of 2)
Device
Stratix II TDO VC C I O Voltage Level in I/O Bank 4
TDI Input
Buffer Power V
C C I O = 3.3 V VC C I O = 2.5 V VC C I O = 1.8 V VC C I O = 1.5 V VC C I O = 1.2 V
v (1)
v (2)
v (3)
Level shifter
required
Level shifter
required
VCC = 2.5 V
v (1), (4)
v (2)
v (3)
Level shifter
required
Level shifter
required
VCC = 1.8 V
v (1), (4)
v (2), (5)
v
Level shifter
required
Level shifter
required
VCC = 1.5 V
v (1), (4)
v (2), (5)
v (6)
v
v
Non-Stratix II VCC = 3.3 V
Notes to Table 2–20:
(1)
(2)
(3)
(4)
(5)
(6)
The TDO output buffer meets VOH (MIN) = 2.4 V.
The TDO output buffer meets VOH (MIN) = 2.0 V.
An external 250-Ω pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
Input buffer must be 3.3-V tolerant.
Input buffer must be 2.5-V tolerant.
Input buffer must be 1.8-V tolerant.
High-Speed
Differential I/O
with DPA
Support
Stratix II devices contain dedicated circuitry for supporting differential
standards at speeds up to 1 Gbps. The LVDS and HyperTransport
differential I/O standards are supported in the Stratix II device. In
addition, the LVPECL I/O standard is supported on input and output
clock pins on the top and bottom I/O banks.
The high-speed differential I/O circuitry supports the following high
speed I/O interconnect standards and applications:
■
■
■
■
SPI-4 Phase 2 (POS-PHY Level 4)
SFI-4
Parallel RapidIO
HyperTransport technology
There are four dedicated high-speed PLLs in the EP2S15 to EP2S30
devices and eight dedicated high-speed PLLs in the EP2S60 to EP2S180
devices to multiply reference clocks and drive high-speed differential
SERDES channels.
Tables 2–21 through 2–26 show the number of channels that each fast PLL
can clock in each of the Stratix II devices. In Tables 2–21 through 2–26 the
first row for each transmitter or receiver provides the number of channels
driven directly by the PLL. The second row below it shows the maximum
channels a PLL can drive if cross bank channels are used from the
adjacent center PLL. For example, in the 484-pin FineLine BGA EP2S15
2–96
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
device, PLL 1 can drive a maximum of 10 transmitter channels in I/O
bank 1 or a maximum of 19 transmitter channels in I/O banks 1 and 2. The
Quartus II software may also merge receiver and transmitter PLLs when
a receiver is driving a transmitter. In this case, one fast PLL can drive both
the maximum numbers of receiver and transmitter channels.
Table 2–21. EP2S15 Device Differential Channels
Package
484-pin FineLine BGA
672-pin FineLine BGA
Transmitter/
Receiver
484-pin FineLine BGA
672-pin FineLine BGA
Altera Corporation
May 2007
Center Fast PLLs
Total
Channels
PLL 1
PLL 2
PLL 3
PLL 4
Transmitter
38 (2)
10
9
9
10
(3)
19
19
19
19
Receiver
42 (2)
11
10
10
11
(3)
21
21
21
21
Transmitter
38 (2)
10
9
9
10
(3)
19
19
19
19
Receiver
42 (2)
11
10
10
11
(3)
21
21
21
21
Table 2–22. EP2S30 Device Differential Channels
Package
Note (1)
Transmitter/
Receiver
Note (1)
Center Fast PLLs
Total
Channels
PLL 1
PLL 2
PLL 3
PLL 4
Transmitter
38 (2)
10
9
9
10
(3)
19
19
19
19
Receiver
42 (2)
11
10
10
11
(3)
21
21
21
21
Transmitter
58 (2)
16
13
13
16
(3)
29
29
29
29
Receiver
62 (2)
17
14
14
17
(3)
31
31
31
31
2–97
Stratix II Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
Table 2–23. EP2S60 Differential Channels
Package
484-pin
FineLine BGA
Center Fast PLLs
Transmitter/
Total
Receiver Channels PLL 1 PLL 2 PLL 3 PLL 4
Transmitter
Receiver
672-pin
FineLine BGA
Transmitter
Receiver
1,020-pin
FineLine BGA
Note (1)
Transmitter
Receiver
Receiver
780-pin
FineLine BGA
Transmitter
Receiver
1,020-pin
FineLine BGA
Transmitter
Receiver
1,508-pin
FineLine BGA
Transmitter
Receiver
PLL 8
PLL 9 PLL 10
10
9
9
10
10
9
9
10
(3)
19
19
19
19
-
-
-
-
42 (2)
11
10
10
11
11
10
10
11
(3)
21
21
21
21
-
-
-
-
58 (2)
16
13
13
16
16
13
13
16
(3)
29
29
29
29
-
-
-
-
62 (2)
17
14
14
17
17
14
14
17
(3)
31
31
31
31
-
-
-
-
84 (2)
21
21
21
21
21
21
21
21
(3)
42
42
42
42
-
-
-
-
84 (2)
21
21
21
21
21
21
21
21
(3)
42
42
42
42
-
-
-
-
Note (1)
Center Fast PLLs
Transmitter/
Total
Receiver Channels PLL 1 PLL 2 PLL 3 PLL 4
484-pin Hybrid Transmitter
FineLine BGA
PLL 7
38 (2)
Table 2–24. EP2S90 Differential Channels
Package
Corner Fast PLLs (4)
Corner Fast PLLs (4)
PLL 7
PLL 8
PLL 9 PLL 10
38 (2)
10
9
9
10
-
-
-
-
(3)
19
19
19
19
-
-
-
-
42 (2)
11
10
10
11
-
-
-
-
(3)
21
21
21
21
-
-
-
-
64 (2)
16
16
16
16
-
-
-
(3)
32
32
32
32
-
-
-
-
68 (2)
17
17
17
17
-
-
-
-
(3)
34
34
34
34
-
-
-
90 (2)
23
22
22
23
23
22
22
23
(3)
45
45
45
45
-
-
-
-
94 (2)
23
24
24
23
23
24
24
23
(3)
46
46
46
46
-
-
-
-
118 (2)
30
29
29
30
30
29
29
30
(3)
59
59
59
59
-
-
-
-
118 (2)
30
29
29
30
30
29
29
30
(3)
59
59
59
59
-
-
-
-
2–98
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Table 2–25. EP2S130 Differential Channels
Package
780-pin
FineLine BGA
Center Fast PLLs
Transmitter/
Total
Receiver Channels PLL 1 PLL 2 PLL 3 PLL 4
Transmitter
Receiver
1,020-pin
FineLine BGA
Transmitter
Receiver
1,508-pin
FineLine BGA
Transmitter
Receiver
1,020-pin
FineLine BGA
Receiver
1,508-pin
FineLine BGA
Transmitter
Receiver
PLL 7
PLL 8
PLL 9 PLL 10
16
16
16
16
-
-
-
(3)
32
32
32
32
-
-
-
-
68 (2)
17
17
17
17
-
-
-
-
(3)
34
34
34
34
-
-
-
88 (2)
22
22
22
22
22
22
22
22
(3)
44
44
44
44
-
-
-
-
92 (2)
23
23
23
23
23
23
23
23
(3)
46
46
46
46
-
-
-
-
156 (2)
37
41
41
37
37
41
41
37
(3)
78
78
78
78
-
-
-
-
156 (2)
37
41
41
37
37
41
41
37
(3)
78
78
78
78
-
-
-
-
Note (1)
Center Fast PLLs
Transmitter/
Total
Receiver Channels PLL 1 PLL 2 PLL 3 PLL 4
Transmitter
Corner Fast PLLs (4)
64 (2)
Table 2–26. EP2S180 Differential Channels
Package
Note (1)
Corner Fast PLLs (4)
PLL 7
PLL 8
PLL 9 PLL 10
88 (2)
22
22
22
22
22
22
22
22
(3)
44
44
44
44
-
-
-
-
92 (2)
23
23
23
23
23
23
23
23
(3)
46
46
46
46
-
-
-
-
156 (2)
37
41
41
37
37
41
41
37
(3)
78
78
78
78
-
-
-
-
156 (2)
37
41
41
37
37
41
41
37
(3)
78
78
78
78
-
-
-
-
Notes to Tables 2–21 to 2–26:
(1)
(2)
(3)
(4)
The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used
as data channels.
This is the maximum number of channels the PLLs can directly drive.
This is the maximum number of channels if the device uses cross bank channels from the adjacent center PLL.
The channels accessible by the center fast PLL overlap with the channels accessible by the corner fast PLL.
Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and
4 with the number of channels accessible by PLLs 7, 8, 9, and 10.
Altera Corporation
May 2007
2–99
Stratix II Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
Dedicated Circuitry with DPA Support
Stratix II devices support source-synchronous interfacing with LVDS or
HyperTransport signaling at up to 1 Gbps. Stratix II devices can transmit
or receive serial channels along with a low-speed or high-speed clock.
The receiving device PLL multiplies the clock by an integer factor W = 1
through 32. For example, a HyperTransport technology application
where the data rate is 1,000 Mbps and the clock rate is 500 MHz would
require that W be set to 2. The SERDES factor J determines the parallel
data width to deserialize from receivers or to serialize for transmitters.
The SERDES factor J can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to
equal the PLL clock-multiplication W value. A design using the dynamic
phase aligner also supports all of these J factor values. For a J factor of 1,
the Stratix II device bypasses the SERDES block. For a J factor of 2, the
Stratix II device bypasses the SERDES block, and the DDR input and
output registers are used in the IOE. Figure 2–58 shows the block diagram
of the Stratix II transmitter channel.
Figure 2–58. Stratix II Transmitter Channel
Data from R4, R24, C4, or
direct link interconnect
+
–
10
Local
Interconnect
Up to 1 Gbps
10
Dedicated
Transmitter
Interface
diffioclk
refclk
Fast
PLL
load_en
Regional or
global clock
Each Stratix II receiver channel features a DPA block for phase detection
and selection, a SERDES, a synchronizer, and a data realigner circuit. You
can bypass the dynamic phase aligner without affecting the basic sourcesynchronous operation of the channel. In addition, you can dynamically
switch between using the DPA block or bypassing the block via a control
signal from the logic array. Figure 2–59 shows the block diagram of the
Stratix II receiver channel.
2–100
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–59. Stratix II Receiver Channel
Data to R4, R24, C4, or
direct link interconnect
Up to 1 Gbps
+
–
D
Q
Data Realignment
Circuitry
10
data
retimed_data
DPA
Synchronizer
Dedicated
Receiver
Interface
DPA_clk
Eight Phase Clocks
8
diffioclk
refclk
Fast
PLL
load_en
Regional or
global clock
An external pin or global or regional clock can drive the fast PLLs, which
can output up to three clocks: two multiplied high-speed clocks to drive
the SERDES block and/or external pin, and a low-speed clock to drive the
logic array. In addition, eight phase-shifted clocks from the VCO can feed
to the DPA circuitry.
f
For more information on the fast PLL, see the PLLs in Stratix II &
Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook
or the Stratix II GX Device Handbook.
The eight phase-shifted clocks from the fast PLL feed to the DPA block.
The DPA block selects the closest phase to the center of the serial data eye
to sample the incoming data. This allows the source-synchronous
circuitry to capture incoming data correctly regardless of the channel-tochannel or clock-to-channel skew. The DPA block locks to a phase closest
to the serial data phase. The phase-aligned DPA clock is used to write the
data into the synchronizer.
The synchronizer sits between the DPA block and the data realignment
and SERDES circuitry. Since every channel utilizing the DPA block can
have a different phase selected to sample the data, the synchronizer is
needed to synchronize the data to the high-speed clock domain of the
data realignment and the SERDES circuitry.
Altera Corporation
May 2007
2–101
Stratix II Device Handbook, Volume 1
High-Speed Differential I/O with DPA Support
For high-speed source synchronous interfaces such as POS-PHY 4,
Parallel RapidIO, and HyperTransport, the source synchronous clock rate
is not a byte- or SERDES-rate multiple of the data rate. Byte alignment is
necessary for these protocols since the source synchronous clock does not
provide a byte or word boundary since the clock is one half the data rate,
not one eighth. The Stratix II device’s high-speed differential I/O
circuitry provides dedicated data realignment circuitry for usercontrolled byte boundary shifting. This simplifies designs while saving
ALM resources. You can use an ALM-based state machine to signal the
shift of receiver byte boundaries until a specified pattern is detected to
indicate byte alignment.
Fast PLL & Channel Layout
The receiver and transmitter channels are interleaved such that each I/O
bank on the left and right side of the device has one receiver channel and
one transmitter channel per LAB row. Figure 2–60 shows the fast PLL and
channel layout in the EP2S15 and EP2S30 devices. Figure 2–61 shows the
fast PLL and channel layout in the EP2S60 to EP2S180 devices.
Figure 2–60. Fast PLL & Channel Layout in the EP2S15 & EP2S30 Devices Note (1)
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
DPA
Clock
LVDS
Clock
4
4
4
2
2
4
Fast
PLL 1
Fast
PLL 4
Fast
PLL 2
Fast
PLL 3
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
DPA
Clock
LVDS
Clock
2
2
4
Note to Figure 2–60:
(1)
See Table 2–21 for the number of channels each device supports.
2–102
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Stratix II Architecture
Figure 2–61. Fast PLL & Channel Layout in the EP2S60 to EP2S180 Devices Note (1)
Fast
PLL 7
Fast
PLL 10
2
2
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
DPA
Clock
LVDS
Clock
4
4
4
2
2
4
Fast
PLL 1
Fast
PLL 4
Fast
PLL 2
Fast
PLL 3
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
DPA
Clock
LVDS
Clock
2
2
2
4
2
Fast
PLL 8
Fast
PLL 9
Note to Figure 2–61:
(1)
See Tables 2–22 through 2–26 for the number of channels each device supports.
Altera Corporation
May 2007
2–103
Stratix II Device Handbook, Volume 1
Document Revision History
Document
Revision History
Table 2–27 shows the revision history for this chapter.
Table 2–27. Document Revision History (Part 1 of 2)
Date and
Document
Version
Changes Made
Summary of Changes
—
May 2007, v4.3 Updated “Clock Control Block” section.
Updated note in the “Clock Control Block” section.
—
Deleted Tables 2-11 and 2-12.
—
Updated notes to:
Figure 2–41
● Figure 2–42
● Figure 2–43
● Figure 2–45
—
Updated notes to Table 2–18.
—
Moved Document Revision History to end of the chapter.
—
August 2006,
v4.2
Updated Table 2–18 with note.
—
April 2006,
v4.1
●
●
●
●
●
●
Updated Table 2–13.
Removed Note 2 from Table 2–16.
Updated “On-Chip Termination” section and Table 2–19 to
include parallel termination with calibration information.
Added new “On-Chip Parallel Termination with Calibration”
section.
Updated Figure 2–44.
December
2005, v4.0
Updated “Clock Control Block” section.
July 2005, v3.1
●
●
●
May 2005, v3.0
●
●
●
●
●
●
March 2005,
2.1
●
●
●
●
Added parallel onchip termination
description and
specification.
Changed RCLK
names to match the
Quartus II software in
Table 2–13.
—
Updated HyperTransport technology information in Table 2–18.
Updated HyperTransport technology information in
Figure 2–57.
Added information on the asynchronous clear signal.
—
Updated “Functional Description” section.
Updated Table 2–3.
Updated “Clock Control Block” section.
Updated Tables 2–17 through 2–19.
Updated Tables 2–20 through 2–22.
Updated Figure 2–57.
—
Updated “Functional Description” section.
Updated Table 2–3.
—
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May 2007
Stratix II Architecture
Table 2–27. Document Revision History (Part 2 of 2)
Date and
Document
Version
January 2005,
v2.0
Changes Made
Summary of Changes
—
●
Updated the “MultiVolt I/O Interface” and “TriMatrix Memory”
sections.
Updated Tables 2–3, 2–17, and 2–19.
October 2004,
v1.2
●
Updated Tables 2–9, 2–16, 2–26, and 2–27.
—
July 2004, v1.1
●
Updated note to Tables 2–9 and 2–16.
Updated Tables 2–16, 2–17, 2–18, 2–19, and 2–20.
Updated Figures 2–41, 2–42, and 2–57.
Removed 3 from list of SERDES factor J.
Updated “High-Speed Differential I/O with DPA Support”
section.
In “Dedicated Circuitry with DPA Support” section, removed
XSBI and changed RapidIO to Parallel RapidIO.
—
●
●
●
●
●
●
February 2004, Added document to the Stratix II Device Handbook.
v1.0
Altera Corporation
May 2007
—
2–105
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Document Revision History
2–106
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
3. Configuration & Testing
SII51003-4.2
IEEE Std. 1149.1
JTAG BoundaryScan Support
All Stratix® II devices provide Joint Test Action Group (JTAG)
boundary-scan test (BST) circuitry that complies with the IEEE
Std. 1149.1. JTAG boundary-scan testing can be performed either before
or after, but not during configuration. Stratix II devices can also use the
JTAG port for configuration with the Quartus® II software or hardware
using either Jam Files (.jam) or Jam Byte-Code Files (.jbc).
Stratix II devices support IOE I/O standard setting reconfiguration
through the JTAG BST chain. The JTAG chain can update the I/O
standard for all input and output pins any time before or during user
mode through the CONFIG_IO instruction. You can use this capability
for JTAG testing before configuration when some of the Stratix II pins
drive or receive from other devices on the board using voltage-referenced
standards. Because the Stratix II device may not be configured before
JTAG testing, the I/O pins may not be configured for appropriate
electrical standards for chip-to-chip communication. Programming those
I/O standards via JTAG allows you to fully test I/O connections to other
devices.
A device operating in JTAG mode uses four required pins, TDI,TDO, TMS,
and TCK, and one optional pin, TRST. The TCK pin has an internal weak
pull-down resistor, while the TDI,TMS and TRST pins have weak internal
pull-ups. The JTAG input pins are powered by the 3.3-V VCCPD pins. The
TDO output pin is powered by the VCCIO power supply of bank 4.
Stratix II devices also use the JTAG port to monitor the logic operation of
the device with the SignalTap® II embedded logic analyzer. Stratix II
devices support the JTAG instructions shown in Table 3–1.
1
Stratix II, Stratix, Cyclone® II, and Cyclone devices must be
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix II, Stratix,
Cyclone II, or Cyclone devices are in the 18th of further position,
they fail configuration. This does not affect SignalTap II.
The Stratix II device instruction register length is 10 bits and the
USERCODE register length is 32 bits. Tables 3–2 and 3–3 show the
boundary-scan register length and device IDCODE information for
Stratix II devices.
Altera Corporation
May 2007
3–1
IEEE Std. 1149.1 JTAG Boundary-Scan Support
Table 3–1. Stratix II JTAG Instructions
JTAG Instruction
Instruction Code
Description
SAMPLE/PRELOAD
00 0000 0101
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
EXTEST(1)
00 0000 1111
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
BYPASS
11 1111 1111
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
USERCODE
00 0000 0111
Selects the 32-bit USERCODE register and places it between the
TDI and TDO pins, allowing the USERCODE to be serially shifted
out of TDO.
IDCODE
00 0000 0110
Selects the IDCODE register and places it between TDI and TDO,
allowing the IDCODE to be serially shifted out of TDO.
HIGHZ (1)
00 0000 1011
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
CLAMP (1)
00 0000 1010
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
ICR instructions
Used when configuring a Stratix II device via the JTAG port with a
USB Blaster, MasterBlaster™, ByteBlasterMV™, or ByteBlaster II
download cable, or when using a .jam or .jbc via an embedded
processor or JRunner.
PULSE_NCONFIG
00 0000 0001
Emulates pulsing the nCONFIG pin low to trigger reconfiguration
even though the physical pin is unaffected.
CONFIG_IO (2)
00 0000 1101
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, during, or after
configuration. Stops configuration if executed during configuration.
Once issued, the CONFIG_IO instruction holds nSTATUS low to
reset the configuration device. nSTATUS is held low until the IOE
configuration register is loaded and the TAP controller state
machine transitions to the UPDATE_DR state.
SignalTap II
instructions
Monitors internal device operation with the SignalTap II embedded
logic analyzer.
Notes to Table 3–1:
(1)
(2)
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
For more information on using the CONFIG_IO instruction, see the MorphIO: An I/O Reconfiguration Solution for
Altera Devices White Paper.
3–2
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Altera Corporation
May 2007
Configuration & Testing
The Quartus II software has an Auto Usercode feature where you can
choose to use the checksum value of a programming file as the JTAG user
code. If selected, the checksum is automatically loaded to the USERCODE
register. Turn on the Auto Usercode option by clicking Device & Pin
Options, then General, in the Settings dialog box (Assignments menu).
Table 3–2. Stratix II Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EP2S15
1,140
EP2S30
1,692
EP2S60
2,196
EP2S90
2,748
EP2S130
3,420
EP2S180
3,948
Table 3–3. 32-Bit Stratix II Device IDCODE
IDCODE (32 Bits) (1)
Device
Version
(4 Bits)
Part Number (16 Bits)
Manufacturer Identity (11
LSB (1 Bit) (2)
Bits)
EP2S15
0000
0010 0000 1001 0001
000 0110 1110
1
EP2S30
0000
0010 0000 1001 0010
000 0110 1110
1
EP2S60
0001
0010 0000 1001 0011
000 0110 1110
1
EP2S90
0000
0010 0000 1001 0100
000 0110 1110
1
EP2S130
0000
0010 0000 1001 0101
000 0110 1110
1
EP2S180
0000
0010 0000 1001 0110
000 0110 1110
1
Notes to Table 3–3:
(1)
(2)
The most significant bit (MSB) is on the left.
The IDCODE's least significant bit (LSB) is always 1.
1
Altera Corporation
May 2007
Stratix, Stratix II, Cyclone, and Cyclone II devices must be
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix, Stratix II,
Cyclone, and Cyclone II devices are in the 18th or after they fail
configuration. This does not affect SignalTap II.
3–3
Stratix II Device Handbook, Volume 1
SignalTap II Embedded Logic Analyzer
f
For more information on JTAG, see the following documents:
■
■
The IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing for Stratix II &
Stratix II GX Devices chapter of the Stratix II Device Handbook,
Volume 2 or the Stratix II GX Device Handbook, Volume 2
Jam Programming & Test Language Specification
SignalTap II
Embedded Logic
Analyzer
Stratix II devices feature the SignalTap II embedded logic analyzer, which
monitors design operation over a period of time through the IEEE
Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed
without bringing internal signals to the I/O pins. This feature is
particularly important for advanced packages, such as FineLine BGA®
packages, because it can be difficult to add a connection to a pin during
the debugging process after a board is designed and manufactured.
Configuration
The logic, circuitry, and interconnects in the Stratix II architecture are
configured with CMOS SRAM elements. Altera® FPGA devices are
reconfigurable and every device is tested with a high coverage
production test program so you do not have to perform fault testing and
can instead focus on simulation and design verification.
Stratix II devices are configured at system power-up with data stored in
an Altera configuration device or provided by an external controller (e.g.,
a MAX® II device or microprocessor). Stratix II devices can be configured
using the fast passive parallel (FPP), active serial (AS), passive serial (PS),
passive parallel asynchronous (PPA), and JTAG configuration schemes.
The Stratix II device’s optimized interface allows microprocessors to
configure it serially or in parallel, and synchronously or asynchronously.
The interface also enables microprocessors to treat Stratix II devices as
memory and configure them by writing to a virtual memory location,
making reconfiguration easy.
In addition to the number of configuration methods supported, Stratix II
devices also offer the design security, decompression, and remote system
upgrade features. The design security feature, using configuration
bitstream encryption and AES technology, provides a mechanism to
protect your designs. The decompression feature allows Stratix II FPGAs
to receive a compressed configuration bitstream and decompress this
data in real-time, reducing storage requirements and configuration time.
The remote system upgrade feature allows real-time system upgrades
from remote locations of your Stratix II designs. For more information,
see “Configuration Schemes” on page 3–7.
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May 2007
Configuration & Testing
Operating Modes
The Stratix II architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power-up,
and before and during configuration. Together, the configuration and
initialization processes are called command mode. Normal device
operation is called user mode.
SRAM configuration elements allow Stratix II devices to be reconfigured
in-circuit by loading new configuration data into the device. With realtime reconfiguration, the device is forced into command mode with a
device pin. The configuration process loads different configuration data,
reinitializes the device, and resumes user-mode operation. You can
perform in-field upgrades by distributing new configuration files either
within the system or remotely.
PORSEL is a dedicated input pin used to select POR delay times of 12 ms
or 100 ms during power-up. When the PORSEL pin is connected to
ground, the POR time is 100 ms; when the PORSEL pin is connected to
VCC, the POR time is 12 ms.
The nIO PULLUP pin is a dedicated input that chooses whether the
internal pull-ups on the user I/O pins and dual-purpose configuration
I/O pins (nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY, nCS, CS,
RUnLU, PGM[2..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLR) are on or
off before and during configuration. A logic high (1.5, 1.8, 2.5, 3.3 V) turns
off the weak internal pull-ups, while a logic low turns them on.
Stratix II devices also offer a new power supply, VCCPD, which must be
connected to 3.3 V in order to power the 3.3-V/2.5-V buffer available on
the configuration input pins and JTAG pins. VCCPD applies to all the JTAG
input pins (TCK, TMS, TDI, and TRST) and the configuration input pins
when VCCSEL is connected to ground. See Table 3–4 for more information
on the pins affected by VCCSEL.
The VCCSEL pin allows the VCCIO setting (of the banks where the
configuration inputs reside) to be independent of the voltage required by
the configuration inputs. Therefore, when selecting the VCCIO, the VIL and
VIH levels driven to the configuration inputs do not have to be a concern.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Configuration
The PLL_ENA pin and the configuration input pins (Table 3–4) have a
dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V input
buffer. The VCCSEL input pin selects which input buffer is used. The 3.3V/2.5-V input buffer is powered by VCCPD, while the 1.8-V/1.5-V input
buffer is powered by VCCIO. Table 3–4 shows the pins affected by VCCSEL.
Table 3–4. Pins Affected by the Voltage Level at VCCSEL
Pin
VCCSEL = LOW (connected
to GND)
VCCSEL = HIGH (connected
to VCCPD)
3.3/2.5-V input buffer is
selected. Input buffer is
powered by VC C P D .
1.8/1.5-V input buffer is
selected. Input buffer is
powered by VC C I O of the I/O
bank.
nSTATUS (when
used as an input)
nCONFIG
CONF_DONE
(when used as an
input)
DATA[7..0]
nCE
DCLK (when used
as an input)
CS
nWS
nRS
nCS
CLKUSR
DEV_OE
DEV_CLRn
RUnLU
PLL_ENA
VCCSEL is sampled during power-up. Therefore, the VCCSEL setting
cannot change on the fly or during a reconfiguration. The VCCSEL input
buffer is powered by VCCINT and must be hardwired to VCCPD or ground.
A logic high VCCSEL connection selects the 1.8-V/1.5-V input buffer, and
a logic low selects the 3.3-V/2.5-V input buffer. VCCSEL should be set to
comply with the logic levels driven out of the configuration device or
MAX® II/microprocessor.
If you need to support configuration input voltages of 3.3 V/2.5 V, you
should set the VCCSEL to a logic low; you can set the VCCIO of the I/O
bank that contains the configuration inputs to any supported voltage. If
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Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Configuration & Testing
you need to support configuration input voltages of 1.8 V/1.5 V, you
should set the VCCSEL to a logic high and the VCCIO of the bank that
contains the configuration inputs to 1.8 V/1.5 V.
f
For more information on multi-volt support, including information on
using TDO and nCEO in multi-volt systems, refer to the Stratix II
Architecture chapter in volume 1 of the Stratix II Device Handbook.
Configuration Schemes
You can load the configuration data for a Stratix II device with one of five
configuration schemes (see Table 3–5), chosen on the basis of the target
application. You can use a configuration device, intelligent controller, or
the JTAG port to configure a Stratix II device. A configuration device can
automatically configure a Stratix II device at system power-up.
You can configure multiple Stratix II devices in any of the five
configuration schemes by connecting the configuration enable (nCE) and
configuration enable output (nCEO) pins on each device.
Stratix II FPGAs offer the following:
■
■
■
Configuration data decompression to reduce configuration file
storage
Design security using configuration data encryption to protect your
designs
Remote system upgrades for remotely updating your Stratix II
designs
Table 3–5 summarizes which configuration features can be used in each
configuration scheme.
Table 3–5. Stratix II Configuration Features (Part 1 of 2)
Configuration
Scheme
FPP
Configuration Method
MAX II device or microprocessor and
flash device
Design Security Decompression
v (1)
Enhanced configuration device
Remote System
Upgrade
v (1)
v
v (2)
v
AS
Serial configuration device
v
v
v (3)
PS
MAX II device or microprocessor and
flash device
v
v
v
Enhanced configuration device
v
v
v
Download cable (4)
v
v
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Configuration
Table 3–5. Stratix II Configuration Features (Part 2 of 2)
Configuration
Scheme
Configuration Method
PPA
MAX II device or microprocessor and
flash device
JTAG
Download cable (4)
Design Security Decompression
Remote System
Upgrade
v
MAX II device or microprocessor and
flash device
Notes for Table 3–5:
(1)
(2)
(3)
(4)
In these modes, the host system must send a DCLK that is 4× the data rate.
The enhanced configuration device decompression feature is available, while the Stratix II decompression feature
is not available.
Only remote update mode is supported when using the AS configuration scheme. Local update mode is not
supported.
The supported download cables include the Altera USB Blaster universal serial bus (USB) port download cable,
MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and the
ByteBlasterMV parallel port download cable.
f
See the Configuring Stratix II & Stratix II GX Devices chapter in volume 2
of the Stratix II Device Handbook or the Stratix II GX Device Handbook for
more information about configuration schemes in Stratix II and
Stratix II GX devices.
Device Security Using Configuration Bitstream Encryption
Stratix II FPGAs are the industry’s first FPGAs with the ability to decrypt
a configuration bitstream using the Advanced Encryption Standard
(AES) algorithm. When using the design security feature, a 128-bit
security key is stored in the Stratix II FPGA. To successfully configure a
Stratix II FPGA that has the design security feature enabled, it must be
configured with a configuration file that was encrypted using the same
128-bit security key. The security key can be stored in non-volatile
memory inside the Stratix II device. This non-volatile memory does not
require any external devices, such as a battery back-up, for storage.
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Stratix II Device Handbook, Volume 1
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May 2007
Configuration & Testing
1
An encryption configuration file is the same size as a nonencryption configuration file. When using a serial configuration
scheme such as passive serial (PS) or active serial (AS),
configuration time is the same whether or not the design
security feature is enabled. If the fast passive parallel (FPP)
scheme us used with the design security or decompression
feature, a 4× DCLK is required. This results in a slower
configuration time when compared to the configuration time of
an FPGA that has neither the design security, nor
decompression feature enabled. For more information about
this feature, refer to AN 341: Using the Design Security Feature in
Stratix II Devices. Contact your local Altera sales representative
to request this document.
Device Configuration Data Decompression
Stratix II FPGAs support decompression of configuration data, which
saves configuration memory space and time. This feature allows you to
store compressed configuration data in configuration devices or other
memory, and transmit this compressed bit stream to Stratix II FPGAs.
During configuration, the Stratix II FPGA decompresses the bit stream in
real time and programs its SRAM cells.
Stratix II FPGAs support decompression in the FPP (when using a
MAX II device/microprocessor and flash memory), AS and PS
configuration schemes. Decompression is not supported in the PPA
configuration scheme nor in JTAG-based configuration.
Remote System Upgrades
Shortened design cycles, evolving standards, and system deployments in
remote locations are difficult challenges faced by modern system
designers. Stratix II devices can help effectively deal with these
challenges with their inherent re-programmability and dedicated
circuitry to perform remote system updates. Remote system updates help
deliver feature enhancements and bug fixes without costly recalls, reduce
time to market, and extend product life.
Stratix II FPGAs feature dedicated remote system upgrade circuitry to
facilitate remote system updates. Soft logic (Nios® processor or user logic)
implemented in the Stratix II device can download a new configuration
image from a remote location, store it in configuration memory, and direct
the dedicated remote system upgrade circuitry to initiate a
reconfiguration cycle. The dedicated circuitry performs error detection
during and after the configuration process, recovers from any error
condition by reverting back to a safe configuration image, and provides
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Configuration
error status information. This dedicated remote system upgrade circuitry
avoids system downtime and is the critical component for successful
remote system upgrades.
RSC is supported in the following Stratix II configuration schemes: FPP,
AS, PS, and PPA. RSC can also be implemented in conjunction with
advanced Stratix II features such as real-time decompression of
configuration data and design security using AES for secure and efficient
field upgrades.
f
See the Remote System Upgrades With Stratix II & Stratix II GX Devices
chapter in volume 2 of the Stratix II Device Handbook or the Stratix II GX
Device Handbook for more information about remote configuration in
Stratix II devices.
Configuring Stratix II FPGAs with JRunner
JRunner is a software driver that configures Altera FPGAs, including
Stratix II FPGAs, through the ByteBlaster II or ByteBlasterMV cables in
JTAG mode. The programming input file supported is in Raw Binary File
(.rbf) format. JRunner also requires a Chain Description File (.cdf)
generated by the Quartus II software. JRunner is targeted for embedded
JTAG configuration. The source code is developed for the Windows NT
operating system (OS), but can be customized to run on other platforms.
f
For more information on the JRunner software driver, see the JRunner
Software Driver: An Embedded Solution to the JTAG Configuration White
Paper and the source files on the Altera web site (www.altera.com).
Programming Serial Configuration Devices with SRunner
A serial configuration device can be programmed in-system by an
external microprocessor using SRunner. SRunner is a software driver
developed for embedded serial configuration device programming that
can be easily customized to fit in different embedded systems. SRunner is
able to read a .rpd file (Raw Programming Data) and write to the serial
configuration devices. The serial configuration device programming time
using SRunner is comparable to the programming time when using the
Quartus II software.
f
For more information about SRunner, see the SRunner: An Embedded
Solution for EPCS Programming White Paper and the source code on the
Altera web site at www.altera.com.
f
For more information on programming serial configuration devices, see
the Serial Configuration Devices (EPCS1 & EPCS4) Data Sheet in the
Configuration Handbook.
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May 2007
Configuration & Testing
Configuring Stratix II FPGAs with the MicroBlaster Driver
The MicroBlasterTM software driver supports an RBF programming input
file and is ideal for embedded FPP or PS configuration. The source code
is developed for the Windows NT operating system, although it can be
customized to run on other operating systems. For more information on
the MicroBlaster software driver, see the Configuring the MicroBlaster Fast
Passive Parallel Software Driver White Paper or the Configuring the
MicroBlaster Passive Serial Software Driver White Paper on the Altera web
site (www.altera.com).
PLL Reconfiguration
The phase-locked loops (PLLs) in the Stratix II device family support
reconfiguration of their multiply, divide, VCO-phase selection, and
bandwidth selection settings without reconfiguring the entire device. You
can use either serial data from the logic array or regular I/O pins to
program the PLL’s counter settings in a serial chain. This option provides
considerable flexibility for frequency synthesis, allowing real-time
variation of the PLL frequency and delay. The rest of the device is
functional while reconfiguring the PLL.
f
Temperature
Sensing Diode
(TSD)
See the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of
the Stratix II Device Handbook or the Stratix II GX Device Handbook for
more information on Stratix II PLLs.
Stratix II devices include a diode-connected transistor for use as a
temperature sensor in power management. This diode is used with an
external digital thermometer device. These devices steer bias current
through the Stratix II diode, measuring forward voltage and converting
this reading to temperature in the form of an 8-bit signed number (7 bits
plus sign). The external device's output represents the junction
temperature of the Stratix II device and can be used for intelligent power
management.
The diode requires two pins (tempdiodep and tempdioden) on the
Stratix II device to connect to the external temperature-sensing device, as
shown in Figure 3–1. The temperature sensing diode is a passive element
and therefore can be used before the Stratix II device is powered.
Altera Corporation
May 2007
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Stratix II Device Handbook, Volume 1
Temperature Sensing Diode (TSD)
Figure 3–1. External Temperature-Sensing Diode
Stratix II Device
Temperature-Sensing
Device
tempdiodep
tempdioden
Table 3–6 shows the specifications for bias voltage and current of the
Stratix II temperature sensing diode.
Table 3–6. Temperature-Sensing Diode Electrical Characteristics
Parameter
IBIAS high
IBIAS low
VBP - VBN
VBN
Series resistance
3–12
Stratix II Device Handbook, Volume 1
Minimum
Typical
Maximum
Unit
80
100
120
μA
8
10
0.3
12
μA
0.9
V
3
Ω
0.7
V
Altera Corporation
May 2007
Configuration & Testing
The temperature-sensing diode works for the entire operating range, as
shown in Figure 3–2.
Figure 3–2. Temperature vs. Temperature-Sensing Diode Voltage
0.95
0.90
100 μA Bias Current
10 μA Bias Current
0.85
0.80
0.75
Voltage
(Across Diode)
0.70
0.65
0.60
0.55
0.50
0.45
0.40
–55
–30
–5
20
45
70
95
120
Temperature (˚C)
The temperature sensing diode is a very sensitive circuit which can be
influenced by noise coupled from other traces on the board, and possibly
within the device package itself, depending on device usage. The
interfacing device registers temperature based on milivolts of difference
as seen at the TSD. Switching I/O near the TSD pins can affect the
temperature reading. Altera recommends you take temperature readings
during periods of no activity in the device (for example, standby mode
where no clocks are toggling in the device), such as when the nearby I/Os
are at a DC state, and disable clock networks in the device.
Automated
Single Event
Upset (SEU)
Detection
Stratix II devices offer on-chip circuitry for automated checking of single
event upset (SEU) detection. Some applications that require the device to
operate error free at high elevations or in close proximity to Earth’s North
or South Pole require periodic checks to ensure continued data integrity.
The error detection cyclic redundancy check (CRC) feature controlled by
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May 2007
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Stratix II Device Handbook, Volume 1
Document Revision History
the Device & Pin Options dialog box in the Quartus II software uses a
32-bit CRC circuit to ensure data reliability and is one of the best options
for mitigating SEU.
You can implement the error detection CRC feature with existing circuitry
in Stratix II devices, eliminating the need for external logic. For Stratix II
devices, CRC is computed by the device during configuration and
checked against an automatically computed CRC during normal
operation. The CRC_ERROR pin reports a soft error when configuration
SRAM data is corrupted, triggering device reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built in the Stratix II devices to perform error
detection automatically. This error detection circuitry in Stratix II devices
constantly checks for errors in the configuration SRAM cells while the
device is in user mode. You can monitor one external pin for the error and
use it to trigger a re-configuration cycle. You can select the desired time
between checks by adjusting a built-in clock divider.
Software Interface
In the Quartus II software version 4.1 and later, you can turn on the
automated error detection CRC feature in the Device & Pin Options
dialog box. This dialog box allows you to enable the feature and set the
internal frequency of the CRC between 400 kHz to 50 MHz. This controls
the rate that the CRC circuitry verifies the internal configuration SRAM
bits in the FPGA device.
For more information on CRC, refer to AN 357: Error Detection Using CRC
in Altera FPGA Devices.
Document
Revision History
Table 3–7 shows the revision history for this chapter.
Table 3–7. Document Revision History (Part 1 of 2)
Date and
Document
Version
Changes Made
May 2007, v4.2 Moved Document Revision History section to the end
of the chapter.
Updated the “Temperature Sensing Diode (TSD)”
section.
3–14
Stratix II Device Handbook, Volume 1
Summary of Changes
—
—
Altera Corporation
May 2007
Configuration & Testing
Table 3–7. Document Revision History (Part 2 of 2)
Date and
Document
Version
Changes Made
Summary of Changes
April 2006,
v4.1
Updated “Device Security Using Configuration
Bitstream Encryption” section.
—
December
2005, v4.0
Updated “Software Interface” section.
—
May 2005, v3.0
●
January 2005,
v2.1
Updated JTAG chain device limits.
—
January 2005,
v2.0
Updated Table 3–3.
—
July 2004, v1.1
●
●
●
●
Updated “IEEE Std. 1149.1 JTAG Boundary-Scan
Support” section.
Updated “Operating Modes” section.
Added “Automated Single Event Upset (SEU)
Detection” section.
Updated “Device Security Using Configuration
Bitstream Encryption” section.
Updated Figure 3–2.
February 2004, Added document to the Stratix II Device Handbook.
v1.0
Altera Corporation
May 2007
—
—
—
3–15
Stratix II Device Handbook, Volume 1
Document Revision History
3–16
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
4. Hot Socketing &
Power-On Reset
SII51004-3.2
Stratix® II devices offer hot socketing, which is also known as hot plug-in
or hot swap, and power sequencing support without the use of any
external devices. You can insert or remove a Stratix II board in a system
during system operation without causing undesirable effects to the
running system bus or the board that was inserted into the system.
The hot socketing feature also removes some of the difficulty when you
use Stratix II devices on printed circuit boards (PCBs) that also contain a
mixture of 5.0-, 3.3-, 2.5-, 1.8-, 1.5- and 1.2-V devices. With the Stratix II hot
socketing feature, you no longer need to ensure a proper power-up
sequence for each device on the board.
The Stratix II hot socketing feature provides:
■
■
■
Board or device insertion and removal without external components
or board manipulation
Support for any power-up sequence
Non-intrusive I/O buffers to system buses during hot insertion
This chapter also discusses the power-on reset (POR) circuitry in Stratix II
devices. The POR circuitry keeps the devices in the reset state until the
VCC is within operating range.
Stratix II
Hot-Socketing
Specifications
Stratix II devices offer hot socketing capability with all three features
listed above without any external components or special design
requirements. The hot socketing feature in Stratix II devices allows:
■
■
■
Altera Corporation
May 2007
The device can be driven before power-up without any damage to
the device itself.
I/O pins remain tri-stated during power-up. The device does not
drive out before or during power-up, thereby affecting other buses in
operation.
Signal pins do not drive the VCCIO, VCCPD, or VCCINT power supplies.
External input signals to I/O pins of the device do not internally
power the VCCIO or VCCINT power supplies of the device via internal
paths within the device.
4–1
Stratix II Hot-Socketing Specifications
Devices Can Be Driven Before Power-Up
You can drive signals into the I/O pins, dedicated input pins and
dedicated clock pins of Stratix II devices before or during power-up or
power-down without damaging the device. Stratix II devices support any
power-up or power-down sequence (VCCIO, VCCINT, and VCCPD) in order
to simplify system level design.
I/O Pins Remain Tri-Stated During Power-Up
A device that does not support hot-socketing may interrupt system
operation or cause contention by driving out before or during power-up.
In a hot socketing situation, Stratix II device's output buffers are turned
off during system power-up or power-down. Stratix II device also does
not drive out until the device is configured and has attained proper
operating conditions.
Signal Pins Do Not Drive the VCCIO, VCCINT or VCCPD Power
Supplies
Devices that do not support hot-socketing can short power supplies
together when powered-up through the device signal pins. This irregular
power-up can damage both the driving and driven devices and can
disrupt card power-up.
Stratix II devices do not have a current path from I/O pins, dedicated
input pins, or dedicated clock pins to the VCCIO, VCCINT, or VCCPD pins
before or during power-up. A Stratix II device may be inserted into (or
removed from) a powered-up system board without damaging or
interfering with system-board operation. When hot-socketing, Stratix II
devices may have a minimal effect on the signal integrity of the
backplane.
1
■
■
You can power up or power down the VCCIO, VCCINT, and VCCPD
pins in any sequence. The power supply ramp rates can range
from 100 μs to 100 ms. All VCC supplies must power down
within 100 ms of each other to prevent I/O pins from driving
out. During hot socketing, the I/O pin capacitance is less than 15
pF and the clock pin capacitance is less than 20 pF. Stratix II
devices meet the following hot socketing specification.
The hot socketing DC specification is: | IIOPIN | < 300 μA.
The hot socketing AC specification is: | IIOPIN | < 8 mA for 10 ns or
less.
4–2
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Hot Socketing & Power-On Reset
IIOPIN is the current at any user I/O pin on the device. This specification
takes into account the pin capacitance, but not board trace and external
loading capacitance. Additional capacitance for trace, connector, and
loading needs must be considered separately. For the AC specification,
the peak current duration is 10 ns or less because of power-up transients.
For more information, refer to the Hot-Socketing & Power-Sequencing
Feature & Testing for Altera Devices white paper.
A possible concern regarding hot-socketing is the potential for latch-up.
Latch-up can occur when electrical subsystems are hot-socketed into an
active system. During hot-socketing, the signal pins may be connected
and driven by the active system before the power supply can provide
current to the device's VCC and ground planes. This condition can lead to
latch-up and cause a low-impedance path from VCC to ground within the
device. As a result, the device extends a large amount of current, possibly
causing electrical damage. Nevertheless, Stratix II devices are immune to
latch-up when hot-socketing.
Hot Socketing
Feature
Implementation
in Stratix II
Devices
The hot socketing feature turns off the output buffer during the power-up
event (either VCCINT, VCCIO, or VCCPD supplies) or power down. The hotsocket circuit will generate an internal HOTSCKT signal when either
VCCINT, VCCIO, or VCCPD is below threshold voltage. The HOTSCKT signal
will cut off the output buffer to make sure that no DC current (except for
weak pull up leaking) leaks through the pin. When VCC ramps up very
slowly, VCC is still relatively low even after the POR signal is released and
the configuration is finished. The CONF_DONE, nCEO, and nSTATUS pins
fail to respond, as the output buffer can not flip from the state set by the
hot socketing circuit at this low VCC voltage. Therefore, the hot socketing
circuit has been removed on these configuration pins to make sure that
they are able to operate during configuration. It is expected behavior for
these pins to drive out during power-up and power-down sequences.
Each I/O pin has the following circuitry shown in Figure 4–1.
Altera Corporation
May 2007
4–3
Stratix II Device Handbook, Volume 1
Hot Socketing Feature Implementation in Stratix II Devices
Figure 4–1. Hot Socketing Circuit Block Diagram for Stratix II Devices
Power On
Reset
Monitor
Output
Weak
Pull-Up
Resistor
PAD
R
Output Enable
Voltage
Tolerance
Control
Hot Socket
Output
Pre-Driver
Input Buffer
to Logic Array
The POR circuit monitors VCCINT voltage level and keeps I/O pins tristated until the device is in user mode. The weak pull-up resistor (R) from
the I/O pin to VCCIO is present to keep the I/O pins from floating. The
3.3-V tolerance control circuit permits the I/O pins to be driven by 3.3 V
before VCCIO and/or VCCINT and/or VCCPD are powered, and it prevents
the I/O pins from driving out when the device is not in user mode. The
hot socket circuit prevents I/O pins from internally powering VCCIO,
VCCINT, and VCCPD when driven by external signals before the device is
powered.
Figure 4–2 shows a transistor level cross section of the Stratix II device
I/O buffers. This design ensures that the output buffers do not drive
when VCCIO is powered before VCCINT or if the I/O pad voltage is higher
than VCCIO. This also applies for sudden voltage spikes during hot
insertion. There is no current path from signal I/O pins to VCCINT or VCCIO
or VCCPD during hot insertion. The VPAD leakage current charges the 3.3-V
tolerant circuit capacitance.
4–4
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
Hot Socketing & Power-On Reset
Figure 4–2. Transistor Level Diagram of FPGA Device I/O Buffers
VPAD
Logic Array
Signal
(1)
(2)
VCCIO
n+
n+
p-well
p+
p+
n+
n-well
p-substrate
Notes to Figure 4–2:
(1)
(2)
This is the logic array signal or the larger of either the VCCIO or VPAD signal.
This is the larger of either the VCCIO or VPAD signal.
Power-On Reset
Circuitry
Stratix II devices have a POR circuit to keep the whole device system in
reset state until the power supply voltage levels have stabilized during
power-up. The POR circuit monitors the VCCINT, VCCIO, and VCCPD voltage
levels and tri-states all the user I/O pins while VCC is ramping up until
normal user levels are reached. The POR circuitry also ensures that all
eight I/O bank VCCIO voltages, VCCPD voltage, as well as the logic array
VCCINT voltage, reach an acceptable level before configuration is
triggered. After the Stratix II device enters user mode, the POR circuit
continues to monitor the VCCINT voltage level so that a brown-out
condition during user mode can be detected. If there is a VCCINT voltage
sag below the Stratix II operational level during user mode, the POR
circuit resets the device.
When power is applied to a Stratix II device, a power-on-reset event
occurs if VCC reaches the recommended operating range within a certain
period of time (specified as a maximum VCC rise time). The maximum
VCC rise time for Stratix II device is 100 ms. Stratix II devices provide a
dedicated input pin (PORSEL) to select POR delay times of 12 or 100 ms
during power-up. When the PORSEL pin is connected to ground, the POR
time is 100 ms. When the PORSEL pin is connected to VCC, the POR time
is 12 ms.
Altera Corporation
May 2007
4–5
Stratix II Device Handbook, Volume 1
Document Revision History
Document
Revision History
Table 4–1 shows the revision history for this chapter.
Table 4–1. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
May 2007, v3.2 Moved the Document Revision History section to the
end of the chapter.
—
April 2006,
v3.1
●
Updated “Signal Pins Do Not Drive the VCCIO,
VCCINT or VCCPD Power Supplies” section.
May 2005, v3.0
●
Updated “Signal Pins Do Not Drive the VCCIO,
VCCINT or VCCPD Power Supplies” section.
Removed information on ESD protection.
January 2005,
v2.1
Updated input rise and fall time.
—
January 2005,
v2.0
Updated the “Hot Socketing Feature Implementation in
Stratix II Devices”, “ESD Protection”, and “Power-On
Reset Circuitry” sections.
—
July 2004, v1.1
●
●
●
Updated all tables.
Added tables.
February 2004, Added document to the Stratix II Device Handbook.
v1.0
4–6
Stratix II Device Handbook, Volume 1
●
Updated hot socketing AC
specification.
—
—
—
Altera Corporation
May 2007
5. DC & Switching
Characteristics
SII51005-4.5
Operating
Conditions
Stratix® II devices are offered in both commercial and industrial grades.
Industrial devices are offered in -4 speed grades and commercial devices
are offered in -3 (fastest), -4, -5 speed grades.
Tables 5–1 through 5–32 provide information about absolute maximum
ratings, recommended operating conditions, DC electrical characteristics,
and other specifications for Stratix II devices.
Absolute Maximum Ratings
Table 5–1 contains the absolute maximum ratings for the Stratix II device
family.
Table 5–1. Stratix II Device Absolute Maximum Ratings
Symbol
Parameter
Notes (1), (2), (3)
Conditions
Minimum
Maximum
Unit
VCCINT
Supply voltage
With respect to ground
–0.5
1.8
V
VCCIO
Supply voltage
With respect to ground
–0.5
4.6
V
VCCPD
Supply voltage
With respect to ground
–0.5
4.6
V
VCCA
Analog power supply for
PLLs
With respect to ground
–0.5
1.8
V
VCCD
Digital power supply for PLLs With respect to ground
–0.5
1.8
V
VI
DC input voltage (4)
–0.5
4.6
V
IOUT
DC output current, per pin
–25
40
mA
TSTG
Storage temperature
No bias
–65
150
°C
TJ
Junction temperature
BGA packages under bias
–55
125
°C
Notes to Tables 5–1
(1)
(2)
(3)
(4)
See the Operating Requirements for Altera Devices Data Sheet.
Conditions beyond those listed in Table 5–1 may cause permanent damage to a device. Additionally, device
operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.
Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
During transitions, the inputs may overshoot to the voltage shown in Table 5–2 based upon the input duty cycle.
The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
Altera Corporation
April 2011
5–1
Operating Conditions
Table 5–2. Maximum Duty Cycles in Voltage Transitions
Symbol
Parameter
Condition
Maximum
Duty Cycles
Unit
VI
Maximum duty cycles
in voltage transitions
VI = 4.0 V
100
%
VI = 4.1 V
90
%
VI = 4.2 V
50
%
VI = 4.3 V
30
%
VI = 4.4 V
17
%
VI = 4.5 V
10
%
Recommended Operating Conditions
Table 5–3 contains the Stratix II device family recommended operating
conditions.
Table 5–3. Stratix II Device Recommended Operating Conditions (Part 1 of 2)
Symbol
Parameter
Conditions
Note (1)
Minimum
Maximum Unit
VCCINT
Supply voltage for internal logic
100 μs ≤ risetime ≤ 100 ms (3)
1.15
1.25
V
VCCIO
Supply voltage for input and
output buffers, 3.3-V operation
100 μs ≤ risetime ≤ 100 ms (3), (6)
3.135
(3.00)
3.465
(3.60)
V
Supply voltage for input and
output buffers, 2.5-V operation
100 μs ≤ risetime ≤ 100 ms (3)
2.375
2.625
V
Supply voltage for input and
output buffers, 1.8-V operation
100 μs ≤ risetime ≤ 100 ms (3)
1.71
1.89
V
Supply voltage for output buffers, 100 μs ≤ risetime ≤ 100 ms (3)
1.5-V operation
1.425
1.575
V
Supply voltage for input and
output buffers, 1.2-V operation
100 μs ≤ risetime ≤ 100 ms (3)
1.14
1.26
V
VCCPD
Supply voltage for pre-drivers as
well as configuration and JTAG
I/O buffers.
100 μs ≤ risetime ≤ 100 ms (4)
3.135
3.465
V
VCCA
Analog power supply for PLLs
100 μs ≤ risetime ≤ 100 ms (3)
1.15
1.25
V
VCCD
Digital power supply for PLLs
100 μs ≤ risetime ≤ 100 ms (3)
1.15
1.25
V
VI
Input voltage (see Table 5–2)
(2), (5)
–0.5
4.0
V
VO
Output voltage
0
VCCIO
V
5–2
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–3. Stratix II Device Recommended Operating Conditions (Part 2 of 2)
Symbol
TJ
Parameter
Conditions
Operating junction temperature
Note (1)
Minimum
For commercial use
Maximum Unit
0
85
°C
For industrial use
–40
100
°C
For military use (7)
–55
125
°C
Notes to Table 5–3:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
During transitions, the inputs may overshoot to the voltage shown in Table 5–2 based upon the input duty cycle.
The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input
currents less than 100 mA and periods shorter than 20 ns.
Maximum VCC rise time is 100 ms, and VCC must rise monotonically from ground to VC C .
VCCPD must ramp-up from 0 V to 3.3 V within 100 μs to 100 ms. If VC C P D is not ramped up within this specified
time, your Stratix II device does not configure successfully. If your system does not allow for a VCCPD ramp-up time
of 100 ms or less, you must hold nCONFIG low until all power supplies are reliable.
All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT, VCCPD, and VCCIO
are powered.
VC C I O maximum and minimum conditions for PCI and PCI-X are shown in parentheses.
For more information, refer to the Stratix II Military Temperature Range Support technical brief.
DC Electrical Characteristics
Table 5–4 shows the Stratix II device family DC electrical characteristics.
Table 5–4. Stratix II Device DC Operating Conditions (Part 1 of 2)
Symbol
Parameter
Conditions
II
Input pin leakage current VI = VCCIOmax to 0 V (2)
IOZ
Tri-stated I/O pin
leakage current
VO = VCCIOmax to 0 V (2)
IC C I N T 0
VCCINT supply current
(standby)
VI = ground, no
load, no toggling
inputs
TJ = 25° C
ICCPD0
VCCPD supply current
(standby)
Altera Corporation
April 2011
VI = ground, no
load, no toggling
inputs
TJ = 25° C,
VCCPD = 3.3V
EP2S15
Note (1)
Minimum Typical Maximum Unit
–10
10
μA
–10
10
μA
(3)
A
0.25
EP2S30
0.30
(3)
A
EP2S60
0.50
(3)
A
EP2S90
0.62
(3)
A
EP2S130
0.82
(3)
A
EP2S180
1.12
(3)
A
EP2S15
2.2
(3)
mA
EP2S30
2.7
(3)
mA
EP2S60
3.6
(3)
mA
EP2S90
4.3
(3)
mA
EP2S130
5.4
(3)
mA
EP2S180
6.8
(3)
mA
5–3
Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–4. Stratix II Device DC Operating Conditions (Part 2 of 2)
Symbol
ICCI00
Parameter
Conditions
VCCIO supply current
(standby)
VI = ground, no
load, no toggling
inputs
TJ = 25° C
Note (1)
Minimum Typical Maximum Unit
EP2S15
4.0
(3)
mA
EP2S30
4.0
(3)
mA
EP2S60
4.0
(3)
mA
EP2S90
4.0
(3)
mA
EP2S130
4.0
(3)
mA
4.0
(3)
mA
Vi = 0; VCCIO = 3.3 V
10
25
50
kΩ
Vi = 0; VCCIO = 2.5 V
15
35
70
kΩ
Vi = 0; VCCIO = 1.8 V
30
50
100
kΩ
Vi = 0; VCCIO = 1.5 V
40
75
150
kΩ
Vi = 0; VCCIO = 1.2 V
50
90
170
kΩ
1
2
kΩ
EP2S180
RCONF (4) Value of I/O pin pull-up
resistor before and
during configuration
Recommended value of
I/O pin external
pull-down resistor before
and during configuration
Notes to Table 5–4:
(1)
(2)
(3)
(4)
Typical values are for TA = 25°C, VCCINT = 1.2 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
This value is specified for normal device operation. The value may vary during power-up. This applies for all
VCCIO settings (3.3, 2.5, 1.8, and 1.5 V).
Maximum values depend on the actual TJ and design utilization. See the Excel-based PowerPlay Early Power
Estimator (available at www.altera.com) or the Quartus II PowerPlay Power Analyzer feature for maximum
values. See the section “Power Consumption” on page 5–20 for more information.
Pin pull-up resistance values are lower if an external source drives the pin higher than VCCIO.
I/O Standard Specifications
Tables 5–5 through 5–32 show the Stratix II device family I/O standard
specifications.
Table 5–5. LVTTL Specifications (Part 1 of 2)
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
VCCIO (1)
Output supply voltage
3.135
3.465
V
VI H
High-level input voltage
1.7
4.0
V
VIL
Low-level input voltage
–0.3
0.8
V
VOH
High-level output voltage
5–4
Stratix II Device Handbook, Volume 1
IOH = –4 mA (2)
2.4
V
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–5. LVTTL Specifications (Part 2 of 2)
Symbol
VOL
Parameter
Low-level output voltage
Conditions
Minimum
IOL = 4 mA (2)
Maximum
Unit
0.45
V
Notes to Tables 5–5:
(1)
(2)
Stratix II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard,
JESD8-B.
This specification is supported across all the programmable drive strength settings available for this I/O standard
as shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–6. LVCMOS Specifications
Symbol
Parameter
Conditions
VCCIO (1)
Output supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
VCCIO = 3.0,
IOH = –0.1 mA (2)
VOL
Low-level output voltage
VCCIO = 3.0,
IOL = 0.1 mA (2)
Minimum
Maximum
Unit
3.135
3.465
V
1.7
4.0
V
–0.3
0.8
V
VCCIO – 0.2
V
0.2
V
Notes to Table 5–6:
(1)
(2)
Stratix II devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard,
JESD8-B.
This specification is supported across all the programmable drive strength available for this I/O standard as
shown in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–7. 2.5-V I/O Specifications
Symbol
Parameter
Conditions
VCCIO (1)
Output supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –1mA (2)
VOL
Low-level output voltage
IOL = 1 mA (2)
Minimum
Maximum
Unit
2.375
2.625
V
1.7
4.0
V
–0.3
0.7
V
2.0
V
0.4
V
Notes to Table 5–7:
(1)
(2)
Stratix II devices VC C I O voltage level support of 2.5 ± -5% is narrower than defined in the Normal Range of the
EIA/JEDEC standard.
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Altera Corporation
April 2011
5–5
Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–8. 1.8-V I/O Specifications
Symbol
Parameter
VCCIO (1)
Output supply voltage
VI H
High-level input voltage
Conditions
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –2 mA (2)
VOL
Low-level output voltage
IOL = 2 mA (2)
Minimum
Maximum
Unit
1.71
1.89
V
0.65 × VCCIO
2.25
V
–0.30
0.35 × VCCIO
VCCIO – 0.45
V
V
0.45
V
Notes to Table 5–8:
(1)
(2)
The Stratix II device family’s VC C I O voltage level support of 1.8 ± -5% is narrower than defined in the Normal
Range of the EIA/JEDEC standard.
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–9. 1.5-V I/O Specifications
Symbol
Parameter
VCCIO (1)
Output supply voltage
VI H
High-level input voltage
Conditions
VIL
Low-level input voltage
VOH
High-level output voltage
IOH = –2 mA (2)
VOL
Low-level output voltage
IOL = 2 mA (2)
Minimum
Maximum
Unit
1.425
1.575
V
0.65 × VCCIO
VCCIO + 0.30
V
–0.30
0.35 × VCCIO
V
0.75 × VCCIO
V
0.25 × VCCIO
V
Notes to Table 5–9:
(1)
(2)
The Stratix II device family’s VC C I O voltage level support of 1.5 ± -5% is narrower than defined in the Normal
Range of the EIA/JEDEC standard.
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Figures 5–1 and 5–2 show receiver input and transmitter output
waveforms, respectively, for all differential I/O standards (LVDS,
LVPECL, and HyperTransport technology).
5–6
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Figure 5–1. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
VCM
Ground
Differential Waveform
VID
p−n=0V
VID
Figure 5–2. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
VCM
Ground
Differential Waveform
VOD
p−n=0V
VOD
Altera Corporation
April 2011
5–7
Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–10. 2.5-V LVDS I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
2.375
2.500
2.625
V
VCCIO
I/O supply voltage for left and
right I/O banks (1, 2, 5, and
6)
VID
Input differential voltage
swing (single-ended)
100
350
900
mV
VICM
Input common mode voltage
200
1,250
1,800
mV
VOD
Output differential voltage
(single-ended)
RL = 100 Ω
250
450
mV
VOCM
Output common mode
voltage
RL = 100 Ω
1.125
1.375
V
RL
Receiver differential input
discrete resistor (external to
Stratix II devices)
90
100
110
Ω
Minimum
Typical
Maximum
Unit
3.135
3.300
3.465
V
Table 5–11. 3.3-V LVDS I/O Specifications
Symbol
Parameter
Conditions
VCCIO (1)
I/O supply voltage for top
and bottom PLL banks (9,
10, 11, and 12)
VID
Input differential voltage
swing (single-ended)
100
350
900
mV
VICM
Input common mode voltage
200
1,250
1,800
mV
VOD
Output differential voltage
(single-ended)
RL = 100 Ω
250
710
mV
VOCM
Output common mode
voltage
RL = 100 Ω
840
1,570
mV
RL
Receiver differential input
discrete resistor (external to
Stratix II devices)
110
Ω
90
100
Note to Table 5–11:
(1)
The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO.
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, VCC_PLL_OUT should be connected to 3.3 V.
5–8
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–12. LVPECL Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
3.135
3.300
3.465
V
600
1,000
mV
VCCIO (1)
I/O supply voltage
VID
Input differential voltage
swing (single-ended)
300
VICM
Input common mode voltage
1.0
2.5
V
VOD
Output differential voltage
(single-ended)
RL = 100 Ω
525
970
mV
VOCM
Output common mode
voltage
RL = 100 Ω
1,650
2,250
mV
RL
Receiver differential input
resistor
110
Ω
90
100
Note to Table 5–12:
(1)
The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO.
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, VCC_PLL_OUT should be connected to 3.3 V.
Table 5–13. HyperTransport Technology Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
2.375
2.500
2.625
V
VCCIO
I/O supply voltage for left and
right I/O banks (1, 2, 5, and 6)
VID
Input differential voltage swing RL = 100 Ω
(single-ended)
300
600
900
mV
VICM
Input common mode voltage
RL = 100 Ω
385
600
845
mV
VOD
Output differential voltage
(single-ended)
RL = 100 Ω
400
600
820
mV
Δ VOD
Change in VOD between high
and low
RL = 100 Ω
75
mV
VOCM
Output common mode voltage RL = 100 Ω
Δ VOCM
Change in VOCM between high
and low
RL
Receiver differential input
resistor
440
600
RL = 100 Ω
780
mV
50
mV
90
100
110
Ω
Minimum
Typical
Maximum
Unit
3.0
3.3
3.6
V
VCCIO + 0.5
V
Table 5–14. 3.3-V PCI Specifications (Part 1 of 2)
Symbol
Parameter
VCCIO
Output supply voltage
VIH
High-level input voltage
Altera Corporation
April 2011
Conditions
0.5 × VCCIO
5–9
Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–14. 3.3-V PCI Specifications (Part 2 of 2)
Symbol
Parameter
Conditions
VIL
Low-level input voltage
VOH
High-level output voltage
IOUT = –500 μA
VOL
Low-level output voltage
IOUT = 1,500 μA
Minimum
Typical
–0.3
Maximum
Unit
0.3 × VCCIO
V
0.9 × VCCIO
V
0.1 × VCCIO
V
Maximum
Unit
3.6
V
Table 5–15. PCI-X Mode 1 Specifications
Symbol
Parameter
Conditions
Minimum
Typical
VCCIO
Output supply voltage
3.0
VIH
High-level input voltage
0.5 × VCCIO
VCCIO + 0.5
V
VIL
Low-level input voltage
–0.30
0.35 × VCCIO
V
VIPU
Input pull-up voltage
VOH
High-level output voltage
IOUT = –500 μA
VOL
Low-level output voltage
IOUT = 1,500 μA
0.7 × VCCIO
V
0.9 × VCCIO
V
0.1 × VCCIO
V
Maximum
Unit
Table 5–16. SSTL-18 Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
VCCIO
Output supply voltage
1.71
1.80
1.89
V
VREF
Reference voltage
0.855
0.900
0.945
V
VTT
Termination voltage
VREF – 0.04
VREF
VREF + 0.04
V
VIH (DC)
High-level DC input voltage
VREF + 0.125
VIL (DC)
Low-level DC input voltage
VREF – 0.125
V
VIH (AC)
High-level AC input voltage
VIL (AC)
Low-level AC input voltage
VOH
High-level output voltage
IOH = –6.7 mA (1)
VOL
Low-level output voltage
IOL = 6.7 mA (1)
V
VREF + 0.25
V
VREF – 0.25
VTT + 0.475
V
V
VTT – 0.475
V
Note to Table 5–16:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
5–10
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–17. SSTL-18 Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.71
1.80
1.89
V
VREF
Reference voltage
0.855
0.900
0.945
V
VTT
Termination voltage
VREF – 0.04
VREF
VREF + 0.04
V
VIH (DC) High-level DC input voltage
VREF + 0.125
V
VIL (DC) Low-level DC input voltage
VREF – 0.125
VIH (AC) High-level AC input voltage
VREF + 0.25
V
VIL (AC) Low-level AC input voltage
VREF – 0.25
VOH
High-level output voltage
IOH = –13.4 mA (1)
VOL
Low-level output voltage
IOL = 13.4 mA (1)
V
VCCIO – 0.28
V
V
0.28
V
Note to Table 5–17:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–18. SSTL-18 Class I & II Differential Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.80
1.89
V
VCCIO
Output supply voltage
1.71
VSWING
(DC)
DC differential input voltage
0.25
VX (AC) AC differential input cross
point voltage
V
(VCCIO/2) – 0.175
(VCCIO/2) + 0.175
V
VSWING
(AC)
AC differential input voltage
VISO
Input clock signal offset
voltage
0.5 × VCCIO
V
ΔVISO
Input clock signal offset
voltage variation
±200
mV
VOX
(AC)
AC differential cross point
voltage
Altera Corporation
April 2011
0.5
(VCCIO/2) – 0.125
V
(VCCIO/2) + 0.125
V
5–11
Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–19. SSTL-2 Class I Specifications
Symbol
Parameter
VCCIO
Output supply voltage
VTT
Termination voltage
Conditions
Minimum
Typical
Maximum
Unit
2.375
2.500
2.625
V
VREF – 0.04
VREF
VREF + 0.04
V
1.188
1.250
VREF
Reference voltage
1.313
V
VIH (DC)
High-level DC input voltage
VREF + 0.18
3.00
V
VIL (DC)
Low-level DC input voltage
–0.30
VREF – 0.18
V
VI H (AC)
High-level AC input voltage
VR E F + 0.35
VI L (AC)
Low-level AC input voltage
VOH
High-level output voltage
IOH = –8.1 mA (1)
VOL
Low-level output voltage
IOL = 8.1 mA (1)
V
VR E F - 0.35
VTT + 0.57
V
V
VTT – 0.57
V
Note to Table 5–19:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–20. SSTL-2 Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
2.375
2.500
2.625
V
VREF – 0.04
VREF
VREF + 0.04
V
1.188
1.250
1.313
V
VCCIO
Output supply voltage
VTT
Termination voltage
VREF
Reference voltage
VIH (DC)
High-level DC input voltage
VREF + 0.18
VCCIO + 0.30
V
VIL (DC)
Low-level DC input voltage
–0.30
VREF – 0.18
V
VR E F + 0.35
VR E F - 0.35
V
VI H (AC)
High-level AC input voltage
VI L (AC)
Low-level AC input voltage
VOH
High-level output voltage
IOH = –16.4 mA (1)
VOL
Low-level output voltage
IOL = 16.4 mA (1)
V
VTT + 0.76
V
VTT – 0.76
V
Note to Table 5–20:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
5–12
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–21. SSTL-2 Class I & II Differential Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
2.500
2.625
V
VCCIO
Output supply voltage
2.375
VSWING
(DC)
DC differential input voltage
0.36
VX (AC) AC differential input cross
point voltage
V
(VCCIO/2) – 0.2
(VCCIO/2) + 0.2
V
VSWING
(AC)
AC differential input voltage
VISO
Input clock signal offset
voltage
0.5 × VCCIO
V
ΔVISO
Input clock signal offset
voltage variation
±200
mV
VOX
(AC)
AC differential output cross
point voltage
0.7
V
(VCCIO/2) – 0.2
(VCCIO/2) + 0.2
V
Table 5–22. 1.2-V HSTL Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.14
1.20
1.26
V
0.50 × VC C I O
0.52 × VC C I O
V
VCCIO
Output supply voltage
VR E F
Reference voltage
0.48 × VC C I O
VIH (DC) High-level DC input voltage
VR E F + 0.08
VC C I O + 0.15
V
VIL (DC) Low-level DC input voltage
–0.15
VR E F – 0.08
V
VIH (AC) High-level AC input voltage
VR E F + 0.15
VC C I O + 0.24
V
VIL (AC) Low-level AC input voltage
–0.24
VR E F – 0.15
V
VOH
High-level output voltage
IO H = 8 mA
VR E F + 0.15
VC C I O + 0.15
V
VOL
Low-level output voltage
IO H = –8 mA
–0.15
VR E F – 0.15
V
Altera Corporation
April 2011
5–13
Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–23. 1.5-V HSTL Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.425
1.500
1.575
V
VREF
Input reference voltage
0.713
0.750
0.788
V
VTT
Termination voltage
0.713
0.750
0.788
V
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
IOH = 8 mA (1)
VOL
Low-level output voltage
IOH = –8 mA (1)
V
VREF – 0.1
V
V
VREF – 0.2
VCCIO – 0.4
V
V
0.4
V
Note to Table 5–23:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–24. 1.5-V HSTL Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.425
1.500
1.575
V
VCCIO
Output supply voltage
VREF
Input reference voltage
0.713
0.750
0.788
V
VTT
Termination voltage
0.713
0.750
0.788
V
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
IOH = 16 mA (1)
VOL
Low-level output voltage
IOH = –16 mA (1)
V
VREF – 0.1
V
VREF – 0.2
V
V
VCCIO – 0.4
V
0.4
V
Note to Table 5–24:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
5–14
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–25. 1.5-V HSTL Class I & II Differential Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.425
1.500
1.575
V
VCCIO
I/O supply voltage
VDIF (DC)
DC input differential voltage
0.2
VCM (DC)
DC common mode input
voltage
0.68
VDIF (AC)
AC differential input voltage
0.4
VOX (AC)
AC differential cross point
voltage
0.68
V
0.90
V
V
0.90
V
Table 5–26. 1.8-V HSTL Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.71
1.80
1.89
V
VREF
Input reference voltage
0.85
0.90
0.95
V
VTT
Termination voltage
0.85
0.90
0.95
V
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
IOH = 8 mA (1)
VOL
Low-level output voltage
IOH = –8 mA (1)
V
VREF – 0.1
V
V
VREF – 0.2
VCCIO – 0.4
V
V
0.4
V
Note to Table 5–26:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Altera Corporation
April 2011
5–15
Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–27. 1.8-V HSTL Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
VCCIO
Output supply voltage
1.71
1.80
1.89
V
VREF
Input reference voltage
0.85
0.90
0.95
V
VTT
Termination voltage
0.85
0.90
0.95
VIH (DC)
DC high-level input voltage
VREF + 0.1
VIL (DC)
DC low-level input voltage
–0.3
VIH (AC)
AC high-level input voltage
VREF + 0.2
VIL (AC)
AC low-level input voltage
VOH
High-level output voltage
IOH = 16 mA (1)
VOL
Low-level output voltage
IOH = –16 mA (1)
V
V
VREF – 0.1
V
V
VREF – 0.2
VCCIO – 0.4
V
V
0.4
V
Note to Table 5–27:
(1)
This specification is supported across all the programmable drive settings available for this I/O standard as shown
in the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook.
Table 5–28. 1.8-V HSTL Class I & II Differential Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Unit
1.71
1.80
1.89
V
VCCIO
I/O supply voltage
VDIF (DC)
DC input differential voltage
0.2
VCCIO + 0.6 V
V
VCM (DC)
DC common mode input
voltage
0.78
1.12
V
VDIF (AC)
AC differential input voltage
0.4
VCCIO + 0.6 V
V
VOX (AC)
AC differential cross point
voltage
0.68
0.90
V
5–16
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Bus Hold Specifications
Table 5–29 shows the Stratix II device family bus hold specifications.
Table 5–29. Bus Hold Parameters
VCCIO Level
Parameter
Conditions
1.2 V
Min
Max
1.5 V
Min
1.8 V
Max
Min
2.5 V
Max
Min
Max
3.3 V
Min
Unit
Max
Low
sustaining
current
VIN > VIL
(maximum)
22.5
25.0
30.0
50.0
70.0
μA
High
sustaining
current
VIN < VIH
(minimum)
–22.5
–25.0
–30.0
–50.0
–70.0
μA
Low
overdrive
current
0 V < VIN <
VCCIO
120
160
200
300
500
μA
High
overdrive
current
0 V < VIN <
VCCIO
–120
–160
–200
–300
–500
μA
2.00
V
Bus-hold
trip point
0.45
0.95
0.50
1.00
0.68
1.07
0.70
1.70
0.80
On-Chip Termination Specifications
Tables 5–30 and 5–31 define the specification for internal termination
resistance tolerance when using series or differential on-chip termination.
Table 5–30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 1 of 2)
Notes (1), 2
Resistance Tolerance
Symbol
25-Ω RS
3.3/2.5
Description
Conditions
Commercial
Max
Industrial
Max
Unit
Internal series termination with
calibration (25-Ω setting)
VC C I O = 3.3/2.5 V
±5
±10
%
Internal series termination without
calibration (25-Ω setting)
VC C I O = 3.3/2.5 V
±30
±30
%
Altera Corporation
April 2011
5–17
Stratix II Device Handbook, Volume 1
Operating Conditions
Table 5–30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 2 of 2)
Notes (1), 2
Resistance Tolerance
Symbol
50-Ω RS
3.3/2.5
Description
Conditions
Commercial
Max
Industrial
Max
Unit
Internal series termination with
calibration (50-Ω setting)
VC C I O = 3.3/2.5 V
±5
±10
%
Internal series termination without
calibration (50-Ω setting)
VC C I O = 3.3/2.5 V
±30
±30
%
50-Ω RT
2.5
Internal parallel termination with
calibration (50-Ω setting)
VC C I O = 1.8 V
±30
±30
%
25-Ω RS
1.8
Internal series termination with
calibration (25-Ω setting)
VC C I O = 1.8 V
±5
±10
%
Internal series termination without
calibration (25-Ω setting)
VC C I O = 1.8 V
±30
±30
%
Internal series termination with
calibration (50-Ω setting)
VC C I O = 1.8 V
±5
±10
%
Internal series termination without
calibration (50-Ω setting)
VC C I O = 1.8 V
±30
±30
%
50-Ω RT
1.8
Internal parallel termination with
calibration (50-Ω setting)
VC C I O = 1.8 V
±10
±15
%
50−Ω RS
1.5
Internal series termination with
calibration (50-Ω setting)
VC C I O = 1.5 V
±8
±10
%
Internal series termination without
calibration (50-Ω setting)
VC C I O = 1.5 V
±36
±36
%
50-Ω RT
1.5
Internal parallel termination with
calibration (50-Ω setting)
VC C I O = 1.5 V
±10
±15
%
50−Ω RS
1.2
Internal series termination with
calibration (50-Ω setting)
VC C I O = 1.2 V
±8
±10
%
Internal series termination without
calibration (50-Ω setting)
VC C I O = 1.2 V
±50
±50
%
Internal parallel termination with
calibration (50-Ω setting)
VC C I O = 1.2 V
±10
±15
%
50-Ω RS
1.8
50-Ω RT
1.2
Notes for Table 5–30:
(1)
(2)
The resistance tolerances for calibrated SOCT and POCT are for the moment of calibration. If the temperature or
voltage changes over time, the tolerance may also change.
On-chip parallel termination with calibration is only supported for input pins.
5–18
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–31. Series & Differential On-Chip Termination Specification for Left & Right I/O Banks
Resistance Tolerance
Symbol
Description
Conditions
Commercial Industrial
Max
Max
Unit
25-Ω RS
3.3/2.5
Internal series termination without
calibration (25-Ω setting)
VC C I O = 3.3/2.5 V
±30
±30
%
50-Ω RS
3.3/2.5/1.8
Internal series termination without
calibration (50-Ω setting)
VC C I O = 3.3/2.5/1.8 V
±30
±30
%
50-Ω RS 1.5
Internal series termination without
calibration (50-Ω setting)
VC C I O = 1.5 V
±36
±36
%
RD
VC C I O = 2.5 V
Internal differential termination for
LVDS or HyperTransport technology
(100-Ω setting)
±20
±25
%
Pin Capacitance
Table 5–32 shows the Stratix II device family pin capacitance.
Table 5–32. Stratix II Device Capacitance
Symbol
Note (1)
Parameter
Typical
Unit
CI O T B
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
5.0
pF
CI O L R
Input capacitance on I/O pins in I/O banks 1, 2, 5, and 6, including highspeed differential receiver and transmitter pins.
6.1
pF
CC L K T B
Input capacitance on top/bottom clock input pins: CLK[4..7] and
CLK[12..15].
6.0
pF
CC L K L R
Input capacitance on left/right clock inputs: CLK0, CLK2, CLK8, CLK10.
6.1
pF
CC L K L R +
Input capacitance on left/right clock inputs: CLK1, CLK3, CLK9, and
CLK11.
3.3
pF
CO U T F B
Input capacitance on dual-purpose clock output/feedback pins in PLL
banks 9, 10, 11, and 12.
6.7
pF
Note to Table 5–32:
(1)
Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement
accuracy is within ±0.5pF
Altera Corporation
April 2011
5–19
Stratix II Device Handbook, Volume 1
Power Consumption
Power
Consumption
Altera® offers two ways to calculate power for a design: the Excel-based
PowerPlay Early Power Estimator power calculator and the Quartus® II
PowerPlay Power Analyzer feature.
The interactive Excel-based PowerPlay Early Power Estimator is typically
used prior to designing the FPGA in order to get an estimate of device
power. The Quartus II PowerPlay Power Analyzer provides better
quality estimates based on the specifics of the design after place-androute is complete. The Power Analyzer can apply a combination of userentered, simulation-derived and estimated signal activities which,
combined with detailed circuit models, can yield very accurate power
estimates.
In both cases, these calculations should only be used as an estimation of
power, not as a specification.
f
For more information about PowerPlay tools, refer to the PowerPlay Early
Power Estimator User Guide and the PowerPlay Early Power Estimator and
PowerPlay Power Analyzer chapters in volume 3 of the Quartus II
Handbook.
The PowerPlay Early Power Estimator is available on the Altera web site
at www.altera.com. See Table 5–4 on page 5–3 for typical ICC standby
specifications.
Timing Model
The DirectDriveTM technology and MultiTrackTM interconnect ensure
predictable performance, accurate simulation, and accurate timing
analysis across all Stratix II device densities and speed grades. This
section describes and specifies the performance, internal timing, external
timing, and PLL, high-speed I/O, external memory interface, and JTAG
timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
1
The timing numbers listed in the tables of this section are
extracted from the Quartus II software version 5.0 SP1.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary. Table 5–33 shows the status of the
Stratix II device timing models.
5–20
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under
worst-case voltage and junction temperature conditions.
Table 5–33. Stratix II Device Timing Model Status
Device
Preliminary
Final
EP2S15
v
EP2S30
v
EP2S60
v
EP2S90
v
EP2S130
v
EP2S180
v
I/O Timing Measurement Methodology
Altera characterizes timing delays at the worst-case process, minimum
voltage, and maximum temperature for input register setup time (tSU)
and hold time (tH). The Quartus II software uses the following equations
to calculate tSU and tH timing for Stratix II devices input signals.
tSU = + data delay from input pin to input register
+ micro setup time of the input register
– clock delay from input pin to input register
tH = – data delay from input pin to input register
+ micro hold time of the input register
+ clock delay from input pin to input register
Figure 5–3 shows the setup and hold timing diagram for input registers.
Altera Corporation
April 2011
5–21
Stratix II Device Handbook, Volume 1
Timing Model
Figure 5–3. Input Register Setup & Hold Timing Diagram
Input Data Delay
micro tSU
micro tH
Input Clock Delay
For output timing, different I/O standards require different baseline
loading techniques for reporting timing delays. Altera characterizes
timing delays with the required termination for each I/O standard and
with 0 pF (except for PCI and PCI-X which use 10 pF) loading and the
timing is specified up to the output pin of the FPGA device. The
Quartus II software calculates the I/O timing for each I/O standard with
a default baseline loading as specified by the I/O standards.
The following measurements are made during device characterization.
Altera measures clock-to-output delays (tCO) at worst-case process,
minimum voltage, and maximum temperature (PVT) for default loading
conditions shown in Table 5–34. Use the following equations to calculate
clock pin to output pin timing for Stratix II devices.
tCO from clock pin to I/O pin = delay from clock pad to I/O output
register + IOE output register clock-to-output delay + delay from
output register to output pin + I/O output delay
txz/tzx from clock pin to I/O pin = delay from clock pad to I/O
output register + IOE output register clock-to-output delay + delay
from output register to output pin + I/O output delay + output
enable pin delay
Simulation using IBIS models is required to determine the delays on the
PCB traces in addition to the output pin delay timing reported by the
Quartus II software and the timing model in the device handbook.
1.
Simulate the output driver of choice into the generalized test setup,
using values from Table 5–34.
2.
Record the time to VMEAS.
3.
Simulate the output driver of choice into the actual PCB trace and
load, using the appropriate IBIS model or capacitance value to
represent the load.
5–22
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
4.
Record the time to VMEAS.
5.
Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in
Table 5–34 using the above equation. Figure 5–4 shows the model of the
circuit that is represented by the output timing of the Quartus II software.
Figure 5–4. Output Delay Timing Reporting Setup Modeled by Quartus II
VTT
VCCIO
RT
Output
Buffer
Output
GND
Outputp
RS
VMEAS
CL
Outputn
RD
GND
Notes to Figure 5–4:
(1)
(2)
(3)
Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
VCCPD is 3.085 V unless otherwise specified.
VCCINT is 1.12 V unless otherwise specified.
Figures 5–5 and 5–6 show the measurement setup for output disable and
output enable timing.
Altera Corporation
April 2011
5–23
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–34. Output Timing Measurement Methodology for Output Pins
Notes (1), (2), (3)
Measurement
Point
Loading and Termination
I/O Standard
RS (Ω)
RD (Ω)
RT (Ω)
VCCIO (V)
VTT (V)
CL (pF)
VMEAS (V)
LVTTL (4)
3.135
0
1.5675
LVCMOS (4)
3.135
0
1.5675
2.5 V (4)
2.375
0
1.1875
1.8 V (4)
1.710
0
0.855
1.5 V (4)
1.425
0
0.7125
PCI (5)
2.970
10
1.485
PCI-X (5)
SSTL-2 Class I
2.970
25
50
2.325
1.123
10
1.485
0
1.1625
SSTL-2 Class II
25
25
2.325
1.123
0
1.1625
SSTL-18 Class I
25
50
1.660
0.790
0
0.83
SSTL-18 Class II
25
25
1.660
0.790
0
0.83
1.8-V HSTL Class I
50
50
1.660
0.790
0
0.83
1.8-V HSTL Class II
25
25
1.660
0.790
0
0.83
1.5-V HSTL Class I
50
50
1.375
0.648
0
0.6875
1.375
0.648
0
0.6875
0
0.570
1.5-V HSTL Class II
1.2-V HSTL with OCT
25
50
1.140
Differential SSTL-2 Class I
50
50
2.325
1.123
0
1.1625
Differential SSTL-2 Class II
25
25
2.325
1.123
0
1.1625
Differential SSTL-18 Class I
50
50
1.660
0.790
0
0.83
Differential SSTL-18 Class II
25
25
1.660
0.790
0
0.83
1.5-V Differential HSTL Class I
50
50
1.375
0.648
0
0.6875
25
1.375
0.648
0
0.6875
1.5-V Differential HSTL Class II
1.8-V Differential HSTL Class I
50
50
1.660
0.790
0
0.83
1.8-V Differential HSTL Class II
25
25
1.660
0.790
0
0.83
LVDS
100
2.325
0
1.1625
HyperTransport
100
2.325
0
1.1625
LVPECL
100
3.135
0
1.5675
Notes to Table 5–34:
(1)
(2)
(3)
(4)
(5)
Input measurement point at internal node is 0.5 × VCCINT.
Output measuring point for VMEAS at buffer output is 0.5 × VCCIO.
Input stimulus edge rate is 0 to VCC in 0.2 ns (internal signal) from the driver preceding the I/O buffer.
Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple
VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V
5–24
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Figure 5–5. Measurement Setup for txz
Note (1)
tXZ, Driving High to Tristate
Enable
OE
OE
½ VCCINT
Dout
Din
100 Ω
Disable
“1”
Din
100 mv
Dout
thz
GND
tXZ, Driving Low to Tristate
Enable
OE
100 Ω
Disable
½ VCCINT
OE
Dout
Din
Din
Dout
“0”
tlz
VCCIO
100 mv
Note to Figure 5–5:
(1)
Altera Corporation
April 2011
VCCINT is 1.12 V for this measurement.
5–25
Stratix II Device Handbook, Volume 1
Timing Model
Figure 5–6. Measurement Setup for tzx
tZX, Tristate to Driving High
Disable
OE
OE
Enable
½ VCCINT
Dout
Din
“1”
Din
1 MΩ
tzh
Dout
½ VCCIO
tZX, Tristate to Driving Low
Disable
Enable
½ VCCINT
OE
1 MΩ
OE
Dout
Din
“0”
Din
½ VCCIO
tzl
Dout
Table 5–35 specifies the input timing measurement setup.
Table 5–35. Timing Measurement Methodology for Input Pins (Part 1 of 2)
Notes (1)–(4)
Measurement Conditions
Measurement Point
I/O Standard
VCCIO (V)
LVTTL (5)
VREF (V)
3.135
Edge Rate (ns)
VM E A S (V)
3.135
1.5675
LVCMOS (5)
3.135
3.135
1.5675
2.5 V (5)
2.375
2.375
1.1875
1.8 V (5)
1.710
1.710
0.855
1.5 V (5)
1.425
1.425
0.7125
PCI (6)
2.970
2.970
1.485
PCI-X (6)
2.970
2.970
1.485
SSTL-2 Class I
2.325
1.163
2.325
1.1625
SSTL-2 Class II
2.325
1.163
2.325
1.1625
SSTL-18 Class I
1.660
0.830
1.660
0.83
SSTL-18 Class II
1.660
0.830
1.660
0.83
1.8-V HSTL Class I
1.660
0.830
1.660
0.83
5–26
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–35. Timing Measurement Methodology for Input Pins (Part 2 of 2)
Notes (1)–(4)
Measurement Conditions
Measurement Point
I/O Standard
VCCIO (V)
VREF (V)
Edge Rate (ns)
VM E A S (V)
1.8-V HSTL Class II
1.660
0.830
1.660
0.83
1.5-V HSTL Class I
1.375
0.688
1.375
0.6875
1.5-V HSTL Class II
1.375
0.688
1.375
0.6875
1.2-V HSTL with OCT
1.140
0.570
1.140
0.570
Differential SSTL-2 Class I
2.325
1.163
2.325
1.1625
Differential SSTL-2 Class II
2.325
1.163
2.325
1.1625
Differential SSTL-18 Class I
1.660
0.830
1.660
0.83
Differential SSTL-18 Class II
1.660
0.830
1.660
0.83
1.5-V Differential HSTL Class I
1.375
0.688
1.375
0.6875
1.5-V Differential HSTL Class II
1.375
0.688
1.375
0.6875
1.8-V Differential HSTL Class I
1.660
0.830
1.660
0.83
1.8-V Differential HSTL Class II
1.660
0.830
LVDS
2.325
1.660
0.83
0.100
1.1625
HyperTransport
2.325
0.400
1.1625
LVPECL
3.135
0.100
1.5675
Notes to Table 5–35:
(1)
(2)
(3)
(4)
(5)
(6)
Input buffer sees no load at buffer input.
Input measuring point at buffer input is 0.5 × VCCIO.
Output measuring point is 0.5 × VCC at internal node.
Input edge rate is 1 V/ns.
Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple
VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V
Performance
Table 5–36 shows Stratix II performance for some common designs. All
performance values were obtained with the Quartus II software
compilation of library of parameterized modules (LPM), or MegaCore®
functions for the finite impulse response (FIR) and fast Fourier transform
(FFT) designs.
Altera Corporation
April 2011
5–27
Stratix II Device Handbook, Volume 1
Timing Model
1
The performance numbers in Table 5–36 are extracted from the
Quartus II software version 5.1 SP1.
Table 5–36. Stratix II Performance Notes (Part 1 of 6)
Note (1)
Resources Used
ALUTs
TriMatrix
Memory
Blocks
DSP
Blocks
-3
Speed
Grade
(2)
-3
Speed
Grade
(3)
-4
Speed
Grade
-5
Speed
Grade
Unit
21
0
0
654.87
625.0
523.83
460.4
MHz
Applications
LE
16-to-1 multiplexer (4)
Performance
32-to-1 multiplexer (4)
38
0
0
519.21
473.26
464.25
384.17
MHz
16-bit counter
16
0
0
566.57
538.79
489.23
421.05
MHz
64-bit counter
64
0
0
244.31
232.07
209.11
181.38
MHz
TriMatrix
Memory
M512
block
Simple dual-port RAM
32 × 18 bit
0
1
0
500.00
476.19
434.02
373.13
MHz
FIFO 32 x 18 bit
22
1
0
500.00
476.19
434.78
373.13
MHz
TriMatrix
Memory
M4K
block
Simple dual-port RAM
128 x 36 bit (8)
0
1
0
540.54
515.46
469.48
401.60
MHz
True dual-port RAM
128 × 18 bit (8)
0
1
0
540.54
515.46
469.48
401.60
MHz
FIFO
128 × 36 bit
22
1
0
530.22
499.00
469.48
401.60
MHz
Simple dual-port RAM
128 × 36 bit (9)
0
1
0
475.28
453.30
413.22
354.10
MHz
True dual-port RAM
128 × 18 bit (9)
0
1
0
475.28
453.30
413.22
354.10
MHz
5–28
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–36. Stratix II Performance Notes (Part 2 of 6)
Note (1)
Resources Used
ALUTs
TriMatrix
Memory
Blocks
DSP
Blocks
-3
Speed
Grade
(2)
-3
Speed
Grade
(3)
-4
Speed
Grade
-5
Speed
Grade
Unit
Single port
RAM 4K × 144 bit
0
1
0
349.65
333.33
303.95
261.09
MHz
Simple dual-port
RAM 4K × 144 bit
0
1
0
420.16
400.00
364.96
313.47
MHz
True dual-port
RAM 4K × 144 bit
0
1
0
349.65
333.33
303.95
261.09
MHz
Single port
RAM 8K × 72 bit
0
1
0
354.60
337.83
307.69
263.85
MHz
Simple dual-port
RAM 8K × 72 bit
0
1
0
420.16
400.00
364.96
313.47
MHz
True dual-port
RAM 8K × 72 bit
0
1
0
349.65
333.33
303.95
261.09
MHz
Single port
RAM 16K × 36 bit
0
1
0
364.96
347.22
317.46
271.73
MHz
Simple dual-port
RAM 16K × 36 bit
0
1
0
420.16
400.00
364.96
313.47
MHz
True dual-port
RAM 16K × 36 bit
0
1
0
359.71
342.46
313.47
268.09
MHz
Single port
RAM 32K × 18 bit
0
1
0
364.96
347.22
317.46
271.73
MHz
Simple dual-port
RAM 32K × 18 bit
0
1
0
420.16
400.0
364.96
313.47
MHz
True dual-port
RAM 32K × 18 bit
0
1
0
359.71
342.46
313.47
268.09
MHz
Single port
RAM 64K × 9 bit
0
1
0
364.96
347.22
317.46
271.73
MHz
Simple dual-port
RAM 64K × 9 bit
0
1
0
420.16
400.0
364.96
313.47
MHz
True dual-port
RAM 64K × 9 bit
0
1
0
359.71
342.46
313.47
268.09
MHz
Applications
TriMatrix
Memory
M-RAM
block
Performance
Altera Corporation
April 2011
5–29
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–36. Stratix II Performance Notes (Part 3 of 6)
Note (1)
Resources Used
ALUTs
TriMatrix
Memory
Blocks
DSP
Blocks
-3
Speed
Grade
(2)
-3
Speed
Grade
(3)
-4
Speed
Grade
-5
Speed
Grade
Unit
9 × 9-bit multiplier (5)
0
0
1
430.29
409.16
373.13
320.10
MHz
18 × 18-bit
multiplier (5)
0
0
1
410.17
390.01
356.12
305.06
MHz
18 × 18-bit
multiplier (7)
0
0
1
450.04
428.08
391.23
335.12
MHz
36 × 36-bit
multiplier (5)
0
0
1
250.00
238.15
217.48
186.60
MHz
36 × 36-bit multiplier
(6)
0
0
1
410.17
390.01
356.12
305.06
MHz
18-bit, four-tap FIR
filter
0
0
1
410.17
390.01
356.12
305.06
MHz
8-bit,16-tap parallel
FIR filter
58
0
4
259.06
240.61
217.15
185.01
MHz
8-bit, 1024-point,
streaming, three
multipliers and five
adders FFT function
2976
22
9
398.72
364.03
355.23
306.37
MHz
8-bit, 1024-point,
streaming, four
multipliers and two
adders FFT function
2781
22
12
398.56
409.16
347.22
311.13
MHz
8-bit, 1024-point,
single output, one
parallel FFT engine,
burst, three multipliers
and five adders FFT
function
984
5
3
425.17
365.76
346.98
292.39
MHz
8-bit, 1024-point,
single output, one
parallel FFT engine,
burst, four multipliers
and two adders FFT
function
919
5
4
427.53
378.78
357.14
307.59
MHz
Applications
DSP
block
Larger
designs
Performance
5–30
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–36. Stratix II Performance Notes (Part 4 of 6)
Note (1)
Resources Used
ALUTs
TriMatrix
Memory
Blocks
DSP
Blocks
-3
Speed
Grade
(2)
-3
Speed
Grade
(3)
-4
Speed
Grade
-5
Speed
Grade
Unit
8-bit, 1024-point,
single output, two
parallel FFT engines,
burst, three multiplier
and five adders FFT
function
1725
10
6
430.29
401.92
373.13
319.08
MHz
8-bit, 1024-point,
single output, two
parallel FFT engines,
burst, four multipliers
and two adders FFT
function
1594
10
8
422.65
407.33
373.13
329.10
MHz
8-bit, 1024-point,
quadrant output, one
parallel FFT engine,
burst, three multipliers
and five adders FFT
function
2361
10
9
315.45
342.81
325.73
284.25
MHz
8-bit, 1024-point,
quadrant output, one
parallel FFT engine,
burst, four multipliers
and two adders FFT
function
2165
10
12
373.13
369.54
317.96
256.14
MHz
8-bit, 1024-point,
quadrant output, two
parallel FFT engines,
burst, three multipliers
and five adders FFT
function
3996
14
18
378.50
367.10
332.33
288.68
MHz
8-bit, 1024-point,
quadrant output, two
parallel FFT engines,
burst, four multipliers
and two adders FFT
function
3604
14
24
391.38
361.14
340.25
280.89
MHz
Applications
Larger
designs
Performance
Altera Corporation
April 2011
5–31
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–36. Stratix II Performance Notes (Part 5 of 6)
Note (1)
Resources Used
ALUTs
TriMatrix
Memory
Blocks
DSP
Blocks
-3
Speed
Grade
(2)
-3
Speed
Grade
(3)
-4
Speed
Grade
-5
Speed
Grade
Unit
8-bit, 1024-point,
quadrant output, four
parallel FFT engines,
burst, three multipliers
and five adders FFT
function
6850
28
36
334.11
345.66
308.54
276.31
MHz
8-bit, 1024-point,
quadrant output, four
parallel FFT engines,
burst, four multipliers
two adders FFT
function
6067
28
48
367.91
349.04
327.33
268.24
MHz
8-bit, 1024-point,
quadrant output, one
parallel FFT engine,
buffered burst, three
multipliers and adders
FFT function
2730
18
9
387.44
388.34
364.56
306.84
MHz
8-bit, 1024-point,
quadrant output, one
parallel FFT engine,
buffered burst, four
multipliers and two
adders FFT function
2534
18
12
419.28
369.66
364.96
307.88
MHz
8-bit, 1024-point,
quadrant output, two
parallel FFT engines,
buffered burst, three
multipliers five adders
FFT function
4358
30
18
396.51
378.07
340.13
291.29
MHz
8-bit, 1024-point,
quadrant output, two
parallel FFT engines,
buffered burst four
multipliers and two
adders FFT function
3966
30
24
389.71
398.08
356.53
280.74
MHz
Applications
Larger
designs
Performance
5–32
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–36. Stratix II Performance Notes (Part 6 of 6)
Note (1)
Resources Used
ALUTs
TriMatrix
Memory
Blocks
DSP
Blocks
-3
Speed
Grade
(2)
-3
Speed
Grade
(3)
-4
Speed
Grade
-5
Speed
Grade
Unit
8-bit, 1024-point,
quadrant output, four
parallel FFT engines,
buffered burst, three
multipliers five adders
FFT function
7385
60
36
359.58
352.98
312.01
278.00
MHz
8-bit, 1024-point,
quadrant output, four
parallel FFT engines,
buffered burst, four
multipliers and two
adders FFT function
6601
60
48
371.88
355.74
327.86
277.62
MHz
Applications
Larger
designs
Performance
Notes for Table 5–36:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
These design performance numbers were obtained using the Quartus II software version 5.0 SP1.
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
This application uses registered inputs and outputs.
This application uses registered multiplier input and output stages within the DSP block.
This application uses registered multiplier input, pipeline, and output stages within the DSP block.
This application uses registered multiplier input with output of the multiplier stage feeding the accumulator or
subtractor within the DSP block.
This application uses the same clock source that is globally routed and connected to ports A and B.
This application uses locally routed clocks or differently sourced clocks for ports A and B.
Altera Corporation
April 2011
5–33
Stratix II Device Handbook, Volume 1
Timing Model
Internal Timing Parameters
See Tables 5–37 through 5–42 for internal timing parameters.
Table 5–37. LE_FF Internal Timing Microparameters
-3 Speed
Grade (1)
Symbol
-3 Speed
Grade (2)
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Min
(3)
Max
Min
(3)
Max
Min
(4)
Max
Min
(3)
Max
tS U
LE register setup time before
clock
90
95
104
104
121
ps
tH
LE register hold time after clock
149
157
172
172
200
ps
tC O
LE register clock-to-output
delay
62
tC L R
Minimum clear pulse width
204
214
234
234
273
ps
tP R E
Minimum preset pulse width
204
214
234
234
273
ps
tC L K L
Minimum clock low time
612
642
703
703
820
ps
tC L K H
Minimum clock high time
612
642
703
703
820
ps
94
62
99
59
62
109
62
127
ps
tL U T
162
378
162
397
162
170
435
162
507
ps
tA D D E R
354
619
354
650
354
372
712
354
829
ps
Notes to Table 5–37:
(1)
(2)
(3)
(4)
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
5–34
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–38. IOE Internal Timing Microparameters
-3 Speed
Grade (1)
Symbol
-3 Speed
Grade (2)
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Min
(3)
Max
Min
(3)
Max
Min
(4)
Max
Min
(3)
Max
tS U
IOE input and output
register setup time
before clock
122
128
140
140
163
ps
tH
IOE input and output
register hold time after
clock
72
75
82
82
96
ps
tC O
IOE input and output
register clock-tooutput delay
101
169
101
177
97
101
194
101
226
ps
tP I N 2 C O M B O U T _ R Row input pin to IOE
combinational output
410
760
410
798
391
410
873
410
1,018
ps
tP I N 2 C O M B O U T _ C Column input pin to
IOE combinational
output
428
787
428
825
408
428
904
428
1,054
ps
1,101
2,439
ps
991
2,246
ps
tC O M B I N 2 P I N _ R
Row IOE data input to
combinational output
pin
1,101
2,026 1,101
2,127
1,854
tC O M B I N 2 P I N _ C
Column IOE data
input to combinational
output pin
991
1,946
tC L R
Minimum clear pulse
width
200
210
229
229
268
ps
tP R E
Minimum preset pulse
width
200
210
229
229
268
ps
tC L K L
Minimum clock low
time
600
630
690
690
804
ps
tC L K H
Minimum clock high
time
600
630
690
690
804
ps
991
1,049 2,329
1,101
944
991
2,131
Notes to Table 5–38:
(1)
(2)
(3)
(4)
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Altera Corporation
April 2011
5–35
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–39. DSP Block Internal Timing Microparameters (Part 1 of 2)
-3 Speed
Grade (1)
Symbol
-3 Speed
Grade (2)
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Min
(3)
Max
Min
(3)
Max
Min
(4)
Max
Min
(3)
Max
tS U
Input, pipeline, and
output register setup
time before clock
50
52
57
57
67
ps
tH
Input, pipeline, and
output register hold
time after clock
180
189
206
206
241
ps
tC O
Input, pipeline, and
output register clockto-output delay
tI N R E G 2 P I P E 9
Input register to DSP
block pipeline register
in 9 × 9-bit mode
1,312 2,030 1,312 2,030 1,250 2,334 1,312 2,720
1,312
ps
tI N R E G 2 P I P E 1 8
Input register to DSP
block pipeline register
in 18 × 18-bit mode
1,302 2,010 1,302 2,110 1,240 2,311 1,302 2,693
1,302
ps
tI N R E G 2 P I P E 3 6
Input register to DSP
block pipeline register
in 36 × 36-bit mode
1,302 2,010 1,302 2,110 1,240 2,311 1,302 2,693
1,302
ps
tP I P E 2 O U T R E G 2 A D D DSP block pipeline
register to output
register delay in twomultipliers adder
mode
0
1,450
0
924
0
880
924
0
924
0
ps
tP I P E 2 O U T R E G 4 A D D DSP block pipeline
register to output
register delay in fourmultipliers adder
mode
1,134 1,850 1,134 1,942 1,080 2,127 1,134 2,479
1,134
ps
tP D 9
Combinational input
to output delay for
9×9
2,100 2,880 2,100 3,024 2,000 3,312 2,100 3,859
2,100
ps
tP D 1 8
Combinational input
to output delay for
18 × 18
2,110 2,990 2,110 3,139 2,010 3,438 2,110 4,006
2,110
ps
tP D 3 6
Combinational input
to output delay for
36 × 36
2,939 4,450 2,939 4,672 2,800 5,117 2,939 5,962
2,939
ps
tC L R
Minimum clear pulse
width
2,212
ps
2,543
2,543
1,667
0
ps
2,322
1,522
0
0
1,943
5–36
Stratix II Device Handbook, Volume 1
924
0
2,964
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–39. DSP Block Internal Timing Microparameters (Part 2 of 2)
-3 Speed
Grade (1)
Symbol
-3 Speed
Grade (2)
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Min
(3)
Max
Min
(3)
Max
Min
(4)
Max
Min
(3)
Max
tC L K L
Minimum clock low
time
1,190
1,249
1,368
1,368
1,594
ps
tC L K H
Minimum clock high
time
1,190
1,249
1,368
1,368
1,594
ps
Notes to Table 5–39:
(1)
(2)
(3)
(4)
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Table 5–40. M512 Block Internal Timing Microparameters (Part 1 of 2)
-3 Speed
Grade (2)
Symbol
-3 Speed
Grade (3)
Note (1)
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Min
(4)
Max
Min
(4)
2.433
Max
1,989 2,664
2,089
Min
(4)
Max
2,089
3,104
tM 5 1 2 R C
Synchronous read cycle
time
2,089
tM 5 1 2 W E R E S U
Write or read enable
setup time before clock
22
23
25
25
29
ps
tM 5 1 2 W E R E H
Write or read enable
hold time after clock
203
213
233
233
272
ps
tM 5 1 2 D ATA S U
Data setup time before
clock
22
23
25
25
29
ps
tM 5 1 2 D ATA H
Data hold time after
clock
203
213
233
233
272
ps
tM 5 1 2 WA D D R S U Write address setup
time before clock
22
23
25
25
29
ps
tM 5 1 2 WA D D R H
Write address hold time
after clock
203
213
233
233
272
ps
tM 5 1 2 R A D D R S U
Read address setup
time before clock
22
23
25
25
29
ps
tM 5 1 2 R A D D R H
Read address hold time
after clock
203
213
233
233
272
ps
Altera Corporation
April 2011
2,318 2,089
Max
Min
(5)
ps
5–37
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–40. M512 Block Internal Timing Microparameters (Part 2 of 2)
-3 Speed
Grade (2)
Symbol
-3 Speed
Grade (3)
Note (1)
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Min
(4)
298
Max
Min
(4)
Max
478
298
501
2,461
Min
(5)
Max
Min
(4)
Max
284
298
548
298
640
ps
2,003
2,102
2,695
2,102
3,141
ps
tM 5 1 2 D ATA C O 1
Clock-to-output delay
when using output
registers
tM 5 1 2 D ATA C O 2
Clock-to-output delay
without output registers
2,102
2,345 2,102
tM 5 1 2 C L K L
Minimum clock low time
1,315
1,380
1,512
1,512
1,762
ps
tM 5 1 2 C L K H
Minimum clock high time 1,315
1,380
1,512
1,512
1,762
ps
tM 5 1 2 C L R
Minimum clear pulse
width
151
165
165
192
ps
144
Notes to Table 5–40:
(1)
(2)
(3)
(4)
(5)
FMAX of M512 block obtained using the Quartus II software does not necessarily equal to 1/TM512RC.
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Table 5–41. M4K Block Internal Timing Microparameters (Part 1 of 2)
-3 Speed
Grade (2)
Symbol
-3 Speed
Grade (3)
Note (1)
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Min
(4)
Max
Min
(4)
Max
2,240
1,462
2,351
Min
(5)
2,575
Max
tM 4 K R C
Synchronous read cycle
time
1,462
tM 4 K W E R E S U
Write or read enable
setup time before clock
22
23
25
25
29
ps
tM 4 K W E R E H
Write or read enable
hold time after clock
203
213
233
233
272
ps
tM 4 K B E S U
Byte enable setup time
before clock
22
23
25
25
29
ps
tM 4 K B E H
Byte enable hold time
after clock
203
213
233
233
272
ps
5–38
Stratix II Device Handbook, Volume 1
1,393
1,462
Max
Min
(4)
1,462 3,000
ps
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–41. M4K Block Internal Timing Microparameters (Part 2 of 2)
-3 Speed
Grade (2)
Symbol
-3 Speed
Grade (3)
Note (1)
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Min
(4)
Max
Min
(4)
Max
Min
(5)
Max
Min
(4)
Max
tM 4 K D ATA A S U
A port data setup time
before clock
22
23
25
25
29
ps
tM 4 K D ATA A H
A port data hold time
after clock
203
213
233
233
272
ps
tM 4 K A D D R A S U
A port address setup
time before clock
22
23
25
25
29
ps
tM 4 K A D D R A H
A port address hold time
after clock
203
213
233
233
272
ps
tM 4 K D ATA B S U
B port data setup time
before clock
22
23
25
25
29
ps
tM 4 K D ATA B H
B port data hold time
after clock
203
213
233
233
272
ps
tM 4 K R A D D R B S U B port address setup
time before clock
22
23
25
25
29
ps
tM 4 K R A D D R B H
B port address hold time
after clock
203
213
233
233
272
ps
tM 4 K D ATA C O 1
Clock-to-output delay
when using output
registers
334
524
334
549
319
334
601
tM 4 K D ATA C O 2
(6)
Clock-to-output delay
without output registers
1,616
2,453
1,616
2,574
1,540
1,616
2,820
tM 4 K C L K H
Minimum clock high time 1,250
1,312
tM 4 K C L K L
Minimum clock low time
1,250
tM 4 K C L R
Minimum clear pulse
width
144
334
701
ps
1,616 3,286
ps
1,437
1,437
1,675
ps
1,312
1,437
1,437
1,675
ps
151
165
165
192
ps
Notes to Table 5–41:
(1)
(2)
(3)
(4)
(5)
(6)
FMAX of M4K Block obtained using the Quartus II software does not necessarily equal to 1/TM4KRC.
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Numbers apply to unpacked memory modes, true dual-port memory modes, and simple dual-port memory modes
that use locally routed or non-identical sources for the A and B port registers.
Altera Corporation
April 2011
5–39
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–42. M-RAM Block Internal Timing Microparameters (Part 1 of 2)
-3 Speed
Grade (2)
Symbol
-3 Speed
Grade (3)
Note (1)
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Min
(4)
Max
Min
(4)
Max
2,774
1,866
2,911
Min
(5)
Synchronous read cycle
time
1,866
tM E G AW E R E S U
Write or read enable
setup time before clock
144
151
165
165
192
ps
tM E G AW E R E H
Write or read enable
hold time after clock
39
40
44
44
52
ps
tM E G A B E S U
Byte enable setup time
before clock
50
52
57
57
67
ps
tM E G A B E H
Byte enable hold time
after clock
39
40
44
44
52
ps
tM E G A D ATA A S U
A port data setup time
before clock
50
52
57
57
67
ps
tM E G A D ATA A H
A port data hold time
after clock
243
255
279
279
325
ps
tM E G A A D D R A S U A port address setup
time before clock
589
618
677
677
789
ps
tM E G A A D D R A H
A port address hold time
after clock
241
253
277
277
322
ps
tM E G A D ATA B S U
B port setup time before
clock
50
52
57
57
67
ps
tM E G A D ATA B H
B port hold time after
clock
243
255
279
279
325
ps
tM E G A A D D R B S U B port address setup
time before clock
589
618
677
677
789
ps
tM E G A A D D R B H
B port address hold time
after clock
241
253
277
277
322
ps
tM E G A D ATA C O 1
Clock-to-output delay
when using output
registers
480
715
480
749
457
480
821
480
957
ps
tM E G A D ATA C O 2
Clock-to-output delay
without output registers
1,950
2,899
1,950
3,042
1,857
1,950
3,332
1,950
3,884
ps
tM E G A C L K L
Minimum clock low time
1,250
5–40
Stratix II Device Handbook, Volume 1
1,437
1,437
3,189
1,777
1,866
Max
tM E G A R C
1,312
1,777
1,866
Max
Min
(4)
1,675
3,716
ps
ps
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–42. M-RAM Block Internal Timing Microparameters (Part 2 of 2)
-3 Speed
Grade (2)
Symbol
-3 Speed
Grade (3)
Note (1)
-4 Speed
Grade
-5 Speed
Grade
Parameter
Unit
Min
(4)
Max
Min
(4)
Max
Min
(5)
Max
Min
(4)
Max
tM E G A C L K H
Minimum clock high
time
1,250
1,312
1,437
1,437
1,675
ps
tM E G A C L R
Minimum clear pulse
width
144
151
165
165
192
ps
Notes to Table 5–42:
(1)
(2)
(3)
(4)
(5)
FMAX of M-RAM Block obtained using the Quartus II software does not necessarily equal to 1/TMEGARC.
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade
devices offer the industrial temperature grade.
For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second
number is the minimum timing parameter for commercial devices.
Stratix II Clock Timing Parameters
See Tables 5–43 through 5–67 for Stratix II clock timing parameters.
Table 5–43. Stratix II Clock Timing Parameters
Symbol
Altera Corporation
April 2011
Parameter
tC I N
Delay from clock pad to I/O input register
tC O U T
Delay from clock pad to I/O output register
tP L L C I N
Delay from PLL inclk pad to I/O input register
tP L L C O U T
Delay from PLL inclk pad to I/O output register
5–41
Stratix II Device Handbook, Volume 1
Timing Model
EP2S15 Clock Timing Parameters
Tables 5–44 though 5–47 show the maximum clock timing parameters for
EP2S15 devices.
Table 5–44. EP2S15 Column Pins Regional Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
tC I N
1.445
1.512
2.487
2.848
3.309
ns
tC O U T
1.288
1.347
2.245
2.570
2.985
ns
Parameter
-4 Speed
Grade
-5 Speed
Grade
Unit
tP L L C I N
0.104
0.102
0.336
0.373
0.424
ns
tP L L C O U T
-0.053
-0.063
0.094
0.095
0.1
ns
-4 Speed
Grade
-5 Speed
Grade
Unit
Table 5–45. EP2S15 Column Pins Global Clock Timing Parameters
Minimum Timing
Parameter
Industrial
Commercial
-3 Speed
Grade
tC I N
1.419
1.487
2.456
2.813
3.273
ns
tC O U T
1.262
1.322
2.214
2.535
2.949
ns
tP L L C I N
0.094
0.092
0.326
0.363
0.414
ns
tP L L C O U T
-0.063
-0.073
0.084
0.085
0.09
ns
Table 5–46. EP2S15 Row Pins Regional Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
1.232
1.288
2.144
Parameter
tC I N
-4 Speed
Grade
-5 Speed
Grade
Unit
2.454
2.848
ns
tC O U T
1.237
1.293
2.140
2.450
2.843
ns
tP L L C I N
-0.109
-0.122
-0.007
-0.021
-0.037
ns
tP L L C O U T
-0.104
-0.117
-0.011
-0.025
-0.042
ns
5–42
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–47. EP2S15 Row Pins Global Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
1.206
1.262
2.113
Parameter
tC I N
-4 Speed
Grade
-5 Speed
Grade
Unit
2.422
2.815
ns
tC O U T
1.211
1.267
2.109
2.418
2.810
ns
tP L L C I N
-0.125
-0.138
-0.023
-0.038
-0.056
ns
tP L L C O U T
-0.12
-0.133
-0.027
-0.042
-0.061
ns
EP2S30 Clock Timing Parameters
Tables 5–48 through 5–51 show the maximum clock timing parameters
for EP2S30 devices.
Table 5–48. EP2S30 Column Pins Regional Clock Timing Parameters
Minimum Timing
Parameter
Industrial
Commercial
-3 Speed
Grade
-4 Speed
Grade
-5 Speed
Grade
Unit
tC I N
1.553
1.627
2.639
3.025
3.509
ns
tC O U T
1.396
1.462
2.397
2.747
3.185
ns
tP L L C I N
0.114
0.113
0.225
0.248
0.28
ns
tP L L C O U T
-0.043
-0.052
-0.017
-0.03
-0.044
ns
-4 Speed
Grade
-5 Speed
Grade
Unit
Table 5–49. EP2S30 Column Pins Global Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
tC I N
1.539
1.613
2.622
3.008
3.501
ns
tC O U T
1.382
1.448
2.380
2.730
3.177
ns
tP L L C I N
0.101
0.098
0.209
0.229
0.267
ns
tP L L C O U T
-0.056
-0.067
-0.033
-0.049
-0.057
ns
Parameter
Altera Corporation
April 2011
5–43
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–50. EP2S30 Row Pins Regional Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
1.304
1.184
1.966
Parameter
tC I N
-4 Speed
Grade
-5 Speed
Grade
Unit
2.251
2.616
ns
tC O U T
1.309
1.189
1.962
2.247
2.611
ns
tP L L C I N
-0.135
–0.158
–0.208
–0.254
–0.302
ns
tP L L C O U T
-0.13
–0.153
–0.212
–0.258
–0.307
ns
-4 Speed
Grade
-5 Speed
Grade
Unit
Table 5–51. EP2S30 Row Pins Global Clock Timing Parameters
Minimum Timing
Parameter
Industrial
Commercial
-3 Speed
Grade
tC I N
1.289
1.352
2.238
2.567
2.990
ns
tC O U T
1.294
1.357
2.234
2.563
2.985
ns
tP L L C I N
-0.14
-0.154
-0.169
-0.205
-0.254
ns
tP L L C O U T
-0.135
-0.149
-0.173
-0.209
-0.259
ns
EP2S60 Clock Timing Parameters
Tables 5–52 through 5–55 show the maximum clock timing parameters
for EP2S60 devices.
Table 5–52. EP2S60 Column Pins Regional Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
tC I N
1.681
1.762
2.945
3.381
3.931
ns
tC O U T
1.524
1.597
2.703
3.103
3.607
ns
tP L L C I N
0.066
0.064
0.279
0.311
0.348
ns
tP L L C O U T
-0.091
-0.101
0.037
0.033
0.024
ns
Parameter
5–44
Stratix II Device Handbook, Volume 1
-4 Speed
Grade
-5 Speed
Grade
Unit
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–53. EP2S60 Column Pins Global Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
tC I N
1.658
1.739
2.920
tC O U T
1.501
1.574
2.678
3.072
3.575
ns
tP L L C I N
0.06
0.057
0.278
0.304
0.355
ns
-0.097
-0.108
0.036
0.026
0.031
ns
-4 Speed
Grade
-5 Speed
Grade
Unit
Parameter
tP L L C O U T
-4 Speed
Grade
-5 Speed
Grade
Unit
3.350
3.899
ns
Table 5–54. EP2S60 Row Pins Regional Clock Timing Parameters
Minimum Timing
Parameter
Industrial
Commercial
-3 Speed
Grade
tC I N
1.463
1.532
2.591
2.972
3.453
ns
tC O U T
1.468
1.537
2.587
2.968
3.448
ns
tP L L C I N
-0.153
-0.167
-0.079
-0.099
-0.128
ns
tP L L C O U T
-0.148
-0.162
-0.083
-0.103
-0.133
ns
-4 Speed
Grade
-5 Speed
Grade
Unit
Table 5–55. EP2S60 Row Pins Global Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
tC I N
1.439
1.508
2.562
2.940
3.421
ns
tC O U T
1.444
1.513
2.558
2.936
3.416
ns
tP L L C I N
-0.161
-0.174
-0.083
-0.107
-0.126
ns
tP L L C O U T
-0.156
-0.169
-0.087
-0.111
-0.131
ns
Parameter
Altera Corporation
April 2011
5–45
Stratix II Device Handbook, Volume 1
Timing Model
EP2S90 Clock Timing Parameters
Tables 5–56 through 5–59 show the maximum clock timing parameters
for EP2S90 devices.
Table 5–56. EP2S90 Column Pins Regional Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
tC I N
1.768
1.850
3.033
3.473
4.040
ns
tC O U T
1.611
1.685
2.791
3.195
3.716
ns
Parameter
-4 Speed
Grade
-5 Speed
Grade
Unit
tP L L C I N
-0.127
-0.117
0.125
0.129
0.144
ns
tP L L C O U T
-0.284
-0.282
-0.117
-0.149
-0.18
ns
Table 5–57. EP2S90 Column Pins Global Clock Timing Parameters
Minimum Timing
Commercial
-3 Speed
Grade
-4 Speed
Grade
-5 Speed
Grade
Unit
Industrial
tC I N
1.783
1.868
3.058
3.502
4.070
ns
tC O U T
1.626
1.703
2.816
3.224
3.746
ns
Parameter
tP L L C I N
-0.137
-0.127
0.115
0.119
0.134
ns
tP L L C O U T
-0.294
-0.292
-0.127
-0.159
-0.19
ns
-4 Speed
Grade
-5 Speed
Grade
Unit
3.124
3.632
ns
Table 5–58. EP2S90 Row Pins Regional Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
1.566
1.638
2.731
Parameter
tC I N
tC O U T
1.571
1.643
2.727
3.120
3.627
ns
tP L L C I N
-0.326
-0.326
-0.178
-0.218
-0.264
ns
tP L L C O U T
-0.321
-0.321
-0.182
-0.222
-0.269
ns
5–46
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–59. EP2S90 Row Pins Global Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
1.585
1.658
2.757
Parameter
tC I N
-4 Speed
Grade
-5 Speed
Grade
Unit
3.154
3.665
ns
tC O U T
1.590
1.663
2.753
3.150
3.660
ns
tP L L C I N
-0.341
-0.341
-0.193
-0.235
-0.278
ns
tP L L C O U T
-0.336
-0.336
-0.197
-0.239
-0.283
ns
EP2S130 Clock Timing Parameters
Tables 5–60 through 5–63 show the maximum clock timing parameters
for EP2S130 devices.
Table 5–60. EP2S130 Column Pins Regional Clock Timing Parameters
Minimum Timing
Parameter
Industrial
Commercial
-3 Speed
Grade
-4 Speed
Grade
-5 Speed
Grade
Unit
tC I N
1.889
1.981
3.405
3.722
4.326
ns
tC O U T
1.732
1.816
3.151
3.444
4.002
ns
tP L L C I N
0.105
0.106
0.226
0.242
0.277
ns
tP L L C O U T
-0.052
-0.059
-0.028
-0.036
-0.047
ns
-4 Speed
Grade
-5 Speed
Grade
Unit
Table 5–61. EP2S130 Column Pins Global Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
tC I N
1.907
1.998
3.420
3.740
4.348
ns
tC O U T
1.750
1.833
3.166
3.462
4.024
ns
tP L L C I N
0.134
0.136
0.276
0.296
0.338
ns
tP L L C O U T
-0.023
-0.029
0.022
0.018
0.014
ns
Parameter
Altera Corporation
April 2011
5–47
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–62. EP2S130 Row Pins Regional Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
1.680
1.760
3.070
Parameter
tC I N
-4 Speed
Grade
-5 Speed
Grade
Unit
3.351
3.892
ns
tC O U T
1.685
1.765
3.066
3.347
3.887
ns
tP L L C I N
-0.113
-0.124
-0.12
-0.138
-0.168
ns
tP L L C O U T
-0.108
-0.119
-0.124
-0.142
-0.173
ns
-4 Speed
Grade
-5 Speed
Grade
Unit
Table 5–63. EP2S130 Row Pins Global Clock Timing Parameters
Minimum Timing
Parameter
Industrial
Commercial
-3 Speed
Grade
tC I N
1.690
1.770
3.075
3.362
3.905
ns
tC O U T
1.695
1.775
3.071
3.358
3.900
ns
tP L L C I N
-0.087
-0.097
-0.075
-0.089
-0.11
ns
tP L L C O U T
-0.082
-0.092
-0.079
-0.093
-0.115
ns
EP2S180 Clock Timing Parameters
Tables 5–64 through 5–67 show the maximum clock timing parameters
for EP2S180 devices.
Table 5–64. EP2S180 Column Pins Regional Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
tC I N
2.001
2.095
3.643
3.984
4.634
ns
tC O U T
1.844
1.930
3.389
3.706
4.310
ns
tP L L C I N
-0.307
-0.297
0.053
0.046
0.048
ns
tP L L C O U T
-0.464
-0.462
-0.201
-0.232
-0.276
ns
Parameter
5–48
Stratix II Device Handbook, Volume 1
-4 Speed
Grade
-5 Speed
Grade
Unit
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–65. EP2S180 Column Pins Global Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
tC I N
2.003
2.100
3.652
3.993
4.648
ns
tC O U T
1.846
1.935
3.398
3.715
4.324
ns
-0.3
-0.29
0.053
0.054
0.058
ns
-0.457
-0.455
-0.201
-0.224
-0.266
ns
-4 Speed
Grade
-5 Speed
Grade
Unit
Parameter
tP L L C I N
tP L L C O U T
-4 Speed
Grade
-5 Speed
Grade
Unit
Table 5–66. EP2S180 Row Pins Regional Clock Timing Parameters
Minimum Timing
Parameter
Industrial
Commercial
-3 Speed
Grade
tC I N
1.759
1.844
3.273
3.577
4.162
ns
tC O U T
1.764
1.849
3.269
3.573
4.157
ns
tP L L C I N
-0.542
-0.541
-0.317
-0.353
-0.414
ns
tP L L C O U T
-0.537
-0.536
-0.321
-0.357
-0.419
ns
-4 Speed
Grade
-5 Speed
Grade
Unit
Table 5–67. EP2S180 Row Pins Global Clock Timing Parameters
Minimum Timing
Industrial
Commercial
-3 Speed
Grade
tC I N
1.763
1.850
3.285
3.588
4.176
ns
tC O U T
1.768
1.855
3.281
3.584
4.171
ns
tP L L C I N
-0.542
-0.542
-0.319
-0.355
-0.42
ns
tP L L C O U T
-0.537
-0.537
-0.323
-0.359
-0.425
ns
Parameter
Altera Corporation
April 2011
5–49
Stratix II Device Handbook, Volume 1
Timing Model
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks
such as global and regional clocks. Therefore, intra-clock network skew
adder is not specified. Table 5–68 specifies the clock skew between any
two clock networks driving registers in the IOE.
Table 5–68. Clock Network Specifications
Name
Description
Min
Typ
Max
Unit
Clock skew adder
EP2S15, EP2S30,
EP2S60 (1)
Inter-clock network, same side
±50
ps
Inter-clock network, entire chip
±100
ps
Clock skew adder
EP2S90 (1)
Inter-clock network, same side
±55
ps
Inter-clock network, entire chip
±110
ps
Clock skew adder
EP2S130 (1)
Inter-clock network, same side
±63
ps
Inter-clock network, entire chip
±125
ps
Clock skew adder
EP2S180 (1)
Inter-clock network, same side
±75
ps
Inter-clock network, entire chip
±150
ps
Note to Table 5–68:
(1)
This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
5–50
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
IOE Programmable Delay
See Tables 5–69 and 5–70 for IOE programmable delay.
Table 5–69. Stratix II IOE Programmable Delay on Column Pins
Minimum
Timing (2)
Parameter
Paths Affected
Available
Settings
Note (1)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Min
Max
Min
Max
Min
Max
Min
Max
Offset Offset Offset Offset Offset Offset Offset Offset
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
Input delay from Pad to I/O
dataout to logic
pin to internal
array
cells
8
0
0
1,696
1,781
0
0
2,881
3,025
0
3,313
0
3,860
Input delay from Pad to I/O input
register
pin to input
register
64
0
0
1,955
2,053
0
0
3,275
3,439
0
3,766
0
4,388
Delay from
output register
to output pin
I/O output
register to pad
2
0
0
316
332
0
0
500
525
0
575
0
670
Output enable
pin delay
tX Z , tZ X
2
0
0
305
320
0
0
483
507
0
556
0
647
Notes to Table 5–69:
(1)
(2)
(3)
The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the
latest version of the Quartus II software.
The first number is the minimum timing parameter for industrial devices. The second number is the minimum
timing parameter for commercial devices.
The first number applies to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. The second number
applies to -3 speed grade EP2S130 and EP2S180 devices.
Altera Corporation
April 2011
5–51
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–70. Stratix II IOE Programmable Delay on Row Pins
Minimum
Timing (2)
Parameter
Paths Affected
Available
Settings
Note (1)
-3 Speed
Grade (3)
-4 Speed
Grade
-5 Speed
Grade
Min
Max
Min
Max
Min
Max
Min
Max
Offset Offset Offset Offset Offset Offset Offset Offset
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
(ps)
Input delay from Pad to I/O
dataout to logic
pin to internal
array
cells
8
0
0
1,697
1,782
0
0
2,876
3,020
0
3,308
0
3,853
Input delay from Pad to I/O input
register
pin to input
register
64
0
0
1,956
2,054
0
0
3,270
3,434
0
3,761
0
4,381
Delay from
output register
to output pin
I/O output
register to pad
2
0
0
316
332
0
0
525
525
0
575
0
670
Output enable
pin delay
tX Z , tZ X
2
0
0
305
320
0
0
507
507
0
556
0
647
Notes to Table 5–70:
(1)
(2)
(3)
The incremental values for the settings are generally linear. For the exact delay associated with each setting, use the
latest version of the Quartus II software.
The first number is the minimum timing parameter for industrial devices. The second number is the minimum
timing parameter for commercial devices.
The first number applies to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices. The second number
applies to -3 speed grade EP2S130 and EP2S180 devices.
Default Capacitive Loading of Different I/O Standards
See Table 5–71 for default capacitive loading of different I/O standards.
Table 5–71. Default Loading of Different I/O Standards for Stratix II (Part 1
of 2)
I/O Standard
Capacitive Load
Unit
LVTTL
0
pF
LVCMOS
0
pF
2.5 V
0
pF
1.8 V
0
pF
1.5 V
0
pF
PCI
10
pF
PCI-X
10
pF
SSTL-2 Class I
0
pF
5–52
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–71. Default Loading of Different I/O Standards for Stratix II (Part 2
of 2)
I/O Standard
SSTL-2 Class II
Altera Corporation
April 2011
Capacitive Load
Unit
0
pF
SSTL-18 Class I
0
pF
SSTL-18 Class II
0
pF
1.5-V HSTL Class I
0
pF
1.5-V HSTL Class II
0
pF
1.8-V HSTL Class I
0
pF
1.8-V HSTL Class II
0
pF
1.2-V HSTL with OCT
0
pF
Differential SSTL-2 Class I
0
pF
Differential SSTL-2 Class II
0
pF
Differential SSTL-18 Class I
0
pF
Differential SSTL-18 Class II
0
pF
1.5-V Differential HSTL Class I
0
pF
1.5-V Differential HSTL Class II
0
pF
1.8-V Differential HSTL Class I
0
pF
1.8-V Differential HSTL Class II
0
pF
LVDS
0
pF
HyperTransport
0
pF
LVPECL
0
pF
5–53
Stratix II Device Handbook, Volume 1
Timing Model
I/O Delays
See Tables 5–72 through 5–76 for I/O delays.
Table 5–72. I/O Delay Parameters
Symbol
Parameter
tD I P
Delay from I/O datain to output pad
tO P
Delay from I/O output register to output pad
tP C O U T
Delay from input pad to I/O dataout to core
tP I
Delay from input pad to I/O input register
Table 5–73. Stratix II I/O Input Delay for Column Pins (Part 1 of 3)
Minimum Timing
I/O Standard
Parameter
Industrial
LVTTL
2.5 V
1.8 V
1.5 V
LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL
Class I
-3 Speed -3 Speed
-4 Speed -5 Speed
Grade
Grade
Grade
Grade
Commercial
(2)
(3)
Unit
tP I
674
707
1223
1282
1405
1637
ps
tP C O U T
408
428
787
825
904
1054
ps
tP I
684
717
1210
1269
1390
1619
ps
tP C O U T
418
438
774
812
889
1036
ps
tP I
747
783
1366
1433
1570
1829
ps
tP C O U T
481
504
930
976
1069
1246
ps
tP I
749
786
1436
1506
1650
1922
ps
tP C O U T
483
507
1000
1049
1149
1339
ps
tP I
674
707
1223
1282
1405
1637
ps
tP C O U T
408
428
787
825
904
1054
ps
tP I
507
530
818
857
939
1094
ps
tP C O U T
241
251
382
400
438
511
ps
tP I
507
530
818
857
939
1094
ps
tP C O U T
241
251
382
400
438
511
ps
tP I
543
569
898
941
1031
1201
ps
tP C O U T
277
290
462
484
530
618
ps
tP I
543
569
898
941
1031
1201
ps
tP C O U T
277
290
462
484
530
618
ps
tP I
560
587
993
1041
1141
1329
ps
tP C O U T
294
308
557
584
640
746
ps
5–54
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–73. Stratix II I/O Input Delay for Column Pins (Part 2 of 3)
Minimum Timing
I/O Standard
Parameter
Industrial
1.5-V HSTL
Class II
1.8-V HSTL
Class I
1.8-V HSTL
Class II
PCI
PCI-X
Differential
SSTL-2 Class I
(1)
Differential
SSTL-2 Class II
(1)
Differential
SSTL-18 Class I
(1)
Differential
SSTL-18 Class II
(1)
1.8-V Differential
HSTL Class I (1)
1.8-V Differential
HSTL Class II (1)
1.5-V Differential
HSTL Class I (1)
1.5-V Differential
HSTL Class II (1)
Altera Corporation
April 2011
tP I
560
-3 Speed -3 Speed
-4 Speed -5 Speed
Grade
Grade
Grade
Grade
Commercial
(2)
(3)
587
993
1041
1141
Unit
1329
ps
tP C O U T
294
308
557
584
640
746
ps
tP I
543
569
898
941
1031
1201
ps
tP C O U T
277
290
462
484
530
618
ps
tP I
543
569
898
941
1031
1201
ps
tP C O U T
277
290
462
484
530
618
ps
tP I
679
712
1214
1273
1395
1625
ps
tP C O U T
413
433
778
816
894
1042
ps
tP I
679
712
1214
1273
1395
1625
ps
tP C O U T
413
433
778
816
894
1042
ps
tP I
507
530
818
857
939
1094
ps
tP C O U T
241
251
382
400
438
511
ps
tP I
507
530
818
857
939
1094
ps
tP C O U T
241
251
382
400
438
511
ps
tP I
543
569
898
941
1031
1201
ps
tP C O U T
277
290
462
484
530
618
ps
tP I
543
569
898
941
1031
1201
ps
tP C O U T
277
290
462
484
530
618
ps
tP I
543
569
898
941
1031
1201
ps
tP C O U T
277
290
462
484
530
618
ps
tP I
543
569
898
941
1031
1201
ps
tP C O U T
277
290
462
484
530
618
ps
tP I
560
587
993
1041
1141
1329
ps
tP C O U T
294
308
557
584
640
746
ps
tP I
560
587
993
1041
1141
1329
ps
tP C O U T
294
308
557
584
640
746
ps
5–55
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–73. Stratix II I/O Input Delay for Column Pins (Part 3 of 3)
Minimum Timing
I/O Standard
Parameter
Industrial
1.2-V HSTL
-3 Speed -3 Speed
-4 Speed -5 Speed
Grade
Grade
Grade
Grade
Commercial
(2)
(3)
Unit
tP I
645
677
1194
1252
-
-
ps
tP C O U T
379
398
758
795
-
-
ps
Notes for Table 5–73:
(1)
(2)
(3)
These I/O standards are only supported on DQS pins.
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Table 5–74. Stratix II I/O Input Delay for Row Pins (Part 1 of 2)
Minimum Timing
I/O Standard
Parameter
Industrial
LVTTL
2.5 V
1.8 V
1.5 V
-3 Speed -3 Speed
-4 Speed -5 Speed
Grade
Grade
Grade
Grade
Commercial
(1)
(2)
Unit
tP I
715
749
1287
1350
1477
1723
ps
tP C O U T
391
410
760
798
873
1018
ps
tP I
726
761
1273
1335
1461
1704
ps
tP C O U T
402
422
746
783
857
999
ps
tP I
788
827
1427
1497
1639
1911
ps
tP C O U T
464
488
900
945
1035
1206
ps
tP I
792
830
1498
1571
1720
2006
ps
tP C O U T
468
491
971
1019
1116
1301
ps
LVCMOS
tP I
715
749
1287
1350
1477
1723
ps
tP C O U T
391
410
760
798
873
1018
ps
SSTL-2 Class I
tP I
547
573
879
921
1008
1176
ps
tP C O U T
223
234
352
369
404
471
ps
tP I
547
573
879
921
1008
1176
ps
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL
Class I
tP C O U T
223
234
352
369
404
471
ps
tP I
577
605
960
1006
1101
1285
ps
tP C O U T
253
266
433
454
497
580
ps
tP I
577
605
960
1006
1101
1285
ps
tP C O U T
253
266
433
454
497
580
ps
tP I
602
631
1056
1107
1212
1413
ps
tP C O U T
278
292
529
555
608
708
ps
5–56
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–74. Stratix II I/O Input Delay for Row Pins (Part 2 of 2)
Minimum Timing
I/O Standard
Parameter
Industrial
1.5-V HSTL
Class II
tP I
1.8-V HSTL
Class I
1.8-V HSTL
Class II
-3 Speed -3 Speed
-4 Speed -5 Speed
Grade
Grade
Grade
Grade
Commercial
(1)
(2)
602
631
1056
1107
1212
Unit
1413
ps
tP C O U T
278
292
529
555
608
708
ps
tP I
577
605
960
1006
1101
1285
ps
tP C O U T
253
266
433
454
497
580
ps
tP I
577
605
960
1006
1101
1285
ps
tP C O U T
253
266
433
454
497
580
ps
LVDS
tP I
515
540
948
994
1088
1269
ps
tP C O U T
191
201
421
442
484
564
ps
HyperTransport
tP I
515
540
948
994
1088
1269
ps
tP C O U T
191
201
421
442
484
564
ps
Notes for Table 5–74:
(1)
(2)
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 1 of 8)
Minimum Timing
I/O Standard
LVTTL
Drive
Parameter
Strength
4 mA
8 mA
12 mA
16 mA
Industrial
-3
-3
-4
-5
Speed Speed
Speed Speed Unit
Commercial Grade Grade Grade Grade
(3)
(4)
tO P
1178
1236
2351
2467
2702
2820
ps
tD I P
1198
1258
2417
2537
2778
2910
ps
tO P
1041
1091
2036
2136
2340
2448
ps
tD I P
1061
1113
2102
2206
2416
2538
ps
tO P
976
1024
2036
2136
2340
2448
ps
tD I P
996
1046
2102
2206
2416
2538
ps
tO P
951
998
1893
1986
2176
2279
ps
tD I P
971
1020
1959
2056
2252
2369
ps
20 mA
tO P
931
976
1787
1875
2054
2154
ps
tD I P
951
998
1853
1945
2130
2244
ps
24 mA
(1)
tO P
924
969
1788
1876
2055
2156
ps
tD I P
944
991
1854
1946
2131
2246
ps
Altera Corporation
April 2011
5–57
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 2 of 8)
Minimum Timing
I/O Standard
LVCMOS
Drive
Parameter
Strength
4 mA
8 mA
12 mA
16 mA
tO P
1041
1091
2036
2136
2340
2448
ps
tD I P
1061
1113
2102
2206
2416
2538
ps
tO P
952
999
1786
1874
2053
2153
ps
tD I P
972
1021
1852
1944
2129
2243
ps
tO P
926
971
1720
1805
1977
2075
ps
tD I P
946
993
1786
1875
2053
2165
ps
tO P
933
978
1693
1776
1946
2043
ps
tD I P
953
1000
1759
1846
2022
2133
ps
tO P
921
965
1677
1759
1927
2025
ps
tD I P
941
987
1743
1829
2003
2115
ps
24 mA
(1)
tO P
909
954
1659
1741
1906
2003
ps
tD I P
929
976
1725
1811
1982
2093
ps
4 mA
tO P
1004
1053
2063
2165
2371
2480
ps
tD I P
1024
1075
2129
2235
2447
2570
ps
8 mA
tO P
955
1001
1841
1932
2116
2218
ps
tD I P
975
1023
1907
2002
2192
2308
ps
20 mA
2.5 V
Industrial
-3
-3
-4
-5
Speed Speed
Speed Speed Unit
Commercial Grade Grade Grade Grade
(3)
(4)
12 mA
16 mA
(1)
tO P
934
980
1742
1828
2002
2101
ps
tD I P
954
1002
1808
1898
2078
2191
ps
tO P
918
962
1679
1762
1929
2027
ps
tD I P
938
984
1745
1832
2005
2117
ps
5–58
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 3 of 8)
Minimum Timing
I/O Standard
1.8 V
Drive
Parameter
Strength
2 mA
Industrial
-3
-3
-4
-5
Speed Speed
Speed Speed Unit
Commercial Grade Grade Grade Grade
(3)
(4)
tO P
1042
1093
2904
3048
3338
3472
ps
tD I P
1062
1115
2970
3118
3414
3562
ps
4 mA
tO P
1047
1098
2248
2359
2584
2698
ps
tD I P
1067
1120
2314
2429
2660
2788
ps
6 mA
tO P
974
1022
2024
2124
2326
2434
ps
tD I P
994
1044
2090
2194
2402
2524
ps
tO P
976
1024
1947
2043
2238
2343
ps
tD I P
996
1046
2013
2113
2314
2433
ps
tO P
933
978
1882
1975
2163
2266
ps
tD I P
953
1000
1948
2045
2239
2356
ps
12 mA
(1)
tO P
934
979
1833
1923
2107
2209
ps
tD I P
954
1001
1899
1993
2183
2299
ps
2 mA
tO P
1023
1073
2505
2629
2879
3002
ps
tD I P
1043
1095
2571
2699
2955
3092
ps
4 mA
tO P
963
1009
2023
2123
2325
2433
ps
tD I P
983
1031
2089
2193
2401
2523
ps
tO P
966
1012
1923
2018
2210
2315
ps
tD I P
986
1034
1989
2088
2286
2405
ps
tO P
926
971
1878
1970
2158
2262
ps
tD I P
946
993
1944
2040
2234
2352
ps
tO P
913
957
1715
1799
1971
2041
ps
tD I P
933
979
1781
1869
2047
2131
ps
12 mA
(1)
tO P
896
940
1672
1754
1921
1991
ps
tD I P
916
962
1738
1824
1997
2081
ps
SSTL-2 Class II 16 mA
tO P
876
918
1609
1688
1849
1918
ps
tD I P
896
940
1675
1758
1925
2008
ps
8 mA
10 mA
1.5 V
6 mA
8 mA (1)
SSTL-2 Class I 8 mA
20 mA
24 mA
(1)
Altera Corporation
April 2011
tO P
877
919
1598
1676
1836
1905
ps
tD I P
897
941
1664
1746
1912
1995
ps
tO P
872
915
1596
1674
1834
1903
ps
tD I P
892
937
1662
1744
1910
1993
ps
5–59
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 4 of 8)
Minimum Timing
I/O Standard
SSTL-18
Class I
Drive
Parameter
Strength
4 mA
tO P
909
953
1690
1773
1942
2012
ps
tD I P
929
975
1756
1843
2018
2102
ps
6 mA
tO P
914
958
1656
1737
1903
1973
ps
tD I P
934
980
1722
1807
1979
2063
ps
8 mA
tO P
894
937
1640
1721
1885
1954
ps
tD I P
914
959
1706
1791
1961
2044
ps
10 mA
SSTL-18
Class II
tO P
898
942
1638
1718
1882
1952
ps
tD I P
918
964
1704
1788
1958
2042
ps
12 mA
(1)
tO P
891
936
1626
1706
1869
1938
ps
tD I P
911
958
1692
1776
1945
2028
ps
8 mA
tO P
883
925
1597
1675
1835
1904
ps
tD I P
903
947
1663
1745
1911
1994
ps
tO P
894
937
1578
1655
1813
1882
ps
16 mA
tD I P
914
959
1644
1725
1889
1972
ps
tO P
890
933
1585
1663
1821
1890
ps
tD I P
910
955
1651
1733
1897
1980
ps
20 mA
(1)
tO P
890
933
1583
1661
1819
1888
ps
tD I P
910
955
1649
1731
1895
1978
ps
4 mA
tO P
912
956
1608
1687
1848
1943
ps
tD I P
932
978
1674
1757
1924
2033
ps
tO P
917
962
1595
1673
1833
1928
ps
tD I P
937
984
1661
1743
1909
2018
ps
tO P
896
940
1586
1664
1823
1917
ps
18 mA
1.8-V HSTL
Class I
Industrial
-3
-3
-4
-5
Speed Speed
Speed Speed Unit
Commercial Grade Grade Grade Grade
(3)
(4)
6 mA
8 mA
10 mA
12 mA
(1)
tD I P
916
962
1652
1734
1899
2007
ps
tO P
900
944
1591
1669
1828
1923
ps
tD I P
920
966
1657
1739
1904
2013
ps
tO P
892
936
1585
1663
1821
1916
ps
tD I P
912
958
1651
1733
1897
2006
ps
5–60
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 5 of 8)
Minimum Timing
I/O Standard
1.8-V HSTL
Class II
1.5-V HSTL
Class I
Drive
Parameter
Strength
16 mA
tO P
877
919
1385
1453
1591
1680
ps
tD I P
897
941
1451
1523
1667
1770
ps
18 mA
tO P
879
921
1394
1462
1602
1691
ps
tD I P
899
943
1460
1532
1678
1781
ps
20 mA
(1)
tO P
879
921
1402
1471
1611
1700
ps
tD I P
899
943
1468
1541
1687
1790
ps
4 mA
tO P
912
956
1607
1686
1847
1942
ps
tD I P
932
978
1673
1756
1923
2032
ps
tO P
917
961
1588
1666
1825
1920
ps
tD I P
937
983
1654
1736
1901
2010
ps
tO P
899
943
1590
1668
1827
1922
ps
tD I P
919
965
1656
1738
1903
2012
ps
10 mA
tO P
900
943
1592
1670
1829
1924
ps
tD I P
920
965
1658
1740
1905
2014
ps
12 mA
(1)
tO P
893
937
1590
1668
1827
1922
ps
tD I P
913
959
1656
1738
1903
2012
ps
6 mA
8 mA
1.5-V HSTL
Class II
Industrial
-3
-3
-4
-5
Speed Speed
Speed Speed Unit
Commercial Grade Grade Grade Grade
(3)
(4)
16 mA
tO P
881
924
1431
1501
1644
1734
ps
tD I P
901
946
1497
1571
1720
1824
ps
tO P
884
927
1439
1510
1654
1744
ps
tD I P
904
949
1505
1580
1730
1834
ps
tO P
886
929
1450
1521
1666
1757
ps
tD I P
906
951
1516
1591
1742
1847
ps
1.2-V HSTL
tO P
958
1004
1602
1681
-
-
ps
tD I P
978
1026
1668
1751
-
-
ps
PCI
tO P
1028
1082
1956
2051
2244
2070
ps
tD I P
1048
1104
2022
2121
2320
2160
ps
tO P
1028
1082
1956
2051
2244
2070
ps
tD I P
1048
1104
2022
2121
2320
2160
ps
18 mA
20 mA
(1)
PCI-X
Altera Corporation
April 2011
5–61
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 6 of 8)
Minimum Timing
I/O Standard
Differential
SSTL-2 Class I
Drive
Parameter
Strength
8 mA
Industrial
-3
-3
-4
-5
Speed Speed
Speed Speed Unit
Commercial Grade Grade Grade Grade
(3)
(4)
tO P
913
957
1715
1799
1971
2041
ps
tD I P
933
979
1781
1869
2047
2131
ps
12 mA
tO P
896
940
1672
1754
1921
1991
ps
tD I P
916
962
1738
1824
1997
2081
ps
Differential
16 mA
SSTL-2 Class II
tO P
876
918
1609
1688
1849
1918
ps
tD I P
896
940
1675
1758
1925
2008
ps
20 mA
tO P
877
919
1598
1676
1836
1905
ps
tD I P
897
941
1664
1746
1912
1995
ps
tO P
872
915
1596
1674
1834
1903
ps
tD I P
892
937
1662
1744
1910
1993
ps
tO P
909
953
1690
1773
1942
2012
ps
tD I P
929
975
1756
1843
2018
2102
ps
6 mA
tO P
914
958
1656
1737
1903
1973
ps
tD I P
934
980
1722
1807
1979
2063
ps
8 mA
tO P
894
937
1640
1721
1885
1954
ps
tD I P
914
959
1706
1791
1961
2044
ps
tO P
898
942
1638
1718
1882
1952
ps
tD I P
918
964
1704
1788
1958
2042
ps
tO P
891
936
1626
1706
1869
1938
ps
tD I P
911
958
1692
1776
1945
2028
ps
tO P
883
925
1597
1675
1835
1904
ps
tD I P
903
947
1663
1745
1911
1994
ps
16 mA
tO P
894
937
1578
1655
1813
1882
ps
tD I P
914
959
1644
1725
1889
1972
ps
18 mA
tO P
890
933
1585
1663
1821
1890
ps
tD I P
910
955
1651
1733
1897
1980
ps
tO P
890
933
1583
1661
1819
1888
ps
tD I P
910
955
1649
1731
1895
1978
ps
24 mA
Differential
SSTL-18
Class I
4 mA
10 mA
12 mA
Differential
SSTL-18
Class II
8 mA
20 mA
5–62
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 7 of 8)
Minimum Timing
I/O Standard
1.8-V
Differential
HSTL Class I
Drive
Parameter
Strength
4 mA
tO P
912
956
1608
1687
1848
1943
ps
tD I P
932
978
1674
1757
1924
2033
ps
6 mA
tO P
917
962
1595
1673
1833
1928
ps
tD I P
937
984
1661
1743
1909
2018
ps
8 mA
tO P
896
940
1586
1664
1823
1917
ps
tD I P
916
962
1652
1734
1899
2007
ps
tO P
900
944
1591
1669
1828
1923
ps
tD I P
920
966
1657
1739
1904
2013
ps
tO P
892
936
1585
1663
1821
1916
ps
tD I P
912
958
1651
1733
1897
2006
ps
tO P
877
919
1385
1453
1591
1680
ps
tD I P
897
941
1451
1523
1667
1770
ps
18 mA
tO P
879
921
1394
1462
1602
1691
ps
tD I P
899
943
1460
1532
1678
1781
ps
20 mA
tO P
879
921
1402
1471
1611
1700
ps
tD I P
899
943
1468
1541
1687
1790
ps
tO P
912
956
1607
1686
1847
1942
ps
tD I P
932
978
1673
1756
1923
2032
ps
tO P
917
961
1588
1666
1825
1920
ps
tD I P
937
983
1654
1736
1901
2010
ps
tO P
899
943
1590
1668
1827
1922
ps
tD I P
919
965
1656
1738
1903
2012
ps
tO P
900
943
1592
1670
1829
1924
ps
ps
10 mA
12 mA
1.8-V
Differential
HSTL Class II
1.5-V
Differential
HSTL Class I
Industrial
-3
-3
-4
-5
Speed Speed
Speed Speed Unit
Commercial Grade Grade Grade Grade
(3)
(4)
16 mA
4 mA
6 mA
8 mA
10 mA
12 mA
Altera Corporation
April 2011
tD I P
920
965
1658
1740
1905
2014
tO P
893
937
1590
1668
1827
1922
tD I P
913
959
1656
1738
1903
2012
5–63
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 8 of 8)
Minimum Timing
I/O Standard
1.5-V
Differential
HSTL Class II
Drive
Parameter
Strength
16 mA
18 mA
20 mA
Industrial
tO P
881
-3
-3
-4
-5
Speed Speed
Speed Speed Unit
Commercial Grade Grade Grade Grade
(3)
(4)
924
1431
1501
1644
1734
ps
tD I P
901
946
1497
1571
1720
1824
ps
tO P
884
927
1439
1510
1654
1744
tD I P
904
949
1505
1580
1730
1834
tO P
886
929
1450
1521
1666
1757
tD I P
906
951
1516
1591
1742
1847
Notes to Table 5–75:
(1)
(2)
(3)
(4)
This is the default setting in the Quartus II software.
These I/O standards are only supported on DQS pins.
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Table 5–76. Stratix II I/O Output Delay for Row Pins (Part 1 of 3)
Minimum Timing
I/O Standard
LVTTL
Drive
Parameter
Strength
4 mA
Unit
tO P
1267
1328
2655
2786
3052
3189
ps
tD I P
1225
1285
2600
2729
2989
3116
ps
tO P
1144
1200
2113
2217
2429
2549
ps
tD I P
1102
1157
2058
2160
2366
2476
ps
12 mA
(1)
tO P
1091
1144
2081
2184
2392
2512
ps
tD I P
1049
1101
2026
2127
2329
2439
ps
4 mA
tO P
1144
1200
2113
2217
2429
2549
ps
tD I P
1102
1157
2058
2160
2366
2476
ps
8 mA (1) tO P
1044
1094
1853
1944
2130
2243
ps
tD I P
1002
1051
1798
1887
2067
2170
ps
8 mA
LVCMOS
Industrial
-3
-3
-4
-5
Speed Speed
Speed Speed
Commercial Grade Grade Grade Grade
(2)
(3)
5–64
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–76. Stratix II I/O Output Delay for Row Pins (Part 2 of 3)
Minimum Timing
I/O Standard
2.5 V
Drive
Parameter
Strength
4 mA
8 mA
12 mA
(1)
1.8 V
2 mA
tO P
1128
1183
2091
2194
2403
2523
ps
tD I P
1086
1140
2036
2137
2340
2450
ps
tO P
1030
1080
1872
1964
2152
2265
ps
tD I P
988
1037
1817
1907
2089
2192
ps
tO P
1012
1061
1775
1862
2040
2151
ps
tD I P
970
1018
1720
1805
1977
2078
ps
tO P
1196
1253
2954
3100
3396
3542
ps
1154
1210
2899
3043
3333
3469
ps
tO P
1184
1242
2294
2407
2637
2763
ps
tD I P
1142
1199
2239
2350
2574
2690
ps
tO P
1079
1131
2039
2140
2344
2462
ps
tD I P
1037
1088
1984
2083
2281
2389
ps
8 mA (1) tO P
1049
1100
1942
2038
2232
2348
ps
tD I P
1007
1057
1887
1981
2169
2275
ps
tO P
1158
1213
2530
2655
2908
3041
ps
tD I P
1116
1170
2475
2598
2845
2968
ps
tO P
1055
1106
2020
2120
2322
2440
ps
tD I P
1013
1063
1965
2063
2259
2367
ps
tO P
1002
1050
1759
1846
2022
2104
ps
tD I P
960
1007
1704
1789
1959
2031
ps
6 mA
2 mA
4 mA
SSTL-2 Class I 8 mA
SSTL-2 Class II 16 mA
(1)
SSTL-18
Class I
Unit
tD I P
4 mA
1.5 V
Industrial
-3
-3
-4
-5
Speed Speed
Speed Speed
Commercial Grade Grade Grade Grade
(2)
(3)
tO P
947
992
1581
1659
1817
1897
ps
tD I P
905
949
1526
1602
1754
1824
ps
4 mA
tO P
990
1038
1709
1793
1964
2046
ps
tD I P
948
995
1654
1736
1901
1973
ps
6 mA
tO P
994
1042
1648
1729
1894
1975
ps
tD I P
952
999
1593
1672
1831
1902
ps
tO P
970
1018
1633
1713
1877
1958
ps
tD I P
928
975
1578
1656
1814
1885
ps
tO P
974
1021
1615
1694
1856
1937
ps
tD I P
932
978
1560
1637
1793
1864
ps
8 mA
10 mA
(1)
Altera Corporation
April 2011
5–65
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–76. Stratix II I/O Output Delay for Row Pins (Part 3 of 3)
Minimum Timing
I/O Standard
1.8-V HSTL
Class I
Drive
Parameter
Strength
4 mA
Unit
tO P
972
1019
1610
1689
1850
1956
ps
tD I P
930
976
1555
1632
1787
1883
ps
6 mA
tO P
975
1022
1580
1658
1816
1920
ps
tD I P
933
979
1525
1601
1753
1847
ps
8 mA
tO P
958
1004
1576
1653
1811
1916
ps
tD I P
916
961
1521
1596
1748
1843
ps
tO P
962
1008
1567
1644
1801
1905
ps
tD I P
920
965
1512
1587
1738
1832
ps
12 mA
(1)
tO P
953
999
1566
1643
1800
1904
ps
tD I P
911
956
1511
1586
1737
1831
ps
4 mA
tO P
970
1018
1591
1669
1828
1933
ps
tD I P
928
975
1536
1612
1765
1860
ps
tO P
974
1021
1579
1657
1815
1919
ps
10 mA
1.5-V HSTL
Class I
Industrial
-3
-3
-4
-5
Speed Speed
Speed Speed
Commercial Grade Grade Grade Grade
(2)
(3)
6 mA
tD I P
932
978
1524
1600
1752
1846
ps
8 mA (1) tO P
960
1006
1572
1649
1807
1911
ps
tD I P
918
963
1517
1592
1744
1838
ps
LVDS
HyperTransport
tO P
1018
1067
1723
1808
1980
2089
ps
tD I P
976
1024
1668
1751
1917
2016
ps
tO P
1005
1053
1723
1808
1980
2089
ps
tD I P
963
1010
1668
1751
1917
2016
ps
Notes to Table 5–76:
(1)
(2)
(3)
This is the default setting in the Quartus II software.
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Maximum Input & Output Clock Toggle Rate
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
5–66
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Table 5–77 specifies the maximum input clock toggle rates. Table 5–78
specifies the maximum output clock toggle rates at 0pF load. Table 5–79
specifies the derating factors for the output clock toggle rate for a non 0pF
load.
To calculate the output toggle rate for a non 0pF load, use this formula:
The toggle rate for a non 0pF load
= 1000 / (1000/ toggle rate at 0pF load + derating factor * load value
in pF /1000)
For example, the output toggle rate at 0pF load for SSTL-18 Class II 20mA
I/O standard is 550 MHz on a -3 device clock output pin. The derating
factor is 94ps/pF. For a 10pF load the toggle rate is calculated as:
1000 / (1000/550 + 94 × 10 /1000) = 363 (MHz)
Tables 5–77 through 5–79 show the I/O toggle rates for Stratix II
devices.
Table 5–77. Maximum Input Toggle Rate on Stratix II Devices (Part 1 of 2)
Column I/O Pins (MHz)
Row I/O Pins (MHz)
Input I/O Standard
Dedicated Clock Inputs
(MHz)
-3
-4
-5
-3
-4
-5
-3
-4
-5
LVTTL
500
500
450
500
500
450
500
500
400
2.5-V LVTTL/CMOS
500
500
450
500
500
450
500
500
400
1.8-V LVTTL/CMOS
500
500
450
500
500
450
500
500
400
1.5-V LVTTL/CMOS
500
500
450
500
500
450
500
500
400
LVCMOS
500
500
450
500
500
450
500
500
400
SSTL-2 Class I
500
500
500
500
500
500
500
500
500
SSTL-2 Class II
500
500
500
500
500
500
500
500
500
SSTL-18 Class I
500
500
500
500
500
500
500
500
500
SSTL-18 Class II
500
500
500
500
500
500
500
500
500
1.5-V HSTL Class I
500
500
500
500
500
500
500
500
500
1.5-V HSTL Class II
500
500
500
500
500
500
500
500
500
1.8-V HSTL Class I
500
500
500
500
500
500
500
500
500
Altera Corporation
April 2011
5–67
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–77. Maximum Input Toggle Rate on Stratix II Devices (Part 2 of 2)
Column I/O Pins (MHz)
Row I/O Pins (MHz)
Input I/O Standard
Dedicated Clock Inputs
(MHz)
-3
-4
-5
-3
-4
-5
-3
-4
-5
1.8-V HSTL Class II
500
500
500
500
500
500
500
500
500
PCI (1)
500
500
450
-
-
-
500
500
400
PCI-X (1)
500
500
450
-
-
-
500
500
400
1.2-V HSTL (2)
280
-
-
-
-
-
280
-
-
Differential SSTL-2 Class I
(1), (3)
500
500
500
-
-
-
500
500
500
Differential SSTL-2 Class II
(1), (3)
500
500
500
-
-
-
500
500
500
Differential SSTL-18 Class I
(1), (3)
500
500
500
-
-
-
500
500
500
Differential SSTL-18 Class II
(1), (3)
500
500
500
-
-
-
500
500
500
1.8-V Differential HSTL
Class I (1), (3)
500
500
500
-
-
-
500
500
500
1.8-V Differential HSTL
Class II (1), (3)
500
500
500
-
-
-
500
500
500
1.5-V Differential HSTL
Class I (1), (3)
500
500
500
-
-
-
500
500
500
1.5-V Differential HSTL
Class II (1), (3)
500
500
500
-
-
-
500
500
500
-
-
-
520
520
420
717
717
640
HyperTransport technology
(4)
LVPECL (1)
-
-
-
-
-
-
450
450
400
LVDS (5)
-
-
-
520
520
420
717
717
640
LVDS (6)
-
-
-
-
-
-
450
450
400
Notes to Table 5–77:
(1)
(2)
(3)
(4)
(5)
(6)
Row clock inputs don’t support PCI, PCI-X, LVPECL, and differential HSTL and SSTL standards.
1.2-V HSTL is only supported on column I/O pins.
Differential HSTL and SSTL standards are only supported on column clock and DQS inputs.
HyperTransport technology is only supported on row I/O and row dedicated clock input pins.
These numbers apply to I/O pins and dedicated clock pins in the left and right I/O banks.
These numbers apply to dedicated clock pins in the top and bottom I/O banks.
5–68
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 1 of 5)
I/O Standard
3.3-V LVTTL
3.3-V LVCMOS
2.5-V
LVTTL/LVCMOS
1.8-V
LVTTL/LVCMOS
1.5-V
LVTTL/LVCMOS
SSTL-2 Class I
SSTL-2 Class II
Altera Corporation
April 2011
Drive
Strength
Column I/O Pins (MHz)
-3
-4
-5
Note (1)
Row I/O Pins (MHz)
-3
-4
-5
Clock Outputs (MHz)
-3
-4
-5
4 mA
270
225
210
270
225
210
270
225
210
8 mA
435
355
325
435
355
325
435
355
325
12 mA
580
475
420
580
475
420
580
475
420
16 mA
720
594
520
-
-
-
720
594
520
20 mA
875
700
610
-
-
-
875
700
610
24 mA
1,030
794
670
-
-
-
1,030
794
670
4 mA
290
250
230
290
250
230
290
250
230
8 mA
565
480
440
565
480
440
565
480
440
12 mA
790
710
670
-
-
-
790
710
670
16 mA
1,020
925
875
-
-
-
1,020
925
875
20 mA
1,066
985
935
-
-
-
1,066
985
24 mA
1,100
1,040
1,000
-
-
-
1,100 1,040
4 mA
230
194
180
230
194
180
230
194
180
8 mA
430
380
380
430
380
380
430
380
380
12 mA
630
575
550
630
575
550
630
575
550
16 mA
930
845
820
-
-
-
930
845
820
2 mA
120
109
104
120
109
104
120
109
104
4 mA
285
250
230
285
250
230
285
250
230
6 mA
450
390
360
450
390
360
450
390
360
8 mA
660
570
520
660
570
520
660
570
520
905
805
755
935
1,000
10 mA
905
805
755
-
-
-
12 mA
1,131
1,040
990
-
-
-
2 mA
244
200
180
244
200
180
244
200
180
4 mA
470
370
325
470
370
325
470
370
325
6 mA
550
430
375
-
-
-
550
430
375
8 mA
625
495
420
-
-
-
625
495
420
1,131 1,040
990
8 mA
400
300
300
-
-
-
400
300
300
12 mA
400
400
350
400
350
350
400
400
350
16 mA
350
350
300
350
350
300
350
350
300
20 mA
400
350
350
-
-
-
400
350
350
24 mA
400
400
350
-
-
-
400
400
350
5–69
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 2 of 5)
I/O Standard
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL
Class I
1.8-V HSTL
Class II
1.5-V HSTL
Class I
1.5-V HSTL
Class II
Differential
SSTL-2 Class I (3)
Differential
SSTL-2 Class II
(3)
Drive
Strength
Column I/O Pins (MHz)
-3
-4
-5
Note (1)
Row I/O Pins (MHz)
-3
-4
-5
Clock Outputs (MHz)
-3
-4
-5
4 mA
200
150
150
200
150
150
200
150
150
6 mA
350
250
200
350
250
200
350
250
200
8 mA
450
300
300
450
300
300
450
300
300
10 mA
500
400
400
500
400
400
500
400
400
12 mA
700
550
400
-
-
-
650
550
400
8 mA
200
200
150
-
-
-
200
200
150
16 mA
400
350
350
-
-
-
400
350
350
18 mA
450
400
400
-
-
-
450
400
400
20 mA
550
500
450
-
-
-
550
500
450
4 mA
300
300
300
300
300
300
300
300
300
6 mA
500
450
450
500
450
450
500
450
450
8 mA
650
600
600
650
600
600
650
600
600
10 mA
700
650
600
700
650
600
700
650
600
12 mA
700
700
650
700
700
650
700
700
650
16 mA
500
500
450
-
-
-
500
500
450
18 mA
550
500
500
-
-
-
550
500
500
20 mA
650
550
550
-
-
-
550
550
550
4 mA
350
300
300
350
300
300
350
300
300
6 mA
500
500
450
500
500
450
500
500
450
8 mA
700
650
600
700
650
600
700
650
600
10 mA
700
700
650
-
-
-
700
700
650
12 mA
700
700
700
-
-
-
700
700
700
16 mA
600
600
550
-
-
-
600
600
550
18 mA
650
600
600
-
-
-
650
600
600
20 mA
700
650
600
-
-
-
700
650
600
8 mA
400
300
300
400
300
300
400
300
300
12 mA
400
400
350
400
400
350
400
400
350
16 mA
350
350
300
350
350
300
350
350
300
20 mA
400
350
350
350
350
297
400
350
350
24 mA
400
400
350
-
-
-
400
400
350
5–70
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 3 of 5)
I/O Standard
Differential
SSTL-18 Class I
(3)
Differential
SSTL-18 Class II
(3)
1.8-V Differential
HSTL Class I (3)
1.8-V Differential
HSTL Class II (3)
1.5-V Differential
HSTL Class I (3)
1.5-V Differential
HSTL Class II (3)
Drive
Strength
Column I/O Pins (MHz)
Note (1)
Row I/O Pins (MHz)
Clock Outputs (MHz)
-3
-4
-5
-3
-4
-5
-3
-4
-5
4 mA
200
150
150
200
150
150
200
150
150
6 mA
350
250
200
350
250
200
350
250
200
8 mA
450
300
300
450
300
300
450
300
300
10 mA
500
400
400
500
400
400
500
400
400
12 mA
700
550
400
350
350
297
650
550
400
8 mA
200
200
150
-
-
-
200
200
150
16 mA
400
350
350
-
-
-
400
350
350
18 mA
450
400
400
-
-
-
450
400
400
20 mA
550
500
450
-
-
-
550
500
450
4 mA
300
300
300
-
-
-
300
300
300
6 mA
500
450
450
-
-
-
500
450
450
8 mA
650
600
600
-
-
-
650
600
600
10 mA
700
650
600
-
-
-
700
650
600
12 mA
700
700
650
-
-
-
700
700
650
16 mA
500
500
450
-
-
-
500
500
450
18 mA
550
500
500
-
-
-
550
500
500
20 mA
650
550
550
-
-
-
550
550
550
4 mA
350
300
300
-
-
-
350
300
300
6 mA
500
500
450
-
-
-
500
500
450
8 mA
700
650
600
-
-
-
700
650
600
10 mA
700
700
650
-
-
-
700
700
650
12 mA
700
700
700
-
-
-
700
700
700
16 mA
600
600
550
-
-
-
600
600
550
18 mA
650
600
600
-
-
-
650
600
600
700
650
600
-
-
-
700
650
600
3.3-V PCI
20 mA
1,000
790
670
-
-
-
1,000
790
670
3.3-V PCI-X
1,000
790
670
-
-
-
1,000
790
670
-
-
-
500
500
500
450
400
300
500
500
500
-
-
-
LVDS (6)
HyperTransport
technology (4), (6)
LVPECL (5)
-
-
-
-
-
-
450
400
300
3.3-V LVTTL
OCT 50 Ω
400
400
350
400
400
350
400
400
350
2.5-V LVTTL
OCT 50 Ω
350
350
300
350
350
300
350
350
300
Altera Corporation
April 2011
5–71
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 4 of 5)
I/O Standard
Drive
Strength
Column I/O Pins (MHz)
-3
-4
-5
Note (1)
Row I/O Pins (MHz)
-3
-4
-5
Clock Outputs (MHz)
-3
-4
-5
1.8-V LVTTL
OCT 50 Ω
700
550
450
700
550
450
700
550
450
3.3-V LVCMOS
OCT 50 Ω
350
350
300
350
350
300
350
350
300
1.5-V LVCMOS
OCT 50 Ω
550
450
400
550
450
400
550
450
400
SSTL-2 Class I
OCT 50 Ω
600
500
500
600
500
500
600
500
500
SSTL-2 Class II
OCT 25 Ω
600
550
500
600
550
500
600
550
500
SSTL-18 Class I
OCT 50 Ω
560
400
350
590
400
350
450
400
350
SSTL-18 Class II
OCT 25 Ω
550
500
450
-
-
-
550
500
450
1.2-V HSTL (2)
OCT 50 Ω
280
-
-
-
-
-
280
-
-
1.5-V HSTL
Class I
OCT 50 Ω
600
550
500
600
550
500
600
550
500
1.8-V HSTL
Class I
OCT 50 Ω
650
600
600
650
600
600
650
600
600
1.8-V HSTL
Class II
OCT 25 Ω
500
500
450
-
-
-
500
500
450
Differential
SSTL-2 Class I
OCT 50 Ω
600
500
500
600
500
500
600
500
500
Differential
SSTL-2 Class II
OCT 25 Ω
600
550
500
600
550
500
600
550
500
Differential
SSTL-18 Class I
OCT 50 Ω
560
400
350
590
400
350
560
400
350
Differential
SSTL-18 Class II
OCT 25 Ω
550
500
450
-
-
-
550
500
450
1.8-V Differential
HSTL Class I
OCT 50 Ω
650
600
600
650
600
600
650
600
600
1.8-V Differential
HSTL Class II
OCT 25 Ω
500
500
450
-
-
-
500
500
450
1.5-V Differential
HSTL Class I
OCT 50 Ω
600
550
500
600
550
500
600
550
500
5–72
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 5 of 5)
Drive
Strength
I/O Standard
OCT 50 Ω
1.2-V Differential
HSTL
Column I/O Pins (MHz)
Note (1)
Row I/O Pins (MHz)
Clock Outputs (MHz)
-3
-4
-5
-3
-4
-5
-3
-4
-5
280
-
-
-
-
-
280
-
-
Notes to Table 5–78:
(1)
(2)
(3)
(4)
(5)
(6)
The toggle rate applies to 0-pF output load for all I/O standards except for LVDS and HyperTransport technology
on row I/O pins. For LVDS and HyperTransport technology on row I/O pins, the toggle rates apply to load from
0 to 5pF.
1.2-V HSTL is only supported on column I/O pins in I/O banks 4, 7, and 8.
Differential HSTL and SSTL is only supported on column clock and DQS outputs.
HyperTransport technology is only supported on row I/O and row dedicated clock input pins.
LVPECL is only supported on column clock pins.
Refer to Tables 5–81 through 5–91 if using SERDES block. Use the toggle rate values from the clock output column
for PLL output.
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 1 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
I/O Standard
3.3-V LVTTL
3.3-V LVCMOS
2.5-V
LVTTL/LVCMOS
Altera Corporation
April 2011
Drive
Strength
Column I/O Pins
Row I/O Pins
Dedicated Clock Outputs
-3
-4
-5
-3
-4
-5
-3
-4
-5
4 mA
478
510
510
478
510
510
466
510
510
8 mA
260
333
333
260
333
333
291
333
333
12 mA
213
247
247
213
247
247
211
247
247
16 mA
136
197
197
-
-
-
166
197
197
20 mA
138
187
187
-
-
-
154
187
187
24 mA
134
177
177
-
-
-
143
177
177
4 mA
377
391
391
377
391
391
377
391
391
8 mA
206
212
212
206
212
212
178
212
212
12 mA
141
145
145
-
-
-
115
145
145
16 mA
108
111
111
-
-
-
86
111
111
20 mA
83
88
88
-
-
-
79
88
88
24 mA
65
72
72
-
-
-
74
72
72
4 mA
387
427
427
387
427
427
391
427
427
8 mA
163
224
224
163
224
224
170
224
224
12 mA
142
203
203
142
203
203
152
203
203
16 mA
120
182
182
-
-
-
134
182
182
5–73
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 2 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
I/O Standard
1.8-V
LVTTL/LVCMOS
1.5-V
LVTTL/LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-2 Class I
SSTL-2 Class II
Drive
Strength
Column I/O Pins
Row I/O Pins
Dedicated Clock Outputs
-3
-4
-5
-3
-4
-5
-3
-4
-5
2 mA
951
1421
1421
951
1421
1421
904
1421
1421
4 mA
405
516
516
405
516
516
393
516
516
6 mA
261
325
325
261
325
325
253
325
325
8 mA
223
274
274
223
274
274
224
274
274
10 mA
194
236
236
-
-
-
199
236
236
12 mA
174
209
209
-
-
-
180
209
209
2 mA
652
963
963
652
963
963
618
963
963
4 mA
333
347
347
333
347
347
270
347
347
6 mA
182
247
247
-
-
-
198
247
247
8 mA
135
194
194
-
-
-
155
194
194
8 mA
364
680
680
364
680
680
350
680
680
12 mA
163
207
207
163
207
207
188
207
207
16 mA
118
147
147
118
147
147
94
147
147
20 mA
99
122
122
-
-
-
87
122
122
24 mA
91
116
116
-
-
-
85
116
116
4 mA
458
570
570
458
570
570
505
570
570
6 mA
305
380
380
305
380
380
336
380
380
8 mA
225
282
282
225
282
282
248
282
282
10 mA
167
220
220
167
220
220
190
220
220
12 mA
129
175
175
-
-
-
148
175
175
8 mA
173
206
206
-
-
-
155
206
206
16 mA
150
160
160
-
-
-
140
160
160
18 mA
120
130
130
-
-
-
110
130
130
20 mA
109
127
127
-
-
-
94
127
127
8 mA
364
680
680
364
680
680
350
680
680
12 mA
163
207
207
163
207
207
188
207
207
16 mA
118
147
147
118
147
147
94
147
147
20 mA
99
122
122
-
-
-
87
122
122
24 mA
91
116
116
-
-
-
85
116
116
5–74
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 3 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
I/O Standard
Drive
Strength
-3
-4
-5
-3
-4
-5
-3
-4
-5
SSTL-18 Class I
4 mA
458
570
570
458
570
570
505
570
570
6 mA
305
380
380
305
380
380
336
380
380
8 mA
225
282
282
225
282
282
248
282
282
10 mA
167
220
220
167
220
220
190
220
220
12 mA
129
175
175
-
-
-
148
175
175
SSTL-18 Class II
1.8-V HSTL
Class I
1.8-V HSTL
Class II
1.5-V HSTL
Class I
1.5-V HSTL
Class II
Differential
SSTL-2 Class II
(3)
Altera Corporation
April 2011
Column I/O Pins
Row I/O Pins
Dedicated Clock Outputs
8 mA
173
206
206
-
-
-
155
206
206
16 mA
150
160
160
-
-
-
140
160
160
18 mA
120
130
130
-
-
-
110
130
130
20 mA
109
127
127
-
-
-
94
127
127
4 mA
245
282
282
245
282
282
229
282
282
6 mA
164
188
188
164
188
188
153
188
188
8 mA
123
140
140
123
140
140
114
140
140
10 mA
110
124
124
110
124
124
108
124
124
12 mA
97
110
110
97
110
110
104
110
110
16 mA
101
104
104
-
-
-
99
104
104
18 mA
98
102
102
-
-
-
93
102
102
20 mA
93
99
99
-
-
-
88
99
99
4 mA
168
196
196
168
196
196
188
196
196
6 mA
112
131
131
112
131
131
125
131
131
8 mA
84
99
99
84
99
99
95
99
99
10 mA
87
98
98
-
-
-
90
98
98
12 mA
86
98
98
-
-
-
87
98
98
16 mA
95
101
101
-
-
-
96
101
101
18 mA
95
100
100
-
-
-
101
100
100
20 mA
94
101
101
-
-
-
104
101
101
8 mA
364
680
680
-
-
-
350
680
680
12 mA
163
207
207
-
-
-
188
207
207
16 mA
118
147
147
-
-
-
94
147
147
20 mA
99
122
122
-
-
-
87
122
122
24 mA
91
116
116
-
-
-
85
116
116
5–75
Stratix II Device Handbook, Volume 1
Timing Model
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 4 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
I/O Standard
Differential
SSTL-18 Class I
(3)
Differential
SSTL-18 Class II
(3)
1.8-V Differential
HSTL Class I (3)
1.8-V Differential
HSTL Class II (3)
1.5-V Differential
HSTL Class I (3)
1.5-V Differential
HSTL Class II (3)
Drive
Strength
Column I/O Pins
Row I/O Pins
Dedicated Clock Outputs
-3
-4
-5
-3
-4
-5
-3
-4
-5
4 mA
458
570
570
-
-
-
505
570
570
6 mA
305
380
380
-
-
-
336
380
380
8 mA
225
282
282
-
-
-
248
282
282
10 mA
167
220
220
-
-
-
190
220
220
12 mA
129
175
175
-
-
-
148
175
175
8 mA
173
206
206
-
-
-
155
206
206
16 mA
150
160
160
-
-
-
140
160
160
18 mA
120
130
130
-
-
-
110
130
130
20 mA
109
127
127
-
-
-
94
127
127
4 mA
245
282
282
-
-
-
229
282
282
6 mA
164
188
188
-
-
-
153
188
188
8 mA
123
140
140
-
-
-
114
140
140
10 mA
110
124
124
-
-
-
108
124
124
12 mA
97
110
110
-
-
-
104
110
110
16 mA
101
104
104
-
-
-
99
104
104
18 mA
98
102
102
-
-
-
93
102
102
20 mA
93
99
99
-
-
-
88
99
99
4 mA
168
196
196
-
-
-
188
196
196
6 mA
112
131
131
-
-
-
125
131
131
8 mA
84
99
99
-
-
-
95
99
99
10 mA
87
98
98
-
-
-
90
98
98
12 mA
86
98
98
-
-
-
87
98
98
16 mA
95
101
101
-
-
-
96
101
101
18 mA
95
100
100
-
-
-
101
100
100
20 mA
94
101
101
-
-
-
104
101
101
3.3-V PCI
134
177
177
-
-
-
143
177
177
3.3-V PCI-X
134
177
177
-
-
-
143
177
177
LVDS
-
-
-
155 (1)
155
(1)
155
(1)
134
134
134
HyperTransport
technology
-
-
-
155 (1)
155
(1)
155
(1)
-
-
-
LVPECL (4)
-
-
-
-
-
-
134
134
134
5–76
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–79. Maximum Output Clock Toggle Rate Derating Factors (Part 5 of 5)
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
I/O Standard
Drive
Strength
Column I/O Pins
Row I/O Pins
Dedicated Clock Outputs
-3
-4
-5
-3
-4
-5
-3
-4
-5
3.3-V LVTTL
OCT
50 Ω
133
152
152
133
152
152
147
152
152
2.5-V LVTTL
OCT
50 Ω
207
274
274
207
274
274
235
274
274
1.8-V LVTTL
OCT
50 Ω
151
165
165
151
165
165
153
165
165
3.3-V LVCMOS
OCT
50 Ω
300
316
316
300
316
316
263
316
316
1.5-V LVCMOS
OCT
50 Ω
157
171
171
157
171
171
174
171
171
SSTL-2 Class I
OCT
50 Ω
121
134
134
121
134
134
77
134
134
SSTL-2 Class II
OCT
25 Ω
56
101
101
56
101
101
58
101
101
SSTL-18 Class I
OCT
50 Ω
100
123
123
100
123
123
106
123
123
SSTL-18 Class II
OCT
25 Ω
61
110
110
-
-
-
59
110
110
1.2-V HSTL (2)
OCT
50 Ω
95
-
-
-
-
-
-
-
95
Notes to Table 5–79:
(1)
(2)
(3)
(4)
For LVDS and HyperTransport technology output on row I/O pins, the toggle rate derating factors apply to loads
larger than 5 pF. In the derating calculation, subtract 5 pF from the intended load value in pF for the correct result.
For a load less than or equal to 5 pF, refer to Table 5–78 for output toggle rates.
1.2-V HSTL is only supported on column I/O pins in I/O banks 4,7, and 8.
Differential HSTL and SSTL is only supported on column clock and DQS outputs.
LVPECL is only supported on column clock outputs.
Duty Cycle
Distortion
Altera Corporation
April 2011
Duty cycle distortion (DCD) describes how much the falling edge of a
clock is off from its ideal position. The ideal position is when both the
clock high time (CLKH) and the clock low time (CLKL) equal half of the
clock period (T), as shown in Figure 5–7. DCD is the deviation of the
non-ideal falling edge from the ideal falling edge, such as D1 for the
falling edge A and D2 for the falling edge B (Figure 5–7). The maximum
DCD for a clock is the larger value of D1 and D2.
5–77
Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Figure 5–7. Duty Cycle Distortion
Ideal Falling Edge
CLKH = T/2
CLKL = T/2
D1
D2
Falling Edge B
Falling Edge A
Clock Period (T)
DCD expressed in absolution derivation, for example, D1 or D2 in
Figure 5–7, is clock-period independent. DCD can also be expressed as a
percentage, and the percentage number is clock-period dependent. DCD
as a percentage is defined as
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the
corresponding I/O element (IOE) block. When the output is a single data
rate signal (non-DDIO), only one edge of the register input clock (positive
or negative) triggers output transitions (Figure 5–8). Therefore, any DCD
present on the input clock signal or caused by the clock input buffer or
different input I/O standard does not transfer to the output signal.
Figure 5–8. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
IOE
NOT
inst1
clk
INPUT
VCC
DFF
PRN
D
Q
OUTPUT
output
CLRN
inst
5–78
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
However, when the output is a double data rate input/output (DDIO)
signal, both edges of the input clock signal (positive and negative) trigger
output transitions (Figure 5–9). Therefore, any distortion on the input
clock and the input clock buffer affect the output DCD.
Figure 5–9. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
IOE
VCC
clk
DFF
PRN
D
INPUT
VCC
Q
CLRN
inst2
OUTPUT
output
DFF
PRN
GND
D
Q
NOT
inst8
CLRN
inst3
When an FPGA PLL generates the internal clock, the PLL output clocks
the IOE block. As the PLL only monitors the positive edge of the reference
clock input and internally re-creates the output clock signal, any DCD
present on the reference clock is filtered out. Therefore, the DCD for a
DDIO output with PLL in the clock path is better than the DCD for a
DDIO output without PLL in the clock path.
Tables 5–80 through 5–87 give the maximum DCD in absolution
derivation for different I/O standards on Stratix II devices. Examples are
also provided that show how to calculate DCD as a percentage.
Table 5–80. Maximum DCD for Non-DDIO Output on Row I/O Pins (Part 1
of 2)
Note (1)
Row I/O Output
Standard
Altera Corporation
April 2011
Maximum DCD for Non-DDIO Output
-3 Devices
-4 & -5 Devices
Unit
3.3-V LVTTTL
245
275
ps
3.3-V LVCMOS
125
155
ps
2.5 V
105
135
ps
5–79
Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Table 5–80. Maximum DCD for Non-DDIO Output on Row I/O Pins (Part 2
of 2)
Note (1)
Row I/O Output
Standard
Maximum DCD for Non-DDIO Output
-3 Devices
-4 & -5 Devices
Unit
1.8 V
180
180
ps
1.5-V LVCMOS
165
195
ps
SSTL-2 Class I
115
145
ps
SSTL-2 Class II
95
125
ps
SSTL-18 Class I
55
85
ps
1.8-V HSTL Class I
80
100
ps
1.5-V HSTL Class I
85
115
ps
LVDS/
HyperTransport
technology
55
80
ps
Note to Table 5–80:
(1)
The DCD specification is based on a no logic array noise condition.
Here is an example for calculating the DCD as a percentage for a
non-DDIO output on a row I/O on a -3 device:
If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum
DCD is 95 ps (see Table 5–80). If the clock frequency is 267 MHz, the clock
period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3745 ps
To calculate the DCD as a percentage:
(T/2 – DCD) / T = (3745ps/2 – 95ps) / 3745ps = 47.5% (for low
boundary)
(T/2 + DCD) / T = (3745ps/2 + 95ps) / 3745ps = 52.5% (for high
boundary)
5–80
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II
non-DDIO row output clock on a –3 device ranges from 47.5% to 52.5%.
Table 5–81. Maximum DCD for Non-DDIO Output on Column I/O
Pins
Note (1)
Column I/O Output
Standard I/O
Standard
Maximum DCD for Non-DDIO Output
Unit
-3 Devices
-4 & -5 Devices
3.3-V LVTTL
190
220
ps
3.3-V LVCMOS
140
175
ps
2.5 V
125
155
ps
1.8 V
80
110
ps
1.5-V LVCMOS
185
215
ps
SSTL-2 Class I
105
135
ps
SSTL-2 Class II
100
130
ps
SSTL-18 Class I
90
115
ps
SSTL-18 Class II
70
100
ps
1.8-V HSTL
Class I
80
110
ps
1.8-V HSTL
Class II
80
110
ps
1.5-V HSTL
Class I
85
115
ps
1.5-V HSTL
Class II
50
80
ps
1.2-V HSTL (2)
170
-
ps
LVPECL
55
80
ps
Notes to Table 5–81:
(1)
(2)
Altera Corporation
April 2011
The DCD specification is based on a no logic array noise condition.
1.2-V HSTL is only supported in -3 devices.
5–81
Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Table 5–82. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3
Devices
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock Port
(No PLL in Clock Path)
Row DDIO Output I/O
Standard
3.3-V LVTTL
TTL/CMOS
SSTL-2
SSTL/HSTL
LVDS/
HyperTransport
Technology
Unit
3.3 & 2.5 V
1.8 & 1.5 V
2.5 V
1.8 & 1.5 V
3.3 V
260
380
145
145
110
ps
3.3-V LVCMOS
210
330
100
100
65
ps
2.5 V
195
315
85
85
75
ps
1.8 V
150
265
85
85
120
ps
1.5-V LVCMOS
255
370
140
140
105
ps
SSTL-2 Class I
175
295
65
65
70
ps
SSTL-2 Class II
170
290
60
60
75
ps
SSTL-18 Class I
155
275
55
50
90
ps
1.8-V HSTL Class I
150
270
60
60
95
ps
1.5-V HSTL Class I
150
270
55
55
90
ps
LVDS/ HyperTransport
technology
180
180
180
180
180
ps
Notes to Table 5–82:
(1)
(2)
The information in Table 5–82 assumes the input clock has zero DCD.
The DCD specification is based on a no logic array noise condition.
Here is an example for calculating the DCD in percentage for a DDIO
output on a row I/O on a -3 device:
If the input I/O standard is SSTL-2 and the DDIO output I/O standard is
SSTL-2 Class II, the maximum DCD is 60 ps (see Table 5–82). If the clock
frequency is 267 MHz, the clock period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3745 ps
Calculate the DCD as a percentage:
(T/2 – DCD) / T = (3745ps/2 – 60ps) / 3745ps = 48.4% (for low
boundary)
(T/2 + DCD) / T = (3745 ps/2 + 60 ps) / 3745ps = 51.6% (for high
boundary)
5–82
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Therefore, the DCD percentage for the 267 MHz SSTL-2 Class II DDIO
row output clock on a –3 device ranges from 48.4% to 51.6%.
Table 5–83. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 & -5
Devices
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock
Port (No PLL in the Clock Path)
Row DDIO Output I/O
Standard
3.3-V LVTTL
TTL/CMOS
SSTL-2
SSTL/HSTL
LVDS/
HyperTransport
Technology
Unit
3.3/2.5 V
1.8/1.5 V
2.5 V
1.8/1.5 V
3.3 V
440
495
170
160
105
ps
3.3-V LVCMOS
390
450
120
110
75
ps
2.5 V
375
430
105
95
90
ps
1.8 V
325
385
90
100
135
ps
1.5-V LVCMOS
430
490
160
155
100
ps
SSTL-2 Class I
355
410
85
75
85
ps
SSTL-2 Class II
350
405
80
70
90
ps
SSTL-18 Class I
335
390
65
65
105
ps
1.8-V HSTL Class I
330
385
60
70
110
ps
1.5-V HSTL Class I
330
390
60
70
105
ps
LVDS/ HyperTransport
technology
180
180
180
180
180
ps
Notes to Table 5–83:
(1)
(2)
Table 5–83 assumes the input clock has zero DCD.
The DCD specification is based on a no logic array noise condition.
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 1 of 2)
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
DDIO Column Output I/O
Standard
3.3-V LVTTL
TTL/CMOS
SSTL-2
SSTL/HSTL
1.2-V
HSTL
Unit
3.3/2.5 V
1.8/1.5 V
2.5 V
1.8/1.5 V
1.2 V
260
380
145
145
145
ps
3.3-V LVCMOS
210
330
100
100
100
ps
2.5 V
195
315
85
85
85
ps
Altera Corporation
April 2011
5–83
Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 2 of 2)
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
DDIO Column Output I/O
Standard
TTL/CMOS
SSTL-2
SSTL/HSTL
1.2-V
HSTL
2.5 V
1.8/1.5 V
1.2 V
Unit
3.3/2.5 V
1.8/1.5 V
1.8 V
150
265
85
85
85
ps
1.5-V LVCMOS
255
370
140
140
140
ps
SSTL-2 Class I
175
295
65
65
65
ps
SSTL-2 Class II
170
290
60
60
60
ps
SSTL-18 Class I
155
275
55
50
50
ps
SSTL-18 Class II
140
260
70
70
70
ps
1.8-V HSTL Class I
150
270
60
60
60
ps
1.8-V HSTL Class II
150
270
60
60
60
ps
1.5-V HSTL Class I
150
270
55
55
55
ps
1.5-V HSTL Class II
125
240
85
85
85
ps
1.2-V HSTL
240
360
155
155
155
ps
LVPECL
180
180
180
180
180
ps
Notes to Table 5–84:
(1)
(2)
Table 5–84 assumes the input clock has zero DCD.
The DCD specification is based on a no logic array noise condition.
Table 5–85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5
Devices (Part 1 of 2)
Notes (1), (2)
DDIO Column Output I/O
Standard
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
TTL/CMOS
SSTL-2
SSTL/HSTL
Unit
3.3/2.5 V
1.8/1.5 V
2.5 V
1.8/1.5 V
440
495
170
160
ps
3.3-V LVCMOS
390
450
120
110
ps
2.5 V
375
430
105
95
ps
1.8 V
325
385
90
100
ps
1.5-V LVCMOS
430
490
160
155
ps
SSTL-2 Class I
355
410
85
75
ps
SSTL-2 Class II
350
405
80
70
ps
3.3-V LVTTL
5–84
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5
Devices (Part 2 of 2)
Notes (1), (2)
DDIO Column Output I/O
Standard
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
TTL/CMOS
3.3/2.5 V
1.8/1.5 V
SSTL-2
SSTL/HSTL
2.5 V
1.8/1.5 V
Unit
SSTL-18 Class I
335
390
65
65
ps
SSTL-18 Class II
320
375
70
80
ps
1.8-V HSTL Class I
330
385
60
70
ps
1.8-V HSTL Class II
330
385
60
70
ps
1.5-V HSTL Class I
330
390
60
70
ps
1.5-V HSTL Class II
330
360
90
100
ps
1.2-V HSTL
420
470
155
165
ps
LVPECL
180
180
180
180
ps
Notes to Table 5–85:
(1)
(2)
Table 5–85 assumes the input clock has zero DCD.
The DCD specification is based on a no logic array noise condition.
Table 5–86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the
Clock Path (Part 1 of 2)
Note (1)
Row DDIO Output I/O
Standard
3.3-V LVTTL
Altera Corporation
April 2011
Maximum DCD (PLL Output Clock Feeding
DDIO Clock Port)
-3 Device
-4 & -5 Device
110
105
Unit
ps
3.3-V LVCMOS
65
75
ps
2.5V
75
90
ps
1.8V
85
100
ps
1.5-V LVCMOS
105
100
ps
SSTL-2 Class I
65
75
ps
SSTL-2 Class II
60
70
ps
SSTL-18 Class I
50
65
ps
1.8-V HSTL Class I
50
70
ps
1.5-V HSTL Class I
55
70
ps
5–85
Stratix II Device Handbook, Volume 1
Duty Cycle Distortion
Table 5–86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the
Clock Path (Part 2 of 2)
Note (1)
Row DDIO Output I/O
Standard
LVDS/ HyperTransport
technology
Maximum DCD (PLL Output Clock Feeding
DDIO Clock Port)
-3 Device
-4 & -5 Device
180
180
Unit
ps
Note to Table 5–86:
(1)
The DCD specification is based on a no logic array noise condition.
Table 5–87. Maximum DCD for DDIO Output on Column I/O with PLL in the
Clock Path
Note (1)
Column DDIO Output I/O
Standard
Maximum DCD (PLL Output Clock Feeding
DDIO Clock Port)
Unit
-3 Device
-4 & -5 Device
3.3-V LVTTL
145
160
ps
3.3-V LVCMOS
100
110
ps
2.5V
85
95
ps
1.8V
85
100
ps
1.5-V LVCMOS
140
155
ps
SSTL-2 Class I
65
75
ps
SSTL-2 Class II
60
70
ps
SSTL-18 Class I
50
65
ps
SSTL-18 Class II
70
80
ps
1.8-V HSTL Class I
60
70
ps
1.8-V HSTL Class II
60
70
ps
1.5-V HSTL Class I
55
70
ps
1.5-V HSTL Class II
85
100
ps
1.2-V HSTL
155
-
ps
LVPECL
180
180
ps
Notes to Table 5–87:
(1)
(2)
The DCD specification is based on a no logic array noise condition.
1.2-V HSTL is only supported in -3 devices.
5–86
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
High-Speed I/O
Specifications
Table 5–88 provides high-speed timing specifications definitions.
Table 5–88. High-Speed Timing Specifications & Definitions
High-Speed Timing Specifications
Definitions
tC
High-speed receiver/transmitter input and output clock period.
fH S C L K
High-speed receiver/transmitter input and output clock frequency.
J
Deserialization factor (width of parallel data bus).
W
PLL multiplication factor.
tR I S E
Low-to-high transmission time.
tF A L L
High-to-low transmission time.
Timing unit interval (TUI)
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency ×
Multiplication Factor) = tC /w).
fH S D R
Maximum/minimum LVDS data transfer rate (fH S D R = 1/TUI), non-DPA.
fH S D R D P A
Maximum/minimum LVDS data transfer rate (fH S D R D PA = 1/TUI), DPA.
Channel-to-channel skew (TCCS)
The timing difference between the fastest and slowest output edges,
including tC O variation and clock skew. The clock is included in the TCCS
measurement.
Sampling window (SW)
The period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
Input jitter
Peak-to-peak input jitter on high-speed PLLs.
Output jitter
Peak-to-peak output jitter on high-speed PLLs.
tDUTY
Duty cycle on high-speed transmitter output clock.
tL O C K
Lock time for high-speed transmitter and receiver PLLs.
Table 5–89 shows the high-speed I/O timing specifications for -3 speed
grade Stratix II devices.
Table 5–89. High-Speed I/O Specifications for -3 Speed Grade (Part 1 of 2)
Notes (1), (2)
-3 Speed Grade
Symbol
Conditions
Unit
Min
fH S C L K (clock frequency)
fH S C L K = f H S D R / W
Altera Corporation
April 2011
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
Typ
Max
16
520
MHz
W = 1 (SERDES bypass, LVDS only)
16
500
MHz
W = 1 (SERDES used, LVDS only)
150
717
MHz
5–87
Stratix II Device Handbook, Volume 1
High-Speed I/O Specifications
Table 5–89. High-Speed I/O Specifications for -3 Speed Grade (Part 2 of 2)
Notes (1), (2)
-3 Speed Grade
Symbol
Conditions
Unit
Min
fH S D R (data rate)
Typ
Max
J = 4 to 10 (LVDS, HyperTransport technology)
150
1,040
Mbps
J = 2 (LVDS, HyperTransport technology)
(4)
760
Mbps
J = 1 (LVDS only)
fH S D R D PA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
(4)
500
Mbps
150
1,040
Mbps
200
ps
TCCS
All differential standards
-
SW
All differential standards
330
Output jitter
-
ps
190
ps
Output tR I S E
All differential I/O standards
160
ps
Output tFA L L
All differential I/O standards
180
ps
55
%
6,400
UI
tDUTY
45
DPA run length
DPA jitter tolerance
DPA lock time
Data channel peak-to-peak jitter
Standard
SPI-4
Parallel Rapid I/O
Miscellaneous
0.44
Training
Pattern
Transition
Density
0000000000
1111111111
10%
256
00001111
25%
256
10010000
50%
256
10101010
100%
256
01010101
50
UI
Number of
repetitions
256
Notes to Table 5–89:
(1)
(2)
(3)
(4)
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
5–88
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–90 shows the high-speed I/O timing specifications for -4 speed
grade Stratix II devices.
Table 5–90. High-Speed I/O Specifications for -4 Speed Grade
Notes (1), (2)
-4 Speed Grade
Symbol
Conditions
Unit
Min
fH S C L K (clock frequency)
fH S C L K = f H S D R / W
fH S D R (data rate)
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
Typ
Max
16
520
MHz
W = 1 (SERDES bypass, LVDS only)
16
500
MHz
W = 1 (SERDES used, LVDS only)
150
717
MHz
J = 4 to 10 (LVDS, HyperTransport technology)
150
1,040
Mbps
J = 2 (LVDS, HyperTransport technology)
(4)
760
Mbps
J = 1 (LVDS only)
fH S D R D PA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
(4)
500
Mbps
150
1,040
Mbps
200
ps
TCCS
All differential standards
-
SW
All differential standards
330
Output jitter
-
ps
190
ps
Output tR I S E
All differential I/O standards
160
ps
Output tFA L L
All differential I/O standards
180
ps
55
%
6,400
UI
tDUTY
45
DPA run length
DPA jitter tolerance
DPA lock time
Data channel peak-to-peak jitter
0.44
Standard
Training
Pattern
Transition
Density
SPI-4
0000000000
1111111111
10%
256
Parallel Rapid I/O
00001111
25%
256
10010000
50%
256
10101010
100%
256
Miscellaneous
01010101
50
UI
Number of
repetitions
256
Notes to Table 5–90:
(1)
(2)
(3)
(4)
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
Altera Corporation
April 2011
5–89
Stratix II Device Handbook, Volume 1
High-Speed I/O Specifications
Table 5–91 shows the high-speed I/O timing specifications for -5 speed
grade Stratix II devices.
Table 5–91. High-Speed I/O Specifications for -5 Speed Grade
Notes (1), (2)
-5 Speed Grade
Symbol
Conditions
Unit
Min
fH S C L K (clock frequency)
fH S C L K = f H S D R / W
fH S D R (data rate)
W = 2 to 32 (LVDS, HyperTransport technology)
(3)
Typ
Max
16
420
MHz
W = 1 (SERDES bypass, LVDS only)
16
500
MHz
W = 1 (SERDES used, LVDS only)
150
640
MHz
J = 4 to 10 (LVDS, HyperTransport technology)
150
840
Mbps
J = 2 (LVDS, HyperTransport technology)
(4)
700
Mbps
J = 1 (LVDS only)
fH S D R D PA (DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
(4)
500
Mbps
150
840
Mbps
200
ps
TCCS
All differential I/O standards
-
SW
All differential I/O standards
440
Output jitter
-
ps
190
ps
Output tR I S E
All differential I/O standards
290
ps
Output tFA L L
All differential I/O standards
290
ps
55
%
6,400
UI
tDUTY
45
DPA run length
DPA jitter tolerance
DPA lock time
Data channel peak-to-peak jitter
Standard
SPI-4
Parallel Rapid I/O
Miscellaneous
0.44
Training
Pattern
Transition
Density
0000000000
1111111111
10%
256
00001111
25%
256
10010000
50%
256
10101010
100%
256
01010101
50
UI
Number of
repetitions
256
Notes to Table 5–91:
(1)
(2)
(3)
(4)
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150 ≤ input clock
frequency × W ≤ 1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and
the clock routing resource (global, regional, or local) utilized. The I/O differential buffer and input register do not
have a minimum toggle rate.
5–90
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
PLL Timing
Specifications
Tables 5–92 and 5–93 describe the Stratix II PLL specifications when
operating in both the commercial junction temperature range (0 to 85 °C)
and the industrial junction temperature range (–40 to 100 °C).
Table 5–92. Enhanced PLL Specifications (Part 1 of 2)
Name
Description
Min
fI N
Input clock frequency
fI N P F D
Input frequency to the
PFD
fI N D U T Y
Input clock duty cycle
40
60
%
fE I N D U T Y
External feedback
input clock duty cycle
40
60
%
tI N J I T T E R
Input or external
feedback clock input
jitter tolerance in
terms of period jitter.
Bandwidth ≤
0.85 MHz
0.5
ns (p-p)
Input or external
feedback clock input
jitter tolerance in
terms of period jitter.
Bandwidth >
0.85 MHz
1.0
ns (p-p)
Max
Unit
2
500
MHz
2
420
MHz
250 ps for ≥ 100 MHz outclk ps or mUI
(p-p)
25 mUI for < 100 MHz outclk
tO U T J I T T E R
Dedicated clock
output period jitter
tF C O M P
External feedback
compensation time
fO U T
Output frequency for
internal global or
regional clock
1.5
(2)
tO U T D U T Y
Duty cycle for external
clock output (when set
to 50%).
45
fS C A N C L K
Scanclk frequency
tC O N F I G P L L
Time required to
reconfigure scan
chains for enhanced
PLLs
fO U T _ E X T
PLL external clock
output frequency
Altera Corporation
April 2011
Typ
50
10
ns
550.0
MHz
55
%
100
MHz
174/fS C A N C L K
1.5
(2)
ns
550.0 (1)
MHz
5–91
Stratix II Device Handbook, Volume 1
PLL Timing Specifications
Table 5–92. Enhanced PLL Specifications (Part 2 of 2)
Name
Description
Min
Typ
Max
Unit
0.03
1
ms
1
ms
500
MHz
16.90
MHz
tL O C K
Time required for the
PLL to lock from the
time it is enabled or
the end of device
configuration
tD L O C K
Time required for the
PLL to lock
dynamically after
automatic clock
switchover between
two identical clock
frequencies
fS W I T C H OV E R
Frequency range
where the clock
switchover performs
properly
fC L B W
PLL closed-loop
bandwidth
0.13
fV C O
PLL VCO operating
range for –3 and –4
speed grade devices
300
1,040
MHz
PLL VCO operating
range for –5 speed
grade devices
300
840
MHz
fS S
Spread-spectrum
modulation frequency
30
150
kHz
% spread
Percent down spread
for a given clock
frequency
0.4
0.6
%
tP L L _ P S E R R
Accuracy of PLL
phase shift
±15
ps
tA R E S E T
Minimum pulse width
on areset signal.
10
ns
tA R E S E T _ R E C O N F I G
Minimum pulse width
on the areset signal
when using PLL
reconfiguration. Reset
the PLL after
scandone goes
high.
500
ns
4
1.20
0.5
Notes to Table 5–92:
(1)
(2)
Limited by I/O fM A X . See Table 5–78 on page 5–69 for the maximum. Cannot exceed fO U T specification.
If the counter cascading feature of the PLL is utilized, there is no minimum output clock frequency.
5–92
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–93. Fast PLL Specifications
Name
fI N
Description
Min
Typ
Max
Unit
Input clock frequency (for -3 and -4 speed
grade devices)
16.08
717
MHz
Input clock frequency (for -5 speed grade
devices)
16.08
640
MHz
fI N P F D
Input frequency to the PFD
16.08
500
MHz
fI N D U T Y
Input clock duty cycle
40
60
%
tI N J I T T E R
Input clock jitter tolerance in terms of period
jitter. Bandwidth ≤ 2 MHz
0.5
ns (p-p)
Input clock jitter tolerance in terms of period
jitter. Bandwidth > 2 MHz
1.0
ns (p-p)
fV C O
fO U T
Upper VCO frequency range for –3 and –4
speed grades
300
1,040
MHz
Upper VCO frequency range for –5 speed
grades
300
840
MHz
Lower VCO frequency range for –3 and –4
speed grades
150
520
MHz
Lower VCO frequency range for –5 speed
grades
150
420
MHz
4.6875
550
MHz
150
1,040
MHz
4.6875
(1)
MHz
100
MHz
PLL output frequency to GCLK or RCLK
PLL output frequency to LVDS or DPA clock
fO U T _ I O
PLL clock output frequency to regular I/O
pin
fS C A N C L K
Scanclk frequency
tC O N F I G P L L
Time required to reconfigure scan chains
for fast PLLs
fC L B W
PLL closed-loop bandwidth
tL O C K
Time required for the PLL to lock from the
time it is enabled or the end of the device
configuration
tP L L _ P S E R R
Accuracy of PLL phase shift
tA R E S E T
75/fS C A N C L K
1.16
5.00
28.00
MHz
0.03
1.00
ms
±15
ps
10
ns
500
ns
Minimum pulse width on areset signal.
tA R E S E T _ R E C O N F I G Minimum pulse width on the areset signal
when using PLL reconfiguration. Reset the
PLL after scandone goes high.
ns
Note to Table 5–93:
(1)
Limited by I/O fM A X . See Table 5–77 on page 5–67 for the maximum.
Altera Corporation
April 2011
5–93
Stratix II Device Handbook, Volume 1
External Memory Interface Specifications
External
Memory
Interface
Specifications
Tables 5–94 through 5–101 contain Stratix II device specifications for the
dedicated circuitry used for interfacing with external memory devices.
Table 5–94. DLL Frequency Range Specifications
Frequency Mode
Frequency Range
Resolution
(Degrees)
0
100 to 175
30
1
150 to 230
22.5
2
200 to 310
30
240 to 400 (–3 speed grade)
36
240 to 350 (–4 and –5 speed grades)
36
3
Table 5–95 lists the maximum delay in the fast timing model for the
Stratix II DQS delay buffer. Multiply the number of delay buffers that you
are using in the DQS logic block to get the maximum delay achievable in
your system. For example, if you implement a 90° phase shift at 200 MHz,
you use three delay buffers in mode 2. The maximum achievable delay
from the DQS block is then 3 × .416 ps = 1.248 ns.
Table 5–95. DQS Delay Buffer Maximum Delay in Fast Timing Model
Frequency Mode
Maximum Delay Per Delay Buffer
(Fast Timing Model)
Unit
0
0.833
ns
1, 2, 3
0.416
ns
Table 5–96. DQS Period Jitter Specifications for DLL-Delayed Clock
(tDQS_JITTER)
Note (1)
Number of DQS Delay Buffer
Stages (2)
Commercial
Industrial
Unit
1
80
110
ps
2
110
130
ps
3
130
180
ps
4
160
210
ps
Notes to Table 5–96:
(1)
(2)
Peak-to-peak period jitter on the phase shifted DQS clock.
Delay stages used for requested DQS phase shift are reported in your project’s
Compilation Report in the Quartus II software.
5–94
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–97. DQS Phase Jitter Specifications for DLL-Delayed Clock
(tDQS PHASE_JITTER) Note (1)
Number of DQS Delay
Buffer Stages (2)
DQS Phase Jitter
Unit
1
30
ps
2
60
ps
3
90
ps
4
120
ps
Notes to Table 5–97:
(1)
(2)
Peak-to-peak phase jitter on the phase shifted DDS clock (digital jitter is caused
by DLL tracking).
Delay stages used for requested DQS phase shift are reported in your project’s
Compilation Report in the Quartus II software.
Table 5–98. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR)
Number of DQS Delay Buffer Stages (2) –3 Speed Grade
(1)
–4 Speed Grade
–5 Speed Grade
Unit
1
25
30
35
ps
2
50
60
70
ps
3
75
90
105
ps
4
100
120
140
ps
Notes to Table 5–98:
(1)
(2)
This error specification is the absolute maximum and minimum error. For example, skew on three delay buffer
stages in a C3 speed grade is 75 ps or ± 37.5 ps.
Delay stages used for requested DQS phase shift are reported in your project’s Compilation Report in the
Quartus II software.
Table 5–99. DQS Bus Clock Skew Adder Specifications
(tDQS_CLOCK_SKEW_ADDER)
Mode
DQS Clock Skew Adder
Unit
×4 DQ per DQS
40
ps
×9 DQ per DQS
70
ps
×18 DQ per DQS
75
ps
×36 DQ per DQS
95
ps
Note to Table 5–99:
(1)
Altera Corporation
April 2011
This skew specification is the absolute maximum and minimum skew. For
example, skew on a ×4 DQ group is 40 ps or ±20 ps.
5–95
Stratix II Device Handbook, Volume 1
JTAG Timing Specifications
Table 5–100. DQS Phase Offset Delay Per Stage
Notes (1), (2), (3)
Speed Grade
Min
Max
Unit
-3
9
14
ps
-4
9
14
ps
-5
9
15
ps
Notes to Table 5–100:
(1)
(2)
(3)
The delay settings are linear.
The valid settings for phase offset are -64 to +63 for frequency mode 0 and -32 to
+31 for frequency modes 1, 2, and 3.
The typical value equals the average of the minimum and maximum values.
Table 5–101. DDIO Outputs Half-Period Jitter
Notes (1), (2)
Name
Description
Max
Unit
tO U T H A L F J I T T E R
Half-period jitter (PLL driving DDIO outputs)
200
ps
Notes to Table 5–101:
(1)
(2)
JTAG Timing
Specifications
The worst-case half period is equal to the ideal half period subtracted by the DCD
and half-period jitter values.
The half-period jitter was characterized using a PLL driving DDIO outputs.
Figure 5–10 shows the timing requirements for the JTAG signals.
Figure 5–10. Stratix II JTAG Waveforms
TMS
TDI
t JCP
t JCH
t JCL
t JPSU
t JPH
TCK
tJPZX
t JPCO
t JPXZ
TDO
5–96
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–102 shows the JTAG timing parameters and values for Stratix II
devices.
Table 5–102. Stratix II JTAG Timing Parameters & Values
Symbol
Parameter
Min
Max
Unit
tJCP
TCK clock period
30
ns
tJCH
TCK clock high time
13
ns
tJCL
TCK clock low time
13
ns
tJPSU
JTAG port setup time
3
ns
tJPH
JTAG port hold time
5
ns
tJPCO
JTAG port clock to output
tJPZX
tJPXZ
11 (1)
ns
JTAG port high impedance to valid output
14 (1)
ns
JTAG port valid output to high impedance
14 (1)
ns
Note to Table 5–102:
(1)
Document
Revision History
A 1 ns adder is required for each VC C I O voltage step down from 3.3 V. For
example, tJPCO = 12 ns if VC C I O of the TDO I/O bank = 2.5 V, or 13 ns if it equals
1.8 V.
Table 5–103 shows the revision history for this chapter.
Table 5–103. Document Revision History (Part 1 of 3)
Date and
Document
Version
Changes Made
Summary of Changes
April 2011, v4.5
Updated Table 5–3.
Added operating junction temperature
for military use.
July 2009, v4.4
Updated Table 5–92.
Updated the spread spectrum
modulation frequency (fS S ) from
(100 kHz–500 kHz) to
(30 kHz–150 kHz).
May 2007, v4.3
●
●
●
Updated RCONF in Table 5–4.
Updated fIN (min) in Table 5–92.
Updated fIN and fINPFD in Table 5–93.
Moved the Document Revision History section to the
end of the chapter.
Altera Corporation
April 2011
—
—
5–97
Stratix II Device Handbook, Volume 1
Document Revision History
Table 5–103. Document Revision History (Part 2 of 3)
Date and
Document
Version
Changes Made
August, 2006,
v4.2
Updated Table 5–73, Table 5–75, Table 5–77,
Table 5–78, Table 5–79, Table 5–81, Table 5–85, and
Table 5–87.
April 2006, v4.1
●
●
●
●
●
●
●
●
●
●
Updated Table 5–3.
Updated Table 5–11.
Updated Figures 5–8 and 5–9.
Added parallel on-chip termination information to
“On-Chip Termination Specifications” section.
Updated Tables 5–28, 5–30,5–31, and 5–34.
Updated Table 5–78, Tables 5–81 through 5–90,
and Tables 5–92, 5–93, and 5–98.
Updated “PLL Timing Specifications” section.
Updated “External Memory Interface
Specifications” section.
Added Tables 5–95 and 5–101.
Updated “JTAG Timing Specifications” section,
including Figure 5–10 and Table 5–102.
Summary of Changes
—
●
●
●
●
●
●
●
●
December 2005,
v4.0
●
●
July 2005, v3.1
●
●
●
●
May 2005, v3.0
●
●
●
●
●
●
Changed 0.2 MHz to 2 MHz in
Table 5–93.
Added new spec for half period
jitter (Table 5–101).
Added support for PLL clock
switchover for industrial
temperature range.
Changed fI N P F D (min) spec from
4 MHz to 2 MHz in Table 5–92.
Fixed typo in tO U T J I T T E R
specification in Table 5–92.
Updated VD I F AC & DC max
specifications in Table 5–28.
Updated minimum values for tJ C H ,
tJ C L , and tJ P S U in Table 5–102.
Update maximum values for tJ P C O ,
tJ P Z X , and tJ P X Z in Table 5–102.
Updated “External Memory Interface
Specifications” section.
Updated timing numbers throughout chapter.
—
Updated HyperTransport technology information in
Table 5–13.
Updated “Timing Model” section.
Updated “PLL Timing Specifications” section.
Updated “External Memory Interface
Specifications” section.
—
Updated tables throughout chapter.
Updated “Power Consumption” section.
Added various tables.
Replaced “Maximum Input & Output Clock Rate”
section with “Maximum Input & Output Clock Toggle
Rate” section.
Added “Duty Cycle Distortion” section.
Added “External Memory Interface Specifications”
section.
—
March 2005,
v2.2
Updated tables in “Internal Timing Parameters”
section.
—
January 2005,
v2.1
Updated input rise and fall time.
—
5–98
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
DC & Switching Characteristics
Table 5–103. Document Revision History (Part 3 of 3)
Date and
Document
Version
January 2005,
v2.0
●
●
●
●
●
●
October 2004,
v1.2
●
July 2004, v1.1
●
●
●
●
●
●
●
●
●
February 2004,
v1.0
Changes Made
Summary of Changes
Updated the “Power Consumption” section.
Added the “High-Speed I/O Specifications” and
“On-Chip Termination Specifications” sections.
Removed the ESD Protection Specifications
section.
Updated Tables 5–3 through 5–13, 5–16 through
5–18, 5–21, 5–35, 5–39, and 5–40.
Updated tables in “Timing Model” section.
Added Tables 5–30 and 5–31.
—
Updated Table 5–3.
Updated introduction text in the “PLL Timing
Specifications” section.
—
Re-organized chapter.
Added typical values and CO U T F B to Table 5–32.
Added undershoot specification to Note (4) for
Tables 5–1 through 5–9.
Added Note (1) to Tables 5–5 and 5–6.
Added VI D and VI C M to Table 5–10.
Added “I/O Timing Measurement Methodology”
section.
Added Table 5–72.
Updated Tables 5–1 through 5–2 and Tables 5–24
through 5–29.
—
Added document to the Stratix II Device Handbook.
Altera Corporation
April 2011
—
5–99
Stratix II Device Handbook, Volume 1
Document Revision History
5–100
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
6. Reference & Ordering
Information
SII51006-2.2
Software
Stratix® II devices are supported by the Altera® Quartus® II design
software, which provides a comprehensive environment for system-on-aprogrammable-chip (SOPC) design. The Quartus II software includes
HDL and schematic design entry, compilation and logic synthesis, full
simulation and advanced timing analysis, SignalTap® II logic analyzer,
and device configuration. See the Quartus II Handbook for more
information on the Quartus II software features.
The Quartus II software supports the Windows XP/2000/NT/98, Sun
Solaris, Linux Red Hat v7.1 and HP-UX operating systems. It also
supports seamless integration with industry-leading EDA tools through
the NativeLink® interface.
Device Pin-Outs
Device pin-outs for Stratix II devices are available on the Altera web site
at (www.altera.com).
Ordering
Information
Figure 6–1 describes the ordering codes for Stratix II devices. For more
information on a specific package, refer to the Package Information for
Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device
Handbook or the Stratix II GX Device Handbook.
Altera Corporation
April 2011
6–1
Document Revision History
Figure 6–1. Stratix II Device Packaging Ordering Information
EP2S
90
F
1508
C
7
ES
Family Signature
EP2S:
Optional Suffix
Stratix II
Indicates specific device options or
shipment method.
ES: Engineering sample
Device Type
15
30
60
90
130
180
Speed Grade
3, 4, or 5, with 3 being the fastest
Operating Temperature
C: Commercial temperature (tJ = 0° C to 85° C)
I: Industrial temperature (tJ = -40° C to 100° C)
Military temperature (tJ = -55° C to 125° C) (1)
Package Type
Pin Count
F: FineLine BGA
H: Hybrid FineLine BGA
Number of pins for a particular FineLine BGA package
Note to Figure 6–1:
(1)
Applicable to I4 devices. For more information, refer to the Stratix II Military Temperature Range Support technical
brief.
Document
Revision History
Table 6–1 shows the revision history for this chapter.
Table 6–1. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
April 2011,
v2.2
Updated Figure 6–1.
May 2007,
v2.1
Moved the Document Revision History section to the end
of the chapter.
—
January
2005, v2.0
Contact information was removed.
—
October
2004, v1.1
Updated Figure 6–1.
—
February
2004, v1.0
Added document to the Stratix II Device Handbook.
—
6–2
Stratix II Device Handbook, Volume 1
Added operating junction temperature
for military use.
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 2
101 Innovation Drive
San Jose, CA 95134
www.altera.com
SII5V2-4.5
Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as
expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
ii
Altera Corporation
Contents
Chapter Revision Dates ........................................................................... xi
About this Handbook ............................................................................. xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiii
Section I. Clock Management
Revision History ....................................................................................................................... Section I–1
Chapter 1. PLLs in Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 1–1
Enhanced PLLs ....................................................................................................................................... 1–5
Enhanced PLL Hardware Overview ............................................................................................. 1–5
Enhanced PLL Software Overview ................................................................................................ 1–9
Enhanced PLL Pins ........................................................................................................................ 1–12
Fast PLLs ............................................................................................................................................... 1–15
Fast PLL Hardware Overview ..................................................................................................... 1–15
Fast PLL Software Overview ........................................................................................................ 1–16
Fast PLL Pins ................................................................................................................................... 1–18
Clock Feedback Modes ....................................................................................................................... 1–20
Source-Synchronous Mode ........................................................................................................... 1–20
No Compensation Mode ............................................................................................................... 1–21
Normal Mode .................................................................................................................................. 1–22
Zero Delay Buffer Mode ................................................................................................................ 1–23
External Feedback Mode ............................................................................................................... 1–24
Hardware Features .............................................................................................................................. 1–25
Clock Multiplication and Division .............................................................................................. 1–26
Phase-Shift Implementation ......................................................................................................... 1–27
Programmable Duty Cycle ........................................................................................................... 1–29
Advanced Clear and Enable Control ........................................................................................... 1–29
Advanced Features .............................................................................................................................. 1–32
Counter Cascading ......................................................................................................................... 1–32
Clock Switchover ............................................................................................................................ 1–33
Reconfigurable Bandwidth ................................................................................................................ 1–44
PLL Reconfiguration ........................................................................................................................... 1–51
Spread-Spectrum Clocking ................................................................................................................ 1–51
Board Layout ........................................................................................................................................ 1–56
VCCA and GNDA ............................................................................................................................ 1–56
Altera Corporation
iii
Contents
Stratix II Device Handbook, Volume 2
VCCD ................................................................................................................................................................................................................... 1–58
External Clock Output Power ...................................................................................................... 1–58
Guidelines ........................................................................................................................................ 1–61
PLL Specifications ................................................................................................................................ 1–62
Clocking ................................................................................................................................................ 1–62
Global and Hierarchical Clocking ................................................................................................ 1–62
Clock Sources Per Region .............................................................................................................. 1–64
Clock Input Connections ............................................................................................................... 1–69
Clock Source Control For Enhanced PLLs .................................................................................. 1–73
Clock Source Control for Fast PLLs ............................................................................................. 1–73
Delay Compensation for Fast PLLs ............................................................................................. 1–75
Clock Output Connections ............................................................................................................ 1–76
Clock Control Block ............................................................................................................................. 1–86
clkena Signals .................................................................................................................................. 1–90
Conclusion ............................................................................................................................................ 1–91
Referenced Documents ....................................................................................................................... 1–91
Document Revision History ............................................................................................................... 1–92
Section II. Memory
Revision History ..................................................................................................................... Section II–1
Chapter 2. TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 2–1
TriMatrix Memory Overview .............................................................................................................. 2–1
Parity Bit Support ............................................................................................................................. 2–3
Byte Enable Support ........................................................................................................................ 2–4
Pack Mode Support .......................................................................................................................... 2–7
Address Clock Enable Support ...................................................................................................... 2–8
Memory Modes ...................................................................................................................................... 2–9
Single-Port Mode ............................................................................................................................ 2–10
Simple Dual-Port Mode ................................................................................................................. 2–12
True Dual-Port Mode ..................................................................................................................... 2–15
Shift-Register Mode ....................................................................................................................... 2–18
ROM Mode ...................................................................................................................................... 2–20
FIFO Buffers Mode ......................................................................................................................... 2–20
Clock Modes ......................................................................................................................................... 2–20
Independent Clock Mode .............................................................................................................. 2–21
Input/Output Clock Mode ........................................................................................................... 2–23
Read/Write Clock Mode ............................................................................................................... 2–26
Single-Clock Mode ......................................................................................................................... 2–28
Designing With TriMatrix Memory .................................................................................................. 2–31
Selecting TriMatrix Memory Blocks ............................................................................................ 2–31
Synchronous and Pseudo-Asynchronous Modes ...................................................................... 2–32
Power-up Conditions and Memory Initialization ..................................................................... 2–32
Read-During-Write Operation at the Same Address ..................................................................... 2–33
iv
Altera Corporation
Contents
Contents
Same-Port Read-During-Write Mode ..........................................................................................
Mixed-Port Read-During-Write Mode ........................................................................................
Conclusion ............................................................................................................................................
Referenced Documents .......................................................................................................................
Document Revision History ...............................................................................................................
2–33
2–34
2–35
2–36
2–36
Chapter 3. External Memory Interfaces in Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 3–1
External Memory Standards ................................................................................................................ 3–4
DDR and DDR2 SDRAM ................................................................................................................. 3–4
RLDRAM II ....................................................................................................................................... 3–8
QDRII SRAM ................................................................................................................................... 3–10
Stratix II and Stratix II GX DDR Memory Support Overview ...................................................... 3–13
DDR Memory Interface Pins ......................................................................................................... 3–14
DQS Phase-Shift Circuitry ............................................................................................................ 3–21
DQS Logic Block ............................................................................................................................. 3–28
DDR Registers ................................................................................................................................. 3–31
PLL ................................................................................................................................................... 3–38
Enhancements In Stratix II and Stratix II GX Devices .................................................................... 3–38
Conclusion ............................................................................................................................................ 3–38
Referenced Documents ....................................................................................................................... 3–39
Document Revision History ............................................................................................................... 3–39
Section III. I/O Standards
Revision History .................................................................................................................... Section III–1
Chapter 4. Selectable I/O Standards in Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 4–1
Stratix II and Stratix II GX I/O Features ............................................................................................ 4–1
Stratix II and Stratix II GX I/O Standards Support .......................................................................... 4–2
Single-Ended I/O Standards .......................................................................................................... 4–3
Differential I/O Standards ............................................................................................................ 4–10
Stratix II and Stratix II GX External Memory Interface .................................................................. 4–19
Stratix II and Stratix II GX I/O Banks ............................................................................................... 4–20
Programmable I/O Standards ...................................................................................................... 4–22
On-Chip Termination .......................................................................................................................... 4–27
On-Chip Series Termination without Calibration ..................................................................... 4–28
On-Chip Series Termination with Calibration ........................................................................... 4–30
On-Chip Parallel Termination with Calibration ........................................................................ 4–31
Design Considerations ........................................................................................................................ 4–33
I/O Termination ............................................................................................................................. 4–33
I/O Banks Restrictions .................................................................................................................. 4–34
I/O Placement Guidelines ............................................................................................................ 4–36
DC Guidelines ................................................................................................................................. 4–39
Conclusion ............................................................................................................................................ 4–42
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Contents
Stratix II Device Handbook, Volume 2
References ............................................................................................................................................. 4–42
Referenced Documents ....................................................................................................................... 4–43
Document Revision History ............................................................................................................... 4–44
Chapter 5. High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX
Devices
Introduction ............................................................................................................................................ 5–1
I/O Banks ................................................................................................................................................ 5–1
Differential Transmitter ........................................................................................................................ 5–6
Differential Receiver .............................................................................................................................. 5–8
Receiver Data Realignment Circuit ............................................................................................... 5–9
Dynamic Phase Aligner ................................................................................................................. 5–10
Synchronizer ................................................................................................................................... 5–12
Differential I/O Termination ............................................................................................................. 5–12
Fast PLL ................................................................................................................................................ 5–13
Clocking ................................................................................................................................................ 5–14
Source Synchronous Timing Budget ........................................................................................... 5–16
Differential Data Orientation ........................................................................................................ 5–17
Differential I/O Bit Position ......................................................................................................... 5–17
Receiver Skew Margin for Non-DPA .......................................................................................... 5–19
Differential Pin Placement Guidelines ............................................................................................. 5–21
High-Speed Differential I/Os and Single-Ended I/Os ............................................................. 5–21
DPA Usage Guidelines .................................................................................................................. 5–22
Non-DPA Differential I/O Usage Guidelines ............................................................................ 5–26
Board Design Considerations ............................................................................................................ 5–27
Conclusion ............................................................................................................................................ 5–28
Referenced Documents ....................................................................................................................... 5–29
Document Revision History ............................................................................................................... 5–29
Section IV. Digital Signal Processing (DSP)
Revision History .................................................................................................................... Section IV–1
Chapter 6. DSP Blocks in Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 6–1
DSP Block Overview ............................................................................................................................. 6–1
Architecture ............................................................................................................................................ 6–8
Multiplier Block ................................................................................................................................ 6–8
Adder/Output Block ..................................................................................................................... 6–16
Operational Modes .............................................................................................................................. 6–21
Simple Multiplier Mode ................................................................................................................ 6–22
Multiply Accumulate Mode ......................................................................................................... 6–25
Multiply Add Mode ....................................................................................................................... 6–26
Software Support ................................................................................................................................. 6–32
Conclusion ............................................................................................................................................ 6–32
Referenced Documents ....................................................................................................................... 6–33
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Contents
Contents
Document Revision History ............................................................................................................... 6–33
Section V. Configuration& Remote System Upgrades
Revision History ..................................................................................................................... Section V–1
Chapter 7. Configuring Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 7–1
Configuration Devices ..................................................................................................................... 7–1
Configuration Features ......................................................................................................................... 7–4
Configuration Data Decompression .............................................................................................. 7–5
Design Security Using Configuration Bitstream Encryption ..................................................... 7–8
Remote System Upgrade ................................................................................................................. 7–9
Power-On Reset Circuit ................................................................................................................... 7–9
VCCPD Pins ....................................................................................................................................... 7–10
VCCSEL Pin .................................................................................................................................... 7–10
Output Configuration Pins ........................................................................................................... 7–13
Fast Passive Parallel Configuration .................................................................................................. 7–14
FPP Configuration Using a MAX II Device as an External Host ............................................ 7–15
FPP Configuration Using a Microprocessor ............................................................................... 7–26
FPP Configuration Using an Enhanced Configuration Device ............................................... 7–26
Active Serial Configuration (Serial Configuration Devices) ......................................................... 7–34
Estimating Active Serial Configuration Time ............................................................................ 7–43
Programming Serial Configuration Devices .............................................................................. 7–43
Passive Serial Configuration .............................................................................................................. 7–46
PS Configuration Using a MAX II Device as an External Host ............................................... 7–47
PS Configuration Using a Microprocessor ................................................................................. 7–54
PS Configuration Using a Configuration Device ....................................................................... 7–55
PS Configuration Using a Download Cable ............................................................................... 7–67
Passive Parallel Asynchronous Configuration ................................................................................ 7–73
JTAG Configuration ............................................................................................................................ 7–84
Jam STAPL ...................................................................................................................................... 7–91
Device Configuration Pins ................................................................................................................. 7–92
Conclusion .......................................................................................................................................... 7–106
Referenced Documents ..................................................................................................................... 7–106
Document Revision History ............................................................................................................. 7–107
Chapter 8. Remote System Upgrades with Stratix II and Stratix II GX Devices
Introduction ............................................................................................................................................ 8–1
Functional Description .......................................................................................................................... 8–2
Configuration Image Types and Pages ......................................................................................... 8–5
Remote System Upgrade Modes ......................................................................................................... 8–8
Overview ........................................................................................................................................... 8–8
Remote Update Mode ...................................................................................................................... 8–9
Local Update Mode ........................................................................................................................ 8–12
Dedicated Remote System Upgrade Circuitry ................................................................................ 8–14
Altera Corporation
vii
Contents
Stratix II Device Handbook, Volume 2
Remote System Upgrade Registers ..............................................................................................
Remote System Upgrade State Machine .....................................................................................
User Watchdog Timer ....................................................................................................................
Interface Signals between Remote System Upgrade Circuitry and FPGA Logic Array ......
Remote System Upgrade Pin Descriptions .................................................................................
Quartus II Software Support ..............................................................................................................
altremote_update Megafunction ..................................................................................................
Remote System Upgrade Atom ....................................................................................................
System Design Guidelines ..................................................................................................................
Remote System Upgrade With Serial Configuration Devices .................................................
Remote System Upgrade With a MAX II Device or Microprocessor and Flash Device ......
Remote System Upgrade with Enhanced Configuration Devices ..........................................
Conclusion ............................................................................................................................................
Referenced Documents .......................................................................................................................
Document Revision History ...............................................................................................................
8–15
8–19
8–20
8–21
8–23
8–24
8–24
8–28
8–28
8–29
8–29
8–30
8–31
8–31
8–32
Chapter 9. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II and Stratix II GX
Devices
Introduction ............................................................................................................................................ 9–1
IEEE Std. 1149.1 BST Architecture ...................................................................................................... 9–2
IEEE Std. 1149.1 Boundary-Scan Register .......................................................................................... 9–4
Boundary-Scan Cells of a Stratix II or Stratix II GX Device I/O Pin ........................................ 9–5
IEEE Std. 1149.1 BST Operation Control ............................................................................................ 9–7
SAMPLE/PRELOAD Instruction Mode ..................................................................................... 9–11
Capture Phase ................................................................................................................................. 9–12
Shift and Update Phases ................................................................................................................ 9–12
EXTEST Instruction Mode ............................................................................................................ 9–13
Capture Phase ................................................................................................................................. 9–14
Shift and Update Phases ................................................................................................................ 9–14
BYPASS Instruction Mode ............................................................................................................ 9–15
IDCODE Instruction Mode ........................................................................................................... 9–16
USERCODE Instruction Mode ..................................................................................................... 9–16
CLAMP Instruction Mode ............................................................................................................ 9–17
HIGHZ Instruction Mode ............................................................................................................. 9–17
I/O Voltage Support in JTAG Chain ................................................................................................ 9–17
Using IEEE Std. 1149.1 BST Circuitry ............................................................................................... 9–19
BST for Configured Devices ............................................................................................................... 9–19
Disabling IEEE Std. 1149.1 BST Circuitry ......................................................................................... 9–20
Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing ............................................................... 9–20
Boundary-Scan Description Language (BSDL) Support ................................................................ 9–21
Conclusion ............................................................................................................................................ 9–21
References ............................................................................................................................................. 9–22
Referenced Documents ....................................................................................................................... 9–22
Document Revision History ............................................................................................................... 9–22
viii
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Contents
Contents
Section VI. PCB Layout Guidelines
Revision History .................................................................................................................... Section VI–1
Chapter 10. Package Information for Stratix II & Stratix II GX Devices
Introduction .......................................................................................................................................... 10–1
Thermal Resistance .............................................................................................................................. 10–2
Package Outlines ................................................................................................................................. 10–5
484-Pin FBGA - Flip Chip .............................................................................................................. 10–5
672-Pin FBGA - Flip Chip .............................................................................................................. 10–6
780-Pin FBGA - Flip Chip .............................................................................................................. 10–9
1,020-Pin FBGA - Flip Chip ......................................................................................................... 10–11
1,152-Pin FBGA - Flip Chip ......................................................................................................... 10–13
1,508-Pin FBGA - Flip Chip ......................................................................................................... 10–15
Document Revision History ............................................................................................................. 10–17
Chapter 11. High-Speed Board Layout Guidelines
Introduction .......................................................................................................................................... 11–1
PCB Material Selection ........................................................................................................................ 11–1
Transmission Line Layout .................................................................................................................. 11–3
Impedance Calculation .................................................................................................................. 11–4
Propagation Delay .......................................................................................................................... 11–8
Pre-Emphasis .................................................................................................................................. 11–9
Routing Schemes for Minimizing Crosstalk & Maintaining Signal Integrity ........................... 11–11
Signal Trace Routing .................................................................................................................... 11–13
Termination Schemes ........................................................................................................................ 11–19
Simple Parallel Termination ....................................................................................................... 11–19
Thevenin Parallel Termination ................................................................................................... 11–20
Active Parallel Termination ........................................................................................................ 11–21
Series-RC Parallel Termination .................................................................................................. 11–22
Series Termination ....................................................................................................................... 11–23
Differential Pair Termination ..................................................................................................... 11–23
Simultaneous Switching Noise ........................................................................................................ 11–24
Power Filtering & Distribution ................................................................................................... 11–26
Electromagnetic Interference (EMI) ................................................................................................ 11–28
Additional FPGA-Specific Information .......................................................................................... 11–29
Configuration ................................................................................................................................ 11–29
JTAG ............................................................................................................................................... 11–30
Test Point ....................................................................................................................................... 11–30
Summary ............................................................................................................................................. 11–30
References ........................................................................................................................................... 11–31
Document Revision History ............................................................................................................. 11–31
Altera Corporation
ix
Contents
x
Stratix II Device Handbook, Volume 2
Altera Corporation
Chapter Revision Dates
The chapters in this book, Stratix II Device Handbook, Volume 2, were revised on the following dates.
Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. PLLs in Stratix II and Stratix II GX Devices
Revised:
July 2009
Part number: SII52001-4.6
Chapter 2. TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Revised:
January 2008
Part number: SII52002-4.5
Chapter 3. External Memory Interfaces in Stratix II and Stratix II GX Devices
Revised:
January 2008
Part number: SII52003-4.5
Chapter 4. Selectable I/O Standards in Stratix II and Stratix II GX Devices
Revised:
January 2008
Part number: SII52004-4.6
Chapter 5. High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Revised:
January 2008
Part number: SII52005-2.2
Chapter 6. DSP Blocks in Stratix II and Stratix II GX Devices
Revised:
January 2008
Part number: SII52006-2.2
Chapter 7. Configuring Stratix II and Stratix II GX Devices
Revised:
January 2008
Part number: SII52007-4.5
Chapter 8. Remote System Upgrades with Stratix II and Stratix II GX Devices
Revised:
January 2008
Part number: SII52008-4.5
Chapter 9. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II and Stratix II GX Devices
Revised:
January 2008
Part number: SII52009-3.3
Altera Corporation
xi
Chapter Revision Dates
Stratix II Device Handbook, Volume 2
Chapter 10. Package Information for Stratix II & Stratix II GX Devices
Revised:
May 2007
Part number: SII52010-4.3
Chapter 11. High-Speed Board Layout Guidelines
Revised:
May 2007
Part number: SII52012-1.4
xii
Altera Corporation
About this Handbook
This handbook provides comprehensive information about the Altera®
Stratix® II family of devices.
How to Contact
Altera
For the most up-to-date information about Altera products, refer to the
following table.
Contact (1)
Contact
Method
Address
Technical support
Website
www.altera.com/support
Technical training
Website
www.altera.com/training
Email
[email protected]
Website
www.altera.com/literature
Product literature
Non-technical support (General) Email
(Software Licensing)
Email
[email protected]
[email protected]
Note to table:
(1)
Typographic
Conventions
Visual Cue
You can also contact your local Altera sales office or sales representative.
This document uses the typographic conventions shown below.
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold
type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial Capital
Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Internal timing parameters and variables are shown in italic type.
Examples: tPIA, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Altera Corporation
xiii
Preliminary
Typographic Conventions
Visual Cue
Stratix II Device Handbook, Volume 2
Meaning
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and
a., b., c., etc.
Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
●
•
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
c
The caution indicates required information that needs special consideration and
understanding and should be read prior to starting or continuing with the
procedure or process.
w
The warning indicates information that should be read prior to starting or
continuing the procedure or processes
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
xiv
Preliminary
Altera Corporation
Section I. Clock
Management
This section provides information on the different types of phase-locked
loops (PLLs). The feature-rich enhanced PLLs assist designers in
managing clocks internally and also have the ability to drive off chip to
control system-level clock networks. The fast PLLs offer general-purpose
clock management with multiplication and phase shifting as well as highspeed outputs to manage the high-speed differential I/O interfaces. This
section contains detailed information on the features, the
interconnections to the logic array and off chip, and the specifications for
both types of PLLs.
This section contains the following chapter:
■
Revision History
Altera Corporation
Chapter 1, PLLs in Stratix II and Stratix II GX Devices
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section I–1
Clock Management
Section I–2
Stratix II Device Handbook, Volume 2
Altera Corporation
1. PLLs in Stratix II and
Stratix II GX Devices
SII52001-4.6
Introduction
Stratix® II and Stratix II GX device phase-locked loops (PLLs) provide
robust clock management and synthesis for device clock management,
external system clock management, and high-speed I/O interfaces.
Stratix II devices have up to 12 PLLs, and Stratix II GX devices have up to
8 PLLs. Stratix II and Stratix II GX PLLs are highly versatile and can be
used as a zero delay buffer, a jitter attenuator, low skew fan out buffer, or
a frequency synthesizer.
Stratix II and Stratix II GX devices feature both enhanced PLLs and fast
PLLs. Stratix II and Stratix II GX devices have up to four enhanced PLLs.
Stratix II devices have up to eight fast PLLs and Stratix II GX devices have
up to four PLLs. Both enhanced and fast PLLs are feature rich, supporting
advanced capabilities such as clock switchover, reconfigurable phase
shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs can be
used for general-purpose clock management, supporting multiplication,
phase shifting, and programmable duty cycle. In addition, enhanced
PLLs support external clock feedback mode, spread-spectrum clocking,
and counter cascading. Fast PLLs offer high speed outputs to manage the
high-speed differential I/O interfaces.
Stratix II and Stratix II GX devices also support a power-down mode
where clock networks that are not being used can easily be turned off,
reducing the overall power consumption of the device. In addition,
Stratix II and Stratix II GX PLLs support dynamic selection of the PLL
input clock from up to five possible sources, giving you the flexibility to
choose from multiple (up to four) clock sources to feed the primary and
secondary clock input ports.
The Altera® Quartus® II software enables the PLLs and their features
without requiring any external devices.
Altera Corporation
July 2009
1–1
Introduction
Tables 1–1 and 1–2 show the PLLs available for each Stratix II and
Stratix II GX device, respectively.
Table 1–1. Stratix II Device PLL Availability
Note (1)
Fast PLLs
Enhanced PLLs
Device
1
2
3
4
7
8
9
EP2S15
v
v
v
EP2S30
v
v
v
EP2S60
v
v
v
v
v
v
v
EP2S90 (2)
v
v
v
v
v
v
v
EP2S130 (3)
v
v
v
v
v
v
EP2S180
v
v
v
v
v
v
10
5
6
11
12
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Notes for Table 1–1:
(1)
(2)
(3)
The EP2S60 device in the 1,020-pin package contains 12 PLLs. EP2S60 devices in the 484-pin and 672-pin packages
contain fast PLLs 1–4 and enhanced PLLs 5 and 6.
EP2S90 devices in the 1020-pin and 1508-pin packages contain 12 PLLs. EP2S90 devices in the 484-pin and 780-pin
packages contain fast PLLs 1–4 and enhanced PLLs 5 and 6.
EP2S130 devices in the 1020-pin and 1508-pin packages contain 12 PLLs. The EP2S130 device in the 780-pin
package contains fast PLLs 1–4 and enhanced PLLs 5 and 6.
Table 1–2. Stratix II GX Device PLL Availability
Note (1)
Fast PLLs
Enhanced PLLs
Device
1
2
EP2SGX30 (2)
v
v
3 (3)
4 (3)
7
8
9 (3) 10 (3)
5
6
v
v
11
12
EP2SGX60 (2)
v
v
v
v
v
v
v
v
EP2SGX90
v
v
v
v
v
v
v
v
EP2SGX130
v
v
v
v
v
v
v
v
Notes for Table 1–2:
(1)
(2)
(3)
The global or regional clocks in a fast PLL’s transceiver block can drive the fast PLL input. A pin or other PLL must
drive the global or regional source. The source cannot be driven by internally generated logic before driving the
fast PLL.
EP2SGX30C and EP2SGX60C devices only have two fast PLLs (PLLs 1 and 2), but the connectivity from these two
PLLs to the global and regional clock networks remains the same as shown in this table.
PLLs 3, 4, 9, and 10 are not available in Stratix II GX devices. however, these PLLs are listed in Table 1–2 because
the Stratix II GX PLL numbering scheme is consistent with Stratix and Stratix II devices.
1–2
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Table 1–3 shows the enhanced PLL and fast PLL features in Stratix II and
Stratix II GX devices.
Table 1–3. Stratix II and Stratix II GX PLL Features
Feature
Clock multiplication and division
Enhanced PLL
Fast PLL
m/(n × post-scale counter) (1)
m/(n × post-scale counter) (2)
Down to 125-ps increments (3)
Down to 125-ps increments (3)
Clock switchover
v
v (4)
PLL reconfiguration
v
v
Reconfigurable bandwidth
v
v
Spread-spectrum clocking
v
Programmable duty cycle
v
Number of clock outputs per PLL (5)
6
Phase shift
Number of dedicated external clock outputs Three differential or six
per PLL
single-ended
Number of feedback clock inputs per PLL
v
4
(6)
1 (7)
Notes to Table 1–3:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For enhanced PLLs, m and n range from 1 to 512 with 50% duty cycle. Post-scale counters range from 1 to 512 with
50% duty cycle. For non-50% duty-cycle clock outputs, post-scale counters range from 1 to 256.
For fast PLLs, n can range from 1 to 4. The post-scale and m counters range from 1 to 32. For non-50% duty-cycle
clock outputs, post-scale counters range from 1 to 16.
The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by eight. The
supported phase-shift range is from 125 to 250 ps. Stratix II and Stratix II GX devices can shift all output
frequencies in increments of at least 45. Smaller degree increments are possible depending on the frequency and
divide parameters. For non-50% duty cycle clock outputs post-scale counters range from 1 to 256.
Stratix II and Stratix II GX fast PLLs only support manual clock switchover.
The clock outputs can be driven to internal clock networks or to a pin.
The PLL clock outputs of the fast PLLs can drive to any I/O pin to be used as an external clock output. For
high-speed differential I/O pins, the device uses a data channel to generate the transmitter output clock
(txclkout).
If the design uses external feedback input pins, you will lose one (or two, if fBIN is differential) dedicated output
clock pin.
Figure 1–1 shows a top-level diagram of Stratix II device and PLL
locations. Figure 1–2 shows a top-level diagram of Stratix II device and
PLL locations. See “Clock Control Block” on page 1–86 for more detail on
PLL connections to global and regional clocks networks.
Altera Corporation
July 2009
1–3
Stratix II Device Handbook, Volume 2
Introduction
Figure 1–1. Stratix II PLL Locations
Enhanced PLL
Enhanced PLL
CLK12-15
11
FPLL7CLK
5
7
RCLK28-31
10
FPLL10CLK
4
3
CLK8-11
9
FPLL9CLK
RCLK24-27
GCLK12-15
RCLK0-3
Fast PLLs
CLK0-3
Fast PLLs
RCLK20-23
GCLK0-3
1
2
GCLK8-11
Q1 Q2
Q4 Q3
RCLK4-7
Fast PLLs
Fast PLLs
RCLK16-19
GCLK4-7
RCLK8-11
FPLL8CLK
RCLK12-15
8
12
6
CLK4-7
Enhanced PLL
1–4
Stratix II Device Handbook, Volume 2
Enhanced PLL
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Figure 1–2. Stratix II GX PLL Locations
CLK[15..12]
FPLL7CLK
7
CLK[3..0]
1
2
11
5
12
6
PLLs
FPLL8CLK
8
CLK[7..4]
Enhanced PLLs
Stratix II and Stratix II GX devices contain up to four enhanced PLLs with
advanced clock management features. The main goal of a PLL is to
synchronize the phase and frequency of an internal and external clock to
an input reference clock. There are a number of components that
comprise a PLL to achieve this phase alignment.
Enhanced PLL Hardware Overview
Stratix II and Stratix II GX PLLs align the rising edge of the reference
input clock to a feedback clock using the phase-frequency detector (PFD).
The falling edges are determined by the duty-cycle specifications. The
PFD produces an up or down signal that determines whether the VCO
needs to operate at a higher or lower frequency.
Altera Corporation
July 2009
1–5
Stratix II Device Handbook, Volume 2
Enhanced PLLs
The PFD output is applied to the charge pump and loop filter, which
produces a control voltage for setting the VCO frequency. If the PFD
produces an up signal, then the VCO frequency increases. A down signal
decreases the VCO frequency. The PFD outputs these up and down
signals to a charge pump. If the charge pump receives an up signal,
current is driven into the loop filter. Conversely, if it receives a down
signal, current is drawn from the loop filter.
The loop filter converts these up and down signals to a voltage that is
used to bias the VCO. The loop filter also removes glitches from the
charge pump and prevents voltage over-shoot, which filters the jitter on
the VCO.
The voltage from the loop filter determines how fast the VCO operates.
The VCO is implemented as a four-stage differential ring oscillator. A
divide counter (m) is inserted in the feedback loop to increase the VCO
frequency above the input reference frequency. VCO frequency (fVCO) is
equal to (m) times the input reference clock (fREF). The input reference
clock (fREF) to the PFD is equal to the input clock (fIN) divided by the prescale counter (n). Therefore, the feedback clock (fFB) applied to one input
of the PFD is locked to the fREF that is applied to the other input of the
PFD.
The VCO output can feed up to six post-scale counters (C0, C1, C2, C3, C4,
and C5). These post-scale counters allow a number of harmonically
related frequencies to be produced within the PLL.
Figure 1–3 shows a simplified block diagram of the major components of
the Stratix II and Stratix II GX enhanced PLL. Figure 1–4 shows the
enhanced PLL’s outputs and dedicated clock outputs.
1–6
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Figure 1–3. Stratix II and Stratix II GX Enhanced PLL
From Adjacent PLL
VCO Phase Selection
Selectable at Each
PLL Output Port
Clock
Switchover
Circuitry
Post-Scale
Counters
÷c0
Spread
Spectrum
Phase Frequency
Detector
INCLK[3..0]
÷c1
4
÷n
PFD
Charge
Pump
Loop
Filter
Global or
Regional
Clock
8
VCO
4
Global
Clocks
8
Regional
Clocks
÷c2
6
÷c3
6
(1)
÷m
I/O Buffers (2)
÷c4
÷c5
FBIN
Shaded Portions of the
PLL are Reconfigurable
Lock Detect
& Filter
to I/O or general
routing
VCO Phase Selection
Affecting All Outputs
Notes to Figure 1–3:
(1)
(2)
(3)
(4)
Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
PLLs 5, 6, 11, and 12 each have six single-ended dedicated clock outputs or three differential dedicated clock
outputs.
If the design uses external feedback input pins, you will lose one (or two, if fBIN is differential) dedicated output
clock pin. Every Stratix II and Stratix II GX device has at least two enhanced PLLs with one single-ended or
differential external feedback input per PLL.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
Altera Corporation
July 2009
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Stratix II Device Handbook, Volume 2
Enhanced PLLs
External Clock Outputs
Enhanced PLLs 5, 6, 11, and 12 each support up to six single-ended clock
outputs (or three differential pairs). See Figure 1–4.
Figure 1–4. External Clock Outputs for Enhanced PLLs 5, 6, 11 and 12
C0
C1
Enhanced
PLL
C2
C3
C4
C5
extclken0
(3)
extclken2
(3)
extclken3
(3)
extclken1
(3)
PLL#_OUT0p
(1)
PLL#_OUT0n
(1)
extclken4
(3)
extclken5
(3)
PLL#_OUT1p
(1)
PLL#_OUT1n
(1)
PLL#_OUT2p
(1), (2)
PLL#_OUT2n
(1), (2)
Notes to Figure 1–4:
(1)
(2)
(3)
These clock output pins can be fed by any one of the C[5..0] counters.
These clock output pins are used as either external clock outputs or for external feedback. If the design uses external
feedback input pins, you will lose one (or two, if fBIN is differential) dedicated output clock pin.
These external clock enable signals are available only when using the altclkctrl megafunction.
Any of the six output counters C[5..0] can feed the dedicated external
clock outputs, as shown in Figure 1–5. Therefore, one counter or
frequency can drive all output pins available from a given PLL. The
dedicated output clock pins (PLL_OUT) from each enhanced PLL are
powered by a separate power pin (e.g., VCC_PLL5_OUT, VCC_PLL6_OUT,
etc.), reducing the overall output jitter by providing improved isolation
from switching I/O pins.
1–8
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Figure 1–5. External Clock Output Connectivity to PLL Output Counters for Enhanced PLLs 5, 6, 11 and 12
Note (1)
C0
C1
6
6
To I/O pins (1)
C3
C4
C5
From internal logic
or IOE
6
Multiplexer Selection
Set in Configuration File
C6
Note to Figure 1–5:
(1)
The design can use each external clock output pin as a general-purpose output pin from the logic array. These pins
are multiplexed with I/O element (IOE) outputs.
Each pin of a single-ended output pair can either be in phase or 180° out
of phase. The Quartus II software places the NOT gate in the design into
the IOE to implement 180° phase with respect to the other pin in the pair.
The clock output pin pairs support the same I/O standards as standard
output pins (in the top and bottom banks) as well as LVDS, LVPECL,
differential HSTL, and differential SSTL. See Table 1–6, in the “Enhanced
PLL Pins” section on page 1–12 to determine which I/O standards the
enhanced PLL clock pins support.
When in single-ended or differential mode, one power pin supports six
single-ended or three differential outputs. Both outputs use the same I/O
standard in single-ended mode to maintain performance. You can also
use the external clock output pins as user output pins if external
enhanced PLL clocking is not needed.
The enhanced PLL can also drive out to any regular I/O pin through the
global or regional clock network.
Enhanced PLL Software Overview
Stratix II and Stratix II GX enhanced PLLs are enabled in the Quartus II
software by using the altpll megafunction. Figure 1–6 shows the
available ports (as they are named in the Quartus II altpll
megafunction) of the Stratix II and Stratix II GX enhanced PLL.
Altera Corporation
July 2009
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Stratix II Device Handbook, Volume 2
Enhanced PLLs
Figure 1–6. Enhanced PLL Ports
(1)
Physical Pin
pllena
(2), (3)
inclk0
(2), (3)
inclk1
C[5..0]
(4)
Signal Driven by Internal Logic
Signal Driven to Internal Logic
Internal Clock Signal
locked
scanwrite
clkloss
activeclock
scanread
scandataout
scandata
clkbad[1..0]
scanclk
scandone
fbin
clkswitch
areset
pfdena
(5)
pll_out0p
pll_out0n
(5)
pll_out1p
(5)
pll_out1n
(5)
pll_out2p
(5)
pll_out2n
(5)
Notes to Figure 1–6:
(1)
(2)
(3)
(4)
(5)
Enhanced and fast PLLs share this input pin.
These are either single-ended or differential pins.
The primary and secondary clock input can be fed from any one of four clock pins located on the same side of the
device as the PLL.
Can drive to the global or regional clock networks or the dedicated external clock output pins.
These dedicated output clocks are fed by the C[5..0] counters.
Tables 1–4 and 1–5 describe all the enhanced PLL ports.
Table 1–4. Enhanced PLL Input Signals (Part 1 of 2)
Port
Description
Source
Destination
inclk0
Primary clock input to the PLL.
Pin or another PLL
n counter
inclk1
Secondary clock input to the PLL.
Pin or another PLL
n counter
fbin
External feedback input to the PLL.
Pin
PFD
pllena
Enable pin for enabling or disabling
all or a set of PLLs. Active high.
Pin
General PLL control
signal
clkswitch
Switch-over signal used to initiate
external clock switch-over control.
Active high.
Logic array
PLL switch-over circuit
1–10
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Table 1–4. Enhanced PLL Input Signals (Part 2 of 2)
Port
Description
Source
Destination
areset
Signal used to reset the PLL which
resynchronizes all the counter
outputs. Active high.
Logic array
General PLL control
signal
pfdena
Enables the outputs from the phase
frequency detector. Active high.
Logic array
PFD
scanclk
Serial clock signal for the real-time
PLL reconfiguration feature.
Logic array
Reconfiguration circuit
scandata
Serial input data stream for the real- Logic array
time PLL reconfiguration feature.
Reconfiguration circuit
scanwrite
Enables writing the data in the scan
chain into the PLL. Active high.
Logic array
Reconfiguration circuit
scanread
Enables scan data to be written into
the scan chain. Active high.
Logic array
Reconfiguration circuit
Table 1–5. Enhanced PLL Output Signals (Part 1 of 2)
Port
Description
Source
Destination
c[5..0]
PLL output counters driving regional, PLL counter
global or external clocks.
Internal or external clock
pll_out [2..0]p
pll_out [2..0]n
PLL counter
These are three differential or six
single-ended external clock output
pins fed from the C[5..0] PLL
counters, and every output can be
driven by any counter. p and n are
the positive (p) and negative (n) pins
for differential pins.
Pin(s)
clkloss
Signal indicating the switch-over
circuit detected a switch-over
condition.
PLL switch-over
circuit
Logic array
clkbad[1..0]
Signals indicating which reference
clock is no longer toggling.
clkbad1 indicates inclk1
status, clkbad0 indicates
inclk0 status. 1= good; 0=bad
PLL switch-over
circuit
Logic array
locked
Lock or gated lock output from lock
detect circuit. Active high.
PLL lock detect
Logic array
activeclock
PLL clock
Signal to indicate which clock
multiplexer
(0 = inclk0 or 1 = inclk1) is
driving the PLL. If this signal is low,
inclk0 drives the PLL, If this signal
is high, inclk1 drives the PLL
Altera Corporation
July 2009
Logic array
1–11
Stratix II Device Handbook, Volume 2
Enhanced PLLs
Table 1–5. Enhanced PLL Output Signals (Part 2 of 2)
Port
Description
Source
Destination
scandataout
Output of the last shift register in the PLL scan chain
scan chain.
Logic array
scandone
Signal indicating when the PLL has
completed reconfiguration. 1 to 0
transition indicates that the PLL has
been reconfigured.
PLL scan chain
Logic array
Enhanced PLL Pins
Table 1–6 lists the I/O standards support by the enhanced PLL clock
outputs.
Table 1–6. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2)
Note (1)
Input
Output
I/O Standard
INCLK
FBIN
EXTCLK
LVTTL
v
v
v
LVCMOS
v
v
v
2.5 V
v
v
v
1.8 V
v
v
v
1.5 V
v
v
v
3.3-V PCI
v
v
v
3.3-V PCI-X
v
v
v
SSTL-2 Class I
v
v
v
SSTL-2 Class II
v
v
v
SSTL-18 Class I
v
v
v
SSTL-18 Class II
v
v
v
1.8-V HSTL Class I
v
v
v
1.8-V HSTL Class II
v
v
v
1.5-V HSTL Class I
v
v
v
1.5-V HSTL Class II
v
v
v
1.2-V HSTL Class I
v
v
v
1.2-V HSTL Class II
v
v
v
1–12
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Table 1–6. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2)
Note (1)
Input
Output
I/O Standard
INCLK
FBIN
EXTCLK
Differential SSTL-2 Class I
v
v
v
Differential SSTL-2 Class II
v
v
v
Differential SSTL-18 Class I
v
v
v
Differential SSTL-18 Class II
v
v
v
1.8-V differential HSTL Class I
v
v
v
1.8-V differential HSTL Class II
v
v
v
1.5-V differential HSTL Class I
v
v
v
1.5-V differential HSTL Class II
v
v
v
LVDS
v
v
v
v
v
v
HyperTransport technology
Differential LVPECL
Note to Table 1–6:
(1)
The enhanced PLL external clock output bank does not allow a mixture of both
single-ended and differential I/O standards.
Table 1–7 shows the physical pins and their purpose for the Stratix II and
Stratix II GX enhanced PLLs. For inclk port connections to pins see
“Clock Control Block” on page 1–86.
Table 1–7. Stratix II and Stratix II GX Enhanced PLL Pins (Part 1 of 3)
Pin
Note (1)
Description
CLK4p/n
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
CLK5p/n
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
CLK6p/n
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
CLK7p/n
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
CLK12p/n
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
CLK13p/n
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
CLK14p/n
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
CLK15p/n
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
PLL5_FBp/n
Single-ended or differential pins that can drive the fbin port for PLL 5.
Altera Corporation
July 2009
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Stratix II Device Handbook, Volume 2
Enhanced PLLs
Table 1–7. Stratix II and Stratix II GX Enhanced PLL Pins (Part 2 of 3)
Pin
Note (1)
Description
PLL6_FBp/n
Single-ended or differential pins that can drive the fbin port for PLL 6.
PLL11_FBp/n
Single-ended or differential pins that can drive the fbin port for PLL 11.
PLL12_FBp/n
Single-ended or differential pins that can drive the fbin port for PLL 12.
PLL_ENA
Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do
not use this pin, connect it to ground.
PLL5_OUT[2..0]p/n
Single-ended or differential pins driven by C[5..0] ports from PLL 5.
PLL6_OUT[2..0]p/n
Single-ended or differential pins driven by C[5..0] ports from PLL 6.
PLL11_OUT[2..0]p/n
Single-ended or differential pins driven by C[5..0] ports from PLL 11.
PLL12_OUT[2..0]p/n
Single-ended or differential pins driven by C[5..0] ports from PLL 12.
VCCA_PLL5
Analog power for PLL 5. You must connect this pin to 1.2 V, even if the PLL is not
used.
GNDA_PLL5
Analog ground for PLL 5. You can connect this pin to the GND plane on the board.
VCCA_PLL6
Analog power for PLL 6. You must connect this pin to 1.2 V, even if the PLL is not
used.
GNDA_PLL6
Analog ground for PLL 6. You can connect this pin to the GND plane on the board.
VCCA_PLL11
Analog power for PLL 11. You must connect this pin to 1.2 V, even if the PLL is not
used.
GNDA_PLL11
Analog ground for PLL 11. You can connect this pin to the GND plane on the
board.
VCCA_PLL12
Analog power for PLL 12. You must connect this pin to 1.2 V, even if the PLL is not
used.
GNDA_PLL12
Analog ground for PLL 12. You can connect this pin to the GND plane on the
board.
VCCD_PLL
Digital power for PLLs. You must connect this pin to 1.2 V, even if the PLL is not
used.
VCC_PLL5_OUT
External clock output VCCIO power for PLL5_OUT0p, PLL5_OUT0n,
PLL5_OUT1p, PLL5_OUT1n, PLL5_OUT2p, and PLL5_OUT2n outputs from
PLL 5.
VCC_PLL6_OUT
External clock output VCCIO power for PLL6_OUT0p, PLL6_OUT0n,
PLL6_OUT1p, PLL6_OUT1n and PLL6_OUT2p, PLL6_OUT2n outputs from
PLL 6.
VCC_PLL11_OUT
External clock output VCCIO power for PLL11_OUT0p, PLL11_OUT0n,
PLL11_OUT1p, PLL11_OUT1n and PLL11_OUT2p, PLL11_OUT2n outputs
from PLL 11.
1–14
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Table 1–7. Stratix II and Stratix II GX Enhanced PLL Pins (Part 3 of 3)
Pin
Note (1)
Description
External clock output VCCIO power for PLL12_OUT0p, PLL12_OUT0n,
PLL12_OUT1p, PLL12_OUT1n and PLL12_OUT2p, PLL12_OUT2n outputs
from PLL 12.
VCC_PLL12_OUT
Note to Table 1–7:
(1)
The negative leg pins (CLKn, PLL_FBn, and PLL_OUTn) are only required with differential signaling.
Fast PLLs
Stratix II devices contain up to eight fast PLLs and Stratix II GX devices
contain up to four fast PLLs. Fast PLLs have high-speed differential I/O
interface capability along with general-purpose features.
Fast PLL Hardware Overview
Figure 1–7 shows a diagram of the fast PLL.
Figure 1–7. Stratix II and Stratix II GX Fast PLL Block Diagram
Global or
regional clock (2)
Clock (1)
Switchover
Circuitry
VCO Phase Selection
Selectable at each PLL
Output Port
Phase
Frequency
Detector
diffioclk0 (3)
4
loaden0 (4)
÷c0
(5)
Clock
Input
Post-Scale
Counters
÷n
PFD
Charge
Pump
Loop
Filter
VCO
÷k
diffioclk1 (3)
8
loaden1 (4)
÷c1
4
Global clocks
÷c2
4
Global or
regional clock (2)
8
Regional clocks
÷c3
÷m
Shaded Portions of the
PLL are Reconfigurable
8
to DPA block
Notes to Figure 1–7:
(1)
(2)
(3)
(4)
(5)
Stratix II and Stratix II GX fast PLLs only support manual clock switchover.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix II devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a high-speed differential I/O support SERDES control signal.
If the design enables this ÷2 counter, then the device can use a VCO frequency range of 150 to 520 MHz.
Altera Corporation
July 2009
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Stratix II Device Handbook, Volume 2
Fast PLLs
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for
source-synchronous transmitters or for general-purpose external clocks.
There are no dedicated external clock output pins. The fast PLL global or
regional outputs can drive any I/O pin as an external clock output pin.
The I/O standards supported by any particular bank determines what
standards are possible for an external clock output driven by the fast PLL
in that bank.
f
For more information, see the Selectable I/O Standards in Stratix II and
Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device
Handbook (or the Stratix II Device Handbook).
Fast PLL Software Overview
Stratix II and Stratix II GX fast PLLs are enabled in the Quartus II
software by using the altpll megafunction. Figure 1–8 shows the
available ports (as they are named in the Quartus II altpll
megafunction) of the Stratix II or Stratix II GX fast PLL.
Figure 1–8. Stratix II and Stratix II GX Fast PLL Ports and Physical Destinations
Physical Pin
inclk0 (1)
C[3..0]
inclk1 (1)
Signal Driven by Internal Logic
Signal Driven to Internal Logic
pllena (2)
Internal Clock Signal
locked
areset
pfdena
scanclk
scandata
scanwrite
scandataout
scandone
scanread
Notes to Figure 1–8:
(1)
(2)
This input pin is either single-ended or differential.
This input pin is shared by all enhanced and fast PLLs.
Tables 1–8 and 1–9 show the description of all fast PLL ports.
Table 1–8. Fast PLL Input Signals (Part 1 of 2)
Name
Description
Source
Destination
inclk0
Primary clock input to the fast PLL.
Pin or another PLL
n counter
inclk1
Secondary clock input to the fast PLL.
Pin or another PLL
n counter
1–16
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PLLs in Stratix II and Stratix II GX Devices
Table 1–8. Fast PLL Input Signals (Part 2 of 2)
Name
Description
Source
Pin
Destination
pllena
Enable pin for enabling or disabling all or a set
of PLLs. Active high.
PLL control signal
clkswitch
Switch-over signal used to initiate external clock Logic array
switch-over control. Active high.
Reconfiguration circuit
areset
Enables the up/down outputs from the
phase-frequency detector. Active high.
Logic array
PLL control signal
pfdena
Enables the up/down outputs from the
phase-frequency detector. Active high.
Logic array
PFD
scanclk
Serial clock signal for the real-time PLL control
feature.
Logic array
Reconfiguration circuit
scandata
Serial input data stream for the real-time PLL
control feature.
Logic array
Reconfiguration circuit
scanwrite
Enables writing the data in the scan chain into
the PLL Active high.
Logic array
Reconfiguration circuit
scanread
Enables scan data to be written into the scan
chain Active high.
Logic array
Reconfiguration circuit
Table 1–9. Fast PLL Output Signals
Name
Description
Source
Destination
c[3..0]
PLL outputs driving regional or global clock.
PLL counter
Internal clock
locked
Lock or gated lock output from lock detect circuit. Active
high.
PLL lock detect
Logic array
scandataout
Output of the last shift register in the scan chain.
PLL scan chain
Logic array
scandone
Signal indicating when the PLL has completed
reconfiguration. 1 to 0 transition indicates the PLL has
been reconfigured.
PLL scan chain
Logic array
Altera Corporation
July 2009
1–17
Stratix II Device Handbook, Volume 2
Fast PLLs
Fast PLL Pins
Table 1–10 shows the I/O standards supported by the fast PLL input
pins.
Table 1–10. I/O Standards Supported for Stratix II and Stratix II GX Fast PLL
Pins
I/O Standard
INCLK
LVTTL
v
LVCMOS
v
2.5 V
v
1.8 V
v
1.5 V
v
3.3-V PCI
3.3-V PCI-X
SSTL-2 Class I
v
SSTL-2 Class II
v
SSTL-18 Class I
v
SSTL-18 Class II
v
1.8-V HSTL Class I
v
1.8-V HSTL Class II
v
1.5-V HSTL Class I
v
1.5-V HSTL Class II
v
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
LVDS
v
HyperTransport technology
v
Differential LVPECL
1–18
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Table 1–11 shows the physical pins and their purpose for the fast PLLs.
For inclk port connections to pins, see “Clocking” on page 1–62.
Table 1–11. Fast PLL Pins (Part 1 of 2)
Pin
Note (1)
Description
CLK0p/n
Single-ended or differential pins that can drive the inclk port for PLLs 1, 2, 7 or 8.
CLK1p/n
Single-ended or differential pins that can drive the inclk port for PLLs 1, 2, 7 or 8.
CLK2p/n
Single-ended or differential pins that can drive the inclk port for PLLs 1, 2, 7 or 8.
CLK3p/n
Single-ended or differential pins that can drive the inclk port for PLLs 1, 2, 7 or 8.
CLK8p/n
Single-ended or differential pins that can drive the inclk port for PLLs 3, 4, 9 or 10.
CLK9p/n
Single-ended or differential pins that can drive the inclk port for PLLs 3, 4, 9 or 10.
CLK10p/n
Single-ended or differential pins that can drive the inclk port for PLLs 3, 4, 9 or 10.
CLK11p/n
Single-ended or differential pins that can drive the inclk port for PLLs 3, 4, 9 or 10.
FPLL7CLKp/n
Single-ended or differential pins that can drive the inclk port for PLL 7.
FPLL8CLKp/n
Single-ended or differential pins that can drive the inclk port for PLL 8.
FPLL9CLKp/n
Single-ended or differential pins that can drive the inclk port for PLL 9.
FPLL10CLKp/n
Single-ended or differential pins that can drive the inclk port for PLL 10.
PLL_ENA
Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do not use
this pin, connect it to GND.
VCCD_PLL
Digital power for PLLs. You must connect this pin to 1.2 V, even if the PLL is not used.
VCCA_PLL1
Analog power for PLL 1. You must connect this pin to 1.2 V, even if the PLL is not used.
GNDA_PLL1
Analog ground for PLL 1. Your can connect this pin to the GND plane on the board.
VCCA_PLL2
Analog power for PLL 2. You must connect this pin to 1.2 V, even if the PLL is not used.
GNDA_PLL2
Analog ground for PLL 2. You can connect this pin to the GND plane on the board.
VCCA_PLL3
Analog power for PLL 3. You must connect this pin to 1.2 V, even if the PLL is not used.
GNDA_PLL3
Analog ground for PLL 3. You can connect this pin to the GND plane on the board.
VCCA_PLL4
Analog power for PLL 4. You must connect this pin to 1.2 V, even if the PLL is not used.
GNDA_PLL4
Analog ground for PLL 4. You can connect this pin to the GND plane on the board.
GNDA_PLL7
Analog ground for PLL 7. You can connect this pin to the GND plane on the board.
VCCA_PLL8
Analog power for PLL 8. You must connect this pin to 1.2 V, even if the PLL is not used.
GNDA_PLL8
Analog ground for PLL 8. You can connect this pin to the GND plane on the board.
VCCA_PLL9
Analog power for PLL 9. You must connect this pin to 1.2 V, even if the PLL is not used.
GNDA_PLL9
Analog ground for PLL 9. You can connect this pin to the GND plane on the board.
VCCA_PLL10
Analog power for PLL 10. You must connect this pin to 1.2 V, even if the PLL is not used.
Altera Corporation
July 2009
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Stratix II Device Handbook, Volume 2
Clock Feedback Modes
Table 1–11. Fast PLL Pins (Part 2 of 2)
Note (1)
Pin
GNDA_PLL10
Description
Analog ground for PLL 10. You can connect this pin to the GND plane on the board.
Note to Table 1–11:
(1)
The negative leg pins (CLKn and FPLL_CLKn) are only required with differential signaling.
Clock Feedback
Modes
Stratix II and Stratix II GX PLLs support up to five different clock
feedback modes. Each mode allows clock multiplication and division,
phase shifting, and programmable duty cycle. Each PLL must be driven
by one of its own dedicated clock input pins for proper clock
compensation. The clock input pin connections for each PLL are listed in
Table 1–20 on page 1–70.
Table 1–12 shows which modes are supported by which PLL type.
Table 1–12. Clock Feedback Mode Availability
Mode Available in
Clock Feedback Mode
Enhanced PLLs
Fast PLLs
Source synchronous mode
Yes
Yes
No compensation mode
Yes
Yes
Normal mode
Yes
Yes
Zero delay buffer mode
Yes
No
External feedback mode
Yes
No
Source-Synchronous Mode
If data and clock arrive at the same time at the input pins, they are
guaranteed to keep the same phase relationship at the clock and data
ports of any IOE input register. Figure 1–9 shows an example waveform
of the clock and data in this mode. This mode is recommended for sourcesynchronous data transfers. Data and clock signals at the IOE experience
similar buffer delays as long as the same I/O standard is used.
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PLLs in Stratix II and Stratix II GX Devices
Figure 1–9. Phase Relationship Between Clock and Data in
Source-Synchronous Mode
Data pin
inclk
Data at register
Clock at register
In source-synchronous mode, enhanced PLLs compensate for clock delay
to the top and bottom IO registers and fast PLLs compensate for clock
delay to the side IO registers. While implementing source-synchronous
receivers in these IO banks, use the corresponding PLL type for best
matching between clock and data delays (from input pins to register
ports).
1
Set the input pin to the register delay chain within the IOE to
zero in the Quartus II software for all data pins clocked by a
source-synchronous mode PLL.
No Compensation Mode
In this mode, the PLL does not compensate for any clock networks. This
provides better jitter performance because the clock feedback into the
PFD does not pass through as much circuitry. Both the PLL internal and
external clock outputs are phase shifted with respect to the PLL clock
input. Figure 1–10 shows an example waveform of the PLL clocks’ phase
relationship in this mode.
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July 2009
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Clock Feedback Modes
Figure 1–10. Phase Relationship between PLL Clocks in No Compensation
Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port (1), (2)
External PLL Clock Outputs (2)
Notes to Figure 1–10.
(1)
(2)
Internal clocks fed by the PLL are phase-aligned to each other.
The PLL clock outputs can lead or lag the PLL input clocks.
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin.
The external clock output pin will have a phase delay relative to the clock
input pin if connected in this mode. In normal mode, the delay
introduced by the GCLK or RCLK network is fully compensated.
Figure 1–11 shows an example waveform of the PLL clocks’ phase
relationship in this mode.
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Figure 1–11. Phase Relationship Between PLL Clocks in Normal Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port
External PLL Clock Outputs (1)
Note to Figure 1–11:
(1)
The external clock output can lead or lag the PLL internal clock signals.
Zero Delay Buffer Mode
In the zero delay buffer mode, the external clock output pin is
phase-aligned with the clock input pin for zero delay through the device.
Figure 1–12 shows an example waveform of the PLL clocks’ phase
relationship in this mode. When using this mode, Altera requires that you
use the same I/O standard on the input clock, and output clocks. When
using single-ended I/O standards, the inclk port of the PLL must be fed
by the dedicated CLKp input pin.
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July 2009
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Clock Feedback Modes
Figure 1–12. Phase Relationship Between PLL Clocks in Zero Delay Buffer
Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port
External PLL
Clock Outputs (1)
Note to Figure 1–12:
(1)
The internal PLL clock output can lead or lag the external PLL clock outputs.
External Feedback Mode
In the external feedback mode, the external feedback input pin, fbin, is
phase-aligned with the clock input pin, (see Figure 1–13). Aligning these
clocks allows you to remove clock delay and skew between devices. This
mode is possible on all enhanced PLLs. PLLs 5, 6, 11, and 12 support
feedback for one of the dedicated external outputs, either one
single-ended or one differential pair. In this mode, one C counter feeds
back to the PLL fbin input, becoming part of the feedback loop. In this
mode, you will be using one of the dedicated external clock outputs (two
if a differential I/O standard is used) as the PLL fbin input pin. When
using this mode, Altera requires that you use the same I/O standard on
the input clock, feedback input, and output clocks. When using
single-ended I/O standards, the inclk port of the PLL must be fed by the
dedicated CLKp input pin.
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Figure 1–13. Phase Relationship Between PLL Clocks in External Feedback
Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at
the Register
Clock Port (1)
External PLL
Clock Outputs (1)
fBIN Clock Input
Note to Figure 1–13:
(1)
Hardware
Features
The PLL clock outputs can lead or lag the fBIN clock input.
Stratix II and Stratix II GX PLLs support a number of features for
general-purpose clock management. This section discusses clock
multiplication and division implementation, phase-shifting
implementations and programmable duty cycles. Table 1–13 shows
which feature is available in which type of Stratix II or Stratix II GX PLL.
Table 1–13. Stratix II and Stratix II GX PLL Hardware Features (Part 1 of 2)
Availability
Hardware Features
Enhanced PLL
Fast PLL
Clock multiplication and division
m (n × post-scale counter)
m (n × post-scale counter)
m counter value
Ranges from 1 through 512
Ranges from 1 through 32
n counter value
Post-scale counter values
Altera Corporation
July 2009
Ranges from 1 through 512
Ranges from 1 through 4
Ranges from 1 through 512 (1)
Ranges from 1 through 32 (2)
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Table 1–13. Stratix II and Stratix II GX PLL Hardware Features (Part 2 of 2)
Availability
Hardware Features
Phase shift
Programmable duty cycle
Enhanced PLL
Fast PLL
Down to 125-ps increments (3)
Down to 125-ps increments (3)
Yes
Yes
Notes to Table 1–13:
(1)
(2)
(3)
Post-scale counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using
a non-50% duty cycle, the post-scale counters range from 1 through 256.
Post-scale counters range from 1 through 32 if the output clock uses a 50% duty cycle. For any output clocks using
a non-50% duty cycle, the post-scale counters range from 1 through 16.
The smallest phase shift is determined by the VCO period divided by 8. For degree increments, the Stratix II device
can shift all output frequencies in increments of at least 45. Smaller degree increments are possible depending on
the frequency and divide parameters.
Clock Multiplication and Division
Each Stratix II PLL provides clock synthesis for PLL output ports using
m/(n × post-scale counter) scaling factors. The input clock is divided by a
pre-scale factor, n, and is then multiplied by the m feedback factor. The
control loop drives the VCO to match fIN (m/n). Each output port has a
unique post-scale counter that divides down the high-frequency VCO.
For multiple PLL outputs with different frequencies, the VCO is set to the
least common multiple of the output frequencies that meets its frequency
specifications. For example, if output frequencies required from one PLL
are 33 and 66 MHz, then the Quartus II software sets the VCO to 660 MHz
(the least common multiple of 33 and 66 MHz within the VCO range).
Then, the post-scale counters scale down the VCO frequency for each
output port.
There is one pre-scale counter, n, and one multiply counter, m, per PLL,
with a range of 1 to 512 for both m and n in enhanced PLLs. For fast PLLs,
m ranges from 1 to 32 while n ranges from 1 to 4. There are six generic
post-scale counters in enhanced PLLs that can feed regional clocks, global
clocks, or external clock outputs, all ranging from 1 to 512 with a 50%
duty cycle setting for each PLL. The post-scale counters range from 1 to
256 with any non-50% duty cycle setting. In fast PLLs, there are four
post-scale counters (C0, C1, C2, C3) for the regional and global clock
output ports. All post-scale counters range from 1 to 32 with a 50% duty
cycle setting. For non-50% duty cycle clock outputs, the post-scale
counters range from 1 to 16. If the design uses a high-speed I/O interface,
you can connect the dedicated dffioclk clock output port to allow the
high-speed VCO frequency to drive the serializer/deserializer (SERDES).
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The Quartus II software automatically chooses the appropriate scaling
factors according to the input frequency, multiplication, and division
values entered into the altpll megafunction.
Phase-Shift Implementation
Phase shift is used to implement a robust solution for clock delays in
Stratix II and Stratix II GX devices. Phase shift is implemented by using a
combination of the VCO phase output and the counter starting time. The
VCO phase output and counter starting time is the most accurate method
of inserting delays, since it is purely based on counter settings, which are
independent of process, voltage, and temperature.
1
Stratix II and Stratix II GX PLLs do not support programmable
delay elements because these delay elements require
considerable area on the die and are sensitive to process,
voltage, and temperature.
You can phase shift the output clocks from the Stratix II or Stratix II GX
enhanced PLL in either:
■
■
Fine resolution using VCO phase taps
Coarse resolution using counter starting time
The VCO phase tap and counter starting time is implemented by allowing
any of the output counters (C[5..0] or m) to use any of the eight phases
of the VCO as the reference clock. This allows you to adjust the delay time
with a fine resolution. The minimum delay time that you can insert using
this method is defined by:
Φfine =
N
1
1
T =
=
8fVCO 8MfREF
8 VCO
where fREF is input reference clock frequency.
For example, if fREF is 100 MHz, n is 1, and m is 8, then fVCO is 800 MHz
and fINE equals 156.25 ps. This phase shift is defined by the PLL
operating frequency, which is governed by the reference clock frequency
and the counter settings.
You can also delay the start of the counters for a predetermined number
of counter clocks. You can express phase shift as:
Φcoarse =
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July 2009
C − 1 (C − 1)N
=
fVco
MfREF
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Hardware Features
where C is the count value set for the counter delay time, (this is the initial
setting in the PLL usage section of the compilation report in the
Quartus II software). If the initial value is 1, C – 1 = 0° phase shift.
Figure 1–14 shows an example of phase shift insertion using the fine
resolution using VCO phase taps method. The eight phases from the VCO
are shown and labeled for reference. For this example, CLK0 is based off
the 0 phase from the VCO and has the C value for the counter set to one.
The CLK1 signal is divided by four, two VCO clocks for high time and two
VCO clocks for low time. CLK1 is based off the 135 phase tap from the
VCO and also has the C value for the counter set to one. The CLK1 signal
is also divided by 4. In this case, the two clocks are offset by 3 FINE. CLK2
is based off the 0phase from the VCO but has the C value for the counter
set to three. This creates a delay of 2 COARSE, (two complete VCO
periods).

Figure 1–14. Delay Insertion Using VCO Phase Output and Counter Delay Time
1/8 tVCO
tVCO
0
45
90
135
180
225
270
315
CLK0
td0-1
CLK1
td0-2
CLK2
You can use the coarse and fine phase shifts as described above to
implement clock delays in Stratix II and Stratix II GX devices. The
phase-shift parameters are set in the Quartus II software.
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PLLs in Stratix II and Stratix II GX Devices
Programmable Duty Cycle
The programmable duty cycle allows enhanced and fast PLLs to generate
clock outputs with a variable duty cycle. This feature is supported on
each enhanced and fast PLL post-scale counter C[]. The duty cycle
setting is achieved by a low and high time count setting for the post-scale
counters. The Quartus II software uses the frequency input and the
required multiply or divide rate to determine the duty cycle choices. The
post-scale counter value determines the precision of the duty cycle. The
precision is defined by 50% divided by the post-scale counter value. The
closest value to 100% is not achievable for a given counter value. For
example, if the C0 counter is ten, then steps of 5% are possible for duty
cycle choices between 5 to 90%.
If the device uses external feedback, you must set the duty cycle for the
counter driving the fbin pin to 50%. Combining the programmable duty
cycle with programmable phase shift allows the generation of precise
non-overlapping clocks.
Advanced Clear and Enable Control
There are several control signals for clearing and enabling PLLs and their
outputs. You can use these signals to control PLL resynchronization and
gate PLL output clocks for low-power applications.
Enhanced Lock Detect Circuit
The lock output indicates that the PLL has locked onto the reference clock.
Without any additional circuitry, the lock signal may toggle as the PLL
begins tracking the reference clock. You may need to gate the lock signal
for use as a system control. Either a gated lock signal or an ungated lock
signal from the locked port can drive the logic array or an output pin. The
Stratix II and Stratix II GX enhanced and fast PLLs include a
programmable counter that holds the lock signal low for a user-selected
number of input clock transitions. This allows the PLL to lock before
enabling the lock signal. You can use the Quartus II software to set the
20-bit counter value.
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Figure 1–15 shows the timing waveform for the lock and gated lock
signals.
Figure 1–15. Timing Waveform for Lock and Gated Lock Signals
PLL_ENA
Reference Clock
Feedback Clock
Lock
Filter Counter
Reaches
Value Count
Gated Lock
The device resets and enables both the counter and the PLL
simultaneously when the pllena signal is asserted or the areset signal
is de-asserted. Enhanced PLLs and fast PLLs support this feature. To
ensure correct circuit operation, and to ensure that the output clocks have
the correct phase relationship with respect to the input clock, Altera
recommends that the input clock be running before the Stratix II device is
finished configuring.
PLL_ENA
The PLL_ENA pin is a dedicated pin that enables or disables all PLLs on
the Stratix II or Stratix II GX device. When the PLL_ENA pin is low, the
clock output ports are driven low and all the PLLs go out of lock. When
the PLL_ENA pin goes high again, the PLLs relock and resynchronize to
the input clocks. You can choose which PLLs are controlled by the
pllena signal by connecting the pllena input port of the altpll
megafunction to the common PLL_ENA input pin.
Also, whenever the PLL loses lock for any reason (be it excessive inclk
jitter, clock switchover, PLL reconfiguration, power supply noise, etc.),
the PLL must be reset with the areset signal to guarantee correct phase
relationship between the PLL output clocks. If the phase relationship
between the input clock versus output clock, and between different
output clocks from the PLL is not important in your design, the PLL need
not be reset.
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The level of the VCCSEL pin selects the PLL_ENA input buffer power.
Therefore, if VCCSEL is high, the PLL_ENA pin’s 1.8/1.5-V input buffer is
powered by VCCIO of the bank that PLL_ENA resides in. If VCCSEL is low
(GND), the PLL_ENA pin’s 3.3/2.5-V input buffer is powered by VCCPD.
f
For more information about the VCCSEL pin, refer to the Configuring
Stratix II and Stratix II GX Devices chapter in volume 2 of the Stratix II GX
Device Handbook (or the Stratix II Device Handbook).
pfdena
The pfdena signals control the phase frequency detector (PFD) output
with a programmable gate. If you disable the PFD, the VCO operates at
its last set value of control voltage and frequency with some long-term
drift to a lower frequency. The system continues running when the PLL
goes out of lock or the input clock is disabled. By maintaining the last
locked frequency, the system has time to store its current settings before
shutting down. You can either use your own control signal or clkloss
or gated locked status signals, to trigger pfdena.
areset
The areset signal is the reset or resynchronization input for each PLL.
The device input pins or internal logic can drive these input signals.
When driven high, the PLL counters reset, clearing the PLL output and
placing the PLL out of lock. The VCO is set back to its nominal setting
(~700 MHz). When driven low again, the PLL will resynchronize to its
input as it relocks. If the target VCO frequency is below this nominal
frequency, then the output frequency starts at a higher value than desired
as the PLL locks.
The areset signal should be asserted every time the PLL loses lock to
guarantee correct phase relationship between the PLL input clock and
output clocks. Users should include the areset signal in designs if any
of the following conditions are true:
■
■
■
1
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July 2009
PLL reconfiguration or clock switchover enabled in the design.
Phase relationships between the PLL input clock and output clocks
need to be maintained after a loss of lock condition.
If the input clock to the PLL is not toggling or is unstable upon power
up, assert the areset signal after the input clock is toggling, making
sure to stay within the input jitter specification.
Altera recommends that you use the areset and locked
signals in your designs to control and observe the status of your
PLL.
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clkena
If the system cannot tolerate the higher output frequencies when using
pfdena higher value, the clkena signals can disable the output clocks
until the PLL locks. The clkena signals control the regional, global, and
external clock outputs. The clkena signals are registered on the falling
edge of the counter output clock to enable or disable the clock without
glitches. See Figure 1–56 in the “Clock Control Block” section on
page 1–86 of this document for more information about the clkena
signals.
Advanced
Features
Stratix II and Stratix II GX PLLs offer a variety of advanced features, such
as counter cascading, clock switchover, PLL reconfiguration,
reconfigurable bandwidth, and spread-spectrum clocking. Table 1–14
shows which advanced features are available in which type of Stratix II or
Stratix II GX PLL.
Table 1–14. Stratix II and Stratix II GX PLL Advanced Features
Availability
Advanced Feature
Enhanced PLLs
Fast PLLs (1)
Counter cascading
v
Clock switchover
v
v
PLL reconfiguration
v
v
Reconfigurable bandwidth
v
v
Spread-spectrum clocking
v
Note to Table 1–14:
(1)
Stratix II and Stratix II GX fast PLLs only support manual clock switchover, not
automatic clock switchover.
Counter Cascading
The Stratix II and Stratix II GX enhanced PLL supports counter cascading
to create post-scale counters larger than 512. This is implemented by
feeding the output of one counter into the input of the next counter in a
cascade chain, as shown in Figure 1–16.
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Figure 1–16. Counter Cascading
VCO Output
VCO Output
VCO Output
C0
C1
C2
VCO Output
C3
VCO Output
C4
VCO Output
C5
When cascading counters to implement a larger division of the
high-frequency VCO clock, the cascaded counters behave as one counter
with the product of the individual counter settings. For example, if C0 = 4
and C1 = 2, then the cascaded value is C0 × C1 = 8.
1
The Stratix II and Stratix II GX fast PLLs does not support
counter cascading.
Counter cascading is set in the configuration file, meaning they can not be
cascaded using PLL reconfiguration.
Clock Switchover
The clock switchover feature allows the PLL to switch between two
reference input clocks. Use this feature for clock redundancy or for a dual
clock domain application such as in a system that turns on the redundant
clock if the primary clock stops running. The design can perform clock
switchover automatically, when the clock is no longer toggling, or based
on a user control signal, clkswitch.
1
Enhanced PLLs support both automatic and manual switchover,
while fast PLLs only support manual switchover.
Automatic Clock Switchover
Stratix II and Stratix II GX device PLLs support a fully configurable clock
switchover capability. Figure 1–17 shows the block diagram of the
switch-over circuit built into the enhanced PLL. When the primary clock
signal is not present, the clock sense block automatically switches from
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Advanced Features
the primary to the secondary clock for PLL reference. The design sends
out the clk0_bad, clk1_bad, and the clk_loss signals from the PLL
to implement a custom switchover circuit.
Figure 1–17. Automatic Clock Switchover Circuit Block Diagram
clk0_bad
clksw
clk0_bad
Activeclock
clkloss
Switch-Over
State
Machine
Clock
Sense
clkswitch
Provides manual
switchover support.
inclk0
n Counter
inclk1
muxout
PFD
refclk
fbclk
There are two possible ways to use the clock switchover feature.
■
Use the switchover circuitry for switching from a primary to
secondary input of the same frequency. For example, in applications
that require a redundant clock with the same frequency as the
primary clock, the switchover state machine generates a signal that
controls the multiplexer select input shown on the bottom of
Figure 1–17. In this case, the secondary clock becomes the reference
clock for the PLL. This automatic switchover feature only works for
switching from the primary to secondary clock.
■
Use the CLKSWITCH input for user- or system-controlled switch
conditions. This is possible for same-frequency switchover or to
switch between inputs of different frequencies. For example, if
inclk0 is 66 MHz and inclk1 is 100 MHz, you must control the
switchover because the automatic clock-sense circuitry cannot
monitor primary and secondary clock frequencies with a frequency
difference of more than 20%. This feature is useful when clock
sources can originate from multiple cards on the backplane,
requiring a system-controlled switchover between frequencies of
operation. You should choose the secondary clock frequency so the
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VCO operates within the recommended range of 500 to 1,000 MHz.
You should also set the m and n counters accordingly to keep the
VCO operating frequency in the recommended range.
Figure 1–18 shows an example waveform of the switchover feature when
using the automatic clkloss detection. Here, the inclk0 signal gets
stuck low. After the inclk0 signal is stuck at low for approximately two
clock cycles, the clock sense circuitry drives the clk0_bad signal high.
Also, because the reference clock signal is not toggling, the clk_loss
signal goes low, indicating a switch condition. Then, the switchover state
machine controls the multiplexer through the clksw signal to switch to
the secondary clock.
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July 2009
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Figure 1–18. Automatic Switchover Upon Clock Loss Detection
inclk0
inclk1
(1)
(2)
muxout
refclk
fbclk
clk0bad
(3)
(4)
clk1bad
lock
activeclock
clkloss
PLL Clock
Output
Notes to Figure 1–18:
(1)
(2)
(3)
(4)
The number of clock edges before allowing switchover is determined by the counter setting.
Switchover is enabled on the falling edge of INCLK1.
The rising edge of FBCLK causes the VCO frequency to decrease.
The rising edge of REFCLK starts the PLL lock process again, and the VCO frequency increases.
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The switch-over state machine has two counters that count the edges of
the primary and the secondary clocks; counter0 counts the number of
inclk0 edges and counter1 counts the number of inclk1 edges. The
counters get reset to zero when the count values reach 1, 1; 1, 2; 2, 1; or 2,
2 for inclock0 and inclock1, respectively. For example, if counter0
counts two edges, its count is set to two and if counter1 counts two
edges before the counter0 sees another edge, they are both reset to 0. If
for some reason one of the counters counts to three, it means the other
clock missed an edge. The clkbad0 or clkbad1 signal goes high, and
the switchover circuitry signals a switch condition. See Figure 1–19.
Figure 1–19. Clock-Edge Detection for Switchover
Reset
Count of three on
single clock indicates
other missed edge.
inclk0
inclk1
clkbad0
Manual Override
When using automatic switchover, you can switch input clocks by using
the manual override feature with the clkswitch input.
1
The manual override feature available in automatic clock
switchover is different from manual clock switchover.
Figure 1–20 shows an example of a waveform illustrating the switchover
feature when controlled by clkswitch. In this case, both clock sources
are functional and inclk0 is selected as the primary clock. clkswitch
goes high, which starts the switchover sequence. On the falling edge of
inclk0, the counter’s reference clock, muxout, is gated off to prevent
any clock glitching. On the falling edge of inclk1, the reference clock
multiplexer switches from inclk0 to inclk1 as the PLL reference and
the activeclock signal changes to indicate which clock is selected as
primary and which is secondary.
The clkloss signal mirrors the clkswitch signal and activeclock
mirrors clksw in this mode. Since both clocks are still functional during
the manual switch, neither clk_bad signal goes high. Since the
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Advanced Features
switchover circuit is edge-sensitive, the falling edge of the clkswitch
signal does not cause the circuit to switch back from inclk1 to inclk0.
When the clkswitch signal goes high again, the process repeats.
clkswitch and automatic switch only work if the clock being switched
to is available. If the clock is not available, the state machine waits until
the clock is available.
Figure 1–20. Clock Switchover Using the CLKSWITCH Control
Note (1)
inclk0
inclk1
muxout
clkswitch
activeclock
clkloss
clk0bad
clk1bad
Note to Figure 1–20:
(1)
Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate a manual clock
switchover event. Failing to meet this requirement causes the clock switchover to not function properly.
Figure 1–21 shows a simulation of using switchover for two different
reference frequencies. In this example simulation, the reference clock is
either 100 or 66 MHz. The PLL begins with fIN = 100 MHz and is allowed
to lock. At 20 s, the clock is switched to the secondary clock, which is at
66 MHz.
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Figure 1–21. Switchover Simulation
Note (1)
10
9
8
7
6
PLL Output
5
Frequency (x10 MHz)
4
3
2
1
0
0
5
10
15
20
25
30
35
40
Time (μs)
Note to Figure 1–21:
(1)
This simulation was performed under the following conditions: the n counter is set to 2, the m counter is set to 16,
and the output counter is set to 8. Therefore, the VCO operates at 800 MHz for the 100-MHz input references and at
528 MHz for the 66-MHz reference input.
Lock Signal-Based Switchover
The lock circuitry can initiate the automatic switchover. This is useful for
cases where the input clock is still clocking, but its characteristics have
changed so that the PLL is not locked to it. The switchover enable is based
on both the gated and ungated lock signals. If the ungated lock is low, the
switchover is not enabled until the gated lock has reached its terminal
count. You must activate the switchover enable if the gated lock is high,
but the ungated lock goes low. The switchover timing for this mode is
similar to the waveform shown in Figure 1–20 for clkswitch control,
except the switchover enable replaces clkswitch. Figure 1–17 shows
the switchover enable circuit when controlled by lock and gated lock.
Figure 1–22. Switchover Enable Circuit
Lock
Gated Lock
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July 2009
Switchover
Enable
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Advanced Features
Manual Clock Switchover
Stratix II and Stratix II GX enhanced and fast PLLs support manual
switchover, where the clkswitch signal controls whether inclk0 or
inclk1 is the input clock to the PLL. If clkswitch is low, then inclk0
is selected; if clkswitch is high, then inclk1 is selected. Figure 1–23
shows the block diagram of the manual switchover circuit in fast PLLs.
The block diagram of the manual switchover circuit in enhanced PLLs is
shown in Figure 1–23.
Figure 1–23. Manual Clock Switchover Circuitry in Fast PLLs
clkswitch
inclk0
n Counter
PFD
inclk1
muxout
refclk
fbclk
Figure 1–24 shows an example of a waveform illustrating the switchover
feature when controlled by clkswitch. In this case, both clock sources
are functional and inclk0 is selected as the primary clock. clkswitch
goes high, which starts the switch-over sequence. On the falling edge of
inclk0, the counter’s reference clock, muxout, is gated off to prevent
any clock glitching. On the rising edge of inclk1, the reference clock
multiplex switches from inclk0 to inclk1 as the PLL reference. When
the clkswitch signal goes low, the process repeats, causing the circuit to
switch back from inclk1 to inclk0.
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Figure 1–24. Manual Switchover
Note (1)
inclk0
inclk1
muxout
clkswitch
Note to Figure 1–24:
(1)
Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate a manual clock
switchover event. Failing to meet this requirement causes the clock switchover to not function properly.
Software Support
Table 1–15 summarizes the signals used for clock switchover.
Table 1–15. altpll Megafunction Clock Switchover Signals
Port
(Part 1 of 2)
Description
Source
Destination
inclk0
Reference clk0 to the PLL.
I/O pin
Clock switchover circuit
inclk1
Reference clk1 to the PLL.
I/O pin
Clock switchover circuit
clkbad0(1)
Signal indicating that inclk0 is no longer Clock switchover
toggling.
circuit
Logic array
clkbad1(1)
Signal indicating that inclk1 is no longer Clock switchover
toggling.
circuit
Logic array
clkswitch
Switchover signal used to initiate clock
Logic array or I/O pin
switchover asynchronously. When used in
manual switchover, clkswitch is used as a
select signal between inclk0 and inclk1
clswitch = 0 inclk0 is selected
and vice versa.
Clock switchover circuit
clkloss(1)
Signal indicating that the switchover
circuit detected a switch condition.
Clock switchover
circuit
Logic array
locked
Signal indicating that the PLL has lost
lock.
PLL
Clock switchover circuit
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Advanced Features
Table 1–15. altpll Megafunction Clock Switchover Signals
Port
(Part 2 of 2)
Description
activeclock(1)
Signal to indicate which clock (0 =
PLL
inclk0, 1= inclk1) is driving the PLL.
Source
Destination
Logic array
Note for Table 1–15:
(1)
These ports are only available for enhanced PLLs and in auto mode and when using automatic switchover.
All the switchover ports shown in Table 1–15 are supported in the
altpll megafunction in the Quartus II software. The altpll
megafunction supports two methods for clock switchover:
■
■
When selecting an enhanced PLL, you can enable both the automatic
and the manual switchover, making all the clock switchover ports
available.
When selecting a fast PLL, you can use only enable the manual clock
switchover option to select between inclk0 or inclk1. The
clkloss, activeclock and the clkbad0, and clkbad1 signals
are not available when manual switchover is selected.
If the primary and secondary clock frequencies are different, the
Quartus II software selects the proper parameters to keep the VCO within
the recommended frequency range.
f
For more information about PLL software support in the Quartus II
software, see the altpll Megafunction User Guide.
Guidelines
Use the following guidelines to design with clock switchover in PLLs.
■
When using automatic switchover, the clkswitch signal has a
minimum pulse width based on the two reference clock periods. The
CLKSWITCH pulse width must be greater than or equal to the period
of the current reference clock (tfrom_clk) multiplied by two plus the
rounded-up version of the ratio of the two reference clock periods.
For example, if tto_clk is equal to tfrom_clk, then the CLKSWITCH pulse
width should be at least three times the period of the clock pulse.
tCLKSWITCHCHmin  tfrom_clk  [2 + intround_up (tto_clk tfrom_clk)]
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■
■
■
■
■
Applications that require a clock switchover feature and a small
frequency drift should use a low-bandwidth PLL. The
low-bandwidth PLL reacts slower than a high-bandwidth PLL to
reference input clock changes. When the switchover happens, a
low-bandwidth PLL propagates the stopping of the clock to the
output slower than a high-bandwidth PLL. A low-bandwidth PLL
filters out jitter on the reference clock. However, be aware that the
low-bandwidth PLL also increases lock time.
Stratix II and Stratix II GX device PLLs can use both the automatic
clock switchover and the clkswitch input simultaneously.
Therefore, the switchover circuitry can automatically switch from the
primary to the secondary clock. Once the primary clock stabilizes
again, the clkswitch signal can switch back to the primary clock.
During switchover, the PLL_VCO continues to run and slows down,
generating frequency drift on the PLL outputs. The clkswitch
signal controls switchover with its rising edge only.
If the clock switchover event is glitch-free, after the switch occurs,
there is still a finite resynchronization period to lock onto a new clock
as the VCO ramps up. The exact amount of time it takes for the PLL
to relock is dependent on the PLL configuration. Use the PLL
programmable bandwidth feature to adjust the relock time.
If the phase relationship between the input clock to the PLL and
output clock from the PLL is important in your design, assert
areset for 10ns after performing a clock switchover. Wait for the
locked signal (or gated lock) to go high before re-enabling the output
clocks from the PLL.
Figure 1–25 shows how the VCO frequency gradually decreases
when the primary clock is lost and then increases as the VCO locks
on to the secondary clock. After the VCO locks on to the secondary
clock, some overshoot can occur (an over-frequency condition) in the
VCO frequency.
Figure 1–25. VCO Switchover Operating Frequency
Primary Clock Stops Running
Frequency Overshoot
Switchover Occurs
ΔFvco
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VCO Tracks Secondary Clock
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Reconfigurable Bandwidth
■
■
Reconfigurable
Bandwidth
Disable the system during switchover if it is not tolerant to frequency
variations during the PLL resynchronization period. There are two
ways to disable the system. First, the system may require some time
to stop before switchover occurs. The switchover circuitry includes
an optional five-bit counter to delay when the reference clock is
switched. You have the option to control the time-out setting on this
counter (up to 32 cycles of latency) before the clock source switches.
You can use these cycles for disaster recovery. The clock output
frequency varies slightly during those 32 cycles since the VCO can
still drift without an input clock. Programmable bandwidth can
control the PLL response to limit drift during this 32 cycle period.
A second option available is the ability to use the PFD enable signal
(pfdena) along with user-defined control logic. In this case you can
use clk0_bad and clk1_bad status signals to turn off the PFD so
the VCO maintains its last frequency. You can also use the state
machine to switch over to the secondary clock. Upon re-enabling the
PFD, output clock enable signals (clkena) can disable clock outputs
during the switchover and resynchronization period. Once the lock
indication is stable, the system can re-enable the output clock(s).
Stratix II and Stratix II GX enhanced and fast PLLs provide advanced
control of the PLL bandwidth using the PLL loop’s programmable
characteristics, including loop filter and charge pump.
Background
PLL bandwidth is the measure of the PLL’s ability to track the input clock
and jitter. The closed-loop gain 3-dB frequency in the PLL determines the
PLL bandwidth. The bandwidth is approximately the unity gain point for
open loop PLL response. As Figure 1–26 shows, these points correspond
to approximately the same frequency.
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Figure 1–26. Open- and Closed-Loop Response Bode Plots
Open-Loop Reponse Bode Plot
Increasing the PLL's
bandwidth in effect pushes
the open loop response out.
0 dB
Gain
Frequency
Closed-Loop Reponse Bode Plot
Gain
Frequency
A high-bandwidth PLL provides a fast lock time and tracks jitter on the
reference clock source, passing it through to the PLL output. A
low-bandwidth PLL filters out reference clock, but increases lock time.
Stratix II and Stratix II GX enhanced and fast PLLs allow you to control
the bandwidth over a finite range to customize the PLL characteristics for
a particular application. The programmable bandwidth feature in
Stratix II and Stratix II GX PLLs benefits applications requiring clock
switchover (e.g., TDMA frequency hopping wireless, and redundant
clocking).
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Reconfigurable Bandwidth
The bandwidth and stability of such a system is determined by the charge
pump current, the loop filter resistor value, the high-frequency capacitor
value (in the loop filter), and the m-counter value. You can use the
Quartus II software to control these factors and to set the bandwidth to
the desired value within a given range.
You can set the bandwidth to the appropriate value to balance the need
for jitter filtering and lock time. Figures 1–27 and 1–28 show the output of
a low- and high-bandwidth PLL, respectively, as it locks onto the input
clock.
Figure 1–27. Low-Bandwidth PLL Lock Time
160
155
Lock Time = 8 μs
150
145
Frequency (MHz)
140
135
130
125
120
0
5
10
15
Time (μs)
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Figure 1–28. High-Bandwidth PLL Lock Time
160
155
Lock Time = 4 μs
150
145
Frequency (MHz)
140
135
130
125
120
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Time (μs)
A high-bandwidth PLL can benefit a system that has two cascaded PLLs.
If the first PLL uses spread spectrum (as user-induced jitter), the second
PLL can track the jitter that is feeding it by using a high-bandwidth
setting. A low-bandwidth PLL can, in this case, lose lock due to the
spread-spectrum-induced jitter on the input clock.
A low-bandwidth PLL benefits a system using clock switchover. When
the clock switchover happens, the PLL input temporarily stops. A
low-bandwidth PLL would react more slowly to changes to its input
clock and take longer to drift to a lower frequency (caused by the input
stopping) than a high-bandwidth PLL. Figures 1–29 and 1–30
demonstrate this property. The two plots show the effects of clock
switchover with a low- or high-bandwidth PLL. When the clock
switchover happens, the output of the low-bandwidth PLL (see
Figure 1–29) drifts to a lower frequency more slowly than the
high-bandwidth PLL output (see Figure 1–30).
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5.0
Reconfigurable Bandwidth
Figure 1–29. Effect of Low Bandwidth on Clock Switchover
164
162
160
158
Frequency (MHz)
Input Clock Stops
Re-lock
156
Initial Lock
154
152
Switchover
150
0
5
10
15
20
25
30
35
Time (μs)
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PLLs in Stratix II and Stratix II GX Devices
Figure 1–30. Effect of High Bandwidth on Clock Switchover
160
Input Clock Stops
Re-lock
155
Initial Lock
150
145
Frequency (MHz)
140
135
Switchover
130
125
0
2
4
6
8
10
12
14
16
18
Time (μs)
Implementation
Traditionally, external components such as the VCO or loop filter control
a PLL’s bandwidth. Most loop filters are made up of passive components
such as resistors and capacitors that take up unnecessary board space and
increase cost. With Stratix II and Stratix II GX PLLs, all the components
are contained within the device to increase performance and decrease
cost.
Stratix II and Stratix II GX device PLLs implement reconfigurable
bandwidth by giving you control of the charge pump current and loop
filter resistor (R) and high-frequency capacitor CH values (see Table 1–16).
The Stratix II and Stratix II GX device enhanced PLL bandwidth ranges
from 130 kHz to 16.9 MHz. The Stratix II and Stratix II GX device fast PLL
bandwidth ranges from 1.16 to 28 MHz.
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20
Reconfigurable Bandwidth
The charge pump current directly affects the PLL bandwidth. The higher
the charge pump current, the higher the PLL bandwidth. You can choose
from a fixed set of values for the charge pump current. Figure 1–31 shows
the loop filter and the components that can be set through the Quartus II
software. The components are the loop filter resistor, R, and the high
frequency capacitor, CH, and the charge pump current, IUP or IDN.
Figure 1–31. Loop Filter Programmable Components
IUP
PFD
R
Ch
IDN
C
Software Support
The Quartus II software provides two levels of bandwidth control.
Megafunction-Based Bandwidth Setting
The first level of programmable bandwidth allows you to enter a value
for the desired bandwidth directly into the Quartus II software using the
altpll megafunction. You can also set the bandwidth parameter in the
altpll megafunction to the desired bandwidth. The Quartus II software
selects the best bandwidth parameters available to match your
bandwidth request. If the individual bandwidth setting request is not
available, the Quartus II software selects the closest achievable value.
Advanced Bandwidth Setting
An advanced level of control is also possible using advanced loop filter
parameters. You can dynamically change the charge pump current, loop
filter resistor value, and the loop filter (high frequency) capacitor value.
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The parameters for these changes are: charge_pump_current,
loop_filter_r, and loop_filter_c. Each parameter supports the
specific range of values listed in Table 1–16.
Table 1–16. Advanced Loop Filter Parameters
Parameter
Values
Resistor values (k)
(1)
High-frequency capacitance values (pF)
(1)
Charge pump current settings (
(1)
Note to Table 1–16:
(1)
f
PLL
Reconfiguration
f
SpreadSpectrum
Clocking
For more information, see AN 367: Implementing PLL Reconfiguration in
Stratix II Devices.
For more information about Quartus II software support of
reconfigurable bandwidth, see the Design Example: Dynamic PLL
Reconfiguration section in volume 3, Verification, of the Quartus II
Development Software Handbook.
PLLs use several divide counters and different VCO phase taps to
perform frequency synthesis and phase shifts. In Stratix II and
Stratix II GX enhanced and fast PLLs, the counter value and phase are
configurable in real time. In addition, you can change the loop filter and
charge pump components, which affect the PLL bandwidth, on the fly.
You can control these PLL components to update the output clock
frequency, PLL bandwidth, and phase-shift variation in real time, without
the need to reconfigure the entire FPGA.
For more information about PLL reconfiguration, see AN 367:
Implementing PLL Reconfiguration in Stratix II Devices.
Digital clocks are square waves with short rise times and a 50% duty
cycle. These high-speed clocks concentrate a significant amount of energy
in a narrow bandwidth at the target frequency and at the higher
frequency harmonics. This results in high energy peaks and increased
electromagnetic interference (EMI). The radiated noise from the energy
peaks travels in free air and, if not minimized, can lead to corrupted data
and intermittent system errors, which can jeopardize system reliability.
Traditional methods for limiting EMI include shielding, filtering, and
multi-layer printed circuit boards (PCBs). However, these methods
significantly increase the overall system cost and sometimes are not
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Spread-Spectrum Clocking
enough to meet EMI compliance. Spread-spectrum technology provides
you with a simple and effective technique for reducing EMI without
additional cost and the trouble of re-designing a board.
Spread-spectrum technology modulates the target frequency over a small
range. For example, if a 100-MHz signal has a 0.5% down-spread
modulation, then the frequency is swept from 99.5 to 100 MHz.
Figure 1–32 gives a graphical representation of the energy present in a
spread-spectrum signal vs. a non-spread spectrum-signal. It is apparent
that instead of concentrating the energy at the target frequency, the
energy is re-distributed across a wider band of frequencies, which
reduces peak energy. Not only is there a reduction in the fundamental
peak EMI components, but there is also a reduction in EMI of the higher
order harmonics. Since some regulations focus on peak EMI emissions,
rather than average EMI emissions, spread-spectrum technology is a
valuable method of EMI reduction.
Figure 1–32. Spread-Spectrum Signal Energy Versus Non-Spread-Spectrum Signal Energy
Spread-Spectrum Signal
Non-Spread-Spectrum Signal
Δ = ~5 dB
Amplitude
(dB)
δ = 0.5%
Frequency
(MHz)
Spread-spectrum technology would benefit a design with high EMI
emissions and/or strict EMI requirements. Device-generated EMI is
dependent on frequency and output voltage swing amplitude and edge
rate. For example, a design using LVDS already has low EMI emissions
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because of the low-voltage swing. The differential LVDS signal also
allows for EMI rejection within the signal. Therefore, this situation may
not require spread-spectrum technology.
1
Spread-spectrum clocking is only supported in Stratix II
enhanced PLLs, not fast PLLs.
Implementation
Stratix II and Stratix II GX device enhanced PLLs feature
spread-spectrum technology to reduce the EMIs emitted from the device.
The enhanced PLL provides approximately 0.5% down spread using a
triangular, also known as linear, modulation profile. The modulation
frequency is programmable and ranges from approximately 30 kHz to
150 kHz. The spread percentage is based on the clock input to the PLL
and the m and n settings. Spread-spectrum technology reduces the peak
energy by four to six dB at the target frequency. However, this number is
dependent on bandwidth and the m and n counter values and can vary
from design to design.
Spread percentage, also known as modulation width, is defined as the
percentage that the design modulates the target frequency. A negative (–)
percentage indicates a down spread, a positive (+) percentage indicates
an up spread, and a (  ) indicates a center spread. Modulation frequency
is the frequency of the spreading signal, or how fast the signal sweeps
from the minimum to the maximum frequency. Down-spread
modulation shifts the target frequency down by half the spread
percentage, centering the modulated waveforms on a new target
frequency.
The m and n counter values are toggled at the same time between two
fixed values. The loop filter then slowly changes the VCO frequency to
provide the spreading effect, which results in a triangular modulation. An
additional spread-spectrum counter (shown in Figure 1–33) sets the
modulation frequency. Figure 1–33 shows how spread-spectrum
technology is implemented in the Stratix II and Stratix II GX device
enhanced PLL.
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Spread-Spectrum Clocking
Figure 1–33. Stratix II and Stratix II GX Spread-Spectrum Circuit Block Diagram
÷n
refclk
Up
PFD
Down
SpreadSpectrum
Counter
÷m
n count1
n count2
m count1
m count2
Figure 1–34 shows a VCO frequency waveform when toggling between
different counter values. Since the enhanced PLL switches between two
different m and n values, the result is a straight line between two
frequencies, which gives a linear modulation. The magnitude of
modulation is determined by the ratio of two m/n sets. The percent
spread is determined by:
percent spread = (fVCOmax - fVCOmin)/fVCOmax = 1 [(m2 × n1)/(m1 × n2)].
The maximum and minimum VCO frequency is defined as:
fVCOmax = (m1/n1) × fREF
fVCOmin = (m2/n2) × fREF
Figure 1–34. VCO Frequency Modulation Waveform
count2 values
count1 values
VCO Frequency
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Software Support
You can enter the desired down-spread percentage and modulation
frequency in the altpll megafunction through the Quartus II software.
Alternatively, the downspread parameter in the altpll megafunction
can be set to the desired down-spread percentage. Timing analysis
ensures the design operates at the maximum spread frequency and meets
all timing requirements.
f
For more information about PLL software support in the Quartus II
software, see the altpll Megafunction User Guide.
Guidelines
If the design cascades PLLs, the source (upstream) PLL should have a
low-bandwidth setting, while the destination (downstream) PLL should
have a high-bandwidth setting. The upstream PLL must have a
low-bandwidth setting because a PLL does not generate jitter higher than
its bandwidth. The downstream PLL must have a high bandwidth setting
to track the jitter. The design must use the spread-spectrum feature in a
low-bandwidth PLL, and, therefore, the Quartus II software
automatically sets the spread-spectrum PLL bandwidth to low.
1
If the programmable or reconfigurable bandwidth features are
used, then you cannot use spread spectrum.
Stratix II and Stratix II GX devices can accept a spread-spectrum input
with typical modulation frequencies. However, the device cannot
automatically detect that the input is a spread-spectrum signal. Instead,
the input signal looks like deterministic jitter at the input of the
downstream PLL.
Spread spectrum can have a minor effect on the output clock by
increasing the period jitter. Period jitter is the deviation of a clock’s cycle
time from its previous cycle position. Period jitter measures the variation
of the clock output transition from its ideal position over consecutive
edges.
With down-spread modulation, the peak of the modulated waveform is
the actual target frequency. Therefore, the system never exceeds the
maximum clock speed. To maintain reliable communication, the entire
system and subsystem should use the Stratix II and Stratix II GX device
as the clock source. Communication could fail if the Stratix II or
Stratix II GX logic array is clocked by the spread-spectrum clock, but the
data it receives from another device is not clocked by the spread
spectrum.
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Board Layout
Since spread spectrum affects the m counter values, all spread-spectrum
PLL outputs are effected. Therefore, if only one spread-spectrum signal is
needed, the clock signal should use a separate PLL without other outputs
from that PLL.
No special considerations are needed when using spread spectrum with
the clock switchover feature. This is because the clock switchover feature
does not affect the m and n counter values, which are the counter values
switching when using spread spectrum.
Board Layout
The enhanced and fast PLL circuits in Stratix II and Stratix II GX devices
contain analog components embedded in a digital device. These analog
components have separate power and ground pins to minimize noise
generated by the digital components. Stratix II and Stratix II GX
enhanced and fast PLLs use separate VCC and ground pins to isolate
circuitry and improve noise resistance.
VCCA and GNDA
Each enhanced and fast PLL uses separate VCC and ground pin pairs for
their analog circuitry. The analog circuit power and ground pin for each
PLL is called VCCA_PLL<PLL number> and GNDA_PLL<PLL number>.
Connect the VCCA power pin to a 1.2-V power supply, even if you do not
use the PLL. Isolate the power connected to VCCA from the power to the
rest of the Stratix II or Stratix II GX device or any other digital device on
the board. You can use one of three different methods of isolating the
VCCA pin: separate VCCA power planes, a partitioned VCCA island within
the VCCINT plane, and thick VCCA traces.
Separate VCCA Power Plane
A mixed signal system is already partitioned into analog and digital
sections, each with its own power planes on the board. To isolate the VCCA
pin using a separate VCCA power plane, connect the VCCA pin to the
analog 1.2-V power plane.
Partitioned VCCA Island Within VCCINT Plane
Fully digital systems do not have a separate analog power plane on the
board. Since it is expensive to add new planes to the board, you can create
islands for VCCA_PLL. Figure 1–35 shows an example board layout with
an analog power island. The dielectric boundary that creates the island
should be 25 mils thick. Figure 1–36 shows a partitioned plane within
VCCINT for VCCA.
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Figure 1–35. VCCINT Plane Partitioned for VCCA Island
Thick VCCA Trace
Because of board constraints, you may not be able to partition a VCCA
island. Instead, run a thick trace from the power supply to each VCCA pin.
The traces should be at least 20 mils thick.
In each of these three cases, you should filter each VCCA_PLL pin with a
decoupling circuit, as shown in Figure 1–36. Place a ferrite bead that
exhibits high impedance at frequencies of 50 MHz or higher and a 10-F
tantalum parallel capacitor where the power enters the board. Decouple
each VCCA_PLL pin with a 0.1-F and 0.001-F parallel combination of
ceramic capacitors located as close as possible to the Stratix II or
Stratix II GX device. You can connect the GNDA_PLL pins directly to the
same ground plane as the device’s digital ground.
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Board Layout
Figure 1–36. PLL Power Schematic for Stratix II and Stratix II GX PLLs
Ferrite
Bead
1.2-V
Supply
10 μF
GND
VCCA_PLL #
(1)
GNDA_PLL #
(1)
0.001 μF
0.1 μF
GND
GND
VCCINT
VCCD_PLL #
GND
GND
Repeat for Each
PLL Power &
Ground Set
Stratix II Device
Note to Figure 1–36
(1)
Applies to PLLs 1 through 12.
VCCD
The digital power and ground pins are labeled VCCD_PLL<PLL number>
and GND. The VCCD pin supplies the power for the digital circuitry in the
PLL. Connect these VCCD pins to the quietest digital supply on the board.
In most systems, this is the digital 1.2-V supply supplied to the device’s
VCCINT pins. Connect the VCCD pins to a power supply even if you do not
use the PLL. When connecting the VCCD pins to VCCINT, you do not need
any filtering or isolation. You can connect the GND pins directly to the
same ground plane as the device’s digital ground. See Figure 1–36.
External Clock Output Power
Enhanced PLLs 5, 6, 11, and 12 also have isolated power pins for their
dedicated external clock outputs (VCC_PLL5_OUT, VCC_PLL6_OUT,
VCC_PLL11_OUT and VCC_PLL12_OUT, respectively). Since the
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dedicated external clock outputs from a particular enhanced PLL are
powered by separate power pins, they are less susceptible to noise. They
also reduce the overall jitter of the output clock by providing improved
isolation from switching I/O pins.
1
I/O pins that reside in PLL banks 9 through 12 are powered by
the VCC_PLL<5, 6, 11, or 12>_OUT pins, respectively. The
EP2S60F484, EP2S60F780, EP2S90H484, EP2S90F780, and
EP2S130F780 devices do not support PLLs 11 and 12. Therefore,
any I/O pins that reside in bank 11 are powered by the VCCIO3
pin, and any I/O pins that reside in bank 12 are powered by the
VCCIO8 pin.
The VCC_PLL_OUT pins can by powered by 3.3, 2.5, 1.8, or 1.5 V,
depending on the I/O standard for the clock output from a particular
enhanced PLL, as shown in Figure 1–37.
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July 2009
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Stratix II Device Handbook, Volume 2
Board Layout
Figure 1–37. External Clock Output Pin Association with Output Power
VCC_PLL5_OUT
PLL5_OUT0p
PLL5_OUT0n
PLL5_OUT1p
PLL5_OUT1n
PLL5_OUT2p
PLL5_OUT2n
Filter each isolated power pin with a decoupling circuit shown in
Figure 1–38. Decouple the isolated power pins with parallel combination
of 0.1- and 0.001-Fceramic capacitors located as close as possible to the
Stratix II or Stratix II GX device.
1–60
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July 2009
PLLs in Stratix II and Stratix II GX Devices
Figure 1–38. Stratix II and Stratix II GX PLL External Clock Output Power Ball
Connection Note (1)
VCCIO
Supply
VCC_PLL#_OUT (1)
0.001 μF
0.1 μF
GND
GND
VCC_PLL#_OUT (1)
0.001 μF
0.1 μF
GND
GND
Stratix II or Stratix II GX Device
Note to Figure 1–38:
(1)
Applies only to enhanced PLLs 5, 6, 11, and 12.
Guidelines
Use the following guidelines for optimal jitter performance on the
external clock outputs from enhanced PLLs 5, 6, 11, and 12. If all outputs
are running at the same frequency, these guidelines are not necessary to
improve performance.
■
■
Use phase shift to ensure edges are not coincident on all the clock
outputs.
Use phase shift to skew clock edges with respect to each other for
best jitter performance.
If you cannot drive multiple clocks of different frequencies and phase
shifts or isolate banks, you should control the drive capability on the
lower-frequency clock. Reducing how much current the output buffer has
to supply can reduce the noise. Minimize capacitive load on the slower
frequency output and configure the output buffer to lower current
strength. The higher-frequency output should have an improved
performance, but this may degrade the performance of your lowerfrequency clock output.
Altera Corporation
July 2009
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Stratix II Device Handbook, Volume 2
PLL Specifications
PLL
Specifications
f
Clocking
See the DC & Switching Characteristics chapter in volume 1 of the
Stratix II GX Device Handbook (or the Stratix II Device Handbook) for
information about PLL timing specifications
Stratix II and Stratix II GX devices provide a hierarchical clock structure
and multiple PLLs with advanced features. The large number of clocking
resources in combination with the clock synthesis precision provided by
enhanced and fast PLLs provides a complete clock-management solution.
Global and Hierarchical Clocking
Stratix II and Stratix II GX devices provide 16 dedicated global clock
networks and 32 regional clock networks. These clocks are organized into
a hierarchical clock structure that allows for 24 unique clock sources per
device quadrant with low skew and delay. This hierarchical clocking
scheme provides up to 48 unique clock domains within the entire
Stratix II or Stratix II GX device. Table 1–17 lists the clock resources
available on Stratix II devices.
There are 16 dedicated clock pins (CLK[15..0]) on Stratix II and
Stratix II GX devices to drive either the global or regional clock networks.
Four clock pins drive each side of the Stratix II device, as shown in
Figures 1–39 and 1–40. Enhanced and fast PLL outputs can also drive the
global and regional clock networks.
Table 1–17. Clock Resource Availability in Stratix II and Stratix II GX Devices (Part 1 of 2)
Description
Number of clock input pins
Stratix II Device Availability
Stratix II GX Device Availability
24
12
Number of global clock networks 16
16
Number of regional clock
networks
32
32
Global clock input sources
Clock input pins, PLL outputs, logic
array
Clock input pins, PLL outputs, logic
array, inter-transceiver clocks
Regional clock input sources
Clock input pins, PLL outputs, logic
array
Clock input pins, PLL outputs, logic
array, inter-transceiver clocks
Number of unique clock sources
in a quadrant
24 (16 global clocks and 8 regional
clocks)
24 (16 GCLK and 8 RCLK clocks)
Number of unique clock sources
in the entire device
48 (16 global clocks and 32 regional
clocks)
48 (16 GCLK and 32 RCLK clocks)
1–62
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Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Table 1–17. Clock Resource Availability in Stratix II and Stratix II GX Devices (Part 2 of 2)
Description
Stratix II Device Availability
Stratix II GX Device Availability
Power-down mode
Global clock networks, regional clock GCLK, RCLK networks, dual-regional
networks, dual-regional clock region clock region
Clocking regions for high fan-out
applications
Quadrant region, dual-regional,
entire device via global clock or
regional clock networks
Quadrant region, dual-regional,
entire device via GCLK or RCLK
networks
Global Clock Network
Global clocks drive throughout the entire device, feeding all device
quadrants. All resources within the device IOEs, adaptive logic modules
(ALMs), digital signal processing (DSP) blocks, and all memory blocks
can use the global clock networks as clock sources. These resources can
also be used for control signals, such as clock enables and synchronous or
asynchronous clears fed by an external pin. Internal logic can also drive
the global clock networks for internally generated global clocks and
asynchronous clears, clock enables, or other control signals with large
fanout. Figure 1–39 shows the 16 dedicated CLK pins driving global clock
networks.
Figure 1–39. Global Clocking
Note (1)
CLK12-15
11
5
10
7
GCLK12 - 15
16
CLK0-3
16
1 GCLK0-3
2
GCLK8-11
16
4
3
CLK8-11
16
GCLK4-7
9
8
12
6
CLK4-7
Note to Figure 1–39:
(1)
Altera Corporation
July 2009
Stratix II GX devices do not have PLLs 3, 4, 9, and 10 or clock pins 8, 9, 10, and 11.
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Stratix II Device Handbook, Volume 2
Clocking
Regional Clock Network
Eight regional clock networks within each quadrant of the Stratix II and
Stratix II GX device are driven by the dedicated CLK[15..0]input pins
or from PLL outputs. The regional clock networks only pertain to the
quadrant they drive into. The regional clock networks provide the lowest
clock delay and skew for logic contained within a single quadrant.
Internal logic can also drive the regional clock networks for internally
generated regional clocks and asynchronous clears, clock enables, or
other control signals with large fanout.The CLK clock pins symmetrically
drive the RCLK networks within a particular quadrant, as shown in
Figure 1–40. Refer to Table 1–18 on page 1–67 and Table 1–19 on
page 1–68 for RCLK connections from CLK pins and PLLs.
Figure 1–40. Regional Clocking
Note (1)
CLK12-15
11
5
7
10
RCLK28-31
RCLK24-27
RCLK20-23
RCLK0-3
CLK0 -3
Q1 Q2
1
2
4
3
Q4 Q3
CLK8-11
RCLK16-19
RCLK4-7
RCLK8-11 RCLK12-15
8
9
12
6
CLK4-7
Note to Figure 1–40:
(1)
Stratix II GX devices do not have PLLs 3, 4, 9, and 10 or clock pins 8, 9, 10, and 11.
Clock Sources Per Region
Each Stratix II and Stratix II GX device has 16 global clock networks and
32 regional clock networks that provide 48 unique clock domains for the
entire device. There are 24 unique clocks available in each quadrant
(16 global clocks and 8 regional clocks) as the input resources for registers
(see Figure 1–41).
1–64
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July 2009
PLLs in Stratix II and Stratix II GX Devices
Figure 1–41. Hierarchical Clock Networks Per Quadrant
Clocks Available
to a Quadrant
or Half-Quadrant
Column I/O Cell
IO_CLK[7..0]
Global Clock Network [15..0]
Clock [23..0]
Lab Row Clock [5..0]
Regional Clock Network [7..0]
Row I/O Cell
IO_CLK[7..0]
Stratix II and Stratix II GX clock networks provide three different clocking
regions:
■
■
■
Entire device clock region
Quadrant clock region
Dual-regional clock region
These clock network options provide more flexibility for routing signals
that have high fan-out to improve the interface timing. By having various
sized clock regions, it is possible to prioritize the number of registers the
network can reach versus the total delay of the network.
In the first clock scheme, a source (not necessarily a clock signal) drives a
global clock network that can be routed through the entire device. This
has the maximum delay for a low skew high fan-out signal but allows the
signal to reach every block within the device. This is a good option for
routing global resets or clear signals.
In the second clock scheme, a source drives a single-quadrant region. This
represents the fastest, low-skew, high-fan-out signal-routing resource
within a quadrant. The limitation to this resource is that it only covers a
single quadrant.
In the third clock scheme, a single source (clock pin or PLL output) can
generate a dual-regional clock by driving two regional clock network
lines (one from each quadrant). This allows logic that spans multiple
quadrants to utilize the same low-skew clock. The routing of this signal
on an entire side has approximately the same speed as in a quadrant clock
region. The internal logic-array routing that can drive a regional clock
also supports this feature. This means internal logic can drive a
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July 2009
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Stratix II Device Handbook, Volume 2
Clocking
dual-regional clock network. Corner fast PLL outputs only span one
quadrant and hence cannot form a dual-regional clock network.
Figure 1–42 shows this feature pictorially.
Figure 1–42. Stratix II and Stratix II GX Dual-Regional Clock Region
Clock pins or PLL outputs
can drive half of the device to
create dual-reginal clocking
regions for improved I/O
interface timing.
The 16 clock input pins, enhanced or fast PLL outputs, and internal logic
array can be the clock input sources to drive onto either global or regional
clock networks. The CLKn pins also drive the global clock network as
shown in Table 1–22 on page 1–72. Tables 1–18 and 1–19 for the
connectivity between CLK pins as well as the global and regional clock
networks.
Clock Inputs
The clock input pins CLK[15..0] are also used for high fan-out control
signals, such as asynchronous clears, presets, clock enables, or protocol
signals such as TRDY and IRDY for PCI through global or regional clock
networks.
Internal Logic Array
Each global and regional clock network can also be driven by logic-array
routing to enable internal logic to drive a high fan-out, low-skew signal.
PLL Outputs
All clock networks can be driven by the PLL counter outputs.
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Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Table 1–18 shows the connection of the clock pins to the global clock
resources. The reason for the higher level of connectivity is to support
user controllable global clock multiplexing.
Table 1–18. Clock Input Pin Connectivity to Global Clock Networks
CLK(p) (Pin)
Clock Resource
0
1
2
3
4
5
6
7
GCLK0
v
v
GCLK1
v
v
GCLK2
v
v
GCLK3
v
v
GCLK4
v
v
GCLK5
v
v
GCLK6
v
v
GCLK7
v
v
8
9
10
11
GCLK8
v
(1)
v
(1)
GCLK9
v
(1)
v
(1)
14
15
GCLK12
v
v
GCLK13
v
v
GCLK10
v
(1)
v
(1)
GCLK11
v
(1)
v
(1)
12
13
GCLK14
v
v
GCLK15
v
v
Note to Table 1–18:
(1)
Clock pins 8, 9, 10, and 11 are not available in Stratix II GX devices. Therefore, these connections do not exist in
Stratix II GX devices.
Altera Corporation
July 2009
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Stratix II Device Handbook, Volume 2
Clocking
Table 1–19 summarizes the connectivity between the clock pins and the
regional clock networks. Here, each clock pin can drive two regional clock
networks, facilitating stitching of the clock networks to support the
ability to drive two quadrants with the same clock or signal.
Table 1–19. Clock Input Pin Connectivity to Regional Clock Networks (Part 1 of 2)
CLK(p) (Pin)
Clock Resource
0
RCLK0
1
2
RCLK7
6
7
8
9
10
11
12
13
14
15
v
RCLK3
RCLK6
5
v
RCLK2
RCLK5
4
v
RCLK1
RCLK4
3
v
v
v
v
v
RCLK8
v
v
RCLK9
v
RCLK10
v
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
v
v
v
v
v
(1)
RCLK16
v
(1)
RCLK17
RCLK18
v
(1)
v
(1)
RCLK19
v
(1)
RCLK20
v
(1)
RCLK21
RCLK22
1–68
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v
(1)
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Table 1–19. Clock Input Pin Connectivity to Regional Clock Networks (Part 2 of 2)
CLK(p) (Pin)
Clock Resource
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
v
(1)
RCLK23
v
RCLK24
v
RCLK25
v
RCLK26
v
RCLK27
v
RCLK28
v
RCLK29
v
RCLK30
v
RCLK31
Note to Table 1–19:
(1)
Clock pins 8, 9, 10, and 11 are not available in Stratix II GX devices. Therefore, these connections do not exist in
Stratix II GX devices.
Clock Input Connections
Four CLK pins drive each enhanced PLL. You can use any of the pins for
clock switchover inputs into the PLL. The CLK pins are the primary clock
source for clock switchover, which is controlled in the Quartus II
software. Enhanced PLLs 5, 6, 11, and 12 also have feedback input pins,
as shown in Table 1–20.
Input clocks for fast PLLs 1, 2, 3, and 4 come from CLK pins. A multiplexer
chooses one of two possible CLK pins to drive each PLL. This multiplexer
is not a clock switchover multiplexer and is only used for clock input
connectivity.
Either an FPLLCLK input pin or a CLK pin can drive the fast PLLs in the
corners (7, 8, 9, and 10) when used for general-purpose applications. CLK
pins cannot drive these fast PLLs in high-speed differential I/O mode.
Altera Corporation
July 2009
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Stratix II Device Handbook, Volume 2
Clocking
Tables 1–20 and 1–21 show which PLLs are available in each Stratix II and
Stratix II GX device, respectively, and which input clock pin drives which
PLLs.
Table 1–20. Stratix II Device PLLs and PLL Clock Pin Drivers (Part 1 of 2)
All Devices
Input Pin
Enhanced
PLLs
Fast PLLs
1
2
3
EP2S60 to EP2S180 Devices
4
5
6
Enhanced
PLLs
Fast PLLs
7
8
CLK0
v
v
v (1) v (1)
CLK1 (2)
v
v
v (1) v (1)
CLK2
v
v
v (1) v (1)
CLK3 (2)
v
v
v (1) v (1)
9
10
11
12
CLK4
v
v
CLK5
v
v
CLK6
v
v
CLK7
v
v
CLK8
v
v
v (1)
v (1)
CLK9 (2)
v
v
v (1)
v (1)
CLK10
v
v
v (1)
v (1)
CLK11 (2)
v
v
v (1)
v (1)
CLK12
v
v
CLK13
v
v
CLK14
v
v
CLK15
v
v
PLL5_FB
v
v
PLL6_FB
v
PLL11_FB
v
PLL12_FB
PLL_ENA
v
v
FPLL7CLK (2)
FPLL8CLK (2)
FPLL9CLK (2)
1–70
Stratix II Device Handbook, Volume 2
v
v
v
v
v
v
v
v
v
v
v
v
v
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Table 1–20. Stratix II Device PLLs and PLL Clock Pin Drivers (Part 2 of 2)
All Devices
Input Pin
Enhanced
PLLs
Fast PLLs
1
2
3
EP2S60 to EP2S180 Devices
4
5
Enhanced
PLLs
Fast PLLs
6
7
8
9
10
11
12
v
FPLL10CLK (2)
Notes to Table 1–20:
(1)
(2)
Clock connection is available. For more information about the maximum frequency, contact Altera Applications.
This is a dedicated high-speed clock input. For more information about the maximum frequency, contact Altera
Applications.
Table 1–21. Stratix II GX Device PLLs and PLL Clock Pin Drivers (Part 1 of 2)
All Devices
EP2SGX60 to EP2SGX130 Devices
Fast PLLs
Enhanced
PLLs
Fast PLLs
Enhanced
PLLs
1
2
5
7
8
11
CLK0
v
v
v(2)
v(2)
CLK1 (2)
CLK2
v
v
v(2)
v(2)
v
v
v(2)
v(2)
CLK3 (2)
v
v
v(2)
v(2)
Input Pin
3 (1) 4 (1)
6
9 (1) 10 (1)
12
v
v
CLK5
v
v
CLK6
v
v
CLK7
v
v
CLK4
CLK8 (4)
CLK9 (3), (4)
CLK10 (4)
CLK11 (3), (4)
CLK12
v
v
CLK13
v
v
CLK14
v
v
CLK15
v
v
PLL5_FB
v
PLL6_FB
PLL11_FB
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July 2009
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v
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Clocking
Table 1–21. Stratix II GX Device PLLs and PLL Clock Pin Drivers (Part 2 of 2)
All Devices
Input Pin
1
EP2SGX60 to EP2SGX130 Devices
Fast PLLs
Enhanced
PLLs
2
5
3 (1) 4 (1)
6
7
Fast PLLs
Enhanced
PLLs
8
11
9 (1) 10 (1)
v
PLL12_FB
PLL_ENA
12
v
v
v
v
v
v
v
v
v
FPLL7CLK (3)
v
FPLL8CLK (3)
FPLL9CLK (3)
FPLL10CLK (3)
Notes to Table 1–21:
(1)
(2)
(3)
(4)
PLLs 3, 4, 9, and 10 are not available in Stratix II GX devices.
Clock connection is available. For more information about the maximum frequency, contact Altera Applications.
This is a dedicated high-speed clock input. For more information about the maximum frequency, contact Altera
Applications.
Input pins CLK[11..8] are not available in Stratix II GX devices.
CLK(n) Pin Connectivity to Global Clock Networks
In Stratix II and Stratix II GX devices, the clk(n) pins can also feed the
global clock network. Table 1–22 shows the clk(n) pin connectivity to
global clock networks.
Table 1–22. CLK(n) Pin Connectivity to Global Clock Network
Clock
Resource
CLK(n) pin
4
GCLK4
GCLK5
GCLK6
GCLK7
5
6
7
12
13
v
v
v
v
v
GCLK13
GCLK15
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15
v
GCLK12
GCLK14
14
v
v
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Clock Source Control For Enhanced PLLs
The clock input multiplexer for enhanced PLLs is shown in Figure 1–43.
This block allows selection of the PLL clock reference from several
different sources. The clock source to an enhanced PLL can come from
any one of four clock input pins CLK[3..0], or from a logic-array clock,
provided the logic array clock is driven by an output from another PLL,
a pin-driven dedicated global or regional clock, or through a clock control
block, provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally
generated global signal cannot drive the PLL. The clock input pin
connections to the respective enhanced PLLs are shown in Table 1–20
above. The multiplexer select lines are set in the configuration file only.
Once programmed, this block cannot be changed without loading a new
configuration file. The Quartus II software automatically sets the
multiplexer select signals depending on the clock sources that a user
selects in the design.
Figure 1–43. Enhanced PLL Clock Input Multiplex Logic
(1)
4
clk[3..0]
inclk0
core_inclk
To the Clock
Switchover Block
(1)
inclk1
4
Note to Figure 1–43:
(1)
The input clock multiplexing is controlled through a configuration file only and
cannot be dynamically controlled in user mode.
Clock Source Control for Fast PLLs
Each center fast PLL has five clock input sources, four from clock input
pins, and one from a logic array signal, provided the logic array signal is
driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block, provided the clock
control block is fed by an output from another PLL or a pin-driven
dedicated global or regional clock. An internally generated global signal
cannot drive the PLL. When using clock input pins as the clock source,
you can perform manual clock switchover among the input clock sources.
Altera Corporation
July 2009
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Stratix II Device Handbook, Volume 2
Clocking
The clock input multiplexer control signals for performing clock
switchover are from core signals. Figure 1–44 shows the clock input
multiplexer control circuit for a center fast PLL.
Figure 1–44. Center Fast PLL Clock Input Multiplexer Control
(1)
core_inclk
clk[3..0]
4
inclk0
To the Clock
Switchover
Block
core_inclk
inclk1
(1)
Note to Figure 1–44:
(1)
The input clock multiplexing is controlled through a configuration file only and
cannot be dynamically controlled in user mode.
Each corner fast PLL has three clock input sources, one from a dedicated
corner clock input pin, one from a center clock input pin, and one from a
logic array clock, provided the logic array signal is driven by an output
from another PLL, a pin-driven dedicated global or regional clock, or
through a clock control block, provided the clock control block is fed by
an output from another PLL or a pin-driven dedicated global or regional
clock. An internally generated global signal cannot drive the PLL.
Figure 1–45 shows a block diagram showing the clock input multiplexer
control circuit for a corner fast PLL. Only the corner FPLLCLK pin is fully
compensated.
Figure 1–45. Corner Fast PLL Clock Input Multiplexer Control
core_inclk
(1)
FPLLCLK
Center
Clocks
4
inclk0
To the Clock
Switchover
Block
inclk1
(1)
core_inclk
Note to Figure 1–45:
(1)
The input clock multiplexing is controlled through a configuration file only and
cannot be dynamically controlled in user mode.
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Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Delay Compensation for Fast PLLs
Each center fast PLL can be fed by any one of four possible input clock
pins. Among the four clock input signals, only two are fully
compensated, i.e., the clock delay to the fast PLL matches the delay in the
data input path when used in the LVDS receiver mode. The two clock
inputs that match the data input path are located right next to the fast
PLL. The two clock inputs that do not match the data input path are
located next to the neighboring fast PLL. Figure 1–46 shows the above
description for the left-side center fast PLL pair. If the PLL is used in
non-LVDS modes, then any of the four dedicated clock inputs can be used
and are compensated.
Fast PLL 1 and PLL 2 can choose among CLK[3..0] as the clock input
source. However, for fast PLL 1, only CLK0 and CLK1 have their delay
matched to the data input path delay when used in the LVDS receiver
mode operation. The delay from CLK2 or CLK3 to fast PLL 1 does not
match the data input delay. For fast PLL 2, only CLK2 and CLK3 have their
delay matched to the data input path delay in LVDS receiver mode
operation. The delay from CLK0 or CLK1 to fast PLL 2 does not match the
data input delay. The same arrangement applies to the right side center
fast PLL pair. For corner fast PLLs, only the corner FPLLCLK pins are fully
compensated. For LVDS receiver operation, it is recommended to use the
delay compensated clock pins only.
Figure 1–46. Delay Compensated Clock Input Pins for Center Fast PLL Pair
CLK0
CLK1
Fast PLL 1
Fast PLL 2
CLK2
CLK3
Altera Corporation
July 2009
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Stratix II Device Handbook, Volume 2
Clocking
Clock Output Connections
Enhanced PLLs have outputs for eight regional clock outputs and four
global clock outputs. There is line sharing between clock pins, global and
regional clock networks and all PLL outputs. See Tables 1–18 through
1–23 and Figures 1–47 through 1–53 to validate your clocking scheme.
The Quartus II software automatically maps to regional and global clocks
to avoid any restrictions. Enhanced PLLs 5, 6, 11, and 12 drive out to
single-ended pins as shown in Table 1–23.
You can connect each fast PLL 1, 2, 3, or 4 output (C0, C1, C2, and C3) to
either a global or a regional clock. There is line sharing between clock
pins, FPLLCLK pins, global and regional clock networks, and all PLL
outputs. The Quartus II software will automatically map to regional and
global clocks to avoid any restrictions.
Figure 1–47 shows the clock input and output connections from the
enhanced PLLs.
1
EP2S15, EP2S30, and EP2SGX30 devices have only two
enhanced PLLs (5, 6), but the connectivity from these two PLLs
to the global or regional clock networks remains the same.
The EP2S60 device in the 1,020-pin package contains 12 PLLs.
EP2S60 devices in the 484-pin and 672-pin packages contain fast
PLLs 1–4 and enhanced PLLs 5 and 6.
EP2S90 devices in the 1020-pin and 1508-pin packages contain
12 PLLs. EP2S90 devices in the 484-pin and 780-pin packages
contain fast PLLs 1–4 and enhanced PLLs 5 and 6.
EP2S130 devices in the 1020-pin and 1508-pin packages contain
12 PLLs. The EP2S130 device in the 780-pin package contains
fast PLLs 1–4 and enhanced PLLs 5 and 6.
1–76
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July 2009
PLLs in Stratix II and Stratix II GX Devices
Figure 1–47. Stratix II and Stratix II GX Top and Bottom Enhanced PLLs, Clock Pin and Logic Array Signal
Connectivity to Global and Regional Clock Networks Notes (1) and (2)
CLK15
CLK13
CLK12
CLK14
PLL5_FB
PLL11_FB
PLL 11
PLL 5
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL5_OUT[2..0]p
PLL5_OUT[2..0]n
RCLK31
RCLK30
RCLK29
RCLK28
PLL11_OUT[2..0]p
PLL11_OUT[2..0]n
Regional
Clocks
RCLK27
RCLK26
RCLK25
RCLK24
G15
G14
G13
G12
Global
Clocks
Regional
Clocks
G4
G5
G6
G7
RCLK8
RCLK9
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
PLL6_OUT[2..0]p
PLL6_OUT[2..0]n
PLL12_OUT[2..0]p
PLL12_OUT[2..0]n
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL 12
PLL 6
PLL12_FB
PLL6_FB
CLK4
CLK6
CLK5
CLK7
Notes to Figure 1–47:
(1)
(2)
The redundant connection dots facilitate stitching of the clock networks to support the ability to drive two
quadrants with the same clock.
The enhanced PLLs can also be driven through the global or regional clock networks. The global or regional clock
input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a
clock control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
global or regional clock. An internally generated global signal cannot drive the PLL.
Altera Corporation
July 2009
1–77
Stratix II Device Handbook, Volume 2
Clocking
Tables 1–23 and 1–24 show the global and regional clocks that the PLL
outputs drive.
Table 1–23. Stratix II Global and Regional Clock Outputs From PLLs
(Part 1 of 3)
PLL Number and Type
EP2S15 through EP2S30 Devices
Clock Network
Enhanced
PLLs
Fast PLLs
1
2
3
EP2S60 through EP2S180 Devices
4
5
6
Enhanced
PLLs
Fast PLLs
7
8
GCLK0
v
v
v
v
GCLK1
v
v
v
v
GCLK2
v
v
v
v
GCLK3
v
v
v
v
9
10
11
12
v
v
GCLK5
v
v
GCLK6
v
v
GCLK7
v
v
GCLK4
GCLK8
v
v
v
v
GCLK9
v
v
v
v
GCLK10
v
v
v
v
GCLK11
v
v
v
v
GCLK12
v
v
GCLK13
v
v
GCLK14
v
v
GCLK15
v
v
RCLK0
v
v
v
RCLK1
v
v
v
RCLK2
v
v
v
RCLK3
v
v
v
RCLK4
v
v
RCLK5
v
v
v
RCLK6
v
v
v
RCLK7
v
v
v
v
RCLK8
v
v
RCLK9
v
v
1–78
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Table 1–23. Stratix II Global and Regional Clock Outputs From PLLs
(Part 2 of 3)
PLL Number and Type
EP2S15 through EP2S30 Devices
Clock Network
Enhanced
PLLs
Fast PLLs
1
2
EP2S60 through EP2S180 Devices
3
4
5
6
Enhanced
PLLs
Fast PLLs
7
8
9
10
11
12
RCLK10
v
v
RCLK11
v
v
RCLK12
v
v
RCLK13
v
v
RCLK14
v
v
v
RCLK15
v
RCLK16
v
v
v
RCLK17
v
v
v
RCLK18
v
v
v
RCLK19
v
v
v
RCLK20
v
v
v
RCLK21
v
v
v
RCLK22
v
v
v
RCLK23
v
v
v
RCLK24
v
v
RCLK25
v
v
RCLK26
v
v
RCLK27
v
v
RCLK28
v
v
RCLK29
v
v
RCLK30
v
v
RCLK31
v
v
External Clock Output
PLL5_OUT[3..0]p/
n
PLL6_OUT[3..0]p/
n
Altera Corporation
July 2009
v
v
1–79
Stratix II Device Handbook, Volume 2
Clocking
Table 1–23. Stratix II Global and Regional Clock Outputs From PLLs
(Part 3 of 3)
PLL Number and Type
EP2S15 through EP2S30 Devices
Clock Network
Enhanced
PLLs
Fast PLLs
1
2
3
EP2S60 through EP2S180 Devices
4
5
Enhanced
PLLs
Fast PLLs
6
7
8
9
10
11
12
v
PLL11_OUT[3..0]p
/n
v
PLL12_OUT[3..0]p
/n
Table 1–24. Stratix II GX Global and Regional Clock Outputs From PLLs (Part 1 of 3)
PLL Number and Type
EP2SGX60 through EP2SGX130 Devices
Notes (2), (3), and (4)
EP2SGX30 Devices
Clock Network
Fast PLLs
1
2
3 (1) 4 (1)
Enhanced
PLLs
5
6
Enhanced
PLLs
Fast PLLs
7
8
GCLK0
v
v
v
v
GCLK1
v
v
v
v
GCLK2
v
v
v
v
GCLK3
v
v
v
v
9 (1) 10(1)
11
12
v
v
GCLK5
v
v
GCLK6
v
v
GCLK7
v
v
GCLK4
GCLK8
GCLK9
GCLK10
GCLK11
GCLK12
v
v
GCLK13
v
v
GCLK14
v
v
GCLK15
v
v
1–80
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Table 1–24. Stratix II GX Global and Regional Clock Outputs From PLLs (Part 2 of 3)
PLL Number and Type
EP2SGX60 through EP2SGX130 Devices
Notes (2), (3), and (4)
EP2SGX30 Devices
Clock Network
Fast PLLs
3 (1) 4 (1)
Enhanced
PLLs
5
6
Fast PLLs
1
2
RCLK0
v
v
v
7
8
RCLK1
v
v
v
RCLK2
v
v
v
RCLK3
v
v
v
RCLK4
v
v
v
RCLK5
v
v
v
RCLK6
v
v
v
RCLK7
v
v
9 (1) 10(1)
Enhanced
PLLs
11
12
v
RCLK8
v
v
RCLK9
v
v
RCLK10
v
v
RCLK11
v
v
RCLK12
v
v
RCLK13
v
v
RCLK14
v
v
RCLK15
v
v
RCLK16
RCLK17
RCLK18
RCLK19
RCLK20
RCLK21
RCLK22
RCLK23
RCLK24
v
v
RCLK25
v
v
RCLK26
v
v
RCLK27
v
v
Altera Corporation
July 2009
1–81
Stratix II Device Handbook, Volume 2
Clocking
Table 1–24. Stratix II GX Global and Regional Clock Outputs From PLLs (Part 3 of 3)
PLL Number and Type
EP2SGX60 through EP2SGX130 Devices
Notes (2), (3), and (4)
EP2SGX30 Devices
Clock Network
Enhanced
PLLs
Fast PLLs
1
2
3 (1) 4 (1)
5
6
Enhanced
PLLs
Fast PLLs
7
8
9 (1) 10(1)
11
RCLK28
v
v
RCLK29
v
v
RCLK30
v
v
RCLK31
v
v
12
External Clock Output
v
PLL5_OUT[3..0]p
/n
v
PLL6_OUT[3..0]p
/n
v
PLL11_OUT[3..0]
p/n
v
PLL12_OUT[3..0]
p/n
Notes to Table 1–24:
(1)
(2)
(3)
(4)
PLLs 3, 4, 9, and 10 are not available in Stratix II GX devices.
The EP2S60 device in the 1,020-pin package contains 12 PLLs. EP2S60 devices in the 484-pin and 672-pin packages
contain fast PLLs 1–4 and enhanced PLLs 5 and 6.
EP2S90 devices in the 1020-pin and 1508-pin packages contain 12 PLLs. EP2S90 devices in the 484-pin and 780-pin
packages contain fast PLLs 1–4 and enhanced PLLs 5 and 6.
EP2S130 devices in the 1020-pin and 1508-pin packages contain 12 PLLs. The EP2S130 device in the 780-pin
package contains fast PLLs 1–4 and enhanced PLLs 5 and 6.
The fast PLLs also drive high-speed SERDES clocks for differential I/O
interfacing. For information about these FPLLCLK pins, contact Altera
Applications.
1–82
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Figures 1–48 through 1–51 show the global and regional clock input and
output connections from the Stratix II fast PLLs.
CLK8
C2
C2
RCK19
RCK17
RCK22
C3
CLK3
Fast
PLL 2
CLK2
CLK1
CLK0
Fast
PLL 1
RCK0
RCK1
RCK2
RCK3
RCK4
RCK5
RCK6
RCK7
GCK0
GCK1
GCK2
GCK3
Logic Array
Signal Input
To Clock
Network
GCK8
GCK9
GCK10
GCK11
RCK16
RCK18
RCK20
RCK21
RCK23
C1
C1
C3
C0
C0
Fast
PLL 3
CLK9
CLK10
C3
C3
C1
C2
C0
C1
C2
C0
Fast
PLL 4
CLK11
Figure 1–48. Stratix II Center Fast PLLs, Clock Pin and Logic Array Signal
Connectivity to Global and Regional Clock Networks Notes (1) and (2)
Notes to Figure 1–48:
(1)
(2)
Altera Corporation
July 2009
The redundant connection dots facilitate stitching of the clock networks to support
the ability to drive two quadrants with the same clock.
The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input.
The global or regional clock input can be driven by an output from another PLL, a
pin-driven dedicated global or regional clock, or through a clock control block,
provided the clock control block is fed by an output from another PLL or a
pin-driven dedicated global or regional clock. An internally generated global
signal cannot drive the PLL.
1–83
Stratix II Device Handbook, Volume 2
Clocking
Figure 1–49. Stratix II GX Center Fast PLLs, Clock Pin and Logic Array Signal Connectivity to Global and
Regional Clock Networks
Notes (1) and (2)
C0
CLK0
Fast
PLL 1
CLK1
C1
C2
C3
Logic Array
Signal Input
To Clock
Network
C0
Fast
PLL 2
CLK2
CLK3
C1
C2
C3
RCK0
RCK2
RCK1
RCK4
RCK3
RCK6
RCK5
GCK0
RCK7
GCK2
GCK1
GCK3
Notes to Figure 1–49:
(1)
(2)
The redundant connection dots facilitate stitching of the clock networks to support the ability to drive two
quadrants with the same clock.
The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. The global or regional clock input
can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock
control block, provided the clock control block is fed by an output from another PLL or a pin-driven dedicated
global or regional clock. An internally generated global signal cannot drive the PLL.
1–84
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
C3
C3
RCK19
RCK17
Fast
PLL 8
FPLL8CLK
FPLL7CLK
Fast
PLL 7
RCK0
RCK4
RCK1
RCK5
RCK2
RCK6
RCK3
RCK7
GCK0
GCK1
GCK2
GCK3
GCK8
GCK9
GCK10
GCK11
RCK16
RCK18
C2
C1
C2
C3
C3
C0
C2
C1
C1
C2
C0
C0
C1
RCK21
RCK20
RCK22
RCK23
C0
Fast
PLL 9
Fast
PLL 10
FPLL10CLK
FPLL9CLK
Figure 1–50. Stratix II Corner Fast PLLs, Clock Pin and Logic Array Signal
Connectivity to Global and Regional Clock Networks Note (1)
Note to Figure 1–50:
(1)
Altera Corporation
July 2009
The corner FPLLs can also be driven through the global or regional clock networks.
The global or regional clock input can be driven by an output from another PLL, a
pin-driven dedicated global or regional clock, or through a clock control block,
provided the clock control block is fed by an output from another PLL or a
pin-driven dedicated global or regional clock. An internally generated global
signal cannot drive the PLL.
1–85
Stratix II Device Handbook, Volume 2
Clock Control Block
Figure 1–51. Stratix II GX Corner Fast PLLs, Clock Pin and Logic Array Signal
Connectivity to Global and Regional Clock Networks
Note (1)
RCK1
RCK3
RCK0
RCK2
RCK4
RCK6
C0
FPLL7CLK
Fast
PLL 7
C1
C2
C3
C0
FPLL8CLK
Fast
PLL 8
C1
C2
C3
RCK5
GCK0
RCK7
GCK2
GCK1
GCK3
Note to Figure 1–51:
(1)
Clock Control
Block
The corner FPLLs can also be driven through the global or regional clock networks.
The global or regional clock input can be driven by an output from another PLL, a
pin-driven dedicated global or regional clock, or through a clock control block,
provided the clock control block is fed by an output from another PLL or a
pin-driven dedicated global or regional clock. An internally generated global
signal cannot drive the PLL.
Each global and regional clock has its own clock control block. The
control block has two functions:
■
■
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable or disable)
1–86
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Figures 1–52 and 1–53 show the global clock and regional clock select
blocks, respectively.
Figure 1–52. Stratix II Global Clock Control Block
CLKp
Pins
PLL Counter
Outputs
CLKSELECT[1..0]
(1)
2
2
CLKn
Pin
Internal
Logic
2
Static Clock
Select (2)
This Multiplexer
Supports User-Controllable
Dynamic Switching
Enable/
Disable
Internal
Logic
GCLK
Notes to Figure 1–52:
(1)
(2)
Altera Corporation
July 2009
These clock select signals can only be dynamically controlled through internal
logic when the device is operating in user mode.
These clock select signals can only be set through a configuration file and cannot
be dynamically controlled during user-mode operation.
1–87
Stratix II Device Handbook, Volume 2
Clock Control Block
Figure 1–53. Regional Clock Control Block
CLKp
Pin
PLL Counter
Outputs (3)
CLKn
Pin (2)
2
Internal
Logic
Static Clock Select (1)
Enable/
Disable
Internal
Logic
RCLK
Notes to Figure 1–53:
(1)
(2)
These clock select signals can only be dynamically controlled through a
configuration file and cannot be dynamically controlled during user-mode
operation.
Only the CLKn pins on the top and bottom for the device feed to regional clock
select blocks.
For the global clock select block, the clock source selection can be
controlled either statically or dynamically. You have the option to
statically select the clock source in configuration file generated by the
Quartus II software, or you can control the selection dynamically by
using internal logic to drive the multiplexer select inputs. When selecting
statically, the clock source can be set to any of the inputs to the select
multiplexer. When selecting the clock source dynamically, you can either
select two PLL outputs (such as CLK0 or CLK1), or a combination of clock
pins or PLL outputs.
When using the altclkctrl megafunction to implement clock source
(dynamics) selection, the inputs from the clock pins feed the
inclock[0..1] ports of the multiplexer, while the PLL outputs feed the
inclock[2..3] ports. You can choose from among these inputs using
the CLKSELECT[1..0] signal.
For the regional clock select block, the clock source selection can only be
controlled statically using configuration bits. Any of the inputs to the
clock select multiplexer can be set as the clock source.
The Stratix II and Stratix II GX clock networks can be disabled (powered
down) by both static and dynamic approaches. When a clock net is
powered down, all the logic fed by the clock net is in an off-state, thereby
reducing the overall power consumption of the device.
1–88
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
The global and regional clock networks that are not used are
automatically powered down through configuration bit settings in the
configuration file (SRAM Object File (.sof) or Programmer Object File
(.pof)) generated by the Quartus II software.
The dynamic clock enable or disable feature allows the internal logic to
control power up or down synchronously on GCLK and RCLK nets,
including dual-regional clock regions. This function is independent of the
PLL and is applied directly on the clock network, as shown in Figure 1–52
on page 1–87 and Figure 1–53 on page 1–88.
The input clock sources and the clkena signals for the global and
regional clock network multiplexers can be set through the Quartus II
software using the altclkctrl megafunction. The dedicated external
clock output pins can also be enabled or disabled using the altclkctrl
megafunction. Figure 1–54 shows the external PLL output clock control
block.
Figure 1–54. Stratix II External PLL Output Clock Control Block
PLL Counter
Outputs (c[5..0])
6
Static Clock Select (1)
Enable/
Disable
Internal
Logic
IOE (2)
Internal
Logic
Static Clock
Select (1)
PLL_OUT
Pin
Notes to Figure 1–54:
(1)
(2)
Altera Corporation
July 2009
These clock select signals can only be set through a configuration file and cannot
be dynamically controlled during user mode operation.
The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The
PLL_OUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an
internal signal or the output of the clock control block.
1–89
Stratix II Device Handbook, Volume 2
Clock Control Block
clkena Signals
Figure 1–55 shows how clkena is implemented.
Figure 1–55. clkena Implementation
clkena
D
Q
clkena_out
clk
clk_out
In Stratix II devices, the clkena signals are supported at the clock
network level. This allows you to gate off the clock even when a PLL is
not being used.
The clkena signals can also be used to control the dedicated external
clocks from enhanced PLLs. Upon re-enabling, the PLL does not need a
resynchronization or relock period unless the PLL is using external
feedback mode. Figure 1–56 shows the waveform example for a clock
output enable. clkena is synchronous to the falling edge of the counter
output.
Figure 1–56. Clkena Signals
counter
output
clkena
clkout
Note to Figure 1–56
(1)
The clkena signals can be used to enable or disable the global and regional networks or the PLL_OUT pins.
1–90
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
The PLL can remain locked independent of the clkena signals since the
loop-related counters are not affected. This feature is useful for
applications that require a low power or sleep mode. Upon re-enabling,
the PLL does not need a resynchronization or relock period. The clkena
signal can also disable clock outputs if the system is not tolerant to
frequency overshoot during resynchronization.
Conclusion
Stratix II and Stratix II GX device enhanced and fast PLLs provide you
with complete control of device clocks and system timing. These PLLs are
capable of offering flexible system-level clock management that was
previously only available in discrete PLL devices. The embedded PLLs
meet and exceed the features offered by these high-end discrete devices,
reducing the need for other timing devices in the system.
Referenced
Documents
This chapter references the following documents:
■
■
■
■
■
■
Altera Corporation
July 2009
altpll Megafunction User Guide
AN 367: Implementing PLL Reconfiguration in Stratix II Devices
Configuring Stratix II and Stratix II GX Devices chapter in volume 2 of
the Stratix II GX Device Handbook (or the Stratix II Device Handbook)
DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Device Handbook (or the Stratix II Device Handbook)
Selectable I/O Standards in Stratix II and Stratix II GX Devices chapter in
volume 2 of the Stratix II GX Device Handbook (or the Stratix II Device
Handbook)
Verification, volume 3 of the Quartus II Development Software
Handbook
1–91
Stratix II Device Handbook, Volume 2
Document Revision History
Document
Revision History
Table 1–25 shows the revision history for this chapter.
Table 1–25. Document Revision History (Part 1 of 2)
Date and
Document
Version
July 2009,
v4.6
Changes Made
●
●
Updated “Manual Override”, “Manual Clock Switchover”,
and “Spread-Spectrum Clocking” sections.
Updated notes to Figure 1–20 and Figure 1–24.
Summary of Changes
●
●
Both inclk0 and inclk1
must be running when the
clkswitch signal goes
high to initiate a manual
clock switchover.
Updated the spread
spectrum modulation
frequency from
(100 kHz–500 kHz) to
(30 kHz–150 kHz).
January 2008,
v4.5
Updated “External Clock Outputs” section.
—
Added the “Referenced Documents” section.
—
Minor text edits.
—
No change
For the Stratix II GX Device Handbook only:
Formerly chapter 6. The chapter number changed due to the
addition of the Stratix II GX Dynamic Reconfiguration chapter.
No content change.
—
May 2007,
v4.4
Updated Table 7–6.
—
Updated notes to:
Figure 7–7
● Figure 7–47
● Figure 7–48
● Figure 7–49
● Figure 7–50
● Figure 7–51
—
Updated the “Clock Source Control For Enhanced PLLs” section.
—
Updated the “Clock Source Control for Fast PLLs” section.
—
●
February 2007 Added “Document Revision History” section to this chapter.
v4.3
Deleted paragraph beginning with “The Stratix II GX PLLs
have the ability...” in the “Enhanced Lock Detect Circuit” section.
—
April 2006,
v4.2
Chapter updated as part of the Stratix II Device Handbook update.
—
No change
Formerly chapter 5. Chapter number change only due to chapter addition to Section I in February 2006; no content change.
—
1–92
Stratix II Device Handbook, Volume 2
—
Altera Corporation
July 2009
PLLs in Stratix II and Stratix II GX Devices
Table 1–25. Document Revision History (Part 2 of 2)
Date and
Document
Version
Changes Made
Summary of Changes
December
2005, v4.1
Chapter updated as part of the Stratix II Device Handbook update.
—
October 2005
v4.0
Added chapter to the Stratix II GX Device Handbook.
—
Altera Corporation
July 2009
1–93
Stratix II Device Handbook, Volume 2
Document Revision History
1–94
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009
Section II. Memory
This section provides information on the TriMatrix™ embedded memory
blocks internal to Stratix® II devices and the supported external memory
interfaces.
This section contains the following chapters:
Revision History
Altera Corporation
■
Chapter 2, TriMatrix Embedded Memory Blocks in Stratix II and
Stratix II GX Devices
■
Chapter 3, External Memory Interfaces in Stratix II and Stratix II GX
Devices
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section II–1
Preliminary
Memory
Section II–2
Preliminary
Stratix II Device Handbook, Volume 2
Altera Corporation
2. TriMatrix Embedded
Memory Blocks in Stratix II
and Stratix II GX Devices
SII52002-4.5
Introduction
Stratix® II and Stratix II GX devices feature the TriMatrix™ memory
structure, consisting of three sizes of embedded RAM blocks that
efficiently address the memory needs of FPGA designs.
TriMatrix memory includes 512-bit M512 blocks, 4-Kbit M4K blocks, and
512-Kbit M-RAM blocks, which are each configurable to support many
features. TriMatrix memory provides up to 9 megabits of RAM at up to
550 MHz operation, and up to 16 terabits per second of total memory
bandwidth per device. This chapter describes TriMatrix memory blocks,
modes, and features.
TriMatrix
Memory
Overview
The TriMatrix architecture provides complex memory functions for
different applications in FPGA designs. For example, M512 blocks are
used for first-in first-out (FIFO) functions and clock domain buffering
where memory bandwidth is critical; M4K blocks are ideal for
applications requiring medium-sized memory, such as asynchronous
transfer mode (ATM) cell processing; and M-RAM blocks are suitable for
large buffering applications, such as internet protocol (IP) packet
buffering and system cache.
The TriMatrix memory blocks support various memory configurations,
including single-port, simple dual-port, true dual-port (also known as
bidirectional dual-port), shift register, and read-only memory (ROM)
modes. The TriMatrix memory architecture also includes advanced
features and capabilities, such as parity-bit support, byte enable support,
pack mode support, address clock enable support, mixed port width
support, and mixed clock mode support.
When applied to input registers, the asynchronous clear signal for the
TriMatrix embedded memory immediately clears the input registers.
However, the output of the memory block does not show the effects until
the next clock edge. When applied to output registers, the asynchronous
clear signal clears the output registers and the effects are seen
immediately.
Altera Corporation
January 2008
2–1
TriMatrix Memory Overview
Table 2–1 summarizes the features supported by the three sizes of
TriMatrix memory.
Table 2–1. Summary of TriMatrix Memory Features
Feature
Maximum performance
Total RAM bits (including parity bits)
M512 Blocks
M4K Blocks
M-RAM Blocks
500 MHz
550 MHz
420 MHz
576
4,608
589,824
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
8K × 64
8K × 72
4K × 128
4K × 144
Parity bits
v
v
v
Byte enable
v
v
v
Pack mode
v
v
Address clock enable
v
v
Configurations
Single-port memory
v
v
v
Simple dual-port memory
v
v
v
v
v
True dual-port memory
Embedded shift register
v
v
ROM
v
v
FIFO buffer
v
v
v
Simple dual-port mixed width support
v
v
v
v
v
True dual-port mixed width support
Memory initialization file (.mif)
v
v
Mixed-clock mode
v
v
v
Power-up condition
Outputs cleared
Outputs cleared
Outputs unknown
Register clears
Output registers only
Output registers
only
Output registers
only
Same-port read-during-write
New data available at
positive clock edge
New data available
at positive clock
edge
New data available
at positive clock
edge
Mixed-port read-during-write
Outputs set to
unknown or old data
Outputs set to
Unknown output
unknown or old data
2–2
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Tables 2–2 and 2–3 show the capacity and distribution of the TriMatrix
memory blocks in each Stratix II and Stratix II GX family member,
respectively.
Table 2–2. TriMatrix Memory Capacity and Distribution in Stratix II Devices
Device
M512
M4K
Columns/Blocks Columns/Blocks
M-RAM
Blocks
Total RAM Bits
EP2S15
4/104
3/78
0
419,328
EP2S30
6/202
4/144
1
1,369,728
EP2S60
7/329
5/255
2
2,544,192
EP2S90
8/488
6/408
4
4,520,448
EP2S130
9/699
7/609
6
6,747,840
EP2S180
11/930
8/768
9
9,383,040
Table 2–3. TriMatrix Memory Capacity and Distribution in Stratix II GX
Devices
Device
M512
M4K
M-RAM
Total RAM Bits
Columns/Blocks Columns/Blocks Blocks
EP2SGX30C
EP2SGX30D
6/202
4/144
1
1,369,728
EP2SGX60C
EP2SGX60D
EP2SGX60E
7/329
5/255
2
2,544,192
EP2SGX90E
EP2SGX90F
8/488
6/408
4
4,520,448
EP2SGX130G
9/699
7/609
6
6,747,840
Parity Bit Support
All TriMatrix memory blocks (M512, M4K, and M-RAM) support one
parity bit for each byte.
Parity bits add to the amount of memory in each random access memory
(RAM) block. For example, the M512 block has 576 bits, 64 of which are
optionally used for parity bit storage. The parity bit, along with logic
implemented in adaptive logic modules (ALMs), implements parity
checking for error detection to ensure data integrity. Parity-size data
words can also be used for other purposes such as storing user-specified
control bits.
Altera Corporation
January 2008
2–3
Stratix II Device Handbook, Volume 2
TriMatrix Memory Overview
f
Refer to the Using Parity to Detect Memory Errors white paper for more
information on using the parity bit to detect memory errors.
Byte Enable Support
All TriMatrix memory blocks support byte enables that mask the input
data so that only specific bytes, nibbles, or bits of data are written. The
unwritten bytes or bits retain the previous written value. The write enable
(wren) signals, along with the byte enable (byteena) signals, control the
RAM blocks’ write operations. The default value for the byte enable
signals is high (enabled), in which case writing is controlled only by the
write enable signals. There is no clear port to the byte enable registers.
M512 Blocks
M512 blocks support byte enables for data widths of 16 and 18 bits only.
For memory block configurations with widths of less than two bytes
(×16/×18), the byte-enable feature is not supported. For memory
configurations less than two bytes wide, the write enable or clock enable
signals can optionally be used to control the write operation. Table 2–4
summarizes the byte selection.
Table 2–4. Byte Enable for Stratix II and Stratix II GX M512 Blocks
byteena[1..0]
data ×16
Note (1)
data ×18
[0] = 1
[7..0]
[8..0]
[1] = 1
[15..8]
[17..9]
Note to Table 2–4:
(1)
Any combination of byte enables is possible.
M4K Blocks
M4K blocks support byte enables for any combination of data widths of
16, 18, 32, and 36 bits only. For memory block configurations with widths
of less than two bytes (×16/×18), the byte-enable feature is not supported.
For memory configurations less than two bytes wide, the write enable or
clock enable signals can optionally be used to control the write operation.
2–4
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Table 2–5 summarizes the byte selection.
Table 2–5. Byte Enable for Stratix II and Stratix II GX M4K Blocks
Note (1)
byteena
[3..0]
data ×16
data ×18
data ×32
data ×36
[0] = 1
[7..0]
[8..0]
[7..0]
[8..0]
[1] = 1
[15..8]
[17..9]
[15..8]
[17..9]
[2] = 1
-
-
[23..16]
[26..18]
[3] = 1
-
-
[31..24]
[35..27]
Note to Table 2–5:
(1)
Any combination of byte enables is possible.
M-RAM Blocks
M-RAM blocks support byte enables for any combination of data widths
of 16, 18, 32, 36, 64, and 72 bits. For memory block configurations with
widths of less than two bytes (×16/×18), the byte-enable feature is not
supported. In the ×128 and ×144 simple dual-port modes, the two sets of
byte enable signals (byteena_a and byteena_b) combine to form the
necessary 16 byte enables. In ×128 and ×144 modes, byte enables are only
supported when using single clock mode. However, the Quartus II
software can implement byte enables in other clocking modes for ×128 or
×144 widths but will use twice as many M-RAM resources. If clock
enables are used in ×128 or ×144 mode, you must use the same clock
enable setting for both the A and B ports. Table 2–6 summarizes the byte
selection for M-RAM blocks.
Table 2–6. Byte Enable for Stratix II and Stratix II GX M-RAM Blocks Note (1)
byteena
data ×16
data ×18
data ×32
data ×36
data ×64
data ×72
[0] = 1
[7..0]
[8..0]
[7..0]
[8..0]
[7..0]
[8..0]
[1] = 1
[15..8]
[17..9]
[15..8]
[17..9]
[15..8]
[17..9]
[2] = 1
-
-
[23..16]
[26..18]
[23..16]
[26..18]
[3] = 1
-
-
[31..24]
[35..27]
[31..24]
[35..27]
[4] = 1
-
-
-
-
[39..32]
[44..36]
[5] = 1
-
-
-
-
[47..40]
[53..45]
[6] = 1
-
-
-
-
[55..48]
[62..54]
[7] = 1
-
-
-
-
[63..56]
[71..63]
Note to Table 2–6:
(1)
Any combination of byte enables is possible.
Altera Corporation
January 2008
2–5
Stratix II Device Handbook, Volume 2
TriMatrix Memory Overview
Table 2–7 summarizes the byte selection for ×144 mode.
Table 2–7. Stratix II and Stratix II GX M-RAM Combined Byte Selection for
×144 Mode Note (1)
byteena
data ×128
data ×144
[0] = 1
[7..0]
[8..0]
[1] = 1
[15..8]
[17..9]
[2] = 1
[23..16]
[26..18]
[3] = 1
[31..24]
[35..27]
[4] = 1
[39..32]
[44..36]
[5] = 1
[47..40]
[53..45]
[6] = 1
[55..48]
[62..54]
[7] = 1
[63..56]
[71..63]
[8] = 1
[71..64]
[80..72]
[9] = 1
[79..72]
[89..73]
[10] = 1
[87..80]
[98..90]
[11] = 1
[95..88]
[107..99]
[12] = 1
[103..96]
[116..108]
[13] = 1
[111..104]
[125..117]
[14] = 1
[119..112]
[134..126]
[15] = 1
[127..120]
[143..135]
Note to Table 2–7:
(1)
Any combination of byte enables is possible.
Byte Enable Functional Waveform
Figure 2–1 shows how the write enable (wren) and byte enable
(byteena) signals control the operations of the RAM.
When a byte enable bit is de-asserted during a write cycle, the
corresponding data byte output appears as a “don't care” or unknown
value. When a byte enable bit is asserted during a write cycle, the
corresponding data byte output will be the newly written data.
2–6
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–1. Stratix II and Stratix II GX Byte Enable Functional Waveform
inclock
wren
address
data
a0
an
a1
contents at a0
contents at a1
10
XX
a1
a2
XXXX
01
11
FFFF
XX
ABFF
FFFF
FFCD
FFFF
contents at a2
q (asynch)
a0
ABCD
XXXX
byteena
a2
ABCD
ABXX
doutn
1
XXCD
ABCD
ABFF
FFCD
ABCD
For more information about MRAM and byte enable for the
Stratix II device family, refer to the Stratix II FPGA Errata Sheet at
the Altera web site at www.altera.com.
Pack Mode Support
Stratix II and Stratix II GX M4K and M-RAM memory blocks support
pack mode. In M4K and M-RAM memory blocks, two single-port
memory blocks can be implemented in a single block under the following
conditions:
■
■
Each of the two independent block sizes is equal to or less than half
of the M4K or M-RAM block size.
Each of the single-port memory blocks is configured in single-clock
mode.
Thus, each of the single-port memory blocks access up to half of the M4K
or M-RAM memory resources such as clock, clock enables, and
asynchronous clear signals.
Refer to “Single-Port Mode” on page 2–10 and “Single-Clock Mode” on
page 2–28 for more information.
Altera Corporation
January 2008
2–7
Stratix II Device Handbook, Volume 2
TriMatrix Memory Overview
Address Clock Enable Support
Stratix II and Stratix II GX M4K and M-RAM memory blocks support
address clock enable, which is used to hold the previous address value for
as long as the signal is enabled. When the memory blocks are configured
in dual-port mode, each port has its own independent address clock
enable.
Figure 2–2 shows an address clock enable block diagram. Placed in the
address register, the address signal output by the address register is fed
back to the input of the register via a multiplexer. The multiplexer output
is selected by the address clock enable (addressstall) signal. Address
latching is enabled when the addressstall signal turns high. The
output of the address register is then continuously fed into the input of
the register; therefore, the address value can be held until the
addressstall signal turns low.
Figure 2–2. Stratix II and Stratix II GX Address Clock Enable Block Diagram
address[0]
1
0
address[N]
1
0
address[0]
register
address[N]
register
address[0]
address[N]
addressstall
clock
Address clock enable is typically used for cache memory applications,
which require one port for read and another port for write. The default
value for the address clock enable signals is low (disabled). Figures 2–3
and 2–4 show the address clock enable waveform during the read and
write cycles, respectively.
2–8
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–3. Stratix II and Stratix II GX Address Clock Enable During Read Cycle Waveform
inclock
rdaddress
a0
a1
a2
a3
a4
a5
a6
rden
addressstall
latched address
(inside memory)
an
q (synch) doutn-1
q (asynch)
a1
a0
dout0
doutn
dout0
doutn
dout1
dout1
dout1
dout1
dout1
a4
a5
dout1
dout4
dout4
dout5
Figure 2–4. Stratix II and Stratix II GX Address Clock Enable During Write Cycle Waveform
inclock
wraddress
a0
a1
a2
a3
a4
a5
a6
00
01
02
03
04
05
06
data
wren
addressstall
latched address
(inside memory)
contents at a0
contents at a1
an
a1
a0
XX
01
02
XX
contents at a3
XX
contents at a5
Memory Modes
Altera Corporation
January 2008
a5
00
XX
contents at a2
contents at a4
a4
03
04
XX
XX
05
Stratix II and Stratix II GX TriMatrix memory blocks include input
registers that synchronize writes, and output registers to pipeline data to
improve system performance. All TriMatrix memory blocks are fully
synchronous, meaning that all inputs are registered, but outputs can be
either registered or unregistered.
2–9
Stratix II Device Handbook, Volume 2
Memory Modes
1
TriMatrix memory does not support asynchronous memory
(unregistered inputs).
Depending on which TriMatrix memory block you use, the memory has
various modes, including:
■
■
■
■
■
■
Single-port
Simple dual-port
True dual-port (bidirectional dual-port)
Shift-register
ROM
FIFO
1
Violating the setup or hold time on the memory block address
registers could corrupt memory contents. This applies to both
read and write operations.
Single-Port Mode
All TriMatrix memory blocks support the single-port mode that supports
non-simultaneous read and write operations. Figure 2–5 shows the
single-port memory configuration for TriMatrix memory.
Figure 2–5. Single-Port Memory Note (1)
data[ ]
address[ ]
wren
byteena[]
addressstall
inclock
inclocken
q[]
outclock
outclocken
outaclr
Note to Figure 2–5:
(1)
Two single-port memory blocks can be implemented in a single M4K or M-RAM
block.
M4K and M-RAM memory blocks can also be halved and used for two
independent single-port RAM blocks. The Altera® Quartus® II software
automatically uses this single-port memory packing when running low
on memory resources. To force two single-port memories into one M4K
or M-RAM block, first ensure that each of the two independent RAM
blocks is equal to or less than half the size of the M4K or M-RAM block.
Secondly, assign both single-port RAMs to the same M4K or M-RAM
block.
2–10
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
In single-port RAM configuration, the outputs can only be in
read-during-write mode, which means that during the write operation,
data written to the RAM flows through to the RAM outputs. When the
output registers are bypassed, the new data is available on the rising edge
of the same clock cycle on which it was written. Refer to “Read-DuringWrite Operation at the Same Address” on page 2–33 for more information
about read-during-write mode. Table 2–8 shows the port width
configurations for TriMatrix blocks in single-port mode.
Table 2–8. Stratix II and Stratix II GX Port Width Configurations for M512,
M4K, and M-RAM Blocks (Single-Port Mode)
Port Width
Configurations
M512 Blocks
M4K Blocks
M-RAM Blocks
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
Figure 2–6 shows timing waveforms for read and write operations in
single-port mode.
Figure 2–6. Stratix II and Stratix II GX Single-Port Timing Waveforms
inclock
wren
address
an-1
an
data (1)
din-1
din
q (synch)
q (asynch)
din-2
din-1
a0
a1
a2
a3
a4
din4
din-1
din
din
dout0
dout0
dout1
dout1
dout2
dout2
dout3
a5
a6
din5
din6
dout3
din4
din4
din5
Note to Figure 2–6:
(1)
The crosses in the data waveform during read mean “don’t care.”
Altera Corporation
January 2008
2–11
Stratix II Device Handbook, Volume 2
Memory Modes
Simple Dual-Port Mode
All TriMatrix memory blocks support simple dual-port mode which
supports a simultaneous read and write operation. Figure 2–7 shows the
simple dual-port memory configuration for TriMatrix memory.
Figure 2–7. Stratix II and Stratix II GX Simple Dual-Port Memory Note (1)
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
rdaddress[ ]
rden
q[ ]
rd_addressstall
rdclock
rdclocken
rd_aclr
Note to Figure 2–7:
(1)
Simple dual-port RAM supports input/output clock mode in addition to the
read/write clock mode shown.
2–12
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
TriMatrix memory supports mixed-width configurations, allowing
different read and write port widths. Tables 2–9 through 2–11 show the
mixed width configurations for the M512, M4K, and M-RAM blocks,
respectively.
Table 2–9. Stratix II and Stratix II GX M512 Block Mixed-Width
Configurations (Simple Dual-Port Mode)
Write Port
Read Port
512 × 1 256 × 2 128 × 4
64 × 8
32 × 16
64 × 9
32 × 18
64 × 9
v
v
32 × 18
v
v
512 × 1
v
v
v
v
v
256 × 2
v
v
v
v
v
128 × 4
v
v
v
v
v
64 × 8
v
v
v
v
v
32 × 16
v
v
v
v
v
Table 2–10. Stratix II and Stratix II GX M4K Block Mixed-Width Configurations (Simple Dual-Port Mode)
Write Port
Read Port
4K × 1
2K × 2
1K × 4
512 × 8 256 × 16 128 × 32 512 × 9 256 × 18 128 × 36
4K × 1
v
v
v
v
v
v
2K × 2
v
v
v
v
v
v
1K × 4
v
v
v
v
v
v
512 × 8
v
v
v
v
v
v
256 × 16
v
v
v
v
v
v
128 × 32
v
v
v
v
v
v
512 × 9
v
v
v
256 × 18
v
v
v
128 × 36
v
v
v
Altera Corporation
January 2008
2–13
Stratix II Device Handbook, Volume 2
Memory Modes
Table 2–11. Stratix II and Stratix II GX M-RAM Block Mixed-Width
Configurations (Simple Dual-Port Mode)
Write Port
Read Port
64K × 9
32K × 18
18K × 36
8K × 72
64K × 9
v
v
v
v
32K × 18
v
v
v
v
18K × 36
v
v
v
v
8K × 72
v
v
v
v
4K × 144
4K × 144
v
In simple dual-port mode, M512 and M4K blocks have one write enable
and one read enable signal. However, M-RAM blocks contain only a
write-enable signal, which is held high to perform a write operation.
M-RAM blocks are always enabled for read operations. If the read
address and the write address select the same address location during a
write operation, M-RAM block output is unknown.
TriMatrix memory blocks do not support a clear port on the write enable
and read enable registers. When the read enable is deactivated, the
current data is retained at the output ports. If the read enable is activated
during a write operation with the same address location selected, the
simple dual-port RAM output is either unknown or can be set to output
the old data stored at the memory address. Refer to “Read-During-Write
Operation at the Same Address” on page 2–33 for more information.
Figure 2–8 shows timing waveforms for read and write operations in
simple dual-port mode.
2–14
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–8. Stratix II and Stratix II GX Simple Dual-Port Timing Waveforms
wrclock
wren
wraddress
an-1
data (1)
din-1
a0
an
a1
a2
din
a3
a4
a5
din4
din5
a6
din6
rdclock
rden (2)
rdaddress
bn
q (synch) doutn-2
q (asynch)
doutn-1
b1
b0
doutn-1
b2
b3
dout0
doutn
dout0
doutn
Notes to Figure 2–8:
(1)
(2)
The crosses in the data waveform during read mean “don’t care.”
The read enable rden signal is not available in M-RAM blocks. The M-RAM block in simple dual-port mode always
reads out the data stored at the current read address location.
True Dual-Port Mode
Stratix II and Stratix II GX M4K and M-RAM memory blocks support the
true dual-port mode. True dual-port mode supports any combination of
two-port operations: two reads, two writes, or one read and one write at
two different clock frequencies. Figure 2–9 shows Stratix II and
Stratix II GX true dual-port memory configuration.
Figure 2–9. Stratix II and Stratix II GX True Dual-Port Memory Note (1)
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
clock_a
enable_a
aclr_a
q_a[]
data_b[ ]
address_b[]
wren_b
byteena_b[]
addressstall_b
clock_b
enable_b
aclr_b
q_b[]
Note to Figure 2–9:
(1)
Altera Corporation
January 2008
True dual-port memory supports input/output clock mode in addition to the
independent clock mode shown.
2–15
Stratix II Device Handbook, Volume 2
Memory Modes
The widest bit configuration of the M4K and M-RAM blocks in true dualport mode is as follows:
■
■
256 × 16-bit (×18-bit with parity) (M4K)
8K × 64-bit (×72-bit with parity) (M-RAM)
The 128 × 32-bit (×36-bit with parity) configuration of the M4K block and
the 4K × 128-bit (×144-bit with parity) configuration of the M-RAM block
are unavailable because the number of output drivers is equivalent to the
maximum bit width of the respective memory block. Because true
dual-port RAM has outputs on two ports, the maximum width of the true
dual-port RAM equals half of the total number of output drivers.
Table 2–12 lists the possible M4K block mixed-port width configurations.
Table 2–12. Stratix II and Stratix II GX M4K Block Mixed-Port Width Configurations (True Dual-Port)
Write Port
Read Port
4K × 1
2K × 2
1K × 4
512 × 8
256 × 16
512 × 9
256 × 18
4K × 1
v
v
v
v
v
2K × 2
v
v
v
v
v
1K × 4
v
v
v
v
v
512 × 8
v
v
v
v
v
256 × 16
v
v
v
v
v
512 × 9
v
v
256 × 18
v
v
Table 2–13 lists the possible M-RAM block mixed-port width
configurations.
Table 2–13. Stratix II and Stratix II GX M-RAM Block Mixed-Port Width
Configurations (True Dual-Port)
Write Port
Read Port
64K × 9
32K × 18
18K × 36
8K × 72
64K × 9
v
v
v
v
32K × 18
v
v
v
v
18K × 36
v
v
v
v
8K × 72
v
v
v
v
2–16
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
In true dual-port configuration, the RAM outputs can only be configured
for read-during-write mode. This means that during write operation,
data being written to the A or B port of the RAM flows through to the A
or B outputs, respectively. When the output registers are bypassed, the
new data is available on the rising edge of the same clock cycle on which
it was written. Refer to “Read-During-Write Operation at the Same
Address” on page 2–33 for waveforms and information on mixed-port
read-during-write mode.
Potential write contentions must be resolved external to the RAM because
writing to the same address location at both ports results in unknown
data storage at that location. For a valid write operation to the same
address of the M-RAM block, the rising edge of the write clock for port A
must occur following the maximum write cycle time interval after the
rising edge of the write clock for port B. Data is written on the rising edge
of the write clock for the M-RAM block.
Because data is written into the M512 and M4K blocks at the falling edge
of the write clock, the rising edge of the write clock for port A should
occur following half of the maximum write cycle time interval after the
falling edge of the write clock for port B. If this timing is not met, the data
stored in that particular address will be invalid.
f
Altera Corporation
January 2008
Refer to the Stratix II Device Family Data Sheet (volume 1) of the Stratix II
Device Handbook or the Stratix II GX Device Family Data Sheet (volume 1)
of the Stratix II GX Device Handbook for the maximum synchronous write
cycle time.
2–17
Stratix II Device Handbook, Volume 2
Memory Modes
Figure 2–10 shows true dual-port timing waveforms for the write
operation at port A and the read operation at port B.
Figure 2–10. Stratix II and Stratix II GX True Dual-Port Timing Waveforms
clk_a
wren_a
address_a
an-1
an
data_a (1)
din-1
din
din-2
q_a (synch)
q_a (asynch)
a0
din-1
din-1
din
a1
a2
dout0
din
dout0
dout1
a3
dout1
dout2
a4
a5
a6
din4
din5
din6
dout2
dout3
din4
dout3
din5
din4
clk_b
wren_b
address_b
bn
q_b (synch)
doutn-2
q_b (asynch)
doutn-1
b1
b0
doutn-1
doutn
doutn
dout0
b2
dout0
dout1
b3
dout1
dout2
Note to Figure 2–10:
(1)
The crosses in the data_a waveform during write mean “don’t care.”
Shift-Register Mode
All Stratix II memory blocks support the shift register mode.
Embedded memory block configurations can implement shift registers
for digital signal processing (DSP) applications, such as finite impulse
response (FIR) filters, pseudo-random number generators, multi-channel
filtering, and auto-correlation and cross-correlation functions. These and
other DSP applications require local data storage, traditionally
implemented with standard flip-flops that quickly exhaust many logic
cells for large shift registers. A more efficient alternative is to use
embedded memory as a shift-register block, which saves logic cell and
routing resources.
The size of a (w × m × n) shift register is determined by the input data
width (w), the length of the taps (m), and the number of taps (n), and
must be less than or equal to the maximum number of memory bits in the
respective block: 576 bits for the M512 block, 4,608 bits for the M4K block,
and 589,824 bits for the MRAM block. In addition, the size of w × n must
be less than or equal to the maximum width of the respective block: 18
2–18
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
bits for the M512 block, 36 bits for the M4K block, and 144 bits for the
MRAM block. If a larger shift register is required, the memory blocks can
be cascaded.
In M512 and M4K blocks, data is written into each address location at the
falling edge of the clock and read from the address at the rising edge of
the clock. The shift-register mode logic automatically controls the
positive and negative edge clocking to shift the data in one clock cycle.
The MRAM block performs reads and writes on the rising edge.
Figure 2–11 shows the TriMatrix memory block in the shift-register mode.
Figure 2–11. Stratix II and Stratix II GX Shift-Register Memory Configuration
w × m × n Shift Register
m-Bit Shift Register
W
W
m-Bit Shift Register
W
W
n Number of Taps
m-Bit Shift Register
W
W
m-Bit Shift Register
W
Altera Corporation
January 2008
W
2–19
Stratix II Device Handbook, Volume 2
Clock Modes
ROM Mode
M512 and M4K memory blocks support ROM mode. A memory
initialization file (.mif) initializes the ROM contents of these blocks. The
address lines of the ROM are registered. The outputs can be registered or
unregistered. The ROM read operation is identical to the read operation
in the single-port RAM configuration.
FIFO Buffers Mode
TriMatrix memory blocks support the FIFO mode. M512 memory blocks
are ideal for designs with many shallow FIFO buffers. All memory
configurations have synchronous inputs; however, the FIFO buffer
outputs are always combinational. Simultaneous read and write from an
empty FIFO buffer is not supported.
f
Clock Modes
Refer to the Single- and Dual-Clock FIFO Megafunctions User Guide and
FIFO Partitioner Megafunction User Guide for more information on FIFO
buffers.
Depending on which TriMatrix memory mode is selected, the following
clock modes are available:
■
■
■
■
Independent
Input/output
Read/write
Single-clock
Table 2–14 shows these clock modes supported by all TriMatrix blocks
when configured as respective memory modes.
Table 2–14. Stratix II and Stratix II GX TriMatrix Memory Clock Modes
Clocking Modes
True Dual-Port
Mode
Independent
v
Input/output
v
2–20
Stratix II Device Handbook, Volume 2
v
v
v
Read/write
Single clock
Simple Dual-Port
Single-Port Mode
Mode
v
v
v
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Independent Clock Mode
The TriMatrix memory blocks can implement independent clock mode
for true dual-port memory. In this mode, a separate clock is available for
each port (A and B). Clock A controls all registers on the port A side,
while clock B controls all registers on the port B side. Each port also
supports independent clock enables for port A and B registers.
Asynchronous clear signals for the registers, however, are supported.
Altera Corporation
January 2008
2–21
Stratix II Device Handbook, Volume 2
(1)
2–22
Stratix II Device Handbook, Volume 2
clock_a
enable_a
wren_a
addressstall_a
address_a[ ]
byteena_a[ ]
data_a[ ]
6
ENA
D
ENA
D
ENA
D
ENA
D
6 LAB Row Clocks
Q
Q
Q
Q
Write
Pulse
Generator
Q
Data Out
Write/Read
Enable
Data In
B
q_a[ ] q_b[ ]
Q
D
ENA
Data Out
Write/Read
Enable
Address Clock
Enable B
Address B
Byte Enable B
Memory Block
256 × 16 (2)
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Address Clock
Enable A
Address A
ENA
D
A
Byte Enable A
Data In
Write
Pulse
Generator
Q
Q
Q
Q
D
ENA
ENA
D
ENA
D
ENA
D
6
clock_b
enable_b
wren_b
addressstall_b
address_b[ ]
byteena_b[ ]
data_b[ ]
Clock Modes
Figure 2–12 shows a TriMatrix memory block in independent clock mode.
Figure 2–12. Stratix II and Stratix II GX TriMatrix Memory Block in Independent
Clock Mode
Note (1)
Note to Figure 2–12:
Violating the setup or hold time on the memory block address registers could
corrupt the memory contents. This applies to both read and write operations.
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Input/Output Clock Mode
Stratix II and Stratix II GX TriMatrix memory blocks can implement
input/output clock mode for true and simple dual-port memory. On each
of the two ports, A and B, one clock controls all registers for the following
inputs into the memory block: data input, write enable, and address. The
other clock controls the blocks’ data output registers. Each memory block
port also supports independent clock enables for input and output
registers. Asynchronous clear signals for the registers, however, are not
supported.
Figures 2–13 through 2–15 show the memory block in input/output clock
mode for true dual-port, simple dual-port, and single-port modes,
respectively.
Altera Corporation
January 2008
2–23
Stratix II Device Handbook, Volume 2
(1)
2–24
Stratix II Device Handbook, Volume 2
inclock
inclocken
wren_a
addressstall_a
address_a[ ]
byteena_a[ ]
data_a[ ]
6
ENA
D
ENA
D
ENA
D
ENA
D
6 LAB Row Clocks
Q
Q
Q
Q
Write
Pulse
Generator
Q
Data Out
Write/Read
Enable
Data In
B
q_a[ ] q_b[ ]
Q
D
ENA
Data Out
Write/Read
Enable
Address Clock
Enable B
Address B
Byte Enable B
Memory Block
256 × 16 (2)
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Address Clock
Enable A
Address A
ENA
D
A
Byte Enable A
Data In
Write
Pulse
Generator
Q
Q
Q
Q
ENA
D
ENA
D
ENA
D
ENA
D
6
outclock
outclocken
wren_b
addressstall_b
address_b[ ]
byteena_b[ ]
data_b[ ]
Clock Modes
Figure 2–13. Stratix II and Stratix II GX Input/Output Clock Mode in True
Dual-Port Mode
Note (1)
Note to Figure 2–13:
Violating the setup or hold time on the memory block address registers could
corrupt the memory contents. This applies to both read and write operations.
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–14. Stratix II and Stratix II GX Input/Output Clock Mode in Simple Dual-Port Mode
Note (1)
6 LAB Row
Clocks
Memory Block
256 ´ 16
Data In 512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
6
data[ ]
D
Q
ENA
rdaddress[ ]
D
Q
ENA
Read Address
Data Out
byteena[ ]
D
Q
ENA
Byte Enable
wraddress[ ]
D
Q
ENA
Write Address
rd_addressstall
Read Address
Clock Enable
wr_addressstall
Write Address
Clock Enable
D
Q
ENA
To MultiTrack
Interconnect (3)
rden (2)
Read Enable
D
Q
ENA
wren
Write Enable
outclocken
inclocken
inclock
D
Q
ENA
Write
Pulse
Generator
outclock
Notes to Figure 2–14:
(1)
(2)
(3)
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
The read enable rden signal is not available in the M-RAM block. An M-RAM block in simple dual-port mode is
always reading out the data stored at the current read address location.
Refer to the Stratix II Device Family Data Sheet (volume 1) of the Stratix II Device Handbook or the Stratix II GX Device
Family Data Sheet (volume 1) of the Stratix II GX Device Handbook for more information on the MultiTrack™
interconnect.
Altera Corporation
January 2008
2–25
Stratix II Device Handbook, Volume 2
Clock Modes
Figure 2–15. Stratix II and Stratix II GX Input/Output Clock Mode in Single-Port Mode
Note (1)
6 LAB Row
Clocks
Memory Block
256 ´ 16
Data In 512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
6
data[ ]
D
Q
ENA
address[ ]
D
Q
ENA
Address
Data Out
byteena[ ]
Byte Enable
D
Q
ENA
D
Q
ENA
To MultiTrack
Interconnect (2)
Address
Clock Enable
addressstall
wren
Write Enable
outclocken
inclocken
D
Q
ENA
inclock
Write
Pulse
Generator
outclock
Notes to Figure 2–15:
(1)
(2)
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
Refer to the Stratix II Device Family Data Sheet (volume 1) of the Stratix II Device Handbook or the Stratix II GX Device
Family Data Sheet (volume 1) of the Stratix II GX Device Handbook for more information on the MultiTrack
interconnect.
Read/Write Clock Mode
Stratix II and Stratix II GX TriMatrix memory blocks can implement
read/write clock mode for simple dual-port memory. This mode uses up
to two clocks. The write clock controls the blocks’ data inputs, write
address, and write enable signals. The read clock controls the data output,
read address, and read enable signals. The memory blocks support
independent clock enables for each clock for the read- and write-side
registers. Asynchronous clear signals for the registers, however, are not
supported. Figure 2–16 shows a memory block in read/write clock mode.
2–26
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–16. Stratix II and Stratix II GX Read/Write Clock Mode
Note (1)
6 LAB Row
Clocks
Memory Block
256 ´ 16
Data In 512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
6
data[ ]
D
Q
ENA
rdaddress[ ]
D
Q
ENA
Read Address
Data Out
byteena[ ]
D
Q
ENA
Byte Enable
wraddress[ ]
D
Q
ENA
Write Address
rd_addressstall
Read Address
Clock Enable
wr_addressstall
Write Address
Clock Enable
D
Q
ENA
To MultiTrack
Interconnect (3)
rden (2)
Read Enable
D
Q
ENA
wren
Write Enable
rdclocken
wrclocken
wrclock
D
Q
ENA
Write
Pulse
Generator
rdclock
Notes to Figure 2–16:
(1)
(2)
(3)
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
The read enable rden signal is not available in the M-RAM block. An M-RAM block in simple dual-port mode is
always reading the data stored at the current read address location.
Refer to the Stratix II Device Family Data Sheet (volume 1) of the Stratix II Device Handbook or the Stratix II GX Device
Family Data Sheet (volume 1) of the Stratix II GX Device Handbook for more information on the MultiTrack
interconnect.
Altera Corporation
January 2008
2–27
Stratix II Device Handbook, Volume 2
Clock Modes
Single-Clock Mode
Stratix II and Stratix II GX TriMatrix memory blocks implement
single-clock mode for true dual-port, simple dual-port, and single-port
memory. In this mode, a single clock, together with clock enable, is used
to control all registers of the memory block. Asynchronous clear signals
for the registers, however, are not supported. Figures 2–17 through 2–19
show the memory block in single-clock mode for true dual-port, simple
dual-port, and single-port modes, respectively.
2–28
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
(1)
Altera Corporation
January 2008
clock
enable
wren_a
addressstall_a
address_a[ ]
byteena_a[ ]
data_a[ ]
6
ENA
D
ENA
D
ENA
D
ENA
D
6 LAB Row Clocks
Q
Q
Q
Q
Write
Pulse
Generator
Q
Data Out
Write/Read
Enable
Data In
B
q_a[ ] q_b[ ]
Q
D
ENA
Data Out
Write/Read
Enable
Address Clock
Enable B
Address B
Byte Enable B
Memory Block
256 × 16 (2)
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
Address Clock
Enable A
Address A
ENA
D
A
Byte Enable A
Data In
Write
Pulse
Generator
Q
Q
Q
Q
ENA
D
ENA
D
ENA
D
ENA
D
6
wren_b
addressstall_b
address_b[ ]
byteena_b[ ]
data_b[ ]
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–17. Stratix II and Stratix II GX Single-Clock Mode in True Dual-Port
Mode
Note (1)
Note to Figure 2–17:
Violating the setup or hold time on the memory block address registers could
corrupt the memory contents. This applies to both read and write operations.
2–29
Stratix II Device Handbook, Volume 2
Clock Modes
Figure 2–18. Stratix II andStratix II GX Single-Clock Mode in Simple Dual-Port Mode
Note (1)
6 LAB Row
Clocks
Memory Block
256 ´ 16
Data In 512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
6
data[ ]
D
Q
ENA
rdaddress[ ]
D
Q
ENA
Read Address
Data Out
byteena[ ]
D
Q
ENA
Byte Enable
wraddress[ ]
D
Q
ENA
Write Address
rd_addressstall
Read Address
Clock Enable
wr_addressstall
Write Address
Clock Enable
D
Q
ENA
To MultiTrack
Interconnect (3)
rden (2)
Read Enable
D
Q
ENA
wren
Write Enable
enable
D
Q
ENA
clock
Write
Pulse
Generator
Notes to Figure 2–18:
(1)
(2)
(3)
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
The read enable rden signal is not available in the M-RAM block. An M-RAM block in simple dual-port mode is
always reading the data stored at the current read address location.
Refer to the Stratix II Device Family Data Sheet (volume 1) of the Stratix II Device Handbook or the Stratix II GX Device
Family Data Sheet (volume 1) of the Stratix II GX Device Handbook for more information on the MultiTrack
interconnect.
2–30
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–19. Stratix II and Stratix II GX Single-Clock Mode in Single-Port Mode
Note (1)
6 LAB Row
Clocks
Memory Block
256 ´ 16
Data In 512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
6
data[ ]
D
Q
ENA
address[ ]
D
Q
ENA
Address
Data Out
byteena[ ]
Byte Enable
D
Q
ENA
D
Q
ENA
To MultiTrack
Interconnect (2)
Address
Clock Enable
addressstall
wren
Write Enable
enable
clock
D
Q
ENA
Write
Pulse
Generator
Notes to Figure 2–19:
(1)
(2)
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
Refer to the Stratix II Device Family Data Sheet (volume 1) of the Stratix II Device Handbook or the Stratix II GX Device
Family Data Sheet (volume 1) of the Stratix II GX Device Handbook for more information on the MultiTrack
interconnect.
Designing With
TriMatrix
Memory
When instantiating TriMatrix memory, it is important to understand the
features that set it apart from other memory architectures. The following
sections describe the unique attributes and functionality of TriMatrix
memory.
Selecting TriMatrix Memory Blocks
The Quartus II software automatically partitions user-defined memory
into embedded memory blocks using the most efficient size
combinations. The memory can also be manually assigned to a specific
block size or a mixture of block sizes. Table 2–1 on page 2–2 is a guide for
selecting a TriMatrix memory block size based on supported features.
Altera Corporation
January 2008
2–31
Stratix II Device Handbook, Volume 2
Designing With TriMatrix Memory
f
Refer to AN 207: TriMatrix Memory Selection Using the Quartus II Software
for more information on selecting the appropriate memory block.
Synchronous and Pseudo-Asynchronous Modes
The TriMatrix memory architecture implements synchronous RAM by
registering the input and output signals to the RAM block. The inputs to
all TriMatrix memory blocks are registered providing synchronous write
cycles, while the output registers can be bypassed. In a synchronous
operation, RAM generates its own self-timed strobe write enable signal
derived from the global or regional clock. In contrast, a circuit using
asynchronous RAM must generate the RAM write enable signal while
ensuring that its data and address signals meet setup and hold time
specifications relative to the write enable signal. During a synchronous
operation, the RAM is used in pipelined mode (inputs and outputs
registered) or flow-through mode (only inputs registered). However, in
an asynchronous memory, neither the input nor the output is registered.
While Stratix II and Stratix II GX devices do not support asynchronous
memory, they do support a pseudo-asynchronous read where the output
data is available during the clock cycle when the read address is driven
into it. Pseudo-asynchronous reading is possible in the simple and true
dual-port modes of the M512 and M4K blocks by clocking the read enable
and read address registers on the negative clock edge and bypassing the
output registers.
f
Refer to AN 210: Converting Memory from Asynchronous to Synchronous for
Stratix and Stratix GX Designs for more information.
Power-up Conditions and Memory Initialization
Upon power up, TriMatrix memory is in an idle state. The M512 and M4K
block outputs always power-up to zero, regardless of whether the output
registers are used or bypassed. Even if an MIF is used to pre-load the
contents of the RAM block, the outputs will still power-up as cleared. For
example, if address 0 is pre-initialized to FF, the M512 and M4K blocks
power up with the output at 00.
M-RAM blocks do not support MIFs; therefore, they cannot be pre-loaded
with data upon power up. M-RAM blocks asynchronous outputs and
memory controls always power up to an unknown state. If M-RAM block
outputs are registered, the registers power up as cleared. When a read is
performed immediately after power up, the output from the read
operation will be undefined since the M-RAM contents are not initialized.
The read operation will continue to be undefined for a given address until
a write operation is performed for that address.
2–32
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Read-DuringWrite Operation
at the Same
Address
The “Same-Port Read-During-Write Mode” on page 2–33 and “MixedPort Read-During-Write Mode” on page 2–34 sections describe the
functionality of the various RAM configurations when reading from an
address during a write operation at that same address. There are two
read-during-write data flows: same-port and mixed-port. Figure 2–20
shows the difference between these flows.
Figure 2–20. Stratix II and Stratix II GX Read-During-Write Data Flow
Port A
data in
Port B
data in
Mixed-port
data flow
Same-port
data flow
Port A
data out
Port B
data out
Same-Port Read-During-Write Mode
For read-during-write operation of a single-port RAM or the same port of
a true dual-port RAM, the new data is available on the rising edge of the
same clock cycle on which it was written. This behavior is valid on all
memory block sizes. Figure 2–21 shows a sample functional waveform.
When using byte enables in true dual-port RAM mode, the outputs for
the masked bytes on the same port are unknown (refer to Figure 2–1 on
page 2–7). The non-masked bytes are read out as shown in Figure 2–21.
Altera Corporation
January 2008
2–33
Stratix II Device Handbook, Volume 2
Read-During-Write Operation at the Same Address
Figure 2–21. Stratix II and Stratix II GX Same-Port Read-During-Write
Functionality Note (1)
inclock
data
A
B
wren
q Old
A
Note to Figure 2–21:
(1)
Outputs are not registered.
Mixed-Port Read-During-Write Mode
This mode is used when a RAM in simple or true dual-port mode has one
port reading and the other port writing to the same address location with
the same clock.
The READ_DURING_WRITE_MODE_MIXED_PORTS parameter for M512
and M4K memory blocks determines whether to output the old data at
the address or a “don’t care” value. Setting this parameter to OLD_DATA
outputs the old data at that address. Setting this parameter to DONT_CARE
outputs a “don’t care” or unknown value. Figures 2–22 and 2–23 show
sample functional waveforms where both ports have the same address.
These figures assume that the outputs are not registered.
The DONT_CARE setting allows memory implementation in any TriMatrix
memory block, whereas the OLD_DATA setting restricts memory
implementation to only M512 or M4K memory blocks. Selecting
DONT_CARE gives the compiler more flexibility when placing memory
functions into TriMatrix memory.
The RAM outputs are unknown for a mixed-port read-during-write
operation of the same address location of an M-RAM block, as shown in
Figure 2–23.
2–34
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–22. Stratix II and Stratix II GX Mixed-Port Read-During-Write:
OLD_DATA
inclock
address_a and
address_b
data_a
Address Q
A
B
wren_a
wren_b
q_b
Old
A
B
Figure 2–23. Stratix II and Stratix II GX Mixed-Port Read-During-Write:
DONT_CARE
inclock
address_a and
address_b
data_a
Address Q
A
B
wren_a
wren_b
q_b
Unknown
B
Mixed-port read-during-write is not supported when two different clocks
are used in a dual-port RAM. The output value is unknown during a
mixed-port read-during-write operation.
Conclusion
Altera Corporation
January 2008
The TriMatrix memory structure of Stratix II and Stratix II GX devices
provides an enhanced RAM architecture with high memory bandwidth.
It addresses the needs of different memory applications in FPGA designs
with features such as different memory block sizes and modes, byte
enables, parity bit storage, address clock enables, mixed clock mode, shift
register mode, mixed-port width support, and true dual-port mode.
2–35
Stratix II Device Handbook, Volume 2
Referenced Documents
Referenced
Documents
This chapter references the following documents:
■
■
■
■
■
■
■
Document
Revision History
AN 207: TriMatrix Memory Selection Using the Quartus II Software
AN 210: Converting Memory from Asynchronous to Synchronous for
Stratix and Stratix GX Designs
FIFO Partitioner Megafunction User Guide
Single- and Dual-Clock FIFO Megafunctions User Guide
Stratix II Device Family Data Sheet (volume 1) of the Stratix II Device
Handbook
Stratix II GX Device Family Data Sheet (volume 1) of the Stratix II GX
Device Handbook
Using Parity to Detect Memory Errors white paper
Table 2–15 shows the revision history for this chapter.
Table 2–15. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
January 2008,
v4.5
Added “Referenced Documents” section.
—
Minor text edits.
—
No change
For the Stratix II GX Device Handbook only:
Formerly chapter 7. The chapter number changed due to
the addition of the Stratix II GX Dynamic Reconfiguration
chapter. No content change.
—
May 2007,
v4.4
Added note to “Byte Enable Functional Waveform” section.
—
Updated “Byte Enable Support” section.
—
February 2007
v4.3
Added the “Document Revision History” section to this
chapter.
—
April 2006,
v4.2
Chapter updated as part of the Stratix II Device Handbook
update.
—
No change
Formerly chapter 6. Chapter number change only due to
chapter addition to Section I in February 2006; no content
change.
—
December
2005, v4.1
Chapter updated as part of the Stratix II Device Handbook
update.
—
October 2005
v4.0
Added chapter to the Stratix II GX Device Handbook.
—
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Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
3. External Memory
Interfaces in Stratix II and
Stratix II GX Devices
SII52003-4.5
Introduction
Stratix® II and Stratix II GX devices support a broad range of external
memory interfaces such as double data rate (DDR) SDRAM, DDR2
SDRAM, RLDRAM II, QDRII SRAM, and single data rate (SDR) SDRAM.
Its dedicated phase-shift circuitry allows the Stratix II or Stratix II GX
device to interface with an external memory at twice the system clock
speed (up to 300 MHz/600 megabits per second (Mbps) with
RLDRAM II). In addition to external memory interfaces, you can also use
the dedicated phase-shift circuitry for other applications that require a
shifted input signal.
Typical I/O architectures transmit a single data word on each positive
clock edge and are limited to the associated clock speed. To achieve a
400-Mbps transfer rate, a SDR system requires a 400-MHz clock. Many
new applications have introduced a DDR I/O architecture as an
alternative to SDR architectures. While SDR architectures capture data on
one edge of a clock, the DDR architectures captures data on both the
rising and falling edges of the clock, doubling the throughput for a given
clock frequency and accelerating performance. For example, a 200-MHz
clock can capture a 400-Mbps data stream, enhancing system
performance and simplifying board design.
Most new memory architectures use a DDR I/O interface. Although
Stratix II and Stratix II GX devices also support the mature and well
established SDR external memory, this chapter focuses on DDR memory
standards. These DDR memory standards cover a broad range of
applications for embedded processor systems, image processing, storage,
communications, and networking.
Stratix II devices offer external memory support in every I/O bank. The
side I/O banks support the PLL-based interfaces running at up to
200 MHz, while the top and bottom I/O banks support PLL- and
DLL-based interfaces. Figure 3–1 shows Stratix II device memory
support.
Altera Corporation
January 2008
3–1
Introduction
Figure 3–1. External Memory Support
DQS8T
VREF0B3
DQS7T
VREF1B3
DQS6T
VREF2B3
DQS5T
VREF3B3
VREF4B3
PLL11
PLL5
Bank 11
Bank 9
DQS4T
DQS3T
DQS2T
DQS1T
DQS0T
VREF0B4
VREF1B4
VREF2B4
VREF3B4
VREF4B4
PLL7
PLL10
VR EF1B 5
PLL1
PLL4
Support PLL-Based
Implementation
Support PLL-Based
Implementation
VR EF1B6
VREF 3B6
VREF 4B6
VREF 0B1
VREF 1B1
Support PLL- and
DLL-Based Implementations
VREF 2B6
Bank 6
Bank 1
VR EF3B1
VR EF0B6
PLL3
VR EF4B1
PLL2
VREF 2B1
VR EF2B5
Bank 5
VREF 4B5
VREF 0B2
VR EF3B5
Bank 2
Support PLL- and
DLL-Based Implementations
VR EF1B2
VR EF2B2
VR EF3B 2
VREF 0B5
Bank 4
VREF 4B2
Bank 3
Bank 12
Bank 8
Bank 10
Bank 7
PLL8
PLL9
VREF4B8
DQS8B
VREF3B8
VREF2B8
DQS7B
VREF1B8
DQS6B
3–2
Stratix II Device Handbook, Volume 2
VREF0B8
DQS5B
PLL12
PLL6
VREF4B7
VREF3B7
VREF2B7
VREF1B7
VREF0B7
DQS4B
DQS3B
DQS2B
DQS1B
DQS0B
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Table 3–1 summarizes the maximum clock rate Stratix II and Stratix II GX
devices can support with external memory devices.
Table 3–1. Stratix II and Stratix II GX Maximum Clock Rate Support for External Memory Interfaces
Notes (1), (2)
–3 Speed Grade (MHz)
–4 Speed Grade (MHz)
–5 Speed Grade (MHz)
Memory Standards
DLL-Based
PLL-Based
DLL-Based PLL-Based
DDR2 SDRAM (3), (5)
333
200
267
DDR SDRAM (3)
200
150
200
DLL-Based
PLL-Based
167
233
167
133
200
100
RLDRAM II
300
200
250 (4)
175
200
175
QDRII SRAM
300
200
250
167
250
167
QDRII+ SRAM
300
(6)
250
(6)
250
(6)
Notes to Table 3–1:
(1)
(2)
(3)
(4)
(5)
(6)
Memory interface timing specifications are dependent on the memory, board, physical interface, and core logic.
Refer to each memory interface application note for more details on how each specification was generated.
The respective Altera MegaCore function and the EP2S60F1020C3 timing information featured in the Quartus® II
software version 6.0 was used to define these clock rates.
This applies for interfaces with both modules and components.
You must underclock a 300-MHz RLDRAM II device to achieve this clock rate.
To achieve speeds greater than 267 MHz (533 Mbps) up to 333 MHz (667 Mbps), you must use the Altera DDR2
SDRAM Controller MegaCore function that features a new dynamic auto-calibration circuit in the data path for
resynchronization. For more information, see the Altera web site at www.altera.com. For interfaces running at
267 MHz or below, continue to use the static resynchronization data path currently supported by the released
version of the MegaCore function.
The lowest frequency at which a QDRII+ SRAM device can operate is 238 MHz. Therefore, the PLL-based
implementation does not support the QDRII+ SRAM interface.
This chapter describes the hardware features in Stratix II and Stratix II GX
devices that facilitate the high-speed memory interfacing for each DDR
memory standard. This chapter focuses primarily on the DLL-based
implementation. The PLL-based implementation is described in
application notes. It then lists the Stratix II and Stratix II GX feature
enhancements from Stratix devices and briefly explains how each
memory standard uses the Stratix II and Stratix II GX features.
f
You can use this document with the following documents:
■
■
■
■
Altera Corporation
January 2008
AN 325: Interfacing RLDRAM II with Stratix II & Stratix GX Devices
AN 326: Interfacing QDRII & QDRII+ SRAM with Stratix II, Stratix,
& Stratix GX Devices
AN 327: Interfacing DDR SDRAM with Stratix II Devices
AN 328: Interfacing DDR2 SDRAM with Stratix II Devices
3–3
Stratix II Device Handbook, Volume 2
External Memory Standards
External
Memory
Standards
The following sections briefly describe the external memory standards
supported by Stratix II and Stratix II GX devices. Altera offers a complete
solution for these memories, including clear-text data path, memory
controller, and timing analysis.
DDR and DDR2 SDRAM
DDR SDRAM is a memory architecture that transmits and receives data
at twice the clock speed. These devices transfer data on both the rising
and falling edge of the clock signal. DDR2 SDRAM is a second generation
memory based on the DDR SDRAM architecture and transfers data to
Stratix II and Stratix II GX devices at up to 333 MHz/667 Mbps. Stratix II
and Stratix II GX devices can support DDR SDRAM at up to
200 MHz/400 Mbps. For PLL-based implementations, Stratix II and
Stratix II GX devices support DDR and DDR2 SDRAM up to 150 MHz
and 200 MHz, respectively.
Interface Pins
DDR and DDR2 SDRAM devices use interface pins such as data (DQ),
data strobe (DQS), clock, command, and address pins. Data is sent and
captured at twice the system clock rate by transferring data on the clock’s
positive and negative edge. The commands and addresses still only use
one active (positive) edge of a clock. DDR and DDR2 SDRAM use
single-ended data strobes (DQS). DDR2 SDRAM can also use optional
differential data strobes (DQS and DQS#). However, Stratix II and
Stratix II GX devices do not use the optional differential data strobes for
DDR2 SDRAM interfaces since DQS and DQSn pins in Stratix II and
Stratix II GX devices are not differential. You can leave the DDR SDRAM
memory DQS# pin unconnected. Only the shifted DQS signal from the
DQS logic block is used to capture data.
DDR and DDR2 SDRAM ×16 devices use two DQS pins, and each DQS
pin is associated with eight DQ pins. However, this is not the same as the
×16/×18 mode in Stratix II and Stratix II GX devices (see “Data and Data
Strobe Pins” on page 3–14). To support a ×16 DDR SDRAM device, you
need to configure Stratix II and Stratix II GX devices to use two sets of DQ
pins in ×8/×9 mode. Similarly if your ×32 memory device uses four DQS
pins where each DQS pin is associated with eight DQ pins, you need to
configure Stratix II and Stratix II GX devices to use four sets of DQS/DQ
groups in ×8/×9 mode.
Connect the memory device’s DQ and DQS pins to Stratix II and
Stratix II GX DQ and DQS pins, respectively, as listed in Stratix II and
Stratix II GX pin tables. DDR and DDR2 SDRAM also uses active-high
data mask, DM, pins for writes. You can connect the memory’s DM pins
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
to any of Stratix II and Stratix II GX I/O pins in the same bank as the DQ
pins of the FPGA. There is one DM pin per DQS/DQ group in a DDR or
DDR2 SDRAM device.
You can also use I/O pins in banks 1, 2, 5, or 6 to interface with DDR and
DDR2 SDRAM devices. These banks do not have dedicated circuitry,
though, and can only support DDR SDRAM at speeds up to 150 MHz and
DDR2 SDRAM at speeds up to 200 MHz. DDR2 SDRAM interfaces using
these banks are supported using the SSTL-18 Class I I/O standard.
f
For more information, see AN 327: Interfacing DDR SDRAM with
Stratix II Devices and AN 328: Interfacing DDR2 SDRAM with Stratix II
Devices.
If the DDR or DDR2 SDRAM device supports error correction coding
(ECC), the design will use an extra DQS/DQ group for the ECC pins.
You can use any of the user I/O pins for commands and addresses to the
DDR and DDR2 SDRAM. You may need to generate these signals from
the system clock’s negative edge.
The clocks to the SDRAM device are called CK and CK# pins. Use any of
the user I/O pins via the DDR registers to generate the CK and CK#
signals to meet the DDR SDRAM or DDR2 SDRAM device’s tDQSS
requirement. The memory device’s tDQSS specification requires that the
write DQS signal’s positive edge must be within 25% of the positive edge
of the DDR SDRAM or DDR2 SDRAM clock input. Using regular I/O
pins for CK and CK# also ensures that any PVT variations on the DQS
signals are tracked the same way by these CK and CK# pins. Figure 3–2
shows a diagram that illustrates how to generate these clocks.
Altera Corporation
January 2008
3–5
Stratix II Device Handbook, Volume 2
External Memory Standards
Figure 3–2. Clock Generation for External Memory Interfaces in Stratix II and Stratix II GX Devices
LE
VCC
IOE
GND
D
Q
D
Q
D
Q
D
Q
VCC
CK (1)
DK (2)
VCC
GND
VCC
CK# (1)
DK# (2)
clk
Notes to Figure 3–2:
(1)
(2)
CK and CK# are the clocks to the memory devices.
DK and DK# are for RLDRAM II interfaces. You can generate DK# and DK from separate pins if the difference of
the Quartus II software’s reported clock-to-out time for these pins meets the RLDRAM II device’s tCKDK
specification.
Read and Write Operations
When reading from the memory, DDR and DDR2 SDRAM devices send
the data edge-aligned with respect to the data strobe. To properly read the
data in, the data strobe needs to be center-aligned with respect to the data
inside the FPGA. Stratix II and Stratix II GX devices feature dedicated
circuitry to shift this data strobe to the middle of the data window.
Figure 3–3 shows an example of how the memory sends out the data and
data strobe for a burst-of-two operation.
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–3. Example of a 90° Shift on the DQS Signal
Notes (1), (2)
DQS pin to
register delay
DQS at
FPGA pin
Preamble
Postamble
DQ at
FPGA pin
DQS at
IOE registers
90˚ degree (3)
DQ at
IOE registers
DQ pin to
register delay
Notes to Figure 3–3:
(1)
(2)
(3)
RLDRAM II and QDRII SRAM memory interfaces do not have preamble and postamble specifications.
DDR2 SDRAM does not support a burst length of two.
The phase shift required for your system should be based on your timing analysis and may not be 90°.
During write operations to a DDR or DDR2 SDRAM device, the FPGA
needs to send the data to the memory center-aligned with respect to the
data strobe. Stratix II and Stratix II GX devices use a PLL to center-align
the data by generating a 0° phase-shifted system clock for the write data
strobes and a –90° phase-shifted write clock for the write data pins for
DDR and DDR2 SDRAM. Figure 3–4 shows an example of the
relationship between the data and data strobe during a burst-of-four
write.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
External Memory Standards
Figure 3–4. DQ and DQS Relationship During a DDR and DDR2 SDRAM Write
Notes (1), (2)
DQS at
FPGA Pin
DQ at
FPGA Pin
Notes to Figure 3–4:
(1)
(2)
This example shows a write for a burst length of four. DDR SDRAM also supports burst lengths of two.
The write clock signals never go to hi-Z state on RLDRAM II and QDRII SRAM memory interfaces because they use
free-running clocks. However, the general timing relationship between data and the read clock shown in this figure
still applies.
f
For more information on DDR SDRAM and DDR2 SDRAM
specifications, refer to JEDEC standard publications JESD79C and
JESD79-2, respectively, from www.jedec.org, or see AN 327: Interfacing
DDR SDRAM with Stratix II Devices and AN 327: Interfacing DDR
SDRAM with Stratix II Devices.
RLDRAM II
RLDRAM II provides fast random access as well as high bandwidth and
high density, making this memory technology ideal for high-speed
network and communication data storage applications. The fast random
access speeds in RLDRAM II devices make them a viable alternative to
SRAM devices at a lower cost. Additionally, RLDRAM II devices have
minimal latency to support designs that require fast response times.
Interface Pins
RLDRAM II devices use interface pins such as data, clock, command, and
address pins. There are two types of RLDRAM II memory: common I/O
(CIO) and separate I/O (SIO). The data pins in a RLDRAM II CIO device
are bidirectional while the data pins in a RLDRAM II SIO device are
unidirectional. Instead of bidirectional data strobes, RLDRAM II uses
differential free-running read and write clocks to accompany the data. As
in DDR or DDR2 SDRAM, data is sent and captured at twice the system
clock rate by transferring data on the clock’s positive and negative edge.
The commands and addresses still only use one active (positive) edge of
a clock.
If the data pins are bidirectional, as in RLDRAM II CIO devices, connect
them to Stratix II and Stratix II GX DQ pins. If the data pins are
unidirectional, as in RLDRAM II SIO devices, connect the RLDRAM II
device Q ports to the Stratix II and Stratix II GX device DQ pins and
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
connect the D ports to any user I/O pins in I/O banks 3, 4, 7, or 8 for
optimal performance. RLDRAM II also uses active-high data mask, DM,
pins for writes. You can connect DM pins to any of the I/O pins in the
same bank as the DQ pins of the FPGA when interfacing with
RLDRAM II CIO devices to any of the I/O pins in the same bank as the D
pins when interfacing with RLDRAM II SIO devices. There is one DM pin
per RLDRAM II device. You can also use I/O pins in banks 1, 2, 5, or 6 to
interface with RLDRAM II devices. However, these banks do not have
dedicated circuitry and can only support RLDRAM II devices at speeds
up to 200 MHz. RLDRAM II interfaces using these banks are supported
using the 1.8-V HSTL Class I I/O support.
Connect the RLDRAM II device’s read clock pins (QK) to Stratix II or
Stratix II GX DQS pins. Because of software requirements, you must
configure the DQS signals as bidirectional pins. However, since QK pins
are output-only pins from the memory, RLDRAM II memory interfacing
in Stratix II and Stratix II GX devices requires that you ground the DQS
pin output enables. Stratix II and Stratix II GX devices use the shifted QK
signal from the DQS logic block to capture data. You can leave the QK#
signal of the RLDRAM II device unconnected, as DQS and DQSn in
Stratix II and Stratix II GX devices are not differential pins.
RLDRAM II devices also have input clocks (CK and CK#) and write
clocks (DK and DK#).
You can use any of the user I/O pins for commands and addresses.
RLDRAM II also offers QVLD pins to indicate the read data availability.
Connect the QVLD pins to the Stratix II or Stratix II GX DQVLD pins,
listed in the pin table.
1
Because the Quartus II software treats the DQVLD pins like DQ
pins, you should ensure that the DQVLD pin is assigned to the
pin table’s recommended pin.
Read and Write Operations
When reading from the RLDRAM II device, data is sent edge-aligned
with the read clock QK and QK#. When writing to the RLDRAM II device,
data must be center-aligned with the write clock (DK and DK#). The
RLDRAM II interface uses the same scheme as in DDR or DDR2 SDRAM
interfaces, where the dedicated circuitry is used during reads to
center-align the data and the read clock inside the FPGA and the PLL
center-aligns the data and write clock outputs. The data and clock
relationship for reads and writes in RLDRAM II is similar to those in DDR
and DDR2 SDRAM as shown in Figures 3–3 and 3–4.
Altera Corporation
January 2008
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External Memory Standards
f
For details on RLDRAM II, see AN 325: Interfacing RLDRAM II with
Stratix II & Stratix GX Devices.
QDRII SRAM
QDRII SRAM is the second generation of QDR SRAM devices. Both
devices can transfer four words per clock cycle, fulfilling the
requirements facing next-generation communications system designers.
QDRII SRAM devices provide concurrent reads and writes, zero latency,
and increased data throughput, allowing simultaneous access to the same
address location. QDRII SRAM is available in burst-of-2 and burst-of-4
devices. Burst-of-2 devices support two-word data transfer on all read
and write transactions, and burst-of-4 devices support four-word data
transfer
Interface Pins
QDRII SRAM uses two separate, unidirectional data ports for read and
write operations, enabling QDR data transfer. QDRII SRAM uses shared
address lines for reads and writes. QDRII SRAM burst-of-two devices
sample the read address on the rising edge of the clock and sample the
write address on the falling edge of the clock while QDRII SRAM
burst-of-four devices sample both read and write addresses on the clock’s
rising edge. Connect the memory device’s Q ports (read data) to the
Stratix II or Stratix II GX DQ pins. You can use any of the Stratix II or
Stratix II GX device user I/O pins in I/O banks 3, 4, 7, or 8 for the D ports
(write data), commands, and addresses. The control signals are sampled
on the rising edge of the clock. You can also use I/O pins in banks 1, 2, 5,
or 6 to interface with QDRII SRAM devices. However, these banks do not
have dedicated circuitry and can only support QDRII SRAM devices at
speeds up to 200 MHz. QDRII SRAM interfaces using these banks are
supported using the 1.8-V HSTL Class I I/O support.
QDRII SRAM uses the following clock signals:
■
■
■
Input clocks K and K#
Output clocks C and C#
Echo clocks CQ and CQ#
Clocks C#, K#, and CQ# are logical complements of clocks C, K, and CQ,
respectively. Clocks C, C#, K, and K# are inputs to the QDRII SRAM while
clocks CQ and CQ# are outputs from the QDRII SRAM. Stratix II and
Stratix II GX devices use single-clock mode for single-device QDRII
SRAM interfacing where the K and K# are used for write operations, and
CQ and CQ# are used for read operations. You should use both C or C#
and K or K# clocks when interfacing with a bank of multiple QDRII
SRAM devices with a single controller.
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
You can generate C, C#, K, and K# clocks using any of the I/O registers
via the DDR registers. Because of strict skew requirements between K and
K# signals, use adjacent pins to generate the clock pair.
Connect CQ and CQ# pins to the Stratix II or Stratix II GX DQS and DQSn
pins for DLL-based implementations. You must configure DQS and
DQSn as bidirectional pins. However, since CQ and CQ# pins are
output-only pins from the memory, the Stratix II or Stratix II GX device
QDRII SRAM memory interface requires that you ground the DQS and
DQSn output enable. To capture data presented by the memory, connect
the shifted CQ signal to the input latch and connect the active-high input
registers and the shifted CQ# signal is connected to the active-low input
register. For PLL-based implementations, connect QK to the input of the
read PLL and leave QK# unconnected.
Read and Write Operations
Figure 3–5 shows the data and clock relationships in QDRII SRAM
devices at the memory pins during reads. Data is output one-and-a-half
clock cycles after a read command is latched into memory. QDRII SRAM
devices send data within a tCO time after each rising edge of the read clock
C or C# in multi-clock mode, or the input clock K or K# in single clock
mode. Data is valid until tDOH time after each rising edge of the read clock
C or C# in multi-clock mode or the input clock K or K# in single clock
mode. The CQ and CQ# clocks are edge-aligned with the read data signal.
These clocks accompany the read data for data capture in Stratix II and
Stratix II GX devices.
Altera Corporation
January 2008
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External Memory Standards
Figure 3–5. Data and Clock Relationship During a QDRII SRAM Read
Note (1)
C/K
C#/K#
tCO (2)
Q
tCO (2)
QA
tCLZ (3)
QA + 1
tDOH (2)
QA + 2
QA + 3
tCHZ (3)
CQ
tCQD (4)
CQ#
tCCQO (5)
tCQOH (5)
tCQD (4)
Notes to Figure 3–5:
(1)
(2)
(3)
(4)
(5)
This relationship is at the memory device. The timing parameter nomenclature is based on the Cypress QDRII
SRAM data sheet for CY7C1313V18.
tCO is the data clock-to-out time and tDOH is the data output hold time between burst.
tCLZ and tCHZ are bus turn-on and turn-off times respectively.
tCQD is the skew between the rising edge of CQ or CQ# and the data edges.
tCCQO and tCQOH are skew measurements between the C or C# clocks (or the K or K# clocks in single-clock mode)
and the CQ or CQ# clocks.
When reading from the QDRII SRAM, data is sent edge-aligned with the
rising edge of the echo clocks CQ and CQ#. Both CQ and CQ# are shifted
inside the FPGA using DQS and DQSn logic blocks to capture the data in
the DDR IOE registers in DLL-based implementations. In PLL-based
implementations, CQ feeds a PLL, which generates the clock to capture
the data in the DDR IOE registers.
When writing to QDRII SRAM devices, data is generated by the write
clock while the K clock is 90° shifted from the write clock, creating a
center-aligned arrangement.
Read and write operations occur during the same clock cycle on
independent read and write data paths along with the cycle-shared
address bus. Performing concurrent reads and writes does not change the
functionality of either transaction. If a read request occurs simultaneously
with a write request at the same address, the new data on D is forwarded
to Q. Therefore, latency is not required to access valid data.
f
For more information on QDRII SRAM, go to www.qdrsram.com or see
AN 326: Interfacing QDRII & QDRII+ SRAM with Stratix II, Stratix, &
Stratix GX Devices.
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Stratix II and
Stratix II GX
DDR Memory
Support
Overview
This section describes Stratix II and Stratix II GX features that enable
high-speed memory interfacing. It first describes Stratix II and
Stratix II GX memory pins and then the DQS phase-shift circuitry and the
DDR I/O registers. Table 3–2 shows the I/O standard associated with the
external memory interfaces.
Table 3–2. External Memory Support in Stratix II and Stratix II GX Devices
Memory Standard
I/O Standard
DDR SDRAM
SSTL-2 Class II
DDR2 SDRAM
SSTL-18 Class II(1)
RLDRAM II (2)
1.8-V HSTL Class I or II (1)
QDRII SRAM (2)
1.8-V HSTL Class I or II (1)
Notes to Table 3–2:
(1)
(2)
Stratix II and Stratix II GX devices support 1.8-V HSTL/SSTL-18 Class I and II
I/O standards in I/O banks 3, 4, 7, and 8. In I/O banks 1, 2, 5, and 6, Class I is
supported for both input and output operations, while Class II is only supported
for input operations for these I/O standards.
For maximum performance, Altera recommends using the 1.8-V HSTL I/O
standard. RLDRAM II and QDRII SRAM devices also support the 1.5-V HSTL
I/O standard.
Stratix II and Stratix II GX devices support the data strobe or read clock
signal (DQS) used in DDR SDRAM, DDR2 SDRAM, RLDRAM II, and
QDRII SRAM devices with dedicated circuitry. Stratix II and Stratix II GX
devices also support the DQSn signal (the DQS complement signal) for
external memory types that require them, for example QDRII SRAM.
DQS and DQSn signals are usually associated with a group of data (DQ)
pins. However, these are not differential buffers and cannot be used in
DDR2 SDRAM or RLDRAM II interfaces.
1
f
You can also interface with these external memory devices
without the use of dedicated circuitry at a lower performance.
For more information, see the appropriate Stratix II or Stratix II GX
memory interfaces application note available at www.altera.com.
Stratix II and Stratix II GX devices contain dedicated circuitry to shift the
incoming DQS signals by 0°, 22.5°, 30°, 36°, 45°, 60°, 67.5°, 72°, 90°, 108°,
120°, or 144°, depending on the delay-locked loop (DLL) mode. There are
four DLL modes. The DQS phase-shift circuitry uses a frequency
reference to dynamically generate control signals for the delay chains in
each of the DQS and DQSn pins, allowing it to compensate for process,
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January 2008
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Stratix II and Stratix II GX DDR Memory Support Overview
voltage, and temperature (PVT) variations. This phase-shift circuitry has
been enhanced in Stratix II and Stratix II GX devices to support more
phase-shift options with less jitter.
Besides the DQS dedicated phase-shift circuitry, each DQS and DQSn pin
has its own DQS logic block that sets the delay for the signal input to the
pin. Using the DQS dedicated phase-shift circuitry with the DQS logic
block allows for phase-shift fine-tuning. Additionally, every IOE in a
Stratix II or Stratix II GX device contains six registers and one latch to
achieve DDR operation.
DDR Memory Interface Pins
Stratix II and Stratix II GX devices use data (DQ), data strobe (DQS and
DQSn), and clock pins to interface with external memory.
Figure 3–6 shows the DQ, DQS, and DQSn pins in the Stratix II or
Stratix II GX I/O banks on the top of the device. A similar arrangement is
repeated at the bottom of the device.
Figure 3–6. DQ and DQS Pins Per I/O Bank
Up to 8 Sets of
DQ & DQS Pins
Up to 10 Sets of
DQ & DQS Pins
DQ
Pins
I/O
Bank 3
DQSn
Pin
DQ
Pins
PLL 11
PLL 5
I/O
Bank 11
I/O
Bank 9
DQS
Pin
DQS
Phase
Shift
Circuitry
I/O
Bank 4
DQSn
Pin
DQS
Pin
Data and Data Strobe Pins
Stratix II and Stratix II GX data pins for the DDR memory interfaces are
called DQ pins. Stratix II and Stratix II GX devices can use either
bidirectional data strobes or unidirectional read clocks. Depending on the
external memory interface, either the memory device’s read data strobes
or read clocks feed the Stratix II or Stratix II GX DQS (and DQSn) pins.
3–14
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Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Stratix II and Stratix II GX DQS pins connect to the DQS pins in DDR and
DDR2 SDRAM interfaces or to the QK pins in RLDRAM II interfaces. The
DQSn pins are not used in these interfaces. Connect the Stratix II or
Stratix II GX DQS and DQSn pins to the QDRII SRAM CQ and CQ# pins,
respectively.
In every Stratix II or Stratix II GX device, the I/O banks at the top (I/O
banks 3 and 4) and bottom (I/O banks 7 and 8) of the device support DDR
memory up to 300 MHz/600 Mbps (with RLDRAM II). These I/O banks
support DQS signals and its complement DQSn signals with DQ bus
modes of ×4, ×8/×9, ×16/×18, or ×32/×36.
In ×4 mode, each DQS/DQSn pin drives up to four DQ pins within that
group. In ×8/×9 mode, each DQS/DQSn pin drives up to nine DQ pins
within that group to support one parity bit and the eight data bits. If the
parity bit or any data bit is not used, the extra DQ pins can be used as
regular user I/O pins. Similarly, with ×16/×18 and ×32/×36 modes, each
DQS/DQSn pin drives up to 18 and 36 DQ pins respectively. There are
two parity bits in the ×16/×18 mode and four parity bits in the ×32/×36
mode. Tables 3–3 through 3–6 show the number of DQS/DQ groups and
non-DQS /DQ supported in each Stratix II or Stratix II GX
density/package combination, respectively, for DLL-based
implementations.
Table 3–3. Stratix II DQS and DQ Bus Mode Support (Part 1 of 2)
Number of
×4 Groups
Number of
×8/×9 Groups
484-pin FineLine BGA
8
4
0
0
672-pin FineLine BGA
18
8
4
0
484-pin FineLine BGA
8
4
0
0
672-pin FineLine BGA
18
8
4
0
484-pin FineLine BGA
8
4
0
0
672-pin FineLine BGA
18
8
4
0
1,020-pin FineLine BGA
36
18
8
4
484-pin Hybrid FineLine BGA
8
4
0
0
Device
EP2S15
EP2S30
EP2S60
EP2S90
Note (1)
Package
Number of
Number of
×16/×18 Groups ×32/×36 Groups
780-pin FineLine BGA
18
8
4
0
1,020-pin FineLine BGA
36
18
8
4
1,508-pin FineLine BGA
36
18
8
4
18
8
4
0
1,020-pin FineLine BGA
36
18
8
4
1,508-pin FineLine BGA
36
18
8
4
EP2S130 780-pin FineLine BGA
Altera Corporation
January 2008
3–15
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
Table 3–3. Stratix II DQS and DQ Bus Mode Support (Part 2 of 2)
Note (1)
Number of
×4 Groups
Number of
×8/×9 Groups
EP2S180 1,020-pin FineLine BGA
36
18
8
4
1,508-pin FineLine BGA
36
18
8
4
Device
Package
Number of
Number of
×16/×18 Groups ×32/×36 Groups
Note to Table 3–3:
(1)
Check the pin table for each DQS/DQ group in the different modes.
Table 3–4. Stratix II non-DQS and DQ Bus Mode Support
Device
Package
Note (1)
Number of
×4 Groups
Number of
×8/×9 Groups
13
7
Number of
Number of
×16/×18 Groups ×32/×36 Groups
EP2S15
484-pin FineLine BGA
672-pin FineLine BGA
24
9
4
2
EP2S30
484-pin FineLine BGA
13
7
3
1
672-pin FineLine BGA
36
15
7
3
EP2S60
484-pin FineLine BGA
13
7
3
1
EP2S90
3
1
672-pin FineLine BGA
36
15
7
3
1,020-pin FineLine BGA
51
26
13
6
780-pin FineLine BGA
40
24
12
6
1,020-pin FineLine BGA
51
25
12
6
1,508-pin FineLine BGA
51
25
12
6
40
24
12
6
1,020-pin FineLine BGA
51
25
12
6
1,508-pin FineLine BGA
51
25
12
6
EP2S180 1,020-pin FineLine BGA
51
25
12
6
1,508-pin FineLine BGA
51
25
12
6
EP2S130 780-pin FineLine BGA
Note to Table 3–4:
(1)
Check the pin table for each DQS/DQ group in the different modes.
3–16
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Table 3–5. Stratix II GX DQS and DQ Bus Mode Support
Device
Package
Note (1)
Number of
×4 Groups
Number of
×8/×9 Groups
Number of
Number of
×16/×18 Groups ×32/×36 Groups
EP2SGX30C
EP2SGX30D
780-pin FineLine BGA
18
8
4
0
EP2SGX60C
EP2SGX60D
780-pin FineLine BGA
18
8
4
0
EP2SGX60E
1,152-pin FineLine BGA
36
18
8
4
EP2SGX90E
1,152-pin FineLine BGA
36
18
8
4
EP2SGX90F
1,508-pin FineLine BGA
36
18
8
4
EP2SGX130G 1,508-pin FineLine BGA
36
18
8
4
Note to Table 3–5:
(1)
Check the pin table for each DQS/DQ group in the different modes.
Table 3–6. Stratix II GX Non-DQS and DQ Bus Mode Support Note (1)
Device
Package
Number of
×4 Groups
Number of
×8/×9 Groups
Number of
Number of
×16/×18 Groups ×32/×36 Groups
8
4
2
EP2SGX30
780-pin FineLine BGA
18
EP2SGX60
780-pin FineLine BGA
18
8
4
2
1,152-pin FineLine BGA
25
13
6
3
EP2SGX90
EP2SGX130
1,152-pin FineLine BGA
25
13
6
3
1,508-pin FineLine BGA
25
12
6
3
1,508-pin FineLine BGA
25
12
6
3
Note to Table 3–6:
(1)
Check the pin table for each DQS/DQ group in the different modes.
1
Altera Corporation
January 2008
To support the RLDRAM II QVLD pin, some of the unused ×4
DQS pins, whose DQ pins were combined to make the bigger
×8/×9, ×16/×18, or ×32/×36 groups, are listed as DQVLD pins
in the Stratix II or Stratix II GX pin table. DQVLD pins are for
input-only operations. The signal coming into this pin can be
captured by the shifted DQS signal like any of the DQ pins.
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Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
The DQS pins are listed in the Stratix II or Stratix II GX pin tables as
DQS[17..0]T or DQS[17..0]B. The T denotes pins on the top of the
device and the B denotes pins on the bottom of the device. The
complement DQSn pins are marked as DQSn[17..0]T or
DQSn[17..0]B. The corresponding DQ pins are marked as
DQ[17..0]T[3..0], where [17..0] indicates which DQS group the
pins belong to. Similarly, the corresponding DQVLD pins are marked as
DQVLD[8..0]T, where [8..0] indicates which DQS group the pins
belong to. The numbering scheme starts from right to left on the package
bottom view. When not used as DQ, DQS, or DQSn pins, these pins are
available as regular I/O pins. Figure 3–7 shows the DQS pins in Stratix II
or Stratix II GX I/O banks.
1
The Quartus II software treats DQVLD pins as regular DQ pins.
Therefore, you must ensure that the DQVLD pin assigned in
your design corresponds to the pin table’s recommended
DQVLD pins.
Figure 3–7. DQS Pins in Stratix II and Stratix II GX I/O Banks
Notes (1), (2), (3)
Up to 8 Sets of
DQ & DQS Pins
Up to 10 Sets of
DQ & DQS Pins
DQ
Pins
I/O
Bank 3
DQSn
Pin
DQS
Pin
DQ
Pins
PLL 11
PLL 5
I/O
Bank 11
I/O
Bank 9
DQS
Phase
Shift
Circuitry
I/O
Bank 4
DQSn
Pin
DQS
Pin
Notes to Figure 3–7:
(1)
(2)
(3)
There are up to 18 pairs of DQS and DQSn pins on both the top and bottom of the device. See Table 3–3 for the exact
number of DQS and DQSn pin pairs in each device package.
See Table 3–7 for the available DQS and DQSn pins in each mode and package.
Each DQS pin has a complement DQSn pin. DQS and DQSn pins are not differential.
The DQ pin numbering is based on ×4 mode. There are up to 8 DQS/DQ
groups in ×4 mode in I/O banks 3 and 8 and up to 10 DQS/DQ groups in
×4 mode in I/O banks 4 and 7. In ×8/×9 mode, two adjacent ×4 DQS/DQ
groups plus one parity pin are combined; one pair of DQS/DQSn pins
from the combined groups can drive all the DQ and parity pins. Since
there is an even number of DQS/DQ groups in an I/O bank, combining
groups is efficient. Similarly, in ×16/×18 mode, four adjacent ×4 DQS/DQ
groups plus two parity pins are combined and one pair of DQS/DQSn
pins from the combined groups can drive all the DQ and parity pins. In
3–18
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Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
×32/×36 mode, eight adjacent DQS/DQ groups are combined and one
pair of DQS/DQSn pins can drive all the DQ and parity pins in the
combined groups.
Table 3–7 shows which DQS and DQSn pins are available in each mode
and package in the Stratix II or Stratix II GX device family.
Table 3–7. Available DQS and DQSn Pins in Each Mode and Package
Note (1)
Package
Mode
484-Pin FineLine BGA
484-Pin Hybrid FineLine BGA
672-Pin FineLine BGA
780-Pin FineLine BGA
1,020-Pin FineLine BGA
1,508-Pin FineLine BGA
×4
7, 9, 11, 13
Odd-numbered pins only
All DQS and DQSn pins
×8/×9
7,11
3, 7, 11, 15
Even-numbered pins only
×16/×18
N/A
5, 13
3, 7, 11, 15
×32/×36
N/A
N/A
5, 13
Note to Table 3–7:
(1)
The numbers correspond to the DQS and DQSn pin numbering in the Stratix II or Stratix II GX pin table. There are
two sets of DQS/DQ groups, one corresponding with the top side of the device and one with the bottom side of
the device.
1
On the top and bottom side of the device, the DQ and DQS pins
must be configured as bidirectional DDR pins to enable the DQS
phase-shift circuitry. The DQSn pins can be configured as input,
output, or bidirectional pins. You can use the altdq and
altdqs megafunctions to configure the DQ and DQS/DQSn
paths, respectively. However, Altera highly recommends that
you use the respective Altera memory controller IP Tool Bench
for your external memory interface data paths. The data path is
clear-text and free to use. You are responsible for your own
timing analysis if you use your own data path. If you only want
to use the DQ and/or DQS pins as inputs, you need to set the
output enable of the DQ and/or DQS pins to ground.
Stratix II or Stratix II GX side I/O banks (I/O banks 1, 2, 5, and 6) support
all the memory interfaces supported in the top and bottom I/O banks. For
optimal performance, use the Altera memory controller IP Tool Bench to
pick the data and strobe pins for these interfaces. Since these I/O banks
do not have any dedicated circuitry for memory interfacing, they can
support DDR SDRAM at speeds up to 150 MHz and other DDR memories
at speeds up to 200 MHz. You need to use the SSTL-18 Class I I/O
standard when interfacing with DDR2 SDRAM devices using pins in I/O
bank 1, 2, 5, or 6. These I/O banks do not support the SSTL-18 Class II and
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
1.8-V HSTL Class II I/O standards on output and bidirectional pins, but
you can use SSTL-18 Class I or 1.8-V HSTL Class I I/O standards for
memory interfaces.
1
The Altera memory controller IP Tool Bench generates the
optimal pin constraints that allow you to interface these
memories at high frequency.
Table 3–8 shows the maximum clock rate supported for the DDR SDRAM
interface in the Stratix II or Stratix II GX device side I/O banks.
Table 3–8. Maximum Clock Rate for DDR and DDR2 SDRAM in Stratix II or Stratix II GX Side I/O Banks
Stratix II or Stratix II GX
Device Speed Grade
DDR SDRAM
(MHz)
DDR2 SDRAM
(MHz)
QDRII SRAM
(MHz)
RLDRAM II
(MHz)
-3
150
200
200
200
-4
133
167
167
175
-5
133
167
167
175
Clock Pins
You can use any of the DDR I/O registers to generate clocks to the
memory device. For better performance, use the same I/O bank as the
data and address/command pins.
Command and Address Pins
You can use any of the user I/O pins in the top or bottom bank of the
device for commands and addresses. For better performance, use the
same I/O bank as the data pins.
Other Pins (Parity, DM, ECC and QVLD Pins)
You can use any of the DQ pins for the parity pins in Stratix II and
Stratix II GX devices. The Stratix II or Stratix II GX device family has
support for parity in the ×8/×9, ×16/×18, and ×32/×36 mode. There is
one parity bit available per 8 bits of data pins.
The data mask, DM, pins are only required when writing to DDR
SDRAM, DDR2 SDRAM, and RLDRAM II devices. A low signal on the
DM pins indicates that the write is valid. If the DM signal is high, the
memory will mask the DQ signals. You can use any of the I/O pins in the
same bank as the DQ pins (or the RLDRAM II SIO’s and QDRII SRAM’s
D pins) for the DM signals. Each group of DQS and DQ signals in DDR
3–20
Stratix II Device Handbook, Volume 2
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
and DDR2 SDRAM devices requires a DM pin. There is one DM pin per
RLDRAM II device. The DDR I/O output registers, clocked by the –90°
shifted clock, creates the DM signals, similar to DQ output signals.
1
Perform timing analysis to calculate your write-clock phase
shift.
Some DDR SDRAM and DDR2 SDRAM devices support error correction
coding (ECC), which is a method of detecting and automatically
correcting errors in data transmission. In a 72-bit DDR SDRAM interface,
there are eight ECC pins in addition to the 64 data pins. Connect the DDR
and DDR2 SDRAM ECC pins to a Stratix II or Stratix II GX device
DQS/DQ group. The memory controller needs extra logic to encode and
decode the ECC data.
QVLD pins are used in RLDRAM II interfacing to indicate the read data
availability. There is one QVLD pin per RLDRAM II device. A high on
QVLD indicates that the memory is outputting the data requested.
Similar to DQ inputs, this signal is edge-aligned with QK/QK# signals
and is sent half a clock cycle before data starts coming out of the memory.
You need to connect QVLD pins to the DQVLD pin on the Stratix II or
Stratix II GX device. The DQVLD pin can be used as a regular user I/O
pin if not used for QVLD. Because the Quartus II software does not
differentiate DQVLD pins from DQ pins, you must ensure that your
design uses the pin table’s recommended DQVLD pin.
DQS Phase-Shift Circuitry
The Stratix II or Stratix II GX phase-shift circuitry and the DQS logic
block control the DQS and DQSn pins. Each Stratix II or Stratix II GX
device contains two phase-shifting circuits. There is one circuit for I/O
banks 3 and 4, and another circuit for I/O banks 7 and 8. The phaseshifting circuit on the top of the device can control all the DQS and DQSn
pins in the top I/O banks and the phase-shifting circuit on the bottom of
the device can control all the DQS and DQSn pins in the bottom I/O
banks. Figure 3–8 shows the DQS and DQSn pin connections to the DQS
logic block and the DQS phase-shift circuitry.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
Figure 3–8. DQS and DQSn Pins and the DQS Phase-Shift Circuitry
Note (1)
From PLL 5 (3)
DQSn
Pin
DQS
Pin
DQSn
Pin
DQS
Pin
Δt
Δt
Δt
Δt
to IOE
to IOE
to IOE
to IOE
CLK[15..12]p (2)
DQS
Phase-Shift
Circuitry
DQS
Pin
DQSn
Pin
DQS
Pin
DQSn
Pin
Δt
Δt
Δt
Δt
to IOE
to IOE
to IOE
to IOE
DQS Logic
Blocks
Notes to Figure 3–8:
(1)
(2)
(3)
There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II or Stratix II GX
device, up to 8 on the left side of the DQS phase-shift circuitry (I/O banks 3 and 8), and up to 10 on the right side
(I/O bank 4 and 7).
Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed
the phase-shift circuitry on the bottom of the device. You can also use a phase-locked loop (PLL) clock output as a
reference clock to the phase-shift circuitry. The reference clock can also be used in the logic array.
You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS
phase-shift circuitry on the bottom of the device.
Figure 3–9 shows the connections between the DQS phase-shift circuitry
and the DQS logic block.
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Note (1)
CLRN
(6)
PRN
Q SCLR
DQS bus
EnableN
DQS'
NOT
A
EN
DQS Logic Block (2)
EN
DQS or DQSn
DQS Delay
Settings to and from the
Logic Array (5)
6
Delay Chains
clock enable
upndn
Phase
Comparator
Input reference
clock (4)
DLL
DQS Phase-Shift Circuitry (3)
Up/Down
Counter
6
6
Phase
Offset
Control
DQS Delay
Settings from the
DQS Phase-Shift
Circuitry
6
6
Phase offset
settings from the
logic array
addnsub
DQS or DQSn
Phase Offset
Settings
D
DQS Logic Block (2)
DQS or DQSn
DQS Logic Block (2)
Q
6
6
6
Bypass
D
Q
6
6
DQS Delay Chain
Update
Enable
Circuitry
B
Postamble Circuitry
gated_dqs control
reset
DFF
VCC
Figure 3–9. DQS Phase-Shift Circuitry and DQS Logic Block Connections
Notes to Figure 3–9:
(1)
(2)
(3)
(4)
(5)
(6)
All features of the DQS phase-shift circuitry and the DQS logic block are accessible from the altdqs megafunction
in the Quartus II software. You should, however, use Altera’s memory controller IP Tool Bench to generate the data
path for your memory interface.
DQS logic block is available on every DQS and DQSn pin.
There is one DQS phase-shift circuit on the top and bottom side of the device.
The input reference clock can come from CLK[15..12]p or PLL 5 for the DQS phase-shift circuitry on the top side
of the device or from CLK[7..4]p or PLL 6 for the DQS phase-shift circuitry on the bottom side of the device.
Each individual DQS and DQSn pair can have individual DQS delay settings to and from the logic array.
This register is one of the DQS IOE input registers.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
The phase-shift circuitry is only used during read transactions where the
DQS and DQSn pins are acting as input clocks or strobes. The phase-shift
circuitry can shift the incoming DQS signal by 0°, 22.5°, 30°, 36°, 45°, 60°,
67.5°, 72°, 90°, 108°, 120°, or 144°. The shifted DQS signal is then used as
clocks at the DQ IOE input registers.
Figure 3–3 shows an example where the DQS signal is shifted by 90°. The
DQS signals goes through the 90° shift delay set by the DQS phase-shift
circuitry and the DQS logic block and some routing delay from the DQS
pin to the DQ IOE registers. The DQ signals only goes through routing
delay from the DQ pin to the DQ IOE registers and maintains the 90°
relationship between the DQS and DQ signals at the DQ IOE registers
since the software will automatically set delay chains to match the routing
delay between the pins and the IOE registers for the DQ and DQS input
paths.
All 18 DQS and DQSn pins on either the top or bottom of the device can
have their input signal phase shifted by a different degree amount but all
must be referenced at one particular frequency. For example you can have
a 90° phase shift on DQS0T and have a 60° phase shift on DQS1T both
referenced from a 200-MHz clock. Not all phase-shift combinations are
supported, however. The phase shifts on the same side of the device must
all be a multiple of 22.5° (up to 90°), a multiple of 30° (up to 120°), or a
multiple of 36° (up to 144°).
In order to generate the correct phase shift with the DLL used, you must
provide a clock signal of the same frequency as the DQS signal to the DQS
phase-shift circuitry. Any of the CLK[15..12]p clock pins can feed the
phase circuitry on the top of the device (I/O banks 3 and 4) or any of the
CLK[7..4]p clock pins can feed the phase circuitry on the bottom of the
device (I/O banks 7 and 8). Stratix II and Stratix II GX devices can also
use PLLs 5 or 6 as the reference clock to the DQS phase-shift circuitry on
the top or bottom of the device, respectively. PLL 5 is connected to the
DQS phase-shift circuitry on the top side of the device and PLL 6 is
connected to the DQS phase-shift circuitry on the bottom side of the
device. Both the top and bottom phase-shift circuits need unique clock
pins or PLL clock outputs for the reference clock.
1
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Stratix II Device Handbook, Volume 2
When you have a PLL dedicated only to generate the DLL input
reference clock, you must set the PLL mode to “No
Compensation” or the Quartus® II software will change it
automatically. Because there are no other PLL outputs used, the
PLL doesn’t need to compensate for any clock paths.
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
DLL
The DQS phase-shift circuitry uses a delay-locked loop (DLL) to
dynamically measure the clock period needed by the DQS/DQSn pin (see
Figure 3–10). The DQS phase-shift circuitry then uses the clock period to
generate the correct phase shift. The DLL in the Stratix II or Stratix II GX
DQS phase-shift circuitry can operate between 100 and 400 MHz. The
phase-shift circuitry needs a maximum of 256 clock cycles to calculate the
correct input clock period. Data sent during these clock cycles may not be
properly captured.
1
Although the DLL can run up to 400 MHz, other factors may
prevent you from interfacing with a 400-MHz external memory
device.
1
You can still use the DQS phase-shift circuitry for any memory
interfaces that are less than 100 MHz. The DQS signal will be
shifted by 2.5 ns and you can add more shift by using the phase
offset module. Even if the DQS signal is not shifted exactly to the
middle of the DQ valid window, the IOE should still be able to
capture the data in this low frequency application.
There are four different frequency modes for the Stratix II or Stratix II GX
DLL. Each frequency mode provides different phase shift, as shown in
Table 3–9.
Table 3–9. Stratix II and Stratix II GS DLL Frequency Modes
Available
Number of
Phase Shift Delay Chains
Frequency
Mode
Frequency Range (MHz)
0
100–175
30, 60, 90,
120
12
1
150–230
22.5, 45,
67.5, 90
16
2
200–310
30, 60, 90,
120
12
3
240–400 (C3 speed grade)
240–350 (C4 and C5 speed grades)
36, 72, 108,
144
10
In frequency mode 0, Stratix II devices use a 6-bit setting to implement the
phase-shift delay. In frequency modes 1, 2, and 3, Stratix II devices only
use a 5-bit setting to implement the phase-shift delay.
The DLL can be reset from either the logic array or a user I/O pin. This
signal is not shown in Figure 3–10. Each time the DLL is reset, you must
wait for 256 clock cycles before you can capture the data properly.
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January 2008
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Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
1
The input reference clock for the DQS phase-shift circuitry on
the top side of the device can come from CLK[15..12]p or
PLL 5. The input reference clock for the DQS phase-shift
circuitry on the bottom side of the device can come from
CLK[7..4]p or PLL 6.
Table 3–10 lists the maximum delay in the fast timing model for the
Stratix II DQS delay buffer. Multiply the number of delay buffers that you
are using in the DQS logic block to get the maximum delay achievable in
your system. For example, if you implement a 90° phase shift at 200 MHz,
you use three delay buffers in mode 2. The maximum achievable delay
from the DQS block is then 3 × .416 ps = 1.248 ns.
Table 3–10. DQS Delay Buffer Maximum Delay in Fast Timing Model
Frequency
Mode
Maximum Delay Per Delay Buffer
(Fast Timing Model)
Unit
0
0.833
ns
1, 2, 3
0.416
ns
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Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–10. Simplified Diagram of the DQS Phase-Shift Circuitry
Note (1)
addnsub
Phase offset settings
from the logic array
DLL
6
Input reference
clock (2)
Phase
Offset
Control
upndn
Phase
Comparator
clock enable
Up/Down
Counter
6
Phase offset
settings (3)
6
Delay Chains
6
DQS delay
settings (4)
6
Notes to Figure 3–10:
(1)
(2)
(3)
(4)
All features of the DQS phase-shift circuitry are accessible from the altdqs megafunction in the Quartus II software.
You should; however, use Altera’s memory controller IP Tool Bench to generate the data path for your memory
interface.
The input reference clock for the DQS phase-shift circuitry on the top side of the device can come from
CLK[15..12]p or PLL 5. The input reference clock for the DQS phase-shift circuitry on the bottom side of the
device can come from CLK[7..4]p or PLL 6.
Phase offset settings can only go to the DQS logic blocks.
DQS delay settings can go to the logic array and/or to the DQS logic block.
The input reference clock goes into the DLL to a chain of up to 16 delay
elements. The phase comparator compares the signal coming out of the
end of the delay element chain to the input reference clock. The phase
comparator then issues the upndn signal to the up/down counter. This
signal increments or decrements a six-bit delay setting (DQS delay
settings) that will increase or decrease the delay through the delay
element chain to bring the input reference clock and the signals coming
out of the delay element chain in phase.
The DQS delay settings contain the control bits to shift the signal on the
input DQS pin by the amount set in the altdqs megafunction. For the 0°
shift, both the DLL and the DQS logic block are bypassed. Since Stratix II
and Stratix II GX DQS and DQ pins are designed such that the pin to IOE
delays are matched, the skew between the DQ and DQS pin at the DQ IOE
registers is negligible when the 0° shift is implemented. You can feed the
DQS delay settings to the DQS logic block and the logic array.
Altera Corporation
January 2008
3–27
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
Phase Offset Control
The DQS phase-shift circuitry also contains a phase offset control module
that can add or subtract a phase offset amount from the DQS delay setting
(phase offset settings from the logic array in Figure 3–10). You should use
the phase offset control module for making small shifts to the input signal
and use the DQS phase-shift circuitry for larger signal shifts. For example,
if you need the input signal to be shifted by 75°, you can set the altdqs
megafunction to generate a 72° phase shift with a phase offset of +3°.
You can either use a static phase offset or a dynamic phase offset to
implement the additional phase shift. The available additional phase shift
is implemented in 2s-complement between settings –64 to +63 for
frequency mode 0, and between settings –32 to +31 for frequency modes
1, 2, and 3. However, the DQS delay settings are at the maximum at
setting 64 for frequency mode 0, and at the maximum at setting 32 for
frequency modes 1, 2, and 3. Therefore, the actual physical offset setting
range will be 64 or 32 subtracted by the DQS delay settings from the DLL.
For example, if the DLL determines that to achieve 30° you will need a
DQS delay setting of 28, you can subtract up to 28 phase offset settings
and you can add up to 36 phase offset settings to achieve the optimal
delay.
1
Each phase offset setting translates to a certain delay, as
specified in the DC & Switching Characteristics of Stratix III
Devices chapter in volume 2 of the Stratix III Device Handbook.
When using the static phase offset, you can specify the phase offset
amount in the altdqs megafunction as a positive number for addition or
a negative number for subtraction. You can also have a dynamic phase
offset that is always added to, subtracted from, or both added to and
subtracted from the DLL phase shift. When you always add or subtract,
you can dynamically input the phase offset amount into the
dll_offset[5..0] port. When you want to both add and subtract
dynamically, you control the addnsub signal in addition to the
dll_offset[5..0] signals.
DQS Logic Block
Each DQS and DQSn pin is connected to a separate DQS logic block (see
Figure 3–11). The logic block contains DQS delay chains and postamble
circuitry.
3–28
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
1
The input reference clock for the DQS phase-shift circuitry on
the top side of the device can come from CLK[15..12]p or
PLL 5. The input reference clock for the DQS phase-shift
circuitry on the bottom side of the device can come from
CLK[7..4]p or PLL 6.
Note (1)
CLRN
(3)
PRN
Q SCLR
DQS bus
EnableN
DQS'
NOT
A
EN
Input Reference
Clock (2)
EN
D
6
DQS Delay
Settings from the
DQS PhaseShift Circuitry
Phase Offset
Settings
6
6
DQS or
DQSn Pin
Bypass
Q
6
6
6
D
Q
6
6
DQS Delay Chain
Update
Enable
Circuitry
B
Postamble Circuitry
gated_dqs control
reset
DFF
VCC
Figure 3–11. Simplified Diagram of the DQS Logic Block
Notes to Figure 3–11:
(1)
(2)
(3)
All features of the DQS logic block are accessible from the altdqs megafunction in the Quartus II software. You
should; however, use Altera’s memory controller IP Tool Bench to generate the data path for your memory interface.
The input reference clock for the DQS phase-shift circuitry on the top side of the device can come from
CLK[15..12]p or PLL 5. The input reference clock for the DQS phase-shift circuitry on the top side of the device
can come from CLK[7..4]p or PLL 6.
This register is one of the DQS IOE input registers.
Altera Corporation
January 2008
3–29
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
DQS Delay Chains
The DQS delay chains consist of a set of variable delay elements to allow
the input DQS and DQSn signals to be shifted by the amount given by the
DQS phase-shift circuitry or the logic array. There are four delay elements
in the DQS delay chain; the first delay chain closest to the DQS pin can
either be shifted by the DQS delay settings or by the sum of the DQS delay
setting and the phase-offset setting. The number of delay chains used is
transparent to the users because the altdqs megafunction automatically
sets it. The DQS delay settings can come from the DQS phase-shift
circuitry on the same side of the device as the target DQS logic block or
from the logic array. When you apply a 0° shift in the altdqs
megafunction, the DQS delay chains are bypassed.
The delay elements in the DQS logic block mimic the delay elements in
the DLL. When the DLL is not used to control the DQS delay chains, you
can input your own 6- or 5-bit settings using the
dqs_delayctrlin[5..0] signals available in the altdqs
megafunction. These settings control 1, 2, 3, or all 4 delay elements in the
DQS delay chains. The amount of delay is equal to the sum of the delay
element’s intrinsic delay and the product of the number of delay steps
and the value of the delay steps.
Both the DQS delay settings and the phase-offset settings pass through a
latch before going into the DQS delay chains. The latches are controlled
by the update enable circuitry to allow enough time for any changes in
the DQS delay setting bits to arrive to all the delay elements. This allows
them to be adjusted at the same time. The update enable circuitry enables
the latch to allow enough time for the DQS delay settings to travel from
the DQS phase-shift circuitry to all the DQS logic blocks before the next
change. It uses the input reference clock to generate the update enable
output. The altdqs megafunction uses this circuit by default. See
Figure 3–12 for an example waveform of the update enable circuitry
output.
The shifted DQS signal then goes to the DQS bus to clock the IOE input
registers of the DQ pins. It can also go into the logic array for
resynchronization purposes. The shifted DQSn signal can only go to the
active-low input register in the DQ IOE and is only used for QDRII SRAM
interfaces.
3–30
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–12. DQS Update Enable Waveform
DLL Counter Update
(Every Eight Cycles)
DLL Counter Update
(Every Eight Cycles)
System Clock
DQS Delay Settings
(Updated every 8 cycles)
6 bit
Update Enable
Circuitry Output
DQS Postamble Circuitry
For external memory interfaces that use a bidirectional read strobe like
DDR and DDR2 SDRAM, the DQS signal is low before going to or coming
from a high-impedance state. See Figure 3–3. The state where DQS is low,
just after a high-impedance state, is called the preamble and the state
where DQS is low, just before it returns to a high-impedance state, is
called the postamble. There are preamble and postamble specifications
for both read and write operations in DDR and DDR2 SDRAM. The DQS
postamble circuitry ensures data is not lost when there is noise on the
DQS line at the end of a read postamble time. It is to be used with one of
the DQS IOE input registers such that the DQS postamble control signal
can ground the shifted DQS signal used to clock the DQ input registers at
the end of a read operation. This ensures that any glitches on the DQS
input signals at the end of the read postamble time do not affect the DQ
IOE registers.
f
See AN 327: Interfacing DDR SDRAM with Stratix II Devices and AN 328:
Interfacing DDR2 SDRAM with Stratix II Devices for more details.
DDR Registers
Each IOE in a Stratix II or Stratix II GX device contains six registers and
one latch. Two registers and a latch are used for input, two registers are
used for output, and two registers are used for output enable control. The
second output enable register provides the write preamble for the DQS
strobe in the DDR external memory interfaces. This active low output
enable register extends the high-impedance state of the pin by a half clock
cycle to provide the external memory’s DQS write preamble time
specification. Figure 3–13 shows the six registers and the latch in the
Stratix II or Stratix II GX IOE and Figure 3–14 shows how the second OE
register extends the DQS high-impedance state by half a clock cycle
during a write operation.
Altera Corporation
January 2008
3–31
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
Figure 3–13. Bidirectional DDR I/O Path in Stratix II and Stratix II GX Devices
Note (1)
DFF
OE
(2)
D
Q
OR2
OE Register AOE (3)
1
0
(4)
DFF
D
Q
OE Register BOE (5)
DFF
datain_l
D
Q
0
1
TRI (6)
I/O Pin (7)
Output Register AO
DFF
Logic Array
datain_h
D
Q
Output Register BO
outclock
combout
DFF
dataout_h
Q
D
Input Register AI
LatchTCHLA
dataout_l
Q
D
DFF
neg_reg_out
Q
D
ENA
Latch C I
Input Register BI (8)
inclock
Notes to Figure 3–13:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
All control signals can be inverted at the IOE. The signal names used here match with Quartus II software naming
convention.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before input to the AOE register during compilation.
The AOE register generates the enable signal for general-purpose DDR I/O applications.
This select line is to choose whether the OE signal should be delayed by half-a-clock cycle.
The BOE register generates the delayed enable signal for the write strobes or write clocks for memory interfaces.
The tristate enable is by default active low. You can, however, design it to be active high. The combinational control
path for the tristate is not shown in this diagram.
You can also have combinational output to the I/O pin; this path is not shown in the diagram.
On the top and bottom I/O banks, the clock to this register can be an inverted register A’s clock or a separate clock
(inverted or non-inverted). On the side I/O banks, you can only use the inverted register A’s clock for this port.
3–32
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Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–14. Extending the OE Disable by Half-a-Clock Cycle for a Write Transaction
Note (1)
System clock
(outclock for DQS)
OE for DQS
(from logic array)
DQS
90˚
Delay
by Half
a Clock
Cycle
Preamble
Postamble
Write Clock
(outclock for DQ,
−90° phase shifted
from System Clock)
datain_h
(from logic array)
D0
D2
datain_l
(from logic array)
D1
D3
OE for DQ
(from logic array)
DQ
D0
D1
D2
D3
Note to Figure 3–14:
(1)
The waveform reflects the software simulation result. The OE signal is an active low on the device. However, the
Quartus II software implements this signal as an active high and automatically adds an inverter before the AOE
register D input.
Figures 3–15 and 3–16 summarize the IOE registers used for the DQ and
DQS signals.
Altera Corporation
January 2008
3–33
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
Figure 3–15. DQ Configuration in Stratix II or Stratix II GX IOE
Note (1)
DFF
(2)
D
OE
Q
OE Register AOE
DFF
D
datain_l
Q
0
TRI
1
Output Register AO
DQ Pin
DFF
Logic Array
D
datain_h
Q
Output Register BO
outclock (3)
DFF
Q
D
dataout_h
Input Register AI
Latch
TCH
LA
Q
dataout_l
D
ENA
Latch C I
DFF
neg_reg_out
Q
D
(4)
Input Register BI (6)
inclock (from DQS bus)
(5)
Notes to Figure 3–15:
(1)
(2)
(3)
(4)
(5)
(6)
You can use the altdq megafunction to generate the DQ signals. You should, however, use Altera’s memory
controller IP Tool Bench to generate the data path for your memory interface. The signal names used here match
with Quartus II software naming convention.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before the OE register AOE during compilation.
The outclock signal for DDR, DDR2 SDRAM, and QDRII SRAM interfaces has a 90° phase-shift relationship with
the system clock. For 300-MHz RLDRAM II interfaces with EP2S60F1020C3, Altera recommends a 75° phase-shift
relationship.
The shifted DQS or DQSn signal can clock this register. Only use the DQSn signal for QDRII SRAM interfaces.
The shifted DQS signal must be inverted before going to the DQ IOE. The inversion is automatic if you use the
altdq megafunction to generate the DQ signals. Connect this port to the combout port in the altdqs
megafunction.
On the top and bottom I/O banks, the clock to this register can be an inverted register A’s clock or a separate clock
(inverted or non-inverted). On the side I/O banks, you can only use the inverted register A’s clock for this port.
3–34
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–16. DQS Configuration in Stratix II or Stratix II GX IOE
Note (1)
DFF
OE
(2)
D
Q
OE Register AOE
OR2
1
0
(3)
DFF
D
Q
OE Register BOE
DFF
Logic Array
datain_h (4)
D
Q
TRI
Output Register AO
DQS Pin (5)
1
0
DFF
datain_l (4)
system clock
D
Q
Output Register BO
combout (7)
Notes to Figure 3–16:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
You can use the altdqs megafunction to generate the DQS signals. You should, however, use Altera’s memory
controller IP Tool Bench to generate the data path for your memory interface. The signal names used here match
with Quartus II software naming convention.
The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before OE register AOE during compilation. In RLDRAM II and QDRII SRAM, the OE signal is always
disabled.
The select line can be chosen in the altdqs megafunction.
The datain_l and datain_h pins are usually connected to ground and VCC, respectively.
DQS postamble circuitry and handling is not shown in this diagram. For more information, see AN 327: Interfacing
DDR SDRAM with Stratix II Devices and AN 328: Interfacing DDR2 SDRAM with Stratix II Devices.
DQS logic blocks are only available with DQS and DQSn pins.
You must invert this signal before it reaches the DQ IOE. This signal is automatically inverted if you use the altdq
megafunction to generate the DQ signals. Connect this port to the inclock port in the altdq megafunction.
Altera Corporation
January 2008
3–35
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX DDR Memory Support Overview
For interfaces to DDR SDRAM, DDR2 SDRAM, and RLDRAM II, the
Stratix II or Stratix II GX DDR IOE structure requires you to invert the
incoming DQS signal to ensure proper data transfer. This is not required
for QDRII SRAM interfaces if the CQ signal is wired to the DQS pin and
the CQ# signal is wired to the DQSn pin. The altdq megafunction, by
default, adds the inverter to the inclock port when it generates DQ
blocks. The megafunction also includes an option to remove the inverter
for QDRII SRAM interfaces. As shown in Figure 3–13, the inclock
signal’s rising edge clocks the AI register, inclock signal’s falling edge
clocks the BI register, and latch CI is opened when inclock is 1. In a DDR
memory read operation, the last data coincides with DQS being low. If
you do not invert the DQS pin, you will not get this last data as the latch
does not open until the next rising edge of the DQS signal.
Figure 3–17 shows waveforms of the circuit shown in Figure 3–15.
The first set of waveforms in Figure 3–17 shows the edge-aligned
relationship between the DQ and DQS signals at the Stratix II or
Stratix II GX device pins. The second set of waveforms in Figure 3–17
shows what happens if the shifted DQS signal is not inverted; the last
data, Dn, does not get latched into the logic array as DQS goes to tristate
after the read postamble time. The third set of waveforms in Figure 3–17
shows a proper read operation with the DQS signal inverted after the 90°
shift; the last data, Dn, does get latched. In this case the outputs of register
AI and latch CI, which correspond to dataout_h and dataout_l ports,
are now switched because of the DQS inversion. Register AI, register BI,
and latch CI refer to the nomenclature in Figure 3–15.
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Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–17. DQ Captures with Non-Inverted and Inverted Shifted DQS
DQ & DQS Signals
DQ at the pin
Dn − 1
Dn
DQS at the pin
Shifted DQS Signal is Not Inverted
DQS shifted
by 90˚
Output of register A1
(dataout_h)
Output of register B1
Output of latch C1
(dataout_l)
Dn − 1
Dn − 2
Dn
Dn − 2
Shifted DQS Signal is Inverted
DQS inverted and
shifted by 90˚
Output of register A1
(dataout_h)
Output of register B1
Output of latch C1
(dataout_l)
Altera Corporation
January 2008
Dn − 2
Dn
Dn − 1
Dn − 3
Dn − 1
3–37
Stratix II Device Handbook, Volume 2
Enhancements In Stratix II and Stratix II GX Devices
PLL
When using the Stratix II and Stratix II GX top and bottom I/O banks
(I/O banks 3, 4, 7, or 8) to interface with a DDR memory, at least one PLL
with two outputs is needed to generate the system clock and the write
clock. The system clock generates the DQS write signals, commands, and
addresses. The write clock is either shifted by –90° or 90° from the system
clock and is used to generate the DQ signals during writes.
For DDR and DDR2 SDRAM interfaces above 200 MHz, Altera also
recommends a second read PLL to help ease resynchronization.
When using the Stratix II and Stratix II GX side I/O banks 1, 2, 5, or 6 to
interface with DDR SDRAM devices, two PLLs may be needed per I/O
bank for best performance. Since the side I/O banks do not have
dedicated circuitry, one PLL captures data from the DDR SDRAM and
another PLL generates the write signals, commands, and addresses to the
DDR SDRAM device. Stratix II and Stratix II GX side I/O banks can
support DDR SDRAM up to 150 MHz.
Enhancements
In Stratix II and
Stratix II GX
Devices
Stratix II and Stratix II GX external memory interfaces support differs
from Stratix external memory interfaces support in the following ways:
■
■
■
■
■
■
■
■
Conclusion
A PLL output can now be used as the input reference clock to the
DLL.
The shifted DQS signal can now go into the logic array.
The DLL in Stratix II and Stratix II GX devices has more phase-shift
options than in Stratix devices. It also has the option to add phase
offset settings.
Stratix II and Stratix II GX devices have DQS logic blocks with each
DQS pin that helps with fine tuning the phase shift.
The DQS delay settings can be routed from the DLL into the logic
array. You can also bypass the DLL and send the DQS delay settings
from the logic array to the DQS logic block.
Stratix II and Stratix II GX devices support DQSn pins.
The DQS/DQ groups now support ×4, ×9, ×18, and ×36 bus modes.
The DQS pins have been enhanced with the DQS postamble circuitry.
Stratix II and Stratix II GX devices support SDR SDRAM, DDR SDRAM,
DDR2 SDRAM, RLDRAM II, and QDRII SRAM external memories.
Stratix II and Stratix II GX devices feature high-speed interfaces that
transfer data between external memory devices at up to 300 MHz/600
Mbps. DQS phase-shift circuitry and DQS logic blocks within the
Stratix II and Stratix II GX devices allow you to fine-tune the phase shifts
for the input clocks or strobes to properly align clock edges as needed to
capture data.
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January 2008
External Memory Interfaces in Stratix II and Stratix II GX Devices
Referenced
Documents
This chapter references the following documents:
■
■
■
■
■
Document
Revision History
AN 325: Interfacing RLDRAM II with Stratix II & Stratix GX Devices
AN 326: Interfacing QDRII & QDRII+ SRAM with Stratix II, Stratix, &
Stratix GX Devices
AN 327: Interfacing DDR SDRAM with Stratix II Devices
AN 328: Interfacing DDR2 SDRAM with Stratix II Devices
DC & Switching Characteristics of Stratix III Devices chapter in
volume 2 of the Stratix III Device Handbook
Table 3–11 shows the revision history for this chapter.
Table 3–11. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
January 2008,
v4.5
Added the “Referenced Documents” section.
—
No change
For the Stratix II GX Device Handbook only:
Formerly chapter 8. The chapter number changed
due to the addition of the Stratix II GX Dynamic
Reconfiguration chapter. No content change.
—
May 2007,
v4.4
Updated the “Phase Offset Control” section.
—
Updated Figure 3–2.
—
Updated Table 3–1.
—
Minor text edits.
Added Table 3–4 and Table 3–6.
—
Updated Note (1) to Figure 3–10.
—
February 2007
v4.3
Added the “Document Revision History” section to
this chapter.
—
April 2006, v4.2
Chapter updated as part of the Stratix II Device
Handbook update.
—
No change
Formerly chapter 7. Chapter number change only
due to chapter addition to Section I in
February 2006; no content change.
—
December 2005
v4.1
Chapter updated as part of the Stratix II Device
Handbook update.
—
October 2005
v4.0
Added chapter to the Stratix II GX Device
Handbook.
—
Altera Corporation
January 2008
3–39
Stratix II Device Handbook, Volume 2
Document Revision History
3–40
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Section III. I/O Standards
This section provides information on Stratix® II single-ended, voltagereferenced, and differential I/O standards.
This section contains the following chapters:
Revision History
Altera Corporation
■
Chapter 4, Selectable I/O Standards in Stratix II and Stratix II GX
Devices
■
Chapter 5, High-Speed Differential I/O Interfaces with DPA in
Stratix II and Stratix II GX Devices
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section III–1
Preliminary
I/O Standards
Section III–2
Preliminary
Stratix II Device Handbook, Volume 2
Altera Corporation
4. Selectable I/O Standards in
Stratix II and Stratix II GX
Devices
SII52004-4.6
Introduction
This chapter provides guidelines for using industry I/O standards in
Stratix® II and Stratix II GX devices, including:
■
■
■
■
■
Stratix II and
Stratix II GX I/O
Features
I/O features
I/O standards
External memory interfaces
I/O banks
Design considerations
Stratix II and the Stratix II GX devices contain an abundance of adaptive
logic modules (ALMs), embedded memory, high-bandwidth digital
signal processing (DSP) blocks, and extensive routing resources, all of
which can operate at very high core speed.
Stratix II and Stratix II GX devices I/O structure is designed to ensure
that these internal capabilities are fully utilized. There are numerous I/O
features to assist in high-speed data transfer into and out of the device
including:
■
■
Single-ended, non-voltage-referenced and voltage-referenced I/O
standards
High-speed differential I/O standards featuring
serializer/deserializer (SERDES), dynamic phase alignment (DPA),
capable of 1 gigabit per second (Gbps) performance for low-voltage
differential signaling (LVDS), Hypertransport technology, HSTL,
SSTL, and LVPECL
1
■
■
■
■
■
■
■
Altera Corporation
January 2008
HSTL and SSTL I/O standards are used only for PLL clock
inputs and outputs in differential mode. LVPECL is
supported on clock input and outputs of the top and bottom
I/O banks.
Double data rate (DDR) I/O pins
Programmable output drive strength for voltage-referenced and
non-voltage-referenced single-ended I/O standards
Programmable bus-hold
Programmable pull-up resistor
Open-drain output
On-chip series termination
On-chip parallel termination
4–1
Stratix II and Stratix II GX I/O Standards Support
■
■
■
f
Stratix II and
Stratix II GX I/O
Standards
Support
On-chip differential termination
Peripheral component interconnect (PCI) clamping diode
Hot socketing
For a detailed description of each I/O feature, refer to the Stratix II
Architecture chapter in volume 1 of the Stratix II Device Handbook or the
Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device
Handbook.
Stratix II and Stratix II GX devices support a wide range of industry I/O
standards. Table 4–1 shows which I/O standards Stratix II devices
support as well as typical applications.
Table 4–1. Stratix II and Stratix II GX I/O Standard Applications (Part 1 of 2)
I/O Standard
Application
LVTTL
General purpose
LVCMOS
General purpose
2.5 V
General purpose
1.8 V
General purpose
1.5 V
General purpose
3.3-V PCI
PC and embedded system
3.3-V PCI-X
PC and embedded system
SSTL-2 Class I
DDR SDRAM
SSTL-2 Class II
DDR SDRAM
SSTL-18 Class I
DDR2 SDRAM
SSTL-18 Class II
DDR2 SDRAM
1.8-V HSTL Class I
QDRII SRAM/RLDRAM II/SRAM
1.8-V HSTL Class II
QDRII SRAM/RLDRAM II/SRAM
1.5-V HSTL Class I
QDRII SRAM/SRAM
1.5-V HSTL Class II
QDRII SRAM/SRAM
1.2-V HSTL
General purpose
Differential SSTL-2 Class I
DDR SDRAM
Differential SSTL-2 Class II
DDR SDRAM
Differential SSTL-18 Class I
DDR2 SDRAM
Differential SSTL-18 Class II
DDR2 SDRAM
1.8-V differential HSTL Class I
Clock interfaces
1.8-V differential HSTL Class II
Clock interfaces
1.5-V differential HSTL Class I
Clock interfaces
4–2
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Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–1. Stratix II and Stratix II GX I/O Standard Applications (Part 2 of 2)
I/O Standard
1.5-V differential HSTL Class II
Application
Clock interfaces
LVDS
High-speed communications
HyperTransport™ technology
PCB interfaces
Differential LVPECL
Video graphics and clock distribution
Single-Ended I/O Standards
In non-voltage-referenced single-ended I/O standards, the voltage at the
input must be above a set voltage to be considered “on” (high, or logic
value 1) or below another voltage to be considered “off” (low, or logic
value 0). Voltages between the limits are undefined logically, and may fall
into either a logic value 0 or 1. The non-voltage-referenced single-ended
I/O standards supported by Stratix II and Stratix II GX devices are:
■
■
■
■
■
■
■
Low-voltage transistor-transistor logic (LVTTL)
Low-voltage complementary metal-oxide semiconductor (LVCMOS)
1.5 V
1.8 V
2.5 V
3.3-V PCI
3.3-V PCI-X
Voltage-referenced, single-ended I/O standards provide faster data rates.
These standards use a constant reference voltage at the input levels. The
incoming signals are compared with this constant voltage and the
difference between the two defines “on” and “off” states.
1
Stratix II and Stratix II GX devices support stub series
terminated logic (SSTL) and high-speed transceiver logic
(HSTL) voltage-referenced I/O standards.
LVTTL
The LVTTL standard is formulated under EIA/JEDEC Standard, JESD8-B
(Revision of JESD8-A): Interface Standard for Nominal 3-V/3.3-V Supply
Digital Integrated Circuits.
The standard defines DC interface parameters for digital circuits
operating from a 3.0- or 3.3-V power supply and driving or being driven
by LVTTL-compatible devices. The 3.3-V LVTTL standard is a
Altera Corporation
January 2008
4–3
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX I/O Standards Support
general-purpose, single-ended standard used for 3.3-V applications. This
I/O standard does not require input reference voltages (VREF) or
termination voltages (VTT).
1
Stratix II and Stratix II GX devices support both input and
output levels for 3.3-V LVTTL operation.
Stratix II Stratix II GX devices support a VCCIO voltage level of 3.3 V  5%
as specified as the narrow range for the voltage supply by the
EIA/JEDEC standard.
LVCMOS
The LVCMOS standard is formulated under EIA/JEDEC Standard,
JESD8-B (Revision of JESD8-A): Interface Standard for Nominal
3-V/3.3-V Supply Digital Integrated Circuits.
The standard defines DC interface parameters for digital circuits
operating from a 3.0- or 3.3-V power supply and driving or being driven
by LVCMOS-compatible devices. The 3.3-V LVCMOS I/O standard is a
general-purpose, single-ended standard used for 3.3-V applications.
While LVCMOS has its own output specification, it specifies the same
input voltage requirements as LVTTL. These I/O standards do not
require VREF or VTT.
1
Stratix II and Stratix II GX devices support both input and
output levels for 3.3-V LVCMOS operation.
Stratix II and Stratix II GX devices support a VCCIO voltage level of
3.3 V  5% as specified as the narrow range for the voltage supply by the
EIA/JEDEC standard.
2.5 V
The 2.5-V I/O standard is formulated under EIA/JEDEC Standard,
EIA/JESD8-5: 2.5-V± 0.2-V (Normal Range), and 1.8-V – 2.7-V (Wide
Range) Power Supply Voltage and Interface Standard for
Non-Terminated Digital Integrated Circuit.
The standard defines the DC interface parameters for high-speed,
low-voltage, non-terminated digital circuits driving or being driven by
other 2.5-V devices. This standard is a general-purpose, single-ended
standard used for 2.5-V applications. It does not require the use of a VREF
or a VTT.
4–4
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
1
Stratix II and Stratix II GX devices support both input and
output levels for 2.5-V operation with VCCIO voltage level
support of 2.5 V ± 5%, which is narrower than defined in the
Normal Range of the EIA/JEDEC standard.
1.8 V
The 1.8-V I/O standard is formulated under EIA/JEDEC Standard,
EIA/JESD8-7: 1.8-V± 0.15-V (Normal Range), and 1.2-V – 1.95-V (Wide
Range) Power Supply Voltage and Interface Standard for
Non-Terminated Digital Integrated Circuit.
The standard defines the DC interface parameters for high-speed,
low-voltage, non-terminated digital circuits driving or being driven by
other 1.8-V devices. This standard is a general-purpose, single-ended
standard used for 1.8-V applications. It does not require the use of a VREF
or a VTT.
1
Stratix II and Stratix II GX devices support both input and
output levels for 1.8-V operation with VCCIO voltage level
support of 1.8 V ± 5%, which is narrower than defined in the
Normal Range of the EIA/JEDEC standard.
1.5 V
The 1.5-V I/O standard is formulated under EIA/JEDEC Standard,
JESD8-11: 1.5-V± 0.1-V (Normal Range) and 0.9-V – 1.6-V (Wide Range)
Power Supply Voltage and Interface Standard for Non-Terminated
Digital Integrated Circuit.
The standard defines the DC interface parameters for high-speed,
low-voltage, non-terminated digital circuits driving or being driven by
other 1.5-V devices. This standard is a general-purpose, single-ended
standard used for 1.5-V applications. It does not require the use of a VREF
or a VTT.
1
Stratix II and Stratix II GX devices support both input and
output levels for 1.5-V operation VCCIO voltage level support of
1.5 V ± 5%, which is narrower than defined in the Normal Range
of the EIA/JEDEC standard.
3.3-V PCI
The 3.3-V PCI I/O standard is formulated under PCI Local Bus
Specification Revision 2.2 developed by the PCI Special Interest Group
(SIG).
Altera Corporation
January 2008
4–5
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX I/O Standards Support
The PCI local bus specification is used for applications that interface to
the PCI local bus, which provides a processor-independent data path
between highly integrated peripheral controller components, peripheral
add-in boards, and processor/memory systems. The conventional PCI
specification revision 2.2 defines the PCI hardware environment
including the protocol, electrical, mechanical, and configuration
specifications for the PCI devices and expansion boards. This standard
requires 3.3-V VCCIO. Stratix II and Stratix II GX devices are fully
compliant with the 3.3-V PCI Local Bus Specification Revision 2.2 and
meet 64-bit/66-MHz operating frequency and timing requirements.
1
The 3.3-V PCI standard does not require input reference
voltages or board terminations. Stratix II and Stratix II GX
devices support both input and output levels.
3.3-V PCI-X
The 3.3-V PCI-X I/O standard is formulated under PCI-X Local Bus
Specification Revision 1.0a developed by the PCI SIG.
The PCI-X 1.0 standard is used for applications that interface to the PCI
local bus. The standard enables the design of systems and devices that
operate at clock speeds up to 133 MHz, or 1 Gbps for a 64-bit bus. The
PCI-X 1.0 protocol enhancements enable devices to operate much more
efficiently, providing more usable bandwidth at any clock frequency. By
using the PCI-X 1.0 standard, you can design devices to meet PCI-X 1.0
requirements and operate as conventional 33- and 66-MHz PCI devices
when installed in those systems. This standard requires 3.3-V VCCIO.
Stratix II and Stratix II GX devices are fully compliant with the 3.3-V
PCI-X Specification Revision 1.0a and meet the 133-MHz operating
frequency and timing requirements. The 3.3-V PCI-X standard does not
require input reference voltages or board terminations.
1
Stratix II and Stratix II GX devices support both input and
output levels operation.
SSTL-2 Class I and SSTL-2 Class II
The 2.5-V SSTL-2 standard is formulated under JEDEC Standard,
JESD8-9A: Stub Series Terminated Logic for 2.5-V (SSTL_2).
The SSTL-2 I/O standard is a 2.5-V memory bus standard used for
applications such as high-speed DDR SDRAM interfaces. This standard
defines the input and output specifications for devices that operate in the
SSTL-2 logic switching range of 0.0 to 2.5 V. This standard improves
4–6
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Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
operation in conditions where a bus must be isolated from large stubs.
SSTL-2 requires a 1.25-V VREF and a 1.25-V VTT to which the series and
termination resistors are connected (Figures 4–1 and 4–2).
1
Stratix II and Stratix II GX devices support both input and
output levels operation.
Figure 4–1. 2.5-V SSTL Class I Termination
VTT = 1.25 V
Output Buffer
50 Ω
25 Ω
Z = 50 Ω
Input Buffer
VREF = 1.25 V
Figure 4–2. 2.5-V SSTL Class II Termination
VTT = 1.25 V
VTT = 1.25 V
Output Buffer
50 Ω
25 Ω
50 Ω
Z = 50 Ω
Input Buffer
VREF = 1.25 V
SSTL-18 Class I and SSTL-18 Class II
The 1.8-V SSTL-18 standard is formulated under JEDEC Standard,
JESD8-15: Stub Series Terminated Logic for 1.8-V (SSTL_18).
The SSTL-18 I/O standard is a 1.8-V memory bus standard used for
applications such as high-speed DDR2 SDRAM interfaces. This standard
is similar to SSTL-2 and defines input and output specifications for
devices that are designed to operate in the SSTL-18 logic switching range
0.0 to 1.8 V. SSTL-18 requires a 0.9-V VREF and a 0.9-V VTT to which the
series and termination resistors are connected.
There are no class definitions for the SSTL-18 standard in the JEDEC
specification. The specification of this I/O standard is based on an
environment that consists of both series and parallel terminating
resistors. Altera provides solutions to two derived applications in JEDEC
specification, and names them Class I and Class II to be consistent with
other SSTL standards. Figures 4–3 and 4–4 show SSTL-18 Class I and II
termination, respectively.
Altera Corporation
January 2008
4–7
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX I/O Standards Support
1
Stratix II and Stratix II GX devices support both input and
output levels operation.
Figure 4–3. 1.8-V SSTL Class I Termination
VTT = 0.9 V
Output Buffer
50 Ω
25 Ω
Z = 50 Ω
Input Buffer
VREF = 0.9 V
Figure 4–4. 1.8-V SSTL Class II Termination
VTT = 0.9 V
VTT = 0.9 V
50 Ω
50 Ω
Output Buffer
25 Ω
Z = 50 Ω
Input Buffer
VREF = 0.9 V
1.8-V HSTL Class I and 1.8-V HSTL Class II
The HSTL standard is a technology-independent I/O standard
developed by JEDEC to provide voltage scalability. It is used for
applications designed to operate in the 0.0- to 1.8-V HSTL logic switching
range such as quad data rate (QDR) memory clock interfaces.
Although JEDEC specifies a maximum VCCIO value of 1.6 V, there are
various memory chip vendors with HSTL standards that require a VCCIO
of 1.8 V. Stratix II and Stratix II GX devices support interfaces to chips
with VCCIO of 1.8 V for HSTL. Figures 4–5 and 4–6 show the nominal VREF
and VTT required to track the higher value of VCCIO. The value of VREF is
selected to provide optimum noise margin in the system.
1
4–8
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX devices support both input and
output levels operation.
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Figure 4–5. 1.8-V HSTL Class I Termination
VTT = 0.9 V
Output Buffer
50 Ω
Z = 50 Ω
Input Buffer
VREF = 0.9 V
Figure 4–6. 1.8-V HSTL Class II Termination
VTT = 0.9 V
VTT = 0.9 V
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
Input Buffer
VREF = 0.9 V
1.5-V HSTL Class I and 1.5-V HSTL Class II
The 1.5-V HSTL standard is formulated under EIA/JEDEC Standard,
EIA/JESD8-6: A 1.5-V Output Buffer Supply Voltage Based Interface
Standard for Digital Integrated Circuits.
The 1.5-V HSTL I/O standard is used for applications designed to operate
in the 0.0- to 1.5-V HSTL logic nominal switching range. This standard
defines single-ended input and output specifications for all
HSTL-compliant digital integrated circuits. The 1.5-V HSTL I/O standard
in Stratix II and Stratix II GX devices are compatible with the 1.8-V HSTL
I/O standard in APEX™ 20KE, APEX 20KC, and in Stratix II and
Stratix II GX devices themselves because the input and output voltage
thresholds are compatible (Figures 4–7 and 4–8).
1
Altera Corporation
January 2008
Stratix II and Stratix II GX devices support both input and
output levels with VREF and VTT.
4–9
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX I/O Standards Support
Figure 4–7. 1.5-V HSTL Class I Termination
VTT = 0.75 V
Output Buffer
50 Ω
Z = 50 Ω
Input Buffer
VREF = 0.75 V
Figure 4–8. 1.5-V HSTL Class II Termination
VTT = 0.75 V
VTT = 0.75 V
Output Buffer
50 Ω
50 Ω
Z = 50 Ω
Input Buffer
VREF = 0.75 V
1.2-V HSTL
Although there is no EIA/JEDEC standard available for the 1.2-V HSTL
standard, Altera supports it for applications that operate in the 0.0 to
1.2-V HSTL logic nominal switching range. 1.2-V HSTL can be terminated
through series or parallel on-chip termination (OCT). Figure 4–9 shows
the termination scheme.
Figure 4–9. 1.2-V HSTL Termination
Output Buffer
Z = 50 Ω
Input Buffer
OCT
VREF = 0.6 V
Differential I/O Standards
Differential I/O standards are used to achieve even faster data rates with
higher noise immunity. Apart from LVDS, LVPECL, and HyperTransport
technology, Stratix II and Stratix II GX devices also support differential
versions of SSTL and HSTL standards.
4–10
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
f
For detailed information on differential I/O standards, refer to the
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II GX Device Handbook.
Differential SSTL-2 Class I and Differential SSTL-2 Class II
The 2.5-V differential SSTL-2 standard is formulated under JEDEC
Standard, JESD8-9A: Stub Series Terminated Logic for 2.5-V (SSTL_2).
This I/O standard is a 2.5-V standard used for applications such as
high-speed DDR SDRAM clock interfaces. This standard supports
differential signals in systems using the SSTL-2 standard and
supplements the SSTL-2 standard for differential clocks. Stratix II and
Stratix II GX devices support both input and output levels. Figures 4–10
and 4–11 shows details on differential SSTL-2 termination.
1
Stratix II and Stratix II GX devices support differential SSTL-2
I/O standards in pseudo-differential mode, which is
implemented by using two SSTL-2 single-ended buffers.
The Quartus® II software only supports pseudo-differential standards on
the INCLK, FBIN and EXTCLK ports of enhanced PLL, as well as on DQS
pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is
used. Two single-ended output buffers are automatically programmed to
have opposite polarity so as to implement a pseudo-differential output. A
proper VREF voltage is required for the two single-ended input buffers to
implement a pseudo-differential input. In this case, only the positive
polarity input is used in the speed path while the negative input is not
connected internally. In other words, only the non-inverted pin is
required to be specified in your design, while the Quartus II software
automatically generates the inverted pin for you.
Although the Quartus II software does not support pseudo-differential
SSTL-2 I/O standards on the left and right I/O banks, you can implement
these standards at these banks. You need to create two pins in the designs
and configure the pins with single-ended SSTL-2 standards. However,
this is limited only to pins that support the differential pin-pair I/O
function and is dependent on the single-ended SSTL-2 standards support
at these banks.
Altera Corporation
January 2008
4–11
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX I/O Standards Support
Figure 4–10. Differential SSTL-2 Class I Termination
VTT = 1.25 V
Differential
Transmitter
50 Ω
VTT = 1.25 V
Differential
Receiver
50 Ω
25 Ω
Z0 = 50 Ω
25 Ω
Z0 = 50 Ω
Figure 4–11. Differential SSTL-2 Class II Termination
VTT = 1.25 V
Differential
Transmitter
50 Ω
VTT = 1.25 V
50 Ω
VTT = 1.25 V
50 Ω
VTT = 1.25 V
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
25 Ω
Z0 = 50 Ω
Differential SSTL-18 Class I and Differential SSTL-18 Class II
The 1.8-V differential SSTL-18 standard is formulated under JEDEC
Standard, JESD8-15: Stub Series Terminated Logic for 1.8-V (SSTL_18).
The differential SSTL-18 I/O standard is a 1.8-V standard used for
applications such as high-speed DDR2 SDRAM interfaces. This standard
supports differential signals in systems using the SSTL-18 standard and
supplements the SSTL-18 standard for differential clocks.
1
4–12
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX devices support both input and
output levels operation.
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Figures 4–12 and 4–13 shows details on differential SSTL-18 termination.
Stratix II and Stratix II GX devices support differential SSTL-18 I/O
standards in pseudo-differential mode, which is implemented by using
two SSTL-18 single-ended buffers.
The Quartus II software only supports pseudo-differential standards on
the INCLK, FBIN and EXTCLK ports of enhanced PLL, as well as on DQS
pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is
used. Two single-ended output buffers are automatically programmed to
have opposite polarity so as to implement a pseudo-differential output. A
proper VREF voltage is required for the two single-ended input buffers to
implement a pseudo-differential input. In this case, only the positive
polarity input is used in the speed path while the negative input is not
connected internally. In other words, only the non-inverted pin is
required to be specified in your design, while the Quartus II software
automatically generates the inverted pin for you.
Although the Quartus II software does not support pseudo-differential
SSTL-18 I/O standards on the left and right I/O banks, you can
implement these standards at these banks. You need to create two pins in
the designs and configure the pins with single-ended SSTL-18 standards.
However, this is limited only to pins that support the differential pin-pair
I/O function and is dependent on the single-ended SSTL-18 standards
support at these banks.
Figure 4–12. Differential SSTL-18 Class I Termination
VTT = 0.9 V
Differential
Transmitter
50 Ω
VTT = 0.9 V
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
25 Ω
Z0 = 50 Ω
Altera Corporation
January 2008
4–13
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX I/O Standards Support
Figure 4–13. Differential SSTL-18 Class II Termination
VTT = 0.9 V
Differential
Transmitter
50 Ω
VTT = 0.9 V
50 Ω
VTT = 0.9 V
50 Ω
VTT = 0.9 V
50 Ω
Differential
Receiver
25 Ω
Z0 = 50 Ω
25 Ω
Z0 = 50 Ω
1.8-V Differential HSTL Class I and 1.8-V Differential HSTL Class II
The 1.8-V differential HSTL specification is the same as the 1.8-V
single-ended HSTL specification. It is used for applications designed to
operate in the 0.0- to 1.8-V HSTL logic switching range such as QDR
memory clock interfaces. Stratix II and Stratix II GX devices support both
input and output levels operation. Figures 4–14 and 4–15 show details on
1.8-V differential HSTL termination.
Stratix II and Stratix II GX devices support 1.8-V differential HSTL I/O
standards in pseudo-differential mode, which is implemented by using
two 1.8-V HSTL single-ended buffers.
The Quartus II software only supports pseudo-differential standards on
the INCLK, FBIN and EXTCLK ports of enhanced PLL, as well as on DQS
pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is
used. Two single-ended output buffers are automatically programmed to
have opposite polarity so as to implement a pseudo-differential output. A
proper VREF voltage is required for the two single-ended input buffers to
implement a pseudo-differential input. In this case, only the positive
polarity input is used in the speed path while the negative input is not
connected internally. In other words, only the non-inverted pin is
required to be specified in your design, while the Quartus II software
automatically generates the inverted pin for you.
Although the Quartus II software does not support 1.8-V
pseudo-differential HSTL I/O standards on left/right I/O banks, you can
implement these standards at these banks. You need to create two pins in
the designs and configure the pins with single-ended 1.8-V HSTL
standards. However, this is limited only to pins that support the
differential pin-pair I/O function and is dependent on the single-ended
1.8-V HSTL standards support at these banks.
4–14
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Figure 4–14. 1.8-V Differential HSTL Class I Termination
VTT = 0.9 V
Differential
Transmitter
50 Ω
VTT = 0.9 V
Differential
Receiver
50 Ω
Z0 = 50 Ω
Z0 = 50 Ω
Figure 4–15. 1.8-V Differential HSTL Class II Termination
VTT = 0.9 V
Differential
Transmitter
50 Ω
VTT = 0.9 V
50 Ω
VTT = 0.9 V
50 Ω
VTT = 0.9 V
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
1.5-V Differential HSTL Class I and 1.5-V Differential HSTL Class II
The 1.5-V differential HSTL standard is formulated under EIA/JEDEC
Standard, EIA/JESD8-6: A 1.5-V Output Buffer Supply Voltage Based
Interface Standard for Digital Integrated Circuits.
The 1.5-V differential HSTL specification is the same as the 1.5-V
single-ended HSTL specification. It is used for applications designed to
operate in the 0.0- to 1.5-V HSTL logic switching range, such as QDR
memory clock interfaces. Stratix II and Stratix II GX devices support both
input and output levels operation. Figures 4–16 and 4–17 show details on
the 1.5-V differential HSTL termination.
Stratix II and Stratix II GX devices support 1.5-V differential HSTL I/O
standards in pseudo-differential mode, which is implemented by using
two 1.5-V HSTL single-ended buffers.
Altera Corporation
January 2008
4–15
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX I/O Standards Support
The Quartus II software only supports pseudo-differential standards on
the INCLK, FBIN and EXTCLK ports of enhanced PLL, as well as on DQS
pins when DQS megafunction (ALTDQS, Bidirectional Data Strobe) is
used. Two single-ended output buffers are automatically programmed to
have opposite polarity so as to implement a pseudo-differential output. A
proper VREF voltage is required for the two single-ended input buffers to
implement a pseudo-differential input. In this case, only the positive
polarity input is used in the speed path while the negative input is not
connected internally. In other words, only the non-inverted pin is
required to be specified in your design, while the Quartus II software
automatically generates the inverted pin for you.
Although the Quartus II software does not support 1.5-V
pseudo-differential HSTL I/O standards on left/right I/O banks, you can
implement these standards at these banks. You need to create two pins in
the designs and configure the pins with single-ended 1.5-V HSTL
standards. However, this is limited only to pins that support the
differential pin-pair I/O function and is dependent on the single-ended
1.8-V HSTL standards support at these banks.
Figure 4–16. 1.5-V Differential HSTL Class I Termination
VTT = 0.75 V
Differential
Transmitter
50 Ω
VTT = 0.75 V
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
4–16
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Figure 4–17. 1.5-V Differential HSTL Class II Termination
VTT = 0.75 V
Differential
Transmitter
50 Ω
VTT = 0.75 V
50 Ω
VTT = 0.75 V
50 Ω
VTT = 0.75 V
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
LVDS
The LVDS standard is formulated under ANSI/TIA/EIA Standard,
ANSI/TIA/EIA-644: Electrical Characteristics of Low Voltage
Differential Signaling Interface Circuits.
The LVDS I/O standard is a differential high-speed, low-voltage swing,
low-power, general-purpose I/O interface standard. In Stratix II devices,
the LVDS I/O standard requires a 2.5-V VCCIO level for the side I/O pins
in banks 1, 2, 5, and 6. The top and bottom banks have different VCCIO
requirements for the LVDS I/O standard. The LVDS clock I/O pins in
banks 9 through 12 require a 3.3-V VCCIO level. Within these banks, the
PLL[5,6,11,12]_OUT[1,2] pins support output only LVDS
operations. The PLL[5,6,11,12]_FB/OUT2 pins support LVDS input
or output operations but cannot be configured for bidirectional LVDS
operations. The LVDS clock input pins in banks 4, 5, 7, and 8 use VCCINT
and have no dependency on the VCCIO voltage level. This standard is used
in applications requiring high-bandwidth data transfer, backplane
drivers, and clock distribution. The ANSI/TIA/EIA-644 standard
specifies LVDS transmitters and receivers capable of operating at
recommended maximum data signaling rates of 655 megabit per second
(Mbps). However, devices can operate at slower speeds if needed, and
there is a theoretical maximum of 1.923 Gbps. Stratix II and Stratix II GX
devices are capable of running at a maximum data rate of 1 Gbps and still
meet the ANSI/TIA/EIA-644 standard.
Because of the low-voltage swing of the LVDS I/O standard, the
electromagnetic interference (EMI) effects are much smaller than
complementary metal-oxide semiconductor (CMOS),
transistor-to-transistor logic (TTL), and positive (or psuedo) emitter
coupled logic (PECL). This low EMI makes LVDS ideal for applications
Altera Corporation
January 2008
4–17
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX I/O Standards Support
with low EMI requirements or noise immunity requirements. The LVDS
standard does not require an input reference voltage. However, it does
require a 100- termination resistor between the two signals at the input
buffer. Stratix II and Stratix II GX devices provide an optional 100-
differential LVDS termination resistor in the device using on-chip
differential termination. Stratix II and Stratix II GX devices support both
input and output levels operation.
Differential LVPECL
The low-voltage positive (or pseudo) emitter coupled logic (LVPECL)
standard is a differential interface standard requiring a 3.3-V VCCIO. The
standard is used in applications involving video graphics,
telecommunications, data communications, and clock distribution. The
high-speed, low-voltage swing LVPECL I/O standard uses a positive
power supply and is similar to LVDS. However, LVPECL has a larger
differential output voltage swing than LVDS. The LVPECL standard does
not require an input reference voltage, but it does require a 100-
termination resistor between the two signals at the input buffer.
Figures 4–18 and 4–19 show two alternate termination schemes for
LVPECL.
1
Stratix II and Stratix II GX devices support both input and
output levels operation.
Figure 4–18. LVPECL DC Coupled Termination
Output Buffer
Input Buffer
Z = 50 Ω
100 Ω
Z = 50 Ω
Figure 4–19. LVPECL AC Coupled Termination
VCCIO
VCCIO
Output Buffer
10 to 100 nF
Z = 50 Ω
R1
R1
R2
R2
Input Buffer
100 Ω
10 to 100 nF
4–18
Stratix II Device Handbook, Volume 2
Z = 50 Ω
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
HyperTransport Technology
The HyperTransport standard is formulated by the HyperTransport
Consortium.
The HyperTransport I/O standard is a differential high-speed,
high-performance I/O interface standard requiring a 2.5- or 3.3-V VCCIO.
This standard is used in applications such as high-performance
networking, telecommunications, embedded systems, consumer
electronics, and Internet connectivity devices. The HyperTransport I/O
standard is a point-to-point standard in which each HyperTransport bus
consists of two point-to-point unidirectional links. Each link is 2 to 32 bits.
The HyperTransport standard does not require an input reference
voltage. However, it does require a 100- termination resistor between
the two signals at the input buffer. Figure 4–20 shows HyperTransport
termination. Stratix II and Stratix II GX devices include an optional 100-
differential HyperTransport termination resistor in the device using
on-chip differential termination.
1
Stratix II and Stratix II GX devices support both input and
output levels operation.
Figure 4–20. HyperTransport Termination
Output Buffer
Input Buffer
Z = 50 Ω
100 Ω
Z = 50 Ω
Stratix II and
Stratix II GX
External
Memory
Interface
f
Altera Corporation
January 2008
The increasing demand for higher-performance data processing systems
often requires memory-intensive applications. Stratix II and Stratix II GX
devices can interface with many types of external memory.
Refer to the External Memory Interfaces in Stratix II & Stratix II GX Devices
chapter in volume 2 of the Stratix II Device Handbook or the External
Memory Interfaces in Stratix II & Stratix II GX Devices chapter in volume 2
of the Stratix II GX Device Handbook for more information on the external
memory interface support in Stratix II or Stratix II GX devices.
4–19
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX I/O Banks
Stratix II and
Stratix II GX I/O
Banks
Stratix II devices have eight general I/O banks and four enhanced
phase-locked loop (PLL) external clock output banks (Figure 4–21). I/O
banks 1, 2, 5, and 6 are on the left or right sides of the device and I/O
banks 3, 4, and 7 through 12 are at the top or bottom of the device.
Figure 4–21. Stratix II I/O Banks Notes (1), (2), (3), (4), (5), (6), (7)
DQS8T
VREF0B3
DQS7T
VREF1B3
DQS6T
VREF2B3
VREF3B3
DQS5T
VREF4B3
PLL11
PLL5
Bank 11
Bank 9
DQS4T
DQS3T
DQS2T
DQS1T
DQS0T
VREF0B4
VREF1B4
VREF2B4
VREF3B4
VREF4B4
PLL7
PLL10
VR EF1B 5
VREF 4B5
VREF 0B2
VR EF3B5
VR EF2B5
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
I/O banks 3, 4, 9 & 11 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
Bank 5
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
VR EF1B2
VR EF2B2
Bank 2
VR EF3B 2
VREF 0B5
Bank 4
VREF 4B2
Bank 3
I/O banks 1, 2, 5 & 6 support LVTTL, LVCMOS,
2.5-V, 1.8-V, 1.5-V, SSTL-2, SSTL-18 Class I,
HSTL-18 Class I, HSTL-15 Class I, LVDS, and
HyperTransport standards for input and output
operations. HSTL-18 Class II, HSTL-15-Class II,
SSTL-18 Class II standards are only supported
for input operations.
PLL1
VR EF1B6
VREF 2B6
Bank 6
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
VREF 4B6
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
VREF 3B6
I/O banks 7, 8, 10 & 12 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
VREF 0B1
VREF 1B1
VREF 2B1
Bank 1
VR EF3B1
VR EF0B6
PLL3
VR EF4B1
PLL2
PLL4
Bank 8
Bank 12
Bank 10
PLL12
PLL6
Bank 7
PLL8
PLL9
VREF4B8
DQS8B
VREF3B8
VREF2B8
DQS7B
VREF1B8
DQS6B
VREF0B8
DQS5B
VREF4B7
VREF3B7
VREF2B7
VREF1B7
VREF0B7
DQS4B
DQS3B
DQS2B
DQS1B
DQS0B
Notes to Figure 4–21:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Figure 4–21 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical
representation only. Refer to the pin list and Quartus II software for exact locations.
Depending on the size of the device, different device members have different numbers of VREF groups.
Banks 9 through 12 are enhanced PLL external clock output banks. These PLL banks utilize the adjacent VREF group
when voltage-referenced standards are implemented. For example, if an SSTL input is implemented in PLL bank
10, the voltage level at VREFB7 is the reference voltage level for the SSTL input.
Differential HSTL and differential SSTL standards are available for bidirectional operations on DQS pin and
input-only operations on PLL clock input pins; LVDS, LVPECL, and HyperTransport standards are available for
input-only operations on PLL clock input pins. Refer to the “Differential I/O Standards” on page 4–10 for more
details.
Quartus II software does not support differential SSTL and differential HSTL standards at left/right I/O banks.
Refer to the “Differential I/O Standards” on page 4–10 if you need to implement these standards at these I/O banks.
Banks 11 and 12 are available only in EP2S60, EP2S90, EP2S130, and EP2S180 devices.
PLLs 7, 8, 9 10, 11, and 12 are available only in EP2S60, EP2S90, EP2S130, and EP2S180 devices.
4–20
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Stratix II GX devices have 6 general I/O banks and 4 enhanced
phase-locked loop (PLL) external clock output banks (Figure 4–22). I/O
banks 9 through 12 are enhanced PLL external clock output banks located
on the top and bottom of the device.
Figure 4–22. Stratix II GX I/O Banks Notes (1), (2), (3), (4)
Bank 2
DQSx8
DQSx8
DQSx8
DQSx8
DQSx8
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
Bank 4
Bank 9
This I/O bank supports LVDS and LVPECL
This I/O bank supports LVDS and LVPECL
standards for input clock operation.
standards for input clock operations.
Differential HSTL and differential SSTL
Differential HSTL and differential SSTL
standards are supported for both input
standards are supported for both input
and output operations. (3)
and output operations. (3)
I/O Banks 3, 4, 9 & 11 support all
single-ended I/O standards for both
input and output operation. All
differential I/O standards are supported
for both input and output operation at
I/O banks 9 & 10.
I/O Banks 1, & 2, support LVTTL, LVCMOS, 2.5 -V, 1.9 -]V, 1.5 -V, SSTL -2, SSTL-18 class I,
LVDS, pseudo-differential SSTL -2, and pseudo-differential SSTL-18 class I standards for both
input and output operations. HSTL, SSTL-18 class II, pseudo-differential HSTL, and
pseudo-differential SSTL-18 class II standards are only supported for input operations. (4)
PLL1
PLL2
PLL8
This I/O bank supports LVDS and LVPECL
standards for input clock operations.
Differential HSTL and differential SSTL
standards are supported for both input
and output operations. (3)
Bank 16
I/O Banks 7, 8, 10 and 12 support all
single-ended I/O standards for both input
and output operation. All differential I/O
standards are supported for both input and output
operations at I/O bank 10 and 12.
Bank 1
VREF0B1 VREF1B1 VREF2B1 VREF3B1 VREF4B1
Bank 11
PLL5
This I/O bank supports LVDS and LVPECL
standards for input clock operations.
Differential HSTL and differential SSTL
standards are supported for both input
and output operations. (3)
Bank 15
VREF0B2 VREF1B2 VREF2B2 VREF3B2 VREF4B2
Bank 3
PLL11
Bank 8
Bank 12
Bank 10
Bank 7
VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
PLL12
PLL6
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
DQSx8
DQSx8
DQSx8
DQSx8
Bank 13
DQSx8
Bank 14
DQSx8
DQSx8
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
Bank 17
DQSx8
PLL7
DQSx8
DQSx8
DQSx8
DQSx8
DQSx8
Notes to Figure 4–22:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Figure 4–22 is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. It is a
graphical representation only.
Depending on size of the device, different device members have different number of VREF groups. Refer to the pin
list and the Quartus II software for exact locations.
Banks 9 through 12 are enhanced PLL external clock output banks.
Horizontal I/O banks feature transceiver and DPA circuitry for high speed differential I/O standards. Refer to the
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II GX Device Handbook, or the Stratix II GX Transceiver User Guide (volume 1) of the Stratix II GX Device
Handbook for more information on differential I/O standards.
Quartus II software does not support differential SSTL and differential HSTL standards at left/right I/O banks.
Refer to the “Differential I/O Standards” on page 4–10 if you need to implement these standards at these I/O banks.
Banks 11 and 12 are available only in EP2SGX60C/D/E, EP2SGX90E/F, and EP2SGX130G.
PLLs 7,8,11, and 12 are available only in EP2SGX60C/D/E, EP2SGXE/F, and EP2SGX130G.
Altera Corporation
January 2008
4–21
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX I/O Banks
Programmable I/O Standards
Stratix II and Stratix II GX device programmable I/O standards deliver
high-speed and high-performance solutions in many complex design
systems. This section discusses the I/O standard support in the I/O
banks of Stratix II and Stratix II GX devices.
Regular I/O Pins
Most Stratix II and Stratix II GX device pins are multi-function pins.
These pins support regular inputs and outputs as their primary function,
and offer an optional function such as DQS, differential pin-pair, or PLL
external clock outputs. For example, you can configure a multi-function
pin in the enhanced PLL external clock output bank as a PLL external
clock output when it is not used as a regular I/O pin.
1
I/O pins that reside in PLL banks 9 through 12 are powered by
the VCC_PLL<5, 6, 11, or 12>_OUT pins, respectively. The
EP2S60F484, EP2S60F780, EP2S90H484, EP2S90F780, and
EP2S130F780 devices do not support PLLs 11 and 12. Therefore,
any I/O pins that reside in bank 11 are powered by the VCCIO3
pin, and any I/O pins that reside in bank 12 are powered by the
VCCIO8 pin.
Table 4–2 shows the I/O standards supported when a pin is used as a
regular I/O pin in the I/O banks of Stratix II and Stratix II GX devices.
Table 4–2. Stratix II and Stratix II GX Regular I/O Standards Support (Part 1 of 2)
Enhanced PLL External
Clock Output Bank (2)
General I/O Bank
I/O Standard
1
2
3
4
5(1) 6(1)
7
8
9
10
11
12
LVTTL
v
v
v
v
v
v
v
v
v
v
v
v
LVCMOS
v
v
v
v
v
v
v
v
v
v
v
v
2.5 V
v
v
v
v
v
v
v
v
v
v
v
v
1.8 V
v
v
v
v
v
v
v
v
v
v
v
v
1.5 V
v
v
v
v
v
v
v
v
v
v
v
v
3.3-V PCI
v
v
v
v
v
v
v
v
3.3-V PCI-X
v
v
v
v
v
v
v
v
SSTL-2 Class I
v
v
v
v
v
v
v
v
v
v
v
v
SSTL-2 Class II
v
v
v
v
v
v
v
v
v
v
v
v
4–22
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–2. Stratix II and Stratix II GX Regular I/O Standards Support (Part 2 of 2)
Enhanced PLL External
Clock Output Bank (2)
General I/O Bank
I/O Standard
1
2
3
4
5(1) 6(1)
7
8
9
10
11
12
SSTL-18 Class I
v
v
v
v
v
v
v
v
v
v
v
v
SSTL-18 Class II
(3)
(3)
v
v
(3)
(3)
v
v
v
v
v
v
1.8-V HSTL Class I
v
v
v
v
v
v
v
v
v
v
v
v
1.8-V HSTL Class II
(3)
(3)
v
v
(3)
(3)
v
v
v
v
v
v
1.5-V HSTL Class I
v
v
v
v
v
v
v
v
v
v
v
v
1.5-V HSTL Class II
(3)
(3)
v
v
(3)
(3)
v
v
v
v
v
v
v
v
v
1.2-V HSTL
Differential SSTL-2 Class I
(4)
(4)
(5)
(5)
(4)
(4)
(5)
(5)
Differential SSTL-2 Class II
(4)
(4)
(5)
(5)
(4)
(4)
(5)
(5)
Differential SSTL-18 Class I
(4)
(4)
(5)
(5)
(4)
(4)
(5)
(5)
Differential SSTL-18 Class II
(4)
(4)
(5)
(5)
(4)
(4)
(5)
(5)
1.8-V differential HSTL Class I
(4)
(4)
(5)
(5)
(4)
(4)
(5)
(5)
1.8-V differential HSTL Class II
(4)
(4)
(5)
(5)
(4)
(4)
(5)
(5)
1.5-V differential HSTL Class I
(4)
(4)
(5)
(5)
(4)
(4)
(5)
(5)
1.5-V differential HSTL Class II
(4)
(4)
(5)
(5)
(4)
(4)
(5)
(5)
LVDS
v
v
(6)
(6)
v
v
(6)
(6)
v
v
v
v
HyperTransport technology
v
v
v
v
(6)
(6)
v
v
v
v
Differential LVPECL
(6)
(6)
Notes to Table 4–2:
(1)
(2)
(3)
(4)
(5)
(6)
This bank is not available in Stratix II GX Devices.
A mixture of single-ended and differential I/O standards is not allowed in enhanced PLL external clock output
bank.
This I/O standard is only supported for the input operation in this I/O bank.
Although the Quartus II software does not support pseudo-differential SSTL/HSTL I/O standards on the left and
right I/O banks, you can implement these standards at these banks. Refer to the “Differential I/O Standards” on
page 4–10 for details.
This I/O standard is supported for both input and output operations for pins that support the DQS function. Refer
to the “Differential I/O Standards” on page 4–10 for details.
This I/O standard is only supported for the input operation for pins that support PLL INCLK function in this I/O
bank.
Altera Corporation
January 2008
4–23
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX I/O Banks
Clock I/O Pins
The PLL clock I/O pins consist of clock inputs (INCLK), external feedback
inputs (FBIN), and external clock outputs (EXTCLK). Clock inputs are
located at the left and right I/O banks (banks 1, 2, 5, and 6) to support fast
PLLs, and at the top and bottom I/O banks (banks 3, 4, 7, and 8) to
support enhanced PLLs. Both external clock outputs and external
feedback inputs are located at enhanced PLL external clock output banks
(banks 9, 10, 11, and 12) to support enhanced PLLs. Table 4–3 shows the
PLL clock I/O support in the I/O banks of Stratix II and Stratix II GX
devices.
Table 4–3. I/O Standards Supported for Stratix II and Stratix II GX PLL Pins (Part 1 of 2)
Enhanced PLL (1)
I/O Standard (2)
Input
Fast PLL
Output
Input
INCLK
FBIN
EXTCLK
INCLK
LVTTL
v
v
v
v
LVCMOS
v
v
v
v
2.5 V
v
v
v
v
1.8 V
v
v
v
v
1.5 V
v
v
v
v
3.3-V PCI
v
v
v
3.3-V PCI-X
v
v
v
SSTL-2 Class I
v
v
v
v
SSTL-2 Class II
v
v
v
v
SSTL-18 Class I
v
v
v
v
SSTL-18 Class II
v
v
v
v
1.8-V HSTL Class I
v
v
v
v
1.8-V HSTL Class II
v
v
v
v
1.5-V HSTL Class I
v
v
v
v
1.5-V HSTL Class II
v
v
v
v
Differential SSTL-2 Class I
v
v
v
Differential SSTL-2 Class II
v
v
v
Differential SSTL-18 Class I
v
v
v
Differential SSTL-18 Class II
v
v
v
4–24
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–3. I/O Standards Supported for Stratix II and Stratix II GX PLL Pins (Part 2 of 2)
Enhanced PLL (1)
I/O Standard (2)
Input
Fast PLL
Output
Input
INCLK
INCLK
FBIN
EXTCLK
1.8-V differential HSTL Class I
v
v
v
1.8-V differential HSTL Class II
v
v
v
1.5-V differential HSTL Class I
v
v
v
1.5-V differential HSTL Class II
v
v
v
LVDS
v
v
v
v
v
HyperTransport technology
v
Differential LVPECL
v
v
Note to Table 4–3:
(1)
(2)
The enhanced PLL external clock output bank does not allow a mixture of both single-ended and differential I/O
standards.
Altera does not support 1.2-V HSTL for PLL input pins on column I/O pins.
f
For more information, refer to the PLLs in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the PLLs
in Stratix II & Straix II GX Devices chapter in volume 2 of the Stratix II GX
Device Handbook.
Voltage Levels
Stratix II device specify a range of allowed voltage levels for supported
I/O standards. Table 4–4 shows only typical values for input and output
VCCIO, VREF, as well as the board VTT.
Table 4–4. Stratix II and Stratix II GX I/O Standards and Voltage Levels (Part 1 of 3) Note (1)
Stratix II and Stratix II GX
VCCIO (V)
I/O Standard
Input Operation
VREF (V)
VTT (V)
Output Operation
Top and
Bottom I/O
Banks
Left and
Right I/O
Banks (3)
Top and
Bottom I/O
Banks
Left and
Right I/O
Banks(3)
Input
Termination
LVTTL
3.3/2.5
3.3/2.5
3.3
3.3
NA
NA
LVCMOS
3.3/2.5
3.3/2.5
3.3
3.3
NA
NA
Altera Corporation
January 2008
4–25
Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX I/O Banks
Table 4–4. Stratix II and Stratix II GX I/O Standards and Voltage Levels (Part 2 of 3) Note (1)
Stratix II and Stratix II GX
VCCIO (V)
I/O Standard
Input Operation
VREF (V)
VTT (V)
Output Operation
Top and
Bottom I/O
Banks
Left and
Right I/O
Banks (3)
Top and
Bottom I/O
Banks
Left and
Right I/O
Banks(3)
Input
Termination
2.5 V
3.3/2.5
3.3/2.5
2.5
2.5
NA
NA
1.8 V
1.8/1.5
1.8/1.5
1.8
1.8
NA
NA
1.5 V
1.8/1.5
1.8/1.5
1.5
1.5
NA
NA
3.3-V PCI
3.3
NA
3.3
NA
NA
NA
3.3-V PCI-X
3.3
NA
3.3
NA
NA
NA
SSTL-2 Class I
2.5
2.5
2.5
2.5
1.25
1.25
SSTL-2 Class II
2.5
2.5
2.5
2.5
1.25
1.25
SSTL-18 Class I
1.8
1.8
1.8
1.8
0.90
0.90
SSTL-18 Class II
1.8
1.8
1.8
NA
0.90
0.90
1.8-V HSTL Class I
1.8
1.8
1.8
1.8
0.90
0.90
1.8-V HSTL Class II
1.8
1.8
1.8
NA
0.90
0.90
1.5-V HSTL Class I
1.5
1.5
1.5
1.5
0.75
0.75
1.5-V HSTL Class II
1.5
1.5
1.5
NA
0.75
0.75
1.2-V HSTL(4)
1.2
NA
1.2
NA
0.6
NA
Differential SSTL-2
Class I
2.5
2.5
2.5
2.5
1.25
1.25
Differential SSTL-2
Class II
2.5
2.5
2.5
2.5
1.25
1.25
Differential SSTL-18
Class I
1.8
1.8
1.8
1.8
0.90
0.90
Differential SSTL-18
Class II
1.8
1.8
1.8
NA
0.90
0.90
1.8-V differential
HSTL Class I
1.8
1.8
1.8
NA
0.90
0.90
1.8-V differential
HSTL Class II
1.8
1.8
1.8
NA
0.90
0.90
1.5-V differential
HSTL Class I
1.5
1.5
1.5
NA
0.75
0.75
1.5-V differential
HSTL Class II
1.5
1.5
1.5
NA
0.75
0.75
3.3/2.5/1.8/1.5
2.5
3.3
2.5
NA
NA
LVDS (2)
4–26
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–4. Stratix II and Stratix II GX I/O Standards and Voltage Levels (Part 3 of 3) Note (1)
Stratix II and Stratix II GX
VCCIO (V)
Input Operation
I/O Standard
VTT (V)
Output Operation
Top and
Bottom I/O
Banks
Left and
Right I/O
Banks (3)
Top and
Bottom I/O
Banks
Left and
Right I/O
Banks(3)
Input
Termination
NA
2.5
NA
2.5
NA
NA
3.3/2.5/1.8/1.5
NA
3.3
NA
NA
NA
HyperTransport
technology
Differential LVPECL
(2)
VREF (V)
Notes to Table 4–4:
(1)
(2)
(3)
(4)
Any input pins with PCI-clamping diode will clamp the VCCIO to 3.3 V.
LVDS and LVPECL output operation in the top and bottom banks is only supported in PLL banks 9-12. The VCCIO
level for differential output operation in the PLL banks is 3.3 V. The VCCIO level for output operation in the left and
right I/O banks is 2.5 V.
The right I/O bank does not apply to the Stratix II GX. The right I/O Bank on Stratix II GX devices consists of
transceivers.
1.2-V HSTL is only supported in I/O banks 4,7, and 8.
f
On-Chip
Termination
Refer to the DC & Switching Characteristics chapter in volume 1 of the
Stratix II Device Handbook or the DC & Switching Characteristics chapter in
volume 1 of the Stratix II GX Device Handbook for detailed electrical
characteristics of each I/O standard.
Stratix II and Stratix II GX devices feature on-chip termination to provide
I/O impedance matching and termination capabilities. Apart from
maintaining signal integrity, this feature also minimizes the need for
external resistor networks, thereby saving board space and reducing
costs.
Stratix II and Stratix II GX devices support on-chip series (RS) and
parallel (RT) termination for single-ended I/O standards and on-chip
differential termination (RD) for differential I/O standards. This section
discusses the on-chip series termination support.
f
Altera Corporation
January 2008
For more information on differential on-chip termination, Refer to the
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
High-Speed Differential I/O Interfaces with DPA in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II GX Device Handbook.
4–27
Stratix II Device Handbook, Volume 2
On-Chip Termination
The Stratix II and Stratix II GX devices supports I/O driver on-chip series
(RS) and parallel (RT) termination through drive strength control for
single-ended I/Os. There are three ways to implement the RS and (RT) in
Stratix II and Stratix II GX devices:
■
■
■
RS without calibration for both row I/Os and column I/Os
RS with calibration only for column I/Os
RT with calibration only for column I/Os
On-Chip Series Termination without Calibration
Stratix II and Stratix II GX devices support driver impedance matching to
provide the I/O driver with controlled output impedance that closely
matches the impedance of the transmission line. As a result, reflections
can be significantly reduced. Stratix II and Stratix II GX devices support
on-chip series termination for single-ended I/O standards (see
Figure 4–23). The RS shown in Figure 4–23 is the intrinsic impedance of
transistors. The typical RS values are 25 and 50. Once matching
impedance is selected, current drive strength is no longer selectable.
1
On-chip series termination without calibration is supported on
output pins or on the output function of bidirectional pins.
Figure 4–23. Stratix II and Stratix II GX On-Chip Series Termination without
Calibration
Stratix II Driver
Series Impedance
Receiving
Device
VCCIO
RS
ZO
RS
GND
4–28
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–5 shows the list of output standards that support on-chip series
termination without calibration.
Table 4–5. Selectable I/O Drivers with On-Chip Series Termination without
Calibration
On-chip Series Termination Setting
I/O Standard
Row I/O
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
Column I/O
Unit
50
50

25
25

50
50

25
25

50
50

25
25

50
50

25
25

50
50

25

50

25

50
1.5-V LVTTL
50
50

1.5-V LVCMOS
50
50

SSTL-2 Class I
50
50

SSTL-2 Class II
25
25

SSTL-18 Class I
50
SSTL-18 Class II
1.8-V HSTL Class I
50
1.8-V HSTL Class II
1.5-V HSTL Class I
50
1.2-V HSTL (1)
50

25

50

25

50

50

Note to Table 4–5:
(1)
1.2-V HSTL is only supported in I/O banks 4,7, and 8.
To use on-chip termination for the SSTL Class I standard, users should
select the 50- on-chip series termination setting for replacing the
external 25- RS (to match the 50- transmission line). For the
SSTL Class II standard, users should select the 25- on-chip series
termination setting (to match the 50- transmission line and the near end
50- pull-up to VTT).
Altera Corporation
January 2008
4–29
Stratix II Device Handbook, Volume 2
On-Chip Termination
f
For more information on tolerance specifications for on-chip termination
without calibration, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook or the DC & Switching
Characteristics chapter in volume 1 of the Stratix II GX Device Handbook.
On-Chip Series Termination with Calibration
Stratix II and Stratix II GX devices support on-chip series termination
with calibration in column I/Os in top and bottom banks. Every column
I/O buffer consists of a group of transistors in parallel. Each transistor can
be individually enabled or disabled. The on-chip series termination
calibration circuit compares the total impedance of the transistor group to
the external 25- or 50- resistors connected to the RUP and RDN pins, and
dynamically enables or disables the transistors until they match (as
shown in Figure 4–24). The RS shown in Figure 4–24 is the intrinsic
impedance of transistors. Calibration happens at the end of device
configuration. Once the calibration circuit finds the correct impedance, it
powers down and stops changing the characteristics of the drivers.
1
On-chip series termination with calibration is supported on
output pins or on the output function of bidirectional pins.
Figure 4–24. Stratix II and Stratix II GX On-Chip Series Termination with
Calibration
Stratix II Driver
Series Impedance
Receiving
Device
VCCIO
RS
ZO
RS
GND
4–30
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–6 shows the list of output standards that support on-chip series
termination with calibration.
Table 4–6. Selectable I/O Drivers with On-Chip Series Termination with
Calibration
On-Chip Series Termination Setting
(Column I/O)
Unit
50

25

50

25

50

25

50

25

50

25

50

25

1.5 LVTTL
50

1.5 LVCMOS
50

SSTL-2 Class I
50

SSTL-2 Class II
25

SSTL-18 Class I
50

SSTL-18 Class II
25

1.8-V HSTL Class I
50

1.8-V HSTL Class II
25

1.5-V HSTL Class I
50

1.2-V HSTL (1)
50

I/O Standard
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
Note to Table 4–6:
(1)
1.2-V HSTL is only supported in I/O banks 4,7, and 8.
On-Chip Parallel Termination with Calibration
Stratix II and Stratix II GX devices support on-chip parallel termination
with calibration in column I/Os in top and bottom banks. Every column
I/O buffer consists of a group of transistors in parallel. Each transistor can
be individually enabled or disabled. The on-chip parallel termination
calibration circuit compares the total impedance of the transistor group to
Altera Corporation
January 2008
4–31
Stratix II Device Handbook, Volume 2
On-Chip Termination
the external 50- resistors connected to the RUP and RDN pins and
dynamically enables or disables the transistors until they match.
Calibration happens at the end of the device configuration. Once the
calibration circuit finds the correct impedance, it powers down and stops
changing the characteristics of the drivers.
Table 4–7. Selectable I/O Drivers with On-Chip Parallel Termination with
Calibration
On-Chip Parallel Termination Setting
(Column I/O)
Unit
50

SSTL-2 Class II
50

SSTL-18 Class I
50

SSTL-18 Class II
50

1.8-V HSTL Class I
50

1.8-V HSTL Class II
50

1.5-V HSTL Class I
50

1.5-V HSTL Class II
50

1.2-V HSTL (1)
50

I/O Standard
SSTL-2 Class I
Note to Table 4–7:
(1)
1.2-V HSTL is only supported in I/O banks 4,7, and 8.
There are two separate sets of calibration circuits in the Stratix II and
Stratix II GX devices:
■
■
One calibration circuit for top banks 3 and 4
One calibration circuit for bottom banks 7 and 8
Calibration circuits rely on the external pull-up reference resistor (RUP)
and pull-down reference resistor (RDN) to achieve accurate on-chip series
and parallel termination. There is one pair of RUP and RDN pins in bank 4
for the calibration circuit for top I/O banks 3 and 4. Similarly, there is one
pair of RUP and RDN pins in bank 7 for the calibration circuit for bottom
I/O banks 7 and 8. Two banks share the same calibration circuitry, so they
must have the same VCCIO voltage if both banks enable on-chip series or
parallel termination with calibration. If banks 3 and 4 have different VCCIO
voltages, only bank 4 can enable on-chip series or parallel termination
with calibration because the RUP and RDN pins are located in bank 4.
Bank 3 still can use on-chip series termination, but without calibration.
The same rule applies to banks 7 and 8.
4–32
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
1
On-chip parallel termination with calibration is only supported
for input pins. Pins configured as bidirectional do not support
on-chip parallel termination.
The RUP and RDN pins are dual-purpose I/Os, which means they can be
used as regular I/Os if the calibration circuit is not used. When used for
calibration, the RUP pin is connected to VCCIO through an external 25- or
50- resistor for an on-chip series termination value of 25  or 50 ,
respectively. The RDN pin is connected to GND through an external 25-
or 50- resistor for an on-chip series termination value of 25  or 50 ,
respectively. For on-chip parallel termination, the RUP pin is connected to
VCCIO through an external 50- resistor, and RDN is connected to GND
through an external 50- resistor.
f
Design
Considerations
For more information on tolerance specifications for on-chip termination
with calibration, refer to the DC & Switching Characteristics chapter in
volume 1 of the Stratix II Device Handbook or the DC & Switching
Characteristics chapter in volume 1 of the Stratix II GX Device Handbook.
While Stratix II and Stratix II GX devices feature various I/O capabilities
for high-performance and high-speed system designs, there are several
other considerations that require attention to ensure the success of those
designs.
I/O Termination
I/O termination requirements for single-ended and differential I/O
standards are discussed in this section.
Single-Ended I/O Standards
Although single-ended, non-voltage-referenced I/O standards do not
require termination, impedance matching is necessary to reduce
reflections and improve signal integrity.
Voltage-referenced I/O standards require both an input reference
voltage, VREF, and a termination voltage, VTT. The reference voltage of the
receiving device tracks the termination voltage of the transmitting device.
Each voltage-referenced I/O standard requires a unique termination
setup. For example, a proper resistive signal termination scheme is critical
in SSTL standards to produce a reliable DDR memory system with
superior noise margin.
Altera Corporation
January 2008
4–33
Stratix II Device Handbook, Volume 2
Design Considerations
Stratix II and Stratix II GX on-chip series and parallel termination
provides the convenience of no external components. External pull-up
resistors can be used to terminate the voltage-referenced I/O standards
such as SSTL-2 and HSTL.
1
Refer to the “Stratix II and Stratix II GX I/O Standards Support”
on page 4–2 for more information on the termination scheme of
various single-ended I/O standards.
Differential I/O Standards
Differential I/O standards typically require a termination resistor
between the two signals at the receiver. The termination resistor must
match the differential load impedance of the bus. Stratix II and
Stratix II GX devices provide an optional differential on-chip resistor
when using LVDS and HyperTransport standards.
I/O Banks Restrictions
Each I/O bank can simultaneously support multiple I/O standards. The
following sections provide guidelines for mixing non-voltage-referenced
and voltage-referenced I/O standards in Stratix II and Stratix II GX
devices.
Non-Voltage-Referenced Standards
Each Stratix II and Stratix II GX device I/O bank has its own VCCIO pins
and supports only one VCCIO, either 1.5, 1.8, 2.5, or 3.3 V. An I/O bank can
simultaneously support any number of input signals with different I/O
standard assignments, as shown in Table 4–8.
For output signals, a single I/O bank supports non-voltage-referenced
output signals that are driving at the same voltage as VCCIO. Since an I/O
bank can only have one VCCIO value, it can only drive out that one value
for non-voltage-referenced signals. For example, an I/O bank with a
2.5-V VCCIO setting can support 2.5-V standard inputs and outputs and
3.3-V LVCMOS inputs (not output or bidirectional pins).
Table 4–8. Acceptable Input Levels for LVTTL and LVCMOS
Acceptable Input Levels (V)
Bank VCCIO
(V)
3.3
2.5
3.3
v
v (1)
2.5
v
v
4–34
Stratix II Device Handbook, Volume 2
(Part 1 of 2)
1.8
1.5
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–8. Acceptable Input Levels for LVTTL and LVCMOS
(Part 2 of 2)
Acceptable Input Levels (V)
Bank VCCIO
(V)
3.3
2.5
1.8
1.5
1.8
v (2)
v (2)
v
v (1)
1.5
v (2)
v (2)
v
v
Notes to Table 4–8:
(1)
(2)
Because the input signal does not drive to the rail, the input buffer does not
completely shut off, and the I/O current is slightly higher than the default value.
These input values overdrive the input buffer, so the pin leakage current is
slightly higher than the default value. To drive inputs higher than VCCIO but less
than 4.0 V, disable the PCI clamping diode and select the Allow LVTTL and
LVCMOS input levels to overdrive input buffer option in the Quartus II
software.
Voltage-Referenced Standards
To accommodate voltage-referenced I/O standards, each Stratix II or
Stratix II GX device’s I/O bank supports multiple VREF pins feeding a
common VREF bus. The number of available VREF pins increases as device
density increases. If these pins are not used as VREF pins, they cannot be
used as generic I/O pins. However, each bank can only have a single
VCCIO voltage level and a single VREF voltage level at a given time.
An I/O bank featuring single-ended or differential standards can support
voltage-referenced standards as long as all voltage-referenced standards
use the same VREF setting.
Because of performance reasons, voltage-referenced input standards use
their own VCCIO level as the power source. For example, you can only
place 1.5-V HSTL input pins in an I/O bank with a 1.5-V VCCIO.
1
Refer to the “Stratix II and Stratix II GX I/O Banks” on
page 4–20 for details on input VCCIO for voltage-referenced
standards.
Voltage-referenced bidirectional and output signals must be the same as
the I/O bank’s VCCIO voltage. For example, you can only place SSTL-2
output pins in an I/O bank with a 2.5-V VCCIO.
1
Altera Corporation
January 2008
Refer to the “I/O Placement Guidelines” on page 4–36 for
details on voltage-referenced I/O standards placement.
4–35
Stratix II Device Handbook, Volume 2
Design Considerations
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards
An I/O bank can support both non-voltage-referenced and
voltage-referenced pins by applying each of the rule sets individually. For
example, an I/O bank can support SSTL-18 inputs and 1.8-V inputs and
outputs with a 1.8-V VCCIO and a 0.9-V VREF. Similarly, an I/O bank can
support 1.5-V standards, 2.5-V (inputs, but not outputs), and HSTL I/O
standards with a 1.5-V VCCIO and 0.75-V VREF.
I/O Placement Guidelines
The I/O placement guidelines help to reduce noise issues that may be
associated with a design such that Stratix II and Stratix II GX FPGAs can
maintain an acceptable noise level on the VCCIO supply. Because Stratix II
and Stratix II GX devices require each bank to be powered separately for
VCCIO, these noise issues have no effect when crossing bank boundaries
and, as such, these rules need not be applied.
This section provides I/O placement guidelines for the programmable
I/O standards supported by Stratix II and Stratix II GX devices and
includes essential information for designing systems using their devices’
selectable I/O capabilities.
VREF Pin Placement Restrictions
There are at least two dedicated VREF pins per I/O bank to drive the VREF
bus. Larger Stratix II and Stratix II GX devices have more VREF pins per
I/O bank. All VREF pins within one I/O bank are shorted together at
device die level.
There are limits to the number of pins that a VREF pin can support. For
example, each output pin adds some noise to the VREF level and an
excessive number of outputs make the level too unstable to be used for
incoming signals.
Restrictions on the placement of single-ended voltage-referenced I/O
pads with respect to VREF pins help maintain an acceptable noise level on
the VCCIO supply and prevent output switching noise from shifting the
VREF rail.
Input Pins
Each VREF pin supports a maximum of 40 input pads.
4–36
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Output Pins
When a voltage-referenced input or bidirectional pad does not exist in a
bank, the number of output pads that can be used in that bank depends
on the total number of available pads in that same bank. However, when
a voltage-referenced input exists, a design can use up to 20 output pads
per VREF pin in a bank.
Bidirectional Pins
Bidirectional pads must satisfy both input and output guidelines
simultaneously. The general formulas for input and output rules are
shown in Table 4–9.
Table 4–9. Bidirectional Pin Limitation Formulas
Rules
Formulas
Input
<Total number of bidirectional pins> + <Total number of VREF
input pins, if any> 40 per VREF pin
Output
<Total number of bidirectional pins> + <Total number of
output pins, if any> – <Total number of pins from smallest
OE group, if more than one OE groups> 20 per VREF pin
■
If the same output enable (OE) controls all the bidirectional pads
(bidirectional pads in the same OE group are driving in and out at the
same time) and there are no other outputs or voltage-referenced
inputs in the bank, then the voltage-referenced input is never active
at the same time as an output. Therefore, the output limitation rule
does not apply. However, since the bidirectional pads are linked to
the same OE, the bidirectional pads will all act as inputs at the same
time. Therefore, there is a limit of 40 input pads, as follows:
<Total number of bidirectional pins> + <Total number of VREF input pins>
40 per VREF pin
■
If any of the bidirectional pads are controlled by different OE and
there are no other outputs or voltage-referenced inputs in the bank,
then one group of bidirectional pads can be used as inputs and
another group is used as outputs. In such cases, the formula for the
output rule is simplified, as follows:
<Total number of bidirectional pins> – <Total number of pins from smallest
OE group> 20 per VREF pin
Altera Corporation
January 2008
4–37
Stratix II Device Handbook, Volume 2
Design Considerations
■
Consider a case where eight bidirectional pads are controlled by
OE1, eight bidirectional pads are controlled by OE2, six bidirectional
pads are controlled by OE3, and there are no other outputs or
voltage-referenced inputs in the bank. While this totals 22
bidirectional pads, it is safely allowable because there would be a
possible maximum of 16 outputs per VREF pin, assuming the worst
case where OE1 and OE2 are active and OE3 is inactive. This is useful
for DDR SDRAM applications.
■
When at least one additional voltage-referenced input and no other
outputs exist in the same VREF group, the bidirectional pad limitation
must simultaneously adhere to the input and output limitations. The
input rule becomes:
<Total number of bidirectional pins> + <Total number of VREF input pins>
40 per VREF pin
Whereas the output rule is simplified as:
<Total number of bidirectional pins> 20 per VREF pin
■
When at least one additional output exists but no voltage-referenced
inputs exist, the output rule becomes:
<Total number of bidirectional pins> + <Total number of output pins> –
<Total number of pins from smallest OE group> 20 per VREF pin
■
When additional voltage-referenced inputs and other outputs exist
in the same VREF group, then the bidirectional pad limitation must
again simultaneously adhere to the input and output limitations. The
input rule is:
<Total number of bidirectional pins> + <Total number of VREF input pins>
40 per VREF pin
Whereas the output rule is given as:
<Total number of bidirectional pins> + <Total number of output pins> –
<Total number of pins from smallest OE group> 20 per VREF pin
I/O Pin Placement with Respect to High-Speed Differential I/O Pins
Regardless of whether or not the SERDES circuitry is utilized, there is a
restriction on the placement of single-ended output pins with respect to
high-speed differential I/O pins. As shown in Figure 4–25, all
4–38
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
single-ended outputs must be placed at least one LAB row away from the
differential I/O pins. There are no restrictions on the placement of
single-ended input pins with respect to differential I/O pins.
Single-ended input pins may be placed within the same LAB row as
differential I/O pins. However, the single-ended input’s IOE register is
not available. The input must be implemented within the core logic.
This single-ended output pin placement restriction only applies when
using the LVDS or HyperTransport I/O standards in the left and right
I/O banks. There are no restrictions for single-ended output pin
placement with respect to differential clock pins in the top and bottom
I/O banks.
Figure 4–25. Single-Ended Output Pin Placement with Respect to Differential
I/O Pins
Single-Ended Output Pin
Differential I/O Pin
Single_Ended Input
Single-Ended Outputs
Not Allowed
Row Boundary
DC Guidelines
Power budgets are essential to ensure the reliability and functionality of
a system application. You are often required to perform power
dissipation analysis on each device in the system to come out with the
total power dissipated in that system, which is composed of a static
component and a dynamic component.
The static power consumption of a device is the total DC current flowing
from VCCIO to ground.
Altera Corporation
January 2008
4–39
Stratix II Device Handbook, Volume 2
Design Considerations
For any ten consecutive pads in an I/O bank of Stratix II and Stratix II GX
devices, Altera recommends a maximum current of 250 mA, as shown in
Figure 4–26, because the placement of VCCIO/ground (GND) bumps are
regular, 10 I/O pins per pair of power pins. This limit is on the static
power consumed by an I/O standard, as shown in Table 4–10. Limiting
static power is a way to improve reliability over the lifetime of the device.
Figure 4–26. DC Current Density Restriction Notes (1), (2)
I/O Pin Sequence
of an I/O Bank
VCC
Any 10 Consecutive Output Pins
pin+9
∑ I pin
≤ 250mA
pin
GND
VCC
Notes to Figure 4–26:
(1)
(2)
The consecutive pads do not cross I/O banks.
VREF pins do not affect DC current calculation because there are no VREF pads.
4–40
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–10 shows the I/O standard DC current specification.
Table 4–10. Stratix II and Stratix II GX I/O Standard DC Current Specification (Part 1 of 2)
Note (1)
IPIN (mA), Top and Bottom I/O Banks
IPIN (mA), Left and Right I/O
Banks(2)
LVTTL
(3)
(3)
LVCMOS
(3)
(3)
2.5 V
(3)
(3)
1.8 V
(3)
(3)
I/O Standard
1.5 V
(3)
(3)
3.3-V PCI
1.5
NA
3.3-V PCI-X
1.5
NA
SSTL-2 Class I
12 (4)
12 (4)
SSTL-2 Class II
24 (4)
16 (4)
SSTL-18 Class I
12 (4)
10 (4)
SSTL-18 Class II
20 (4)
NA
1.8-V HSTL Class I
12 (4)
12
1.8-V HSTL Class II
20 (4)
NA
1.5-V HSTL Class I
12 (4)
8
1.5-V HSTL Class II
20 (4)
NA
12
12
Differential SSTL-2 Class I
Differential SSTL-2 Class II
24
16
Differential SSTL-18 Class I
12
10
Differential SSTL-18 Class II
20
NA
1.8-V differential HSTL Class I
12
12
1.8-V differential HSTL Class II
20
NA
1.5-V differential HSTL Class I
12
8
1.5-V differential HSTL Class II
20
NA
Altera Corporation
January 2008
4–41
Stratix II Device Handbook, Volume 2
Conclusion
Table 4–10. Stratix II and Stratix II GX I/O Standard DC Current Specification (Part 2 of 2)
IPIN (mA), Top and Bottom I/O Banks
I/O Standard
Note (1)
IPIN (mA), Left and Right I/O
Banks(2)
Notes to Table 4–10:
(1)
(2)
(3)
(4)
The current value obtained for differential HSTL and differential SSTL standards is per pin and not per differential
pair, as opposed to the per-pair current value of LVDS and HyperTransport standards.
This does not apply to the right I/O banks of Stratix II GX devices. Stratix II GX devices have transceivers on the
right I/O banks.
The DC power specification of each I/O standard depends on the current sourcing and sinking capabilities of the
I/O buffer programmed with that standard, as well as the load being driven. LVTTL, LVCMOS, 2.5-V, 1.8-V, and
1.5-V outputs are not included in the static power calculations because they normally do not have resistor loads in
real applications. The voltage swing is rail-to-rail with capacitive load only. There is no DC current in the system.
This IPIN value represents the DC current specification for the default current strength of the I/O standard. The IPIN
varies with programmable drive strength and is the same as the drive strength as set in Quartus II software. Refer
to the Stratix II Architecture chapter in volume 1 of the Stratix II Device Handbook or the Stratix II GX Architecture
chapter in volume 1 of the Stratix II GX Device Handbook for a detailed description of the programmable drive
strength feature of voltage-referenced I/O standards.
Table 4–10 only shows the limit on the static power consumed by an I/O
standard. The amount of power used at any moment could be much
higher, and is based on the switching activities.
Conclusion
Stratix II and Stratix II GX devices provide I/O capabilities that allow
you to work in compliance with current and emerging I/O standards and
requirements. With the Stratix II or Stratix II GX devices features, such as
programmable driver strength, you can reduce board design interface
costs and increase the development flexibility.
References
Refer to the following references for more information:
■
■
■
■
Interface Standard for Nominal 3V/ 3.3-V Supply Digital Integrated
Circuits, JESD8-B, Electronic Industries Association, September 1999.
2.5-V +/- 0.2V (Normal Range) and 1.8-V to 2.7V (Wide Range)
Power Supply Voltage and Interface Standard for Non-terminated
Digital Integrated Circuits, JESD8-5, Electronic Industries
Association, October 1995.
1.8-V +/- 0.15 V (Normal Range) and 1.2 V - 1.95 V (Wide Range)
Power Supply Voltage and Interface Standard for Non-terminated
Digital Integrated Circuits, JESD8-7, Electronic Industries
Association, February 1997.
1.5-V +/- 0.1 V (Normal Range) and 0.9 V - 1.6 V (Wide Range) Power
Supply Voltage and Interface Standard for Non-terminated Digital
Integrated Circuits, JESD8-11, Electronic Industries Association,
October 2000.
4–42
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
■
■
■
■
■
■
Referenced
Documents
This chapter references the following documents:
■
■
■
■
■
■
■
■
■
■
■
Altera Corporation
January 2008
PCI Local Bus Specification, Revision 2.2, PCI Special Interest Group,
December 1998.
PCI-X Local Bus Specification, Revision 1.0a, PCI Special Interest
Group.
Stub Series Terminated Logic for 2.5-V (SSTL-2), JESD8-9A,
Electronic Industries Association, December 2000.
Stub Series Terminated Logic for 1.8 V (SSTL-18), Preliminary JC42.3,
Electronic Industries Association.
High-Speed Transceiver Logic (HSTL)—A 1.5-V Output Buffer
Supply Voltage Based Interface Standard for Digital Integrated
Circuits, EIA/JESD8-6, Electronic Industries Association, August
1995.
Electrical Characteristics of Low Voltage Differential Signaling
(LVDS) Interface Circuits, ANSI/TIA/EIA-644, American National
Standards Institute/Telecommunications Industry/Electronic
Industries Association, October 1995.
DC & Switching Characteristics chapter in volume 1 of the Stratix II
Device Handbook
DC & Switching Characteristics chapter in volume 1 of the
Stratix II GX Device Handbook
External Memory Interfaces in Stratix II & Stratix II GX Devices chapter
in volume 2 of the Stratix II Device Handbook
External Memory Interfaces in Stratix II & Stratix II GX Devices chapter
in volume 2 of the Stratix II GX Device Handbook
High-Speed Differential I/O Interfaces with DPA in Stratix II &
Stratix II GX Devices chapter in volume 2 of the Stratix II Device
Handbook
High-Speed Differential I/O Interfaces with DPA in Stratix II &
Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device
Handbook
PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II Device Handbook
PLLs in Stratix II & Straix II GX Devices chapter in volume 2 of the
Stratix II GX Device Handbook
Stratix II Architecture chapter in volume 1 of the Stratix II Device
Handbook
Stratix II GX Architecture chapter in volume 1 of the Stratix II GX
Device Handbook
Stratix II GX Transceiver User Guide (volume 1) of the Stratix II GX
Device Handbook
4–43
Stratix II Device Handbook, Volume 2
Document Revision History
Document
Revision History
Table 4–11 shows the revision history for this chapter.
Table 4–11. Document Revision History (Part 1 of 2)
Date and
Document
Version
January 2008
v4.6
Changes Made
Summary of Changes
Updated Figure 4–22.
—
Updated Note 4 to Table 4–2.
—
Added “Referenced Documents” section.
—
Minor text edits.
—
No change
For the Stratix II GX Device Handbook only:
Formerly chapter 9. The chapter number
changed due to the addition of the Stratix II GX
Dynamic Reconfiguration chapter. No content
change.
—
May 2007
v4.5
Added a note to the “On-Chip Series Termination
with Calibration” section.
—
Added a note to the “On-Chip Series Termination
without Calibration” section
—
Updated note to the “Stratix II and Stratix II GX
I/O Features” section.
—
Updated the “LVDS” section.
—
Updated note to “1.5 V” section
—
●
●
Updated Note (1) for Table 10–4
Updated Note (2) for Table 10–3
—
Updated Table 10–2, column heading for columns
9 and 10.
—
Updated Table 10–10.
—
Fixed typo in the “Stratix II and Stratix II GX I/O
Features” section
—
February 2007 Added the “Document Revision History” section
v4.4
to this chapter.
—
August 2006
v4.3
—
Updated Table 9–2, Table 9–4, Table 9–5,
Table 9–6, and Table 9–7.
April 2006 v4.2 Chapter updated as part of the Stratix II Device
Handbook update.
—
No change
—
Formerly chapter 8. Chapter number change only
due to chapter addition to Section I in
February 2006; no content change.
4–44
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–11. Document Revision History (Part 2 of 2)
Date and
Document
Version
Changes Made
Summary of Changes
December
2005 v4.1
Chapter updated as part of the Stratix II Device
Handbook update.
—
October 2005
v4.0
Added chapter to the Stratix II GX Device
Handbook.
—
Altera Corporation
January 2008
4–45
Stratix II Device Handbook, Volume 2
Document Revision History
4–46
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
5. High-Speed Differential I/O
Interfaces with DPA in Stratix II
and Stratix II GX Devices
SII52005-2.2
Introduction
Stratix® II and Stratix® II GX device family offers up to 1-Gbps
differential I/O capabilities to support source-synchronous
communication protocols such as HyperTransport™ technology, Rapid
I/O, XSBI, and SPI.
Stratix II and Stratix II GX devices have the following dedicated circuitry
for high-speed differential I/O support:
■
■
■
■
■
■
■
Differential I/O buffer
Transmit serializer
Receive deserializer
Data realignment circuit
Dynamic phase aligner (DPA)
Synchronizer (FIFO buffer)
Analog PLLs (fast PLLs)
For high-speed differential interfaces, Stratix II and Stratix II GX devices
can accommodate different differential I/O standards, including the
following:
■
■
■
■
■
1
I/O Banks
Altera Corporation
January 2008
LVDS
HyperTransport technology
HSTL
SSTL
LVPECL
HSTL, SSTL, and LVPECL I/O standards can be used only for
PLL clock inputs and outputs in differential mode.
Stratix II and Stratix II GX inputs and outputs are partitioned into banks
located on the periphery of the die. The inputs and outputs that support
LVDS and HyperTransport technology are located in row I/O banks, two
on the left and two on the right side of the Stratix II device and two on the
left side of the Stratix II GX device. LVPECL, HSTL, and SSTL standards
are supported on certain top and bottom banks of the die (banks 9 to 12)
when used as differential clock inputs/outputs. Differential HSTL and
SSTL standards can be supported on banks 3, 4, 7, and 8 if the pins on
these banks are used as DQS/DQSn pins. Figures 5–1 and 5–2 show
where the banks and the PLLs are located on the die.
5–1
I/O Banks
Figure 5–1. Stratix II I/O Banks Note (1), (2), (3), (4), (5), (6), and (7)
DQS8T
VREF0B3
DQS7T
VREF1B3
DQS6T
VREF2B3
VREF3B3
DQS5T
VREF4B3
PLL11
PLL5
Bank 11
Bank 9
DQS4T
DQS3T
DQS2T
DQS1T
DQS0T
VREF0B4
VREF1B4
VREF2B4
VREF3B4
VREF4B4
PLL7
PLL10
VR EF1B 5
VREF 4B5
VREF 0B2
VR EF3B5
I/O banks 3, 4, 9 & 11 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
I/O banks 1, 2, 5 & 6 support LVTTL, LVCMOS,
2.5-V, 1.8-V, 1.5-V, SSTL-2, SSTL-18 Class I,
HSTL-18 Class I, HSTL-15 Class I, LVDS, and
HyperTransport standards for input and output
operations. HSTL-18 Class II, HSTL-15-Class II,
SSTL-18 Class II standards are only supported
for input operations.
PLL1
PLL4
VR EF1B6
VREF 2B6
VREF 3B6
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
VREF 4B6
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
Bank 6
I/O banks 7, 8, 10 & 12 support all
single-ended I/O standards and
differential I/O standards except for
HyperTransport technology for
both input and output operations.
VREF 0B1
VREF 1B1
Bank 1
VR EF3B1
VR EF0B6
PLL3
VR EF4B1
PLL2
VREF 2B1
VR EF2B5
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
Bank 5
VR EF2B2
This I/O bank supports LVDS
and LVPECL standards for input
clock operations. Differential
HSTL and differential SSTL
standards are supported for both
input and output operations.
VR EF1B2
Bank 2
VR EF3B 2
VREF 0B5
Bank 4
VREF 4B2
Bank 3
Bank 12
Bank 8
Bank 10
Bank 7
PLL8
PLL9
VREF4B8
DQS8B
VREF3B8
VREF2B8
DQS7B
VREF1B8
DQS6B
VREF0B8
DQS5B
PLL12
PLL6
VREF4B7
VREF3B7
VREF2B7
VREF1B7
VREF0B7
DQS4B
DQS3B
DQS2B
DQS1B
DQS0B
Notes to Figure 5–1:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Figure 5–1 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical
representation only. See the pin list and Quartus II software for exact locations.
Depending on the size of the device, different device members have different numbers of VREF groups.
Banks 9 through 12 are enhanced PLL external clock output banks. These PLL banks utilize the adjacent VREF group
when voltage-referenced standards are implemented. For example, if an SSTL input is implemented in PLL bank
10, the voltage level at VREFB7 is the reference voltage level for the SSTL input.
Differential HSTL and differential SSTL standards are available for bidirectional operations on DQS pin and
input-only operations on PLL clock input pins; LVDS, LVPECL, and HyperTransport standards are available for
input-only operations on PLL clock input pins. See the Selectable I/O standards in Stratix II & Stratix II GX Devices
chapter in volume 2 of the Stratix II Device Handbook for more details.
Quartus II software does not support differential SSTL and differential HSTL standards at left/right I/O banks. See
the Selectable I/O standards in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook if
you need to implement these standards at these I/O banks.
Banks 11 and 12 are available only in EP2S60, EP2S90, EP2S130, and EP2S180 devices.
PLLs 7, 8, 9, 10, 11, and 12 are available only in EP2S60, EP2S90, EP2S130, and EP2S180 devices.
5–2
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Figure 5–2. Stratix II GX I/O Banks Note (1), (2), (3), (4), (5), (6), and (7)
DQS ×8
PLL7
DQS ×8
DQS ×8
DQS ×8
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Bank 4
Bank 9
VREF3B1 VREF4B1
Bank 1
VREF0B1 VREF1B1
14
17
I/O banks 1 & 2 support LVTTL, LVCMOS,
2.5 V, 1.8 V, 1.5 V, SSTL-2, SSTL-18 class I,
LVDS, pseudo-differential SSTL-2 and pseudo-differential
SSTL-18 class I standards for both input and output
operations. HSTL, SSTL-18 class II,
pseudo-differential HSTL and pseudo-differential
SSTL-18 class II standards are only supported for
input operations. (4)
PLL2
I/O banks 7, 8, 10 and 12 support all single-ended I/O
standards for both input and output operations. All differential
I/O standards are supported for both input and output operations
at I/O banks 10 and 12.
This I/O bank supports LVDS
This I/O bank supports LVDS
and LVPECL standards for input clock operation.
and LVPECL standards for input clock
Differential HSTL and differential
operation. Differential HSTL and differential
SSTL standards are supported
SSTL standards are supported
for both input and output operations. (3)
for both input and output operations. (3)
Bank 8
PLL8
This I/O bank supports LVDS
and LVPECL standards for input clock
operation. Differential HSTL and
differential SSTL standards are
supported for both input and output
operations. (3)
VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Bank 12
Bank 10
PLL12
PLL6
16
This I/O bank supports LVDS
and LVPECL standards
for input clock operations. Differential HSTL
and differential SSTL standards
are supported for both input
and output operations. (3)
I/O Banks 3, 4, 9, and 11 support all single-ended
I/O standards for both input and output operations.
All differential I/O standards are supported for both
input and output operations at I/O banks 9 and 11.
PLL1
VREF2B1
DQS ×8
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
13
Bank 11
PLL5
15
Bank 2
VREF0B2 VREF1B2
VREF2B2
VREF3B2 VREF4B2
Bank 3
PLL11
Bank 7
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
DQS ×8
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Notes to Figure 5–2:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Figure 5–2 is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. It is a graphical
representation only.
Depending on size of the device, different device members have different number of VREF groups. Refer to the pin
list and the Quartus II software for exact locations.
Banks 9 through 12 are enhanced PLL external clock output banks.
Horizontal I/O banks feature transceiver and DPA circuitry for high speed differential I/O standards.
Quartus II software does not support differential SSTL and differential HSTL standards at left/right I/O banks.
Refer to the “Differential Pin Placement Guidelines” on page 5–21 if you need to implement these standards at these
I/O banks.
Banks 11 and 12 are available only in EP2SGX60C/D/E, EP2SGX90E/F, and EP2SGX130G.
PLLs 7, 8, 11, and 12 are available only in EP2SGX60C/D/E, EP2SGXE/F, and EP2SGX130G.
Altera Corporation
January 2008
5–3
Stratix II Device Handbook, Volume 2
I/O Banks
Table 5–1 lists the differential I/O standards supported by each bank.
Table 5–1. Supported Differential I/O Types
Bank
Row I/O (Banks 1, 2, 5 and 6) (2)
Type
Clock Inputs
Clock
Outputs
Data or
Regular I/O
Pins
Column I/O (Banks, 3, 4 and 7 through 12)
Clock Inputs
Clock
Outputs
Data or
Regular I/O
Pins
Differential HSTL
v
v
(1)
Differential SSTL
v
v
(1)
v
v
v
v
LVPECL
LVDS
v
v
v
HyperTransport
technology
v
v
v
Note to Table 5–1:
(1)
(2)
Used as both inputs and outputs on the DQS/DQSn pins.
Banks 5 and 6 are not available in Stratix II GX devices.
Table 5–2 shows the total number of differential channels available in
Stratix II devices. The available channels are divided evenly between the
left and right banks of the die. Non-dedicated clocks in the left and right
banks can also be used as data receiver channels. The total number of
receiver channels includes these four non-dedicated clock channels. Pin
migration is available for different size devices in the same package.
Table 5–2. Differential Channels in Stratix II Devices (Part 1 of 2) Notes (1), (2), and (3)
484-Pin
484-Pin Hybrid
FineLine BGA FineLine BGA
672-Pin
FineLine BGA
EP2S15
38 transmitters
42 receivers
38 transmitters
42 receivers
EP2S30
38 transmitters
42 receivers
58 transmitters
62 receivers
EP2S60
38 transmitters
42 receivers
58 transmitters
62 receivers
Device
EP2S90
38 transmitters
42 receivers
EP2S130
5–4
Stratix II Device Handbook, Volume 2
780-Pin
FineLine BGA
1,020-Pin
FineLine BGA
1,508-Pin
FineLine BGA
Within the
1,508-pin Fin
84 transmitters
84 receivers
64 transmitters
68 receivers
90 transmitters 118 transmitters
94 receivers
118 receivers
64 transmitters
68 receivers
88 transmitters 156 transmitters
92 receivers
156 receivers
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Table 5–2. Differential Channels in Stratix II Devices (Part 2 of 2) Notes (1), (2), and (3)
Device
484-Pin
484-Pin Hybrid
FineLine BGA FineLine BGA
672-Pin
FineLine BGA
EP2S180
780-Pin
FineLine BGA
1,020-Pin
FineLine BGA
1,508-Pin
FineLine BGA
Within the
1,508-pin Fin
88 transmitters 156 transmitters
92 receivers
156 receivers
Notes to Table 5–2:
(1)
(2)
(3)
Pin count does not include dedicated PLL input pins.
The total number of receiver channels includes the four non-dedicated clock channels that can optionally be used as data
channels.
Within the 1,508-pin FineLine BGA package, 92 receiver channels and 92 transmitter channels are vertically migratable.
Table 5–3 shows the total number of differential channels available in
Stratix II GX devices. Non-dedicated clocks in the left bank can also be
used as data receiver channels. The total number of receiver channels
includes these four non-dedicated clock channels. Pin migration is
available for different size devices in the same package.
Table 5–3. Differential Channels in Stratix II GX Devices
Device
780-Pin FineLine
BGA
EP2SGX30
29 transmitters
31receivers
EP2SGX60
29 transmitters
31 receivers
EP2SGX90
EP2SGX130
1,152-Pin FineLine
BGA
Notes (1), (2), (3)
1,508-Pin FineLine
BGA
42 transmitters
42 receivers
45 transmitters
47 receivers
59 transmitters
59 receivers
71 transmitters
73 receivers
Notes to Table 5–3:
(1)
(2)
(3)
Altera Corporation
January 2008
Pin count does not include dedicated PLL input pins.
The total number of receiver channels includes the four non-dedicated clock
channels that can optionally be used as data channels.
EP2SGX30CF780 devices with four transceiver channels are vertically migratable to
EP2SGX60CF780 devices with four transceiver channels. EP2SGX30DF780 devices
with eight transceiver channels are vertically migratable to EP2SGX60DF780
devices with eight transceiver channels. EP2SGX60EF1152 devices with 12
transceiver channels are vertically migratable to EP2SGX90EF1152 devices with 12
transceiver channels. EP2SGX90FF1508 devices with 16 transceiver channels are
vertically migratable to EP2SGX130GF1508 devices with 20 transceiver channels.
5–5
Stratix II Device Handbook, Volume 2
Differential Transmitter
Differential
Transmitter
The Stratix II and Stratix II GX transmitter has dedicated circuitry to
provide support for LVDS and HyperTransport signaling. The dedicated
circuitry consists of a differential buffer, a serializer, and a shared fast
PLL. The differential buffer can drive out LVDS or HyperTransport signal
levels that are statically set in the Quartus® II software. The serializer
takes data from a parallel bus up to 10 bits wide from the internal logic,
clocks it into the load registers, and serializes it using the shift registers
before sending the data to the differential buffer. The most significant bit
(MSB) is transmitted first. The load and shift registers are clocked by the
diffioclk (a fast PLL clock running at the serial rate) and controlled by
the load enable signal generated from the fast PLL. The serialization
factor can be statically set to 4, 6, 7, 8, or 10 using the
Quartus II software. The load enable signal is automatically generated by
the fast PLL and is derived from the serialization factor setting. Figure 5–3
is a block diagram of the Stratix II transmitter.
Figure 5–3. Transmitter Block Diagram
Serializer
10
TX_OUT
Internal
Logic
diffioclk
Fast PLL
load_en
Each Stratix II and Stratix II GX transmitter data channel can be
configured to operate as a transmitter clock output. This flexibility allows
the designer to place the output clock near the data outputs to simplify
board layout and reduce clock-to-data skew. Different applications often
require specific clock to data alignments or specific data rate to clock rate
factors. The transmitter can output a clock signal at the same rate as the
data with a maximum frequency of 717 MHz. The output clock can also
be divided by a factor of 2, 4, 8, or 10, depending on the serialization
factor. The phase of the clock in relation to the data can be set at 0° or 180°
(edge or center aligned). The fast PLL provides additional support for
5–6
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
other phase shifts in 45° increments. These settings are made statically in
the Quartus II MegaWizard® software. Figure 5–4 shows the transmitter
in clock output mode.
Figure 5–4. Transmitter in Clock Output Mode
Transmitter Circuit
Parallel
Series
tx_outclock
Internal
Logic
diffioclk
load_en
The serializer can be bypassed to support DDR (2) and SDR (1)
operations. The I/O element (IOE) contains two data output registers that
each can operate in either DDR or SDR mode. The clock source for the
registers in the IOE can come from any routing resource, from the fast
PLL, or from the enhanced PLL. Figure 5–5 shows the bypass path.
Figure 5–5. Serializer Bypass
IOE Supports SDR, DDR, or
Non-Registered Data Path
IOE
Internal Logic
tx_out
Serializer
Not used (connection exists)
Altera Corporation
January 2008
5–7
Stratix II Device Handbook, Volume 2
Differential Receiver
Differential
Receiver
The receiver has dedicated circuitry to support high-speed LVDS and
HyperTransport signaling, along with enhanced data reception. Each
receiver consists of a differential buffer, dynamic phase aligner (DPA),
synchronization FIFO buffer, data realignment circuit, deserializer, and a
shared fast PLL. The differential buffer receives LVDS or HyperTransport
signal levels, which are statically set by the Quartus II software. The DPA
block aligns the incoming data to one of eight clock phases to maximize
the receiver’s skew margin. The DPA circuit can be bypassed on a
channel-by-channel basis if it is not needed. Set the DPA bypass statically
in the Quartus II MegaWizard Plug-In Manager or dynamically by using
the optional RX_DPLL_ENABLE port.
The synchronizer circuit is a 1-bit wide by 6-bit deep FIFO buffer that
compensates for any phase difference between the DPA block and the
deserializer. If necessary, the data realignment circuit inserts a single bit
of latency in the serial bit stream to align the word boundary. The
deserializer includes shift registers and parallel load registers, and sends
a maximum of 10 bits to the internal logic. The data path in the receiver is
clocked by either the diffioclk signal or the DPA recovered clock. The
deserialization factor can be statically set to 4, 5, 6, 7, 8, 9, or 10 by using
the Quartus II software. The fast PLL automatically generates the load
enable signal, which is derived from the deserialization factor setting.
Figure 5–6 shows a block diagram of the receiver.
Figure 5–6. Receiver Block Diagram
DPA Bypass Multiplexer
Up to 1 Gbps
+
–
D
Q
Data
Realignment
Circuitry
10
Internal
Logic
Dedicated
Receiver
Interface
data retimed_data
DPA
Synchronizer
DPA_clk
Eight Phase Clocks
8
rx_inclk
Fast
PLL
5–8
Stratix II Device Handbook, Volume 2
diffioclk
load_en
Regional or
Global Clock
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
The deserializer, like the serializer, can also be bypassed to support DDR
(2) and SDR (1) operations. The DPA and data realignment circuit
cannot be used when the deserializer is bypassed. The IOE contains two
data input registers that can operate in DDR or SDR mode. The clock
source for the registers in the IOE can come from any routing resource,
from the fast PLL, or from the enhanced PLL. Figure 5–7 shows the
bypass path.
Figure 5–7. Deserializer Bypass
IOE Supports SDR, DDR, or
Non-Registered Data Path
IOE
rx_in
Deserializer
PLD Logic
Array
DPA
Circuitry
Receiver Data Realignment Circuit
The data realignment circuit aligns the word boundary of the incoming
data by inserting bit latencies into the serial stream. An optional
RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each
receiver independently controlled from the internal logic. The data slips
one bit for every pulse on the RX_CHANNEL_DATA_ALIGN port. The
following are requirements for the RX_CHANNEL_DATA_ALIGN port:
■
■
■
■
Altera Corporation
January 2008
The minimum pulse width is one period of the parallel clock in the
logic array.
The minimum low time between pulses is one period of parallel
clock.
There is no maximum high or low time.
Valid data is available two parallel clock cycles after the rising edge
of RX_CHANNEL_DATA_ALIGN.
5–9
Stratix II Device Handbook, Volume 2
Differential Receiver
Figure 5–8 shows receiver output (RX_OUT) after one bit slip pulse with
the deserialization factor set to 4.
Figure 5–8. Data Realignment Timing
inclk
rx_in
3
2
1
0
3
2
1
0
3
2
1
0
rx_outclock
rx_channel_data_align
3210
rx_out
321x
xx21
0321
The data realignment circuit can have up to 11 bit-times of insertion
before a rollover occurs. The programmable bit rollover point can be from
1 to 11 bit-times independent of the deserialization factor. An optional
status port, rx_cda_max, is available to the FPGA from each channel to
indicate when the preset rollover point is reached.
Figure 5–9 illustrates a preset value of four bit-times before rollover
occurs. The rx_cda_max signal pulses for one rx_outclk cycle to
indicate that the rollover has occurred.
Figure 5–9. Receiver Data Re-alignment Rollover
inclk
rx_channel_data_align
rx_outclk
rx_cda_max
Dynamic Phase Aligner
The DPA block takes in high-speed serial data from the differential input
buffer and selects one of eight phase clocks to sample the data. The DPA
chooses a phase closest to the phase of the serial data. The maximum
phase offset between the data and the phase-aligned clock is 1/8 UI,
which is the maximum quantization error of the DPA. The eight phases
5–10
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
are equally divided, giving a 45-degree resolution. Figure 5–10 shows the
possible phase relationships between the DPA clocks and the incoming
serial data.
Figure 5–10. DPA Clock Phase to Data Bit Relationship
rx_in
D0
D1
D2
D3
D4
Dn
0˚
45˚
90˚
135˚
180˚
225˚
270˚
315˚
Tvco
0.125Tvco
Each DPA block continuously monitors the phase of the incoming data
stream and selects a new clock phase if needed. The selection of a new
clock phase can be prevented by the optional RX_DPLL_HOLD port, which
is available for each channel.
The DPA block requires a training pattern and a training sequence of at
least 256 repetitions of the training pattern. The training pattern is not
fixed, so you can use any training pattern with at least one transition on
each channel. An optional output port, RX_DPA_LOCKED, is available to
the internal logic, to indicate when the DPA block has settled on the
closest phase to the incoming data phase. The RX_DPA_LOCKED
de-asserts, depending on what is selected in the Quartus II MegaWizard
Plug-In, when either a new phase is selected, or when the DPA has moved
two phases in the same direction. The data may still be valid even when
the RX_DPA_LOCKED is deasserted. Use data checkers to validate the data
when RX_DPA_LOCKED is deasserted.
An independent reset port, RX_RESET, is available to reset the DPA
circuitry. The DPA circuit must be retrained after reset.
Altera Corporation
January 2008
5–11
Stratix II Device Handbook, Volume 2
Differential I/O Termination
Synchronizer
The synchronizer is a 1-bit  6-bit deep FIFO buffer that compensates for
the phase difference between the recovered clock from the DPA circuit
and the diffioclk that clocks the rest of the logic in the receiver. The
synchronizer can only compensate for phase differences, not frequency
differences between the data and the receiver’s INCLK. An optional port,
RX_FIFO_RESET, is available to the internal logic to reset the
synchronizer. The synchronizer is automatically reset when the DPA first
locks to the incoming data. Altera® recommends using RX_FIFO_RESET
to reset the synchronizer when the DPA signals a loss-of-lock condition
beyond the initial locking condition.
Differential I/O
Termination
f
Stratix II and Stratix II GX devices provide an on-chip 100-differential
termination option on each differential receiver channel for LVDS and
HyperTransport standards. The on-chip termination eliminates the need
to supply an external termination resistor, simplifying the board design
and reducing reflections caused by stubs between the buffer and the
termination resistor. You can enable on-chip termination in the Quartus II
assignments editor. Differential on-chip termination is supported across
the full range of supported differential data rates.
For more information, refer to the High-Speed I/O Specifications section
of the DC & Switching Characteristics chapter in volume 1 of the Stratix II
Device Handbook or the High-Speed I/O Specifications section of the
DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Device Handbook.
Figure 5–11 illustrates on-chip termination.
Figure 5–11. On-Chip Differential Termination
Stratix II Differential
Receiver with On-Chip
100 Ω Termination
LVDS/HT
Transmitter
Z0 = 50 Ω
RD
Z0 = 50 Ω
On-chip differential termination is supported on all row I/O pins and on
clock pins CLK[0, 2, 8, 10]. The clock pins CLK[1, 3, 9, 11],
and FPLL[7..10]CLK, and the clocks in the top and bottom I/O banks
(CLK[4..7, 12..15]) do not support differential on-chip termination.
5–12
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Fast PLL
The high-speed differential I/O receiver and transmitter channels use the
fast PLL to generate the parallel global clocks (rx- or tx- clock) and
high-speed clocks (diffioclk). Figure 5–12 shows the locations of the
fast PLLs. The fast PLL VCO operates at the clock frequency of the data
rate. Each fast PLL offers a single serial data rate support, but up to two
separate serialization and/or deserialization factors (from the C0 and C1
fast PLL clock outputs) can be used. Clock switchover and dynamic fast
PLL reconfiguration is available in high-speed differential I/O support
mode.
f
For additional information on the fast PLL, refer to the PLLs in Stratix II
& Stratix II GX Devices chapter in volume 2 of the Stratix II Handbook or
the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II GX Handbook.
Figure 5–12 shows a block diagram of the fast PLL in high-speed
differential I/O support mode.
Figure 5–12. Fast PLL Block Diagram
Global or
regional clock (2)
Clock (1)
Switchover
Circuitry
VCO Phase Selection
Selectable at each PLL
Output Port
Phase
Frequency
Detector
diffioclk0 (3)
4
loaden0 (4)
÷c0
(5)
Clock
Input
Post-Scale
Counters
÷n
PFD
Charge
Pump
Loop
Filter
VCO
÷k
diffioclk1 (3)
8
loaden1 (4)
÷c1
4
Global clocks
÷c2
4
Global or
regional clock (2)
8
Regional clocks
÷c3
÷m
Shaded Portions of the
PLL are Reconfigurable
8
to DPA block
Notes to Figure 5–12:
(1)
(2)
(3)
(4)
(5)
Stratix II fast PLLs only support manual clock switchover.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or pin-driven dedicated global or regional clock.
In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix II devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a high-speed differential I/O support SERDES control signal.
If the design enables this ÷2 counter, the device can use a VCO frequency range of 150 to 520 MHz.
Altera Corporation
January 2008
5–13
Stratix II Device Handbook, Volume 2
Clocking
Clocking
The fast PLLs feed in to the differential receiver and transmitter channels
through the LVDS/DPA clock network. The center fast PLLs can
independently feed the banks above and below them. The corner PLLs
can feed only the banks adjacent to them. Figures 5–13 and 5–14 show the
LVDS and DPA clock networks of the Stratix II devices.
Figure 5–13. Fast PLL and LVDS/DPA Clock for EP2S15, EP2S30, and EP2S60 Devices Note (1)
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
DPA
Clock
LVDS
Clock 4
4
4
2
2
Fast
PLL 1
Fast
PLL 4
Fast
PLL 2
Fast
PLL 3
4
2
2
4
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
DPA
Clock
LVDS
Clock 4
Note to Figure 5–13:
(1)
Figure 5–13 applies to EP2S60 devices in the 484 and 672 pin packages.
5–14
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Figure 5–14. Fast PLL and LVDS/DPA Clocks for EP2S60, EP2S90, EP2S130 and EP2S180 Devices Note (1)
Fast
PLL 7
Fast
PLL 10
2
2
4
LVDS
Clock
DPA
Clock
Quadrant
DPA
Clock
Quadrant
LVDS
Clock
4
4
4
2
2
Fast
PLL 1
Fast
PLL 4
Fast
PLL 2
Fast
PLL 3
LVDS
Clock
4
DPA
Clock
Quadrant
DPA
Clock
Quadrant
LVDS
Clock
2
2
4
2
2
Fast
PLL 8
Fast
PLL 9
Note to Figure 5–14:
(1)
Figure 5–14 applies only to the EP2S60 in the 1020 Stratix II GX device.
Figures 5–15 and 5–16 show the Fast PLL and LVDS/DPA clock of the
Stratix II GX devices.
Figure 5–15. Fast PLL and LVDS/DPA Clock for EP2SGX30C/D and EP2SGX60C/D Devices
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
4
2
2
Fast
PLL 1
No Fast PLLs on
Right Side of
Stratix II GX Devices
Fast
PLL 2
4
4
Altera Corporation
January 2008
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
5–15
Stratix II Device Handbook, Volume 2
Clocking
Figure 5–16. Fast PLL and LVDS/DPA Clocks for EP2SGX60E, EP2SGX90 and EP2SGX130 Devices
Fast
PLL 7
2
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
4
2
Fast
PLL 1
No Fast PLLs on
Right Side of
Stratix II GX Devices
Fast
PLL 2
2
Quadrant
4
LVDS
Clock
Quadrant
DPA
Clock
2
Fast
PLL 8
Source Synchronous Timing Budget
This section discusses the timing budget, waveforms, and specifications
for source-synchronous signaling in Stratix II and Stratix II GX devices.
LVDS and HyperTransport I/O standards enable high-speed data
transmission. This high data transmission rate results in better overall
system performance. To take advantage of fast system performance, it is
important to understand how to analyze timing for these high-speed
signals. Timing analysis for the differential block is different from
traditional synchronous timing analysis techniques.
Rather than focusing on clock-to-output and setup times,
source-synchronous timing analysis is based on the skew between the
data and the clock signals. High-speed differential data transmission
requires the use of timing parameters provided by IC vendors and is
strongly influenced by board skew, cable skew, and clock jitter. This
section defines the source-synchronous differential data orientation
timing parameters, the timing budget definitions for Stratix II and
Stratix II GX devices, and how to use these timing parameters to
determine a design's maximum performance.
5–16
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Differential Data Orientation
There is a set relationship between an external clock and the incoming
data. For operation at 1 Gbps and SERDES factor of 10, the external clock
is multiplied by 10, and phase-alignment can be set in the PLL to coincide
with the sampling window of each data bit. The data is sampled on the
falling edge of the multiplied clock. Figure 5–17 shows the data bit
orientation of the 10 mode.
Figure 5–17. Bit Orientation in the Quartus II Software
inclock/outclock
10 LVDS Bits
MSB
data in
n-1
n-0
9
8
7
6
5
4
3
LSB
2
1
0
high-frequency clock
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at
high frequencies. Figure 5–18 shows the data bit orientation for a channel
operation. These figures are based on the following:
■
■
■
SERDES factor equals clock multiplication factor
Edge alignment is selected for phase alignment
Implemented in hard SERDES
For other serialization factors use the Quartus II software tools and find
the bit position within the word. The bit positions after deserialization are
listed in Table 5–4.
Figure 5–18 also shows a functional waveform. Timing waveforms may
produce different results. Altera recommends performing a timing
simulation to predict actual device behavior.
Altera Corporation
January 2008
5–17
Stratix II Device Handbook, Volume 2
Clocking
Figure 5–18. Bit Order for One Channel of Differential Data
Transmitter Channel
Operation (x8 Mode)
tx_outclock
Previous Cycle
tx_out
X
X
X
X
X
X
X
Current Cycle
7
X
6
5
4
3
Next Cycle
2
1
MSB
0
X
X
X
X
X
X
X
X
X
X
X
X
LSB
Receiver Channel
Operation (x4 Mode)
rx_inclock
rx_in
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
rx_outclock
XXXX
rx_out [3..0]
XXXX
XXXX
3210
Receiver Channel
Operation (x8 Mode)
rx_inclock
rx_in
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
rx_outclock
rx_out [7..0]
XXXXXXXX
5–18
Stratix II Device Handbook, Volume 2
XXXXXXXX
XXXX7654
3210XXXX
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Table 5–4 shows the conventions for differential bit naming for
18 differential channels. The MSB and LSB positions increase with the
number of channels used in a system.
Table 5–4. LVDS Bit Naming
Receiver Channel Data
Number
Internal 8-Bit Parallel Data
MSB Position
LSB Position
1
7
0
2
15
8
3
23
16
4
31
24
5
39
32
6
47
40
7
55
48
8
63
56
9
71
64
10
79
72
11
87
80
12
95
88
13
103
96
14
111
104
15
119
112
16
127
120
17
135
128
18
143
136
Receiver Skew Margin for Non-DPA
Changes in system environment, such as temperature, media (cable,
connector, or PCB) loading effect, the receiver's setup and hold times, and
internal skew, reduce the sampling window for the receiver. The timing
margin between the receiver’s clock input and the data input sampling
window is called Receiver Skew Margin (RSKM). Figure 5–19 shows the
relationship between the RSKM and the receiver’s sampling window.
Altera Corporation
January 2008
5–19
Stratix II Device Handbook, Volume 2
Clocking
TCCS, RSKM, and the sampling window specifications are used for
high-speed source-synchronous differential signals without DPA. When
using DPA, these specifications are exchanged for the simpler single DPA
jitter tolerance specification. For instance, the receiver skew is why each
input with DPA selects a different phase of the clock, thus removing the
requirement for this margin.
Figure 5–19. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA
Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal
Clock
TCCS
Receiver
Input Data
TCCS
Sampling
Window (SW)
RSKM
tSW (min)
Bit n
Timing Budget
RSKM
Internal tSW (max)
Clock
Bit n
Falling Edge
TUI
External
Clock
Clock Placement
Internal
Clock
Synchronization
Transmitter
Output Data
RSKM
RSKM
TCCS
TCCS
2
TSWEND
Receiver
Input Data
TSWBEGIN
5–20
Stratix II Device Handbook, Volume 2
Sampling
Window
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Differential Pin
Placement
Guidelines
In order to ensure proper high-speed operation, differential pin
placement guidelines have been established. The Quartus II compiler
automatically checks that these guidelines are followed and will issue an
error message if these guidelines are not met. PLL driving distance
information is separated into guidelines with and without DPA usage.
High-Speed Differential I/Os and Single-Ended I/Os
When a differential channel or channels of side banks are used (with or
without DPA), you must adhere to the guidelines described in the
following sections.
■
■
■
■
■
Altera Corporation
January 2008
Single-ended I/Os are allowed in the same bank as the LVDS
channels (with or without DPA) as long as the single-ended I/O
standard uses the same VCCIO as the LVDS bank.
Single-ended inputs can be in the same LAB row. Outputs cannot be
on the same LAB row with LVDS I/Os. If input registers are used in
the IOE, single-ended inputs cannot be in the same LAB row as an
LVDS SERDES block.
LVDS (non-SERDES) I/Os are allowed in the same row as LVDS
SERDES but the use of IOE registers are not allowed.
Single-ended outputs are limited to 120 mA drive strength on LVDS
banks (with or without DPA).
●
LVTTL equation for maximum number of I/Os in an LVDS
bank:
• 120 mA = (number of LVTTL outputs) × (drive strength of
each LVTTL output)
●
SSTL-2 equation:
• 120 mA = (number of SSTL-2 I/Os) × (drive strength of each
output) ÷ 2
●
LVTTL and SSTL-2 mix equation:
• 120 mA= (total drive strength of all LVTTL outputs) + (total
drive strength of all SSTL2 outputs) ÷ 2
Single-ended inputs can be in the same LAB row as a differential
channel using the SERDES circuitry; however, IOE input registers are
not available for the single-ended I/Os placed in the same LAB row
as differential I/Os. The same rule for input registers applies for nonSERDES differential inputs placed within the same LAB row as a
SERDES differential channel. The input register must be
implemented within the core logic. The same rule for input registers
applies for non-SERDES differential inputs placed within the same
LAB row as a SERDES differential channel.
5–21
Stratix II Device Handbook, Volume 2
Differential Pin Placement Guidelines
■
Single-ended output pins must be at least one LAB row away from
differential output pins, as shown in Figure 5–20.
Figure 5–20. Single-Ended Output Pin Placement with Respect to Differential I/O Pins
Single-Ended Output Pin
Differential I/O Pin
Single_Ended Input
Single-Ended Outputs
Not Allowed
Row Boundary
DPA Usage Guidelines
The Stratix II and Stratix II GX device have differential receivers and
transmitters on the Row banks of the device. Each receiver has a
dedicated DPA circuit to align the phase of the clock to the data phase of
its associated channel. When a channel or channels of left or right banks
are used in DPA mode, the guidelines listed below must be adhered to.
Fast PLL/DPA Channel Driving Distance
■
Each fast PLL can drive up to 25 contiguous rows in DPA mode in a
single bank (not including the reference clock row). The unbonded
SERDES I/O rows are included in the 25 row calculation. These
channels can be anywhere in the bank, their distance from the PLL is
not relevant, but the channels must be within 25 rows of each other.
5–22
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
■
■
Unused channels can be within the 25 row span, but all used
channels must be in DPA mode from the same fast PLL. Center fast
PLLs can drive two I/O banks simultaneously, up to 50 channels (25
on the upper bank and 25 on the lower bank) as shown in
Figure 5–21.
If one center fast PLL drives DPA channels in the upper and lower
banks, the other center fast PLL cannot be used for DPA.
Figure 5–21. Driving Capabilities of a Center Fast PLL
DPA
DPA
Top Channels Driven
by Center PLL
DPA
DPA
DPA
Ref CLK
Ref Clk
Fast PLL
Center PLL
Used for DPA
Fast PLL
Center PLL
Used for DPA
Ref CLK
Ref Clk
DPA
DPA
DPA
DPA
Bottom Channels
Driven by Center PLL
DPA
Altera Corporation
January 2008
5–23
Stratix II Device Handbook, Volume 2
Differential Pin Placement Guidelines
Using Corner and Center Fast PLLs
■
■
If a differential bank is being driven by two fast PLLs, where the
corner PLL is driving one group and the center fast PLL is driving
another group, there must be at least 1 row of separation between the
two groups of DPA channels (see Figure 5–22). The two groups can
operate at independent frequencies. Not all the channels are bonded
out of the die. Each LAB row is considered a channel, whether or not
it has I/O support.
No separation is necessary if a single fast PLL is driving DPA
channels as well as non-DPA channels as long as the DPA channels
are contiguous.
Figure 5–22. Usage of Corner and Center Fast PLLs Driving DPA Channels in a
Single Bank
Fast PLL
Corner PLL
Used for DPA
Ref CLK
Ref Clk
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Channels Driven
by Corner PLL
Diff I/O
Unused
One Unused
Channel for Buffer
Diff I/O
Diff I/O
Channels Driven
by Center PLL
Diff I/O
Diff I/O
Diff I/O
Ref CLK
Fast PLL
5–24
Stratix II Device Handbook, Volume 2
Ref Clk
Center PLL
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Using Both Center Fast PLLs
■
■
Both center fast PLLs can be used for DPA as long as they drive DPA
channels in their adjacent quadrant only. See Figure 5–23.
Both center fast PLLs cannot be used for DPA if one of the fast PLLs
drives the top and bottom banks, or if they are driving cross banks
(e.g., the lower fast PLL drives the top bank and the top fast PLL
drives the lower bank).
Figure 5–23. Center Fast PLL Usage When Driving DPA Channels
DPA
DPA
Channels Driven by
the Upper Center PLL
DPA
DPA
DPA
Ref CLK
Ref Clk
Fast PLL
Center PLL
Driving Top Bank
Fast PLL
Center PLL
Driving Lower Bank
Ref CLK
Ref Clk
DPA
DPA
DPA
DPA
Channels Driven by
the Lower Center PLL
DPA
Altera Corporation
January 2008
5–25
Stratix II Device Handbook, Volume 2
Differential Pin Placement Guidelines
Non-DPA Differential I/O Usage Guidelines
When a differential channel or channels of left or right banks are used in
non-DPA mode, you must adhere to the guidelines in the following
sections.
Fast PLL/Differential I/O Driving Distance
■
As shown in Figure 5–24, each fast PLL can drive all the channels in
the entire bank.
Figure 5–24. Fast PLL Driving Capability When Driving Non-DPA Differential
Channels
Fast PLL
Corner PLL
Ref CLK
Ref CLK
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Each PLL Can Drive
the Entire Bank
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
5–26
Stratix II Device Handbook, Volume 2
Ref CLK
Ref CLK
Fast PLL
Center PLL
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Using Corner and Center Fast PLLs
■
■
■
The corner and center fast PLLs can be used as long as the channels
driven by separate fast PLLs do not have their transmitter or receiver
channels interleaved. Figure 5–25 shows illegal placement of
differential channels when using corner and center fast PLLs.
If one fast PLL is driving transmitter channels only, and the other fast
PLL drives receiver channels only, the channels driven by those fast
PLLs can overlap each other.
Center fast PLLs can be used for both transmitter and receiver
channels.
Figure 5–25. Illegal Placement of Interlaced Duplex Channels in an I/O Bank
Fast PLL
Corner PLL
Ref CLK
Ref CLK
Duplex Channel Driven
by Center PLL
Duplex Channel Driven
by Corner PLL
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Interleaved Duplex
Channel is Not Allowed
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Board Design
Considerations
f
Altera Corporation
January 2008
Ref CLK
Ref CLK
Fast PLL
Center PLL
This section explains how to achieve the optimal performance from the
Stratix II and Stratix II GX high-speed I/O block and ensure first-time
success in implementing a functional design with optimal signal quality.
For more information on board layout recommendations and I/O pin
terminations, refer to AN 224: High-Speed Board Layout Guidelines.
5–27
Stratix II Device Handbook, Volume 2
Conclusion
To achieve the best performance from the device, pay attention to the
impedances of traces and connectors, differential routing, and
termination techniques.
f
Use this section together with the Stratix II Device Family Data Sheet in
volume 1 of the Stratix II Device Handbook.
The Stratix II and Stratix II GX high-speed module generates signals that
travel over the media at frequencies as high as one Gbps. Board designers
should use the following guidelines:
■
■
■
■
■
■
■
■
■
■
■
■
■
Conclusion
Base board designs on controlled differential impedance. Calculate
and compare all parameters such as trace width, trace thickness, and
the distance between two differential traces.
Place external reference resistors as close to receiver input pins as
possible.
Use surface mount components.
Avoid 90° or 45° corners.
Use high-performance connectors such as HMZD or VHDM
connectors for backplane designs. Two suppliers of highperformance connectors are Teradyne Corp (www.teradyne.com)
and Tyco International Ltd. (www.tyco.com).
Design backplane and card traces so that trace impedance matches
the connector’s or the termination’s impedance.
Keep an equal number of vias for both signal traces.
Create equal trace lengths to avoid skew between signals. Unequal
trace lengths also result in misplaced crossing points and system
margins when the TCCS value increases.
Limit vias, because they cause impedance discontinuities.
Use the common bypass capacitor values such as 0.001, 0.01, and
0.1 F to decouple the fast PLL power and ground planes. You can
also use 0.0047 F and 0.047 F.
Keep switching TTL signals away from differential signals to avoid
possible noise coupling.
Do not route TTL clock signals to areas under or above the
differential signals.
Route signals on adjacent layers orthogonally to each other.
Stratix II and Stratix II GX high-speed differential inputs and outputs,
with their DPA and data realignment circuitry, allow users to build a
robust multi-Gigabit system. The DPA circuitry allows users to
compensate for any timing skews resulting from physical layouts. The
data realignment circuitry allows the devices to align the data packet
between the transmitter and receiver. Together with the on-chip
differential termination, Stratix II and Stratix II GX devices can be used as
a single-chip solution for high-speed applications.
5–28
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Referenced
Documents
This chapter references the following documents:
■
■
■
■
■
■
■
Document
Revision History
AN 224: High-Speed Board Layout Guidelines
DC & Switching Characteristics chapter in volume 1 of the Stratix II
Device Handbook
DC & Switching Characteristics chapter in volume 1 of the
Stratix II GX Device Handbook
PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II Handbook
PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II GX Handbook
Selectable I/O standards in Stratix II & Stratix II GX Devices chapter in
volume 2 of the Stratix II Device Handbook
Stratix II Device Family Data Sheet in volume 1 of the Stratix II Device
Handbook
Table 5–5 shows the revision history for this chapter.
Table 5–5. Document Revision History (Part 1 of 2)
Date and
Document Version
Changes Made
January 2008, v2.2 Updated Figure 5–2.
May 2007, v2.1
Altera Corporation
January 2008
Summary of Changes
—
Added “Referenced Documents” section.
—
Minor text edits.
—
Added Figure 5–9.
—
Updated “Receiver Data Realignment Circuit”.
—
For the Stratix II GX Device Handbook only:
Formerly chapter 10. The chapter number changed
due to the addition of the Stratix II GX Dynamic
Reconfiguration chapter.
—
Updated entire chapter to include Stratix II GX
information.
—
Changed chapter part number.
—
Fixed two types in “High-Speed Differential I/Os
and Single-Ended I/Os” section
—
5–29
Stratix II Device Handbook, Volume 2
Document Revision History
Table 5–5. Document Revision History (Part 2 of 2)
Date and
Document Version
February 2007
v2.0
Changes Made
Summary of Changes
This chapter changed from High-Speed, SourceSynchronous Differential I/O Interfaces in Stratix II
GX Devices to “High-Speed Differential I/O
Interfaces with DPA in Stratix II and Stratix II GX
Devices”.
—
Added the “Document Revision History” section to
this chapter.
—
Added “and Stratix II GX” after each instance of
“Stratix II”.
—
Updated Figures 10–4, 10–20, 10–22.
—
Updated Note (4) of Figure 10–2.
—
Updated Table 10–1.
—
Updated the following sections:
● “I/O Banks”
● “Differential I/O Termination”
● “Fast PLL ”
● “Differential I/O Bit Position”
● “DPA Usage Guidelines”
● “Fast PLL/DPA Channel Driving Distance”
—
Updated Note (1) of Tables 10–2 and 10–3.
—
Added Note (5) to Figure 10–11.
—
Added Table 10–3.
—
Added Figures 10–14, 10–15, 10–19.
—
Deleted old section called High-Speed Differential
I/Os and Single-Ended I/Os and added a new
“High-Speed Differential I/Os and Single-Ended
I/Os” section.
—
Deleted DPA and Single-Ended I/Os section.
—
Updated title and added Note (1) to Figure 10–12.
—
Added Note (1) to Figure 10–13.
April 2006, v1.2
●
●
—
Updated all the MegaWizard Plug-In Manager
figures to match the Quartus II software GUI.
Updated “Dedicated Source-Synchronous
Circuitry” section, including Table 10–3.
—
February 2006,
v1.1
●
Updated chapter number from 9 to 10.
Updated Figures 10–11 and 10–12.
—
October 2005
v1.0
Added chapter to the Stratix II GX Device
Handbook.
—
●
5–30
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Section IV. Digital Signal
Processing (DSP)
This section provides information for design and optimization of digital
signal processing (DSP) functions and arithmetic operations in the onchip DSP blocks.
This section contains the following chapter:
■
Revision History
Altera Corporation
Chapter 6, DSP Blocks in Stratix II and Stratix II GX Devices
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section IV–1
Preliminary
Digital Signal Processing (DSP)
Section IV–2
Preliminary
Stratix II Device Handbook, Volume 2
Altera Corporation
6. DSP Blocks in Stratix II and
Stratix II GX Devices
SII52006-2.2
Introduction
Stratix® II and Stratix II GX devices have dedicated digital signal
processing (DSP) blocks optimized for DSP applications requiring high
data throughput. These DSP blocks combined with the flexibility of
programmable logic devices (PLDs), provide you with the ability to
implement various high performance DSP functions easily. Complex
systems such as CDMA2000, voice over Internet protocol (VoIP), highdefinition television (HDTV) require high performance DSP blocks to
process data. These system designs typically use DSP blocks as finite
impulse response (FIR) filters, complex FIR filters, fast Fourier transform
(FFT) functions, discrete cosine transform (DCT) functions, and
correlators.
Stratix II and Stratix II GX DSP blocks consist of a combination of
dedicated blocks that perform multiplication, addition, subtraction,
accumulation, and summation operations. You can configure these blocks
to implement arithmetic functions like multipliers, multiply-adders and
multiply-accumulators which are necessary for most DSP functions.
Along with the DSP blocks, the TriMatrixTM memory structures in
Stratix II and Stratix II GX devices also support various soft multiplier
implementations. The combination of soft multipliers and dedicated DSP
blocks increases the number of multipliers available in Stratix II and
Stratix II GX devices and provides you with a wide variety of
implementation options and flexibility when designing your systems.
f
DSP Block
Overview
See the Stratix II Device Family Data Sheet in volume 1 of the Stratix II
Device Handbook or the Stratix II GX Device Family Data Sheet in volume 1
of the Stratix II GX Device Handbook for more information on Stratix II
and Stratix II GX devices, respectively.
Each Stratix II and Stratix II GX device has two to four columns of DSP
blocks that efficiently implement multiplication, multiply-accumulate
(MAC) and multiply-add functions. Figure 6–1 shows the arrangement of
one of the DSP block columns with the surrounding LABs. Each DSP
block can be configured to support:
■
■
■
Altera Corporation
January 2008
Eight 9 × 9-bit multipliers
Four 18 × 18-bit multipliers
One 36 × 36-bit multiplier
6–1
DSP Block Overview
Figure 6–1. DSP Blocks Arranged in Columns with Adjacent LABs
DSP Block
Column
4 LAB
Rows
DSP Block
The multipliers then feed an adder or accumulator block within the DSP
block. Stratix II and Stratix II GX device multipliers support rounding
and saturation on Q1.15 input formats. The DSP block also has input
registers that can be configured to operate in a shift register chain for
efficient implementation of functions like FIR filters. The accumulator
within the DSP block can be initialized to any value and supports
rounding and saturation on Q1.15 input formats to the multiplier. A
single DSP block can be broken down to operate different configuration
modes simultaneously.
1
6–2
Stratix II Device Handbook, Volume 2
For more information on Q1.15 formatting, see “Saturation and
Rounding” on page 6–13.
Altera Corporation
January 2008
DSP Blocks in Stratix II and Stratix II GX Devices
The number of DSP blocks per column and the number of columns
available increases with device density. Table 6–1 shows the number of
DSP blocks in each Stratix II device and the multipliers that you can
implement.
Table 6–1. Number of DSP Blocks in Stratix II Devices
Device
DSP Blocks
9×9
Multipliers
Note (1)
18 × 18
Multipliers
36 × 36
Multipliers
EP2S15
12
96
48
12
EP2S30
16
128
64
16
EP2S60
36
288
144
36
EP2S90
48
384
192
48
EP2S130
63
504
252
63
EP2S180
96
768
384
96
Note to Table 6–1:
(1)
Each device has either the number of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.
Table 6–2 shows the number of DSP blocks in each Stratix II GX device
and the multipliers that you can implement.
Table 6–2. Number of DSP Blocks in Stratix II GX Devices
Note (1)
DSP Blocks
9×9
Multipliers
18 × 18
Multipliers
36 × 36
Multipliers
EP2SGX30C
EP2SGX30D
16
128
64
16
EP2SGX60C
EP2SGX60D
EP2SGX60E
36
288
144
36
EP2SGX90E
EP2SGX90F
48
384
192
48
EP2SGX130G
63
504
252
63
Device
Note to Table 6–2:
(1)
Altera Corporation
January 2008
Each device has either the number of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.
6–3
Stratix II Device Handbook, Volume 2
DSP Block Overview
In addition to the DSP block multipliers, you can use the Stratix II or
Stratix II GX device’s TriMatrix memory blocks for soft multipliers. The
availability of soft multipliers increases the number of multipliers
available within the device. Table 6–3 shows the total number of
multipliers available in Stratix II devices using DSP blocks and soft
multipliers.
Table 6–3. Number of Multipliers in Stratix II Devices
Device
EP2S15
DSP Blocks
(18 × 18)
Soft Multipliers
(16 × 16) (1), (2)
Total
Multipliers (3), (4)
48
100
148 (3.08)
EP2S30
64
189
253 (3.95)
EP2S60
144
325
469 (3.26)
EP2S90
192
509
701 (3.65)
EP2S130
252
750
1,002 (3.98)
EP2S130
384
962
1,346 (3.51)
Notes to Table 6–3:
(1)
(2)
(3)
(4)
Soft multipliers implemented in sum of multiplication mode. RAM blocks are
configured with 18-bit data widths and sum of coefficients up to 18-bits.
Soft multipliers are only implemented in M4K and M512 TriMatrix memory
blocks, not M-RAM blocks.
The number in parentheses represents the increase factor, which is the total
number of multipliers with soft multipliers divided by the number of 18 × 18
multipliers supported by DSP blocks only.
The total number of multipliers may vary according to the multiplier mode used.
6–4
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
DSP Blocks in Stratix II and Stratix II GX Devices
Table 6–4 shows the total number of multipliers available in Stratix II GX
devices using DSP blocks and soft multipliers.
Table 6–4. Number of Multipliers in Stratix II GX Devices
DSP Blocks
(18 × 18)
Soft Multipliers
(16 × 16) (1), (2)
Total
Multipliers (3), (4)
EP2SGX30C
EP2SGX30D
64
189
253 (3.95)
EP2SGX60C
EP2SGX60D
EP2SGX60E
144
325
469 (3.26)
EP2SGX90E
EP2SGX90F
192
509
701 (3.65)
EP2SGX130G
252
750
1,002 (3.98)
Device
Notes to Table 6–4:
(1)
(2)
(3)
(4)
f
Altera Corporation
January 2008
Soft multipliers implemented in sum of multiplication mode. RAM blocks are
configured with 18-bit data widths and sum of coefficients up to 18-bits.
Soft multipliers are only implemented in M4K and M512 TriMatrix memory
blocks, not M-RAM blocks.
The number in parentheses represents the increase factor, which is the total
number of multipliers with soft multipliers divided by the number of 18 × 18
multipliers supported by DSP blocks only.
The total number of multipliers may vary according to the multiplier mode used.
Refer to the Stratix II Architecture chapter in volume 1 of the Stratix II
Device Handbook or the Stratix II GX Architecture chapter in volume 1 of
the Stratix II GX Device Handbook for more information on Stratix II or
Stratix II GX TriMatrix memory blocks. Refer to AN 306: Implementing
Multipliers in FPGA Devices for more information on soft multipliers.
6–5
Stratix II Device Handbook, Volume 2
DSP Block Overview
Figure 6–2 shows the DSP block configured for 18 × 18 multiplier mode.
Figure 6–3 shows the 9 × 9 multiplier configuration of the DSP block.
Figure 6–2. DSP Block in 18 × 18 Mode
Optional Serial Shift
Register Inputs from
Previous DSP Block
Output
Selection
Multiplexer
Adder Output Block
PRN
D
Multiplier Block
Q
PRN
ENA
CLRN
From the row
interface block
Q1.15
Round/
Saturate
PRN
D
Q
D
Q
ENA
CLRN
ENA
CLRN
D
Adder/
Subtractor/
Accumulator
1
Q1.15
Round/
Saturate
PRN
Q
PRN
ENA
CLRN
D
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
Q1.15
Round/
Saturate
PRN
Q
D
Q
ENA
CLRN
Summation
Block
ENA
CLRN
Adder
D
Q
ENA
CLRN
D
PRN
Q
PRN
ENA
CLRN
Q1.15
Round/
Saturate
PRN
D
Q
D
Q
ENA
CLRN
D
Adder/
Subtractor/
Accumulator
2
D
Q1.15
Round/
Saturate
PRN
Q
PRN
ENA
CLRN
Optional Serial Shift
Register Outputs to
Next DSP Block
in the Column
Summation Stage
for Adding Four
Multipliers Together
ENA
CLRN
Q1.15
Round/
Saturate
PRN
Q
ENA
CLRN
D
Q
ENA
CLRN
Optional Pipline
Register Stage
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
to MultiTrack
Interconnect
6–6
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
DSP Blocks in Stratix II and Stratix II GX Devices
Figure 6–3. DSP Block in 9 × 9 Mode
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
Adder/
Subtractor/
1a
CLRN
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
CLRN
Summation
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
Adder/
Subtractor/
1b
CLRN
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
Output
Selection
Multiplexer
CLRN
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
D
Q
ENA
CLRN
Adder/
Subtractor/
2a
CLRN
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
CLRN
Summation
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
Adder/
Subtractor/
2b
CLRN
D
Q
ENA
CLRN
D
Q
ENA
D
Q
ENA
CLRN
CLRN
To MultiTrack
Interconnect
Altera Corporation
January 2008
6–7
Stratix II Device Handbook, Volume 2
Architecture
Architecture
The DSP block consists of the following elements:
■
■
■
■
■
A multiplier block
An adder/subtractor/accumulator block
A summation block
Input and output interfaces
Input and output registers
Multiplier Block
Each multiplier block has the following elements:
■
■
■
■
Input registers
A multiplier block
A rounding and/or saturation stage for Q1.15 input formats
A pipeline output register
6–8
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
DSP Blocks in Stratix II and Stratix II GX Devices
Figure 6–4 shows the multiplier block architecture.
Figure 6–4. Multiplier Block Architecture
mult_round (1)
mult_saturate (1)
signa (1)
signb (1)
aclr[3..0]
shiftinb
clock[3..0]
shiftina
ena[3..0]
sourcea
D
Data A
Data Out
Q
ENA
Q1.15
Round/
Saturate
CLRN
sourceb
(3)
D
Data B
D
Q
ENA
CLRN
(2)
Q
Output
Register
Pipeline
Register
ENA
mult_is_saturated
CLRN
D
Q
ENA
CLRN
Multiplier Block
DSP Block
shiftoutb shiftouta
Notes to Figure 6–4:
(1)
(2)
(3)
These signals are not registered or registered once to match the data path pipeline.
You can send these signals through either one or two pipeline registers.
The rounding and/or saturation is only supported in 18 × 18-bit signed multiplication for Q1.15 inputs.
Input Registers
Each multiplier operand can feed an input register or directly to the
multiplier. The following DSP block signals control each input register
within the DSP block:
■
■
■
clock[3..0]
ena[3..0]
aclr[3..0]
The input registers feed the multiplier and drive two dedicated shift
output lines, shiftouta and shiftoutb. The dedicated shift outputs
from one multiplier block directly feed input registers of the adjacent
multiplier below it within the same DSP block or the first multiplier in the
next DSP block to form a shift register chain, as shown in Figure 6–5. The
Altera Corporation
January 2008
6–9
Stratix II Device Handbook, Volume 2
Architecture
dedicated shift register chain spans a single column but longer shift
register chains requiring multiple columns can be implemented using
regular FPGA routing resources. Therefore, this shift register chain can be
of any length up to 768 registers in the largest member of the Stratix II or
Stratix II GX device family.
Shift registers are useful in DSP functions like FIR filters. When
implementing 9 × 9 and 18 × 18 multipliers, you do not need external
logic to create the shift register chain because the input shift registers are
internal to the DSP block. This implementation significantly reduces the
LE resources required, avoids routing congestion, and results in
predictable timing.
Stratix II and Stratix II GX DSP blocks allow you to dynamically select
whether a particular multiplier operand is fed by regular data input or
the dedicated shift register input using the sourcea and sourceb
signals. A logic 1 value on the sourcea signal indicates that data A is fed
by the dedicated scan-chain; a logic 0 value indicates that it is fed by
regular data input. This feature allows the implementation of a
dynamically loadable shift register where the shift register operates
normally using the scan-chains and can also be loaded dynamically in
parallel using the data input value.
6–10
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
DSP Blocks in Stratix II and Stratix II GX Devices
Figure 6–5. Shift Register Chain
Note (1)
DSP Block 0
Data A
D
Q
A[n] × B[n]
ENA
CLRN
Data B
D
Q1.15
Round/
Saturate
D
Q
ENA
CLRN
Q
ENA
CLRN
shiftoutb
shiftouta
D
Q
A[n − 1] × B[n − 1]
ENA
CLRN
D
Q1.15
Round/
Saturate
D
Q
ENA
CLRN
Q
ENA
CLRN
shiftoutb
shiftouta
DSP Block 1
D
Q
A[n − 2] × B[n − 2]
ENA
CLRN
D
Q1.15
Round/
Saturate
D
Q
ENA
CLRN
Q
ENA
CLRN
shiftoutb
shiftouta
Note to Figure 6–5:
(1)
Either Data A or Data B input can be set to a parallel input for constant coefficient multiplication.
Altera Corporation
January 2008
6–11
Stratix II Device Handbook, Volume 2
Architecture
Table 6–5 shows the summary of input register modes for the DSP block.
Table 6–5. Input Register Modes
Register Input
Mode
9×9
18 × 18
36 × 36
Parallel input
v
v
v
Shift register input
v
v
Multiplier Stage
The multiplier stage supports 9 × 9, 18 × 18, or 36 × 36 multipliers as well
as other smaller multipliers in between these configurations. See
“Operational Modes” on page 6–21 for details. Depending on the data
width of the multiplier, a single DSP block can perform many
multiplications in parallel.
Each multiplier operand can be a unique signed or unsigned number.
Two signals, signa and signb, control the representation of each
operand respectively. A logic 1 value on the signa signal indicates that
data A is a signed number while a logic 0 value indicates an unsigned
number. Table 6–6 shows the sign of the multiplication result for the
various operand sign representations. The result of the multiplication is
signed if any one of the operands is a signed value.
Table 6–6. Multiplier Sign Representation
Data A (signa Value)
Data B (signb Value)
Result
Unsigned (logic 0)
Unsigned (logic 0)
Unsigned
Unsigned (logic 0)
Signed (logic 1)
Signed
Signed (logic 1)
Unsigned (logic 0)
Signed
Signed (logic 1)
Signed (logic 1)
Signed
There is only one signa and one signb signal for each DSP block.
Therefore, all of the data A inputs feeding the same DSP block must have
the same sign representation. Similarly, all of the data B inputs feeding the
same DSP block must have the same sign representation. The multiplier
offers full precision regardless of the sign representation.
1
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Stratix II Device Handbook, Volume 2
When the signa and signb signals are unused, the Quartus® II
software sets the multiplier to perform unsigned multiplication
by default.
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January 2008
DSP Blocks in Stratix II and Stratix II GX Devices
Saturation and Rounding
The DSP blocks have hardware support to perform optional saturation
and rounding after each 18 × 18 multiplier for Q1.15 input formats.
1
Designs must use 18 × 18 multipliers for the saturation and
rounding options because the Q1.15 input format requires 16-bit
input widths.
1
Q1.15 input format multiplication requires signed multipliers.
The most significant bit (MSB) in the Q1.15 input format
represents the value’s sign bit. Use signed multipliers to ensure
the proper sign extension during multiplication.
The Q1.15 format uses 16 bits to represent each fixed point input. The
MSB is the sign bit, and the remaining 15-bits are used to represent the
value after the decimal place (or the fractional value). This Q1.15 value is
equivalent to an integer number representation of the 16-bits divided by
215, as shown in the following equations.
−
1
2
1
8
= 1 100 0000 0000 0000 = −
= 0 001 0000 0000 0000 =
0x4000
215
0x1000
215
All Q1.15 numbers are between –1 and 1.
When performing multiplication, even though the Q1.15 input only uses
16 of the 18 multiplier inputs, the entire 18-bit input bus is transmitted to
the multiplier. This is like a 1.17 input, where the two least significant bits
(LSBs) are always 0.
The multiplier output will be a 2.34 value (36 bits total) before performing
any rounding or saturation. The two MSBs are sign bits. Since the output
only requires one sign bit, you can ignore one of the two MSBs, resulting
in a Q1.34 value before rounding or saturation.
When the design performs saturation, the multiplier output gets
saturated to 0x7FFFFFFF in a 1.31 format. This uses bits [34..3] of the
overall 36-bit multiplier output. The three LSBs are set to 0.
The DSP block obtains the mult_is_saturated or
accum_is_saturated overflow signal value from the LSB of the
multiplier or accumulator output. Therefore, whenever saturation occurs,
the LSB of the multiplier or accumulator output will send a 1 to the
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Architecture
mult_is_saturated or accum_is_saturated overflow signal. At
all other times, this overflow signal is 0 when saturation is enabled or
reflects the value of the LSB of the multiplier or accumulator output.
When the design performs rounding, it adds 0x00008000 in 1.31 format to
the multiplier output, and it only uses bits [34..15] of the overall 36-bit
multiplier output. Adding 0x00008000 in 1.31 format to the 36-bit
multiplier result is equivalent to adding 0x0 0004 0000 in 2.34 format. The
16 LSBs are set to 0. Figure 6–6 shows which bits are used when the design
performs rounding and saturation for the multiplication.
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January 2008
DSP Blocks in Stratix II and Stratix II GX Devices
Figure 6–6. Rounding and Saturation Bits
18 × 18 Multiplication
1 Sign
Bit
15 Bits
2 LSBs
18
00
2 Sign
Bits (1)
31 Bits
3 LSBs
36
000
1 Sign
Bit
15 Bits
2 LSBs
18
00
Saturated Output Result
2 Sign
Bits (1)
31 Bits
1 11
3 LSBs
111000
Rounded Output Result
2 Sign
Bits (1)
31 Bits
2 Sign
Bits (1)
3 LSBs
000
+
15 Bits
18 Bits
0000 000 0 0000 000001 0000 000 0 0000 000000
19 LSBs
are Ignored
=
00 0000 000 0 0000 00000
Note to Figure 6–6:
(1)
Both sign bits are the same. The design only uses one sign bit, and the other one is ignored.
If the design performs a multiply_accumulate or multiply_add
operation, the multiplier output is input to the
adder/subtractor/accumulator blocks as a 2.31 value, and the three LSBs
are 0.
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January 2008
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Architecture
Pipeline Registers
The output from the multiplier can feed a pipeline register or this register
can be bypassed. Pipeline registers may be implemented for any
multiplier size and increase the DSP block’s maximum performance,
especially when using the subsequent DSP block adder stages. Pipeline
registers split up the long signal path between the
adder/subtractor/accumulator block and the adder/output block,
creating two shorter paths.
Adder/Output Block
The adder/output block has the following elements:
■
■
■
■
An adder/subtractor/accumulator block
A summation block
An output select multiplexer
Output registers
Figure 6–7 shows the adder/output block architecture.
The adder/output block can be configured as:
■
■
■
■
■
An output interface
An accumulator which can be optionally loaded
A one-level adder
A two-level adder with dynamic addition/subtraction control on the
first-level adder
The final stage of a 36-bit multiplier, 9 × 9 complex multiplier, or
18 × 18 complex multiplier
The output select multiplexer sets the output configuration of the DSP
block. The output registers can be used to register the output of the
adder/output block.
1
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The adder/output block cannot be used independently from the
multiplier.
Altera Corporation
January 2008
DSP Blocks in Stratix II and Stratix II GX Devices
Figure 6–7. Adder/Output Block Architecture
Note (1)
adder1_round (2)
Accumulator Feedback
Output Select
Multiplexer
Result A /
accum_sload_upper_data
Output Registers
accum_sload0 (2)
addnsub1 (2)
Adder/
Subtractor/
Accumulator 1
overflow0
Q1.15
Rounding
(3)
Result B
signa (2)
Summation
Output
Register Block
signb (2)
Result C /
accum_sload_upper_data
accum_sload1 (2)
addnsub3 (2)
Adder/
Subtractor/
Accumulator 2
Q1.15
Rounding
(3)
overflow1
Result D
adder3_round (2)
Accumulator Feedback
Notes to Figure 6–7:
(1)
(2)
(3)
The adder/output block is in 18 × 18 mode. In 9 × 9 mode, there are four adder/subtractor blocks and two
summation blocks.
You can send these signals through a pipeline register. The pipeline length can be set to 1 or 2.
Q1.15 inputs are not available in 9 × 9 or 36 × 36 modes.
Adder/Subtractor/Accumulator Block
The adder/subtractor/accumulator block is the first level adder stage of
the adder/output block. This block can be configured as an accumulator
or as an adder/subtractor.
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January 2008
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Architecture
Accumulator
When the adder/subtractor/accumulator is configured as an
accumulator, the output of the adder/output block feeds back to the
accumulator as shown in Figure 6–7. The accumulator can be set up to
perform addition only, subtraction only or the addnsub signal can be
used to dynamically control the accumulation direction. A logic 1 value
on the addnsub signal indicates that the accumulator is performing
addition while a logic 0 value indicates subtraction.
Each accumulator can be cleared by either clearing the DSP block output
register or by using the accum_sload signal. The accumulator clear
using the accum_sload signal is independent from the resetting of the
output registers so the accumulation can be cleared and a new one can
begin without losing any clock cycles. The accum_sload signal controls
a feedback multiplexer that specifies that the output of the multiplier
should be summed with a zero instead of the accumulator feedback path.
The accumulator can also be initialized/preloaded with a non-zero value
using the accum_sload signal and the accum_sload_upper_data
bus with one clock cycle latency. Preloading the accumulator is done by
adding the result of the multiplier with the value specified on the
accum_sload_upper_data bus. As in the case of the accumulator
clearing, the accum_sload signal specifies to the feedback multiplexer
that the accum_sload_upper_data signal should feed the
accumulator instead of the accumulator feedback signal. The
accum_sload_upper_data signal only loads the upper 36-bits of the
accumulator. To load the entire accumulator, the value for the lower
16-bits must be sent through the multiplier feeding that accumulator with
the multiplier set to perform a multiplication by one.
The overflow signal will go high on the positive edge of the clock when
the accumulator detects an overflow or underflow. The overflow signal
will stay high for only one clock cycle after an overflow or underflow is
detected even if the overflow or underflow condition is still present. A
latch external to the DSP block has to be used to preserve the overflow
signal indefinitely or until the latch is cleared.
The DSP blocks support Q1.15 input format saturation and rounding in
each accumulator. The following signals are available that can control if
saturation or rounding or both is performed to the output of the
accumulator:
■
■
■
accum_round
accum_saturation
accum_is_saturated output
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DSP Blocks in Stratix II and Stratix II GX Devices
Each DSP block has two sets of accum_round and accum_saturation
signals which control if rounding or saturation is performed on the
accumulator output respectively (one set of signals for each
accumulator). Rounding and saturation of the accumulator output is only
available when implementing an 16 × 16 multiplier-accumulator to
conform to the bit widths required for Q1.15 input format computation.
A logic 1 value on the accum_round and accum_saturation signal
indicates that rounding or saturation is performed while a logic 0
indicates that no rounding or saturation is performed. A logic 1 value on
the accum_is_saturated output signal tells you that saturation has
occurred to the result of the accumulator.
Figure 6–10 shows the DSP block configured to perform multiplieraccumulator operations.
Adder/Subtractor
The addnsub1 or addnsub3 signals specify whether you are performing
addition or subtraction. A logic 1 value on the addnsub1 or addnsub3
signals indicates that the adder/subtractor is performing addition while
a logic 0 value indicates subtraction. These signals can be dynamically
controlled using logic external to the DSP block. If the first stage is
configured as a subtractor, the output is A – B and C – D.
The adder/subtractor block share the same signa and signb signals as
the multiplier block. The signa and signb signals can be pipelined with
a latency of one or two clock cycles or not.
The DSP blocks support Q1.15 input format rounding (not saturation)
after each adder/subtractor. The addnsub1_round and
addnsub3_round signals determine if rounding is performed to the
output of the adder/subtractor.
The addnsub1_round signal controls the rounding of the top
adder/subtractor and the addnsub3_round signal controls the
rounding of the bottom adder/subtractor. Rounding of the adder output
is only available when implementing an 16 × 16 multiplier-adder to
conform to the bit widths required for Q1.15 input format computation.
A logic 1 value on the addnsub_round signal indicates that rounding is
performed while a logic 0 indicates that no rounding is performed.
Summation Block
The output of the adder/subtractor block feeds an optional summation
block, which is an adder block that sums the outputs of both
adder/subtractor blocks. The summation block is used when more than
two multiplier results are summed. This is useful in applications such as
FIR filtering.
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January 2008
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Architecture
Output Select Multiplexer
The outputs of the different elements of the adder/output block are
routed through an output select multiplexer. Depending on the
operational mode of the DSP block, the output multiplexer selects
whether the outputs of the DSP blocks comes from the outputs of the
multiplier block, the outputs of the adder/subtractor/accumulator, or the
output of the summation block. The output select multiplier
configuration is set automatically by software, based on the DSP block
operational mode you specify.
Output Registers
You can use the output registers to register the DSP block output. The
following signals can control each output register within the DSP block:
■
■
■
clock[3..0]
ena[3..0]
aclr[3..0]
The output registers can be used in any DSP block operational mode.
1
f
The output registers form part of the accumulator in the
multiply-accumulate mode.
Refer to the Stratix II Architecture chapter in volume 1 of the Stratix II
Device Handbook or the Stratix II GX Architecture chapter in volume 1 of
the Stratix II GX Device Handbook for more information on the DSP block
routing and interface.
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Stratix II Device Handbook, Volume 2
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DSP Blocks in Stratix II and Stratix II GX Devices
Operational
Modes
The DSP block can be used in one of four basic operational modes, or a
combination of two modes, depending on the application needs.
Table 6–7 shows the four basic operational modes and the number of
multipliers that can be implemented within a single DSP block
depending on the mode.
Table 6–7. DSP Block Operational Modes
Number of Multipliers
Mode
9×9
Simple multiplier
Eight multipliers
with eight product
outputs
18 × 18
Four multipliers
with four product
outputs
36 × 36
One multiplier
Two 52-bit
multiplyaccumulate blocks
-
Two-multiplier
adder
Four two-multiplier Two two-multiplier
adder (one
adder (two 9 × 9
complex multiply) 18 × 18 complex
multiply)
-
Four-multiplier
adder
Two four-multiplier
adder
-
Multiply
accumulate
-
One four-multiplier
adder
The Quartus II software includes megafunctions used to control the mode
of operation of the multipliers. After you make the appropriate parameter
settings using the megafunction’s MegaWizard® Plug-In Manager, the
Quartus II software automatically configures the DSP block.
Stratix II and Stratix II GX DSP blocks can operate in different modes
simultaneously. For example, a single DSP block can be broken down to
operate a 9 × 9 multiplier as well as an 18 × 18 multiplier-adder where
both multiplier's input a and input b have the same sign representations.
This increases DSP block resource efficiency and allows you to implement
more multipliers within a Stratix II or Stratix II GX device. The Quartus II
software automatically places multipliers that can share the same DSP
block resources within the same block.
Additionally, you can set up each Stratix II or Stratix II GX DSP block to
dynamically switch between the following three modes:
■
■
■
Altera Corporation
January 2008
Up to four 18-bit independent multipliers
Up to two 18-bit multiplier-accumulators
One 36-bit multiplier
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Stratix II Device Handbook, Volume 2
Operational Modes
Each half of a Stratix II or Stratix II GX DSP block has separate mode
control signals, which allows you to implement multiple 18-bit
multipliers or multiplier-accumulators within the same DSP block and
dynamically switch them independently (if they are in separate DSP
block halves). If the design requires a 36-bit multiplier, you must switch
the entire DSP block to accommodate the it since the multiplier requires
the entire DSP block. The smallest input bit width that supports dynamic
mode switching is 18 bits.
Simple Multiplier Mode
In simple multiplier mode, the DSP block performs individual
multiplication operations for general-purpose multipliers and for
applications such as computing equalizer coefficient updates which
require many individual multiplication operations.
9- and 18-Bit Multipliers
Each DSP block multiplier can be configured for 9- or 18-bit
multiplication. A single DSP block can support up to eight individual
9 × 9 multipliers or up to four individual 18 × 18 multipliers. For operand
widths up to 9-bits, a 9 × 9 multiplier will be implemented and for
operand widths from 10- to 18-bits, an 18 × 18 multiplier will be
implemented. Figure 6–8 shows the DSP block in the simple multiplier
operation mode.
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DSP Blocks in Stratix II and Stratix II GX Devices
Figure 6–8. Simple Multiplier Mode
mult_round (1)
mult_saturate (1)
signa (1)
signb (1)
aclr[3..0]
shiftinb
clock[3..0]
shiftina
ena[3..0]
sourcea
Output Register
D
Data A
Data Out
Q
ENA
CLRN
D
Q
ENA
Q1.15
Round/
Saturate
sourceb
(3)
D
Data B
CLRN
Q
mult_is_saturated (2)
D
Q
ENA
ENA
D
Q
ENA
CLRN
CLRN
CLRN
Multiplier Block
DSP Block
shiftoutb
shiftouta
Notes to Figure 6–8:
(1)
(2)
(3)
These signals are not registered or registered once to match the data path pipeline.
This signal has the same latency as the data path.
The rounding and saturation is only supported in 18- × 18-bit signed multiplication for Q1.15 inputs.
The multiplier operands can accept signed integers, unsigned integers or
a combination of both. The signa and signb signals can be changed
dynamically and can be registered in the DSP block. Additionally, the
multiplier inputs and result can be registered independently. The pipeline
registers within the DSP block can be used to pipeline the multiplier
result, increasing the performance of the DSP block.
36-Bit Multiplier
The 36-bit multiplier is also a simple multiplier mode but uses the entire
DSP block, including the adder/output block to implement the
36 × 36-bit multiplication operation. The device inputs 18-bit sections of
the 36-bit input into the four 18-bit multipliers. The adder/output block
adds the partial products obtained from the multipliers using the
summation block. Pipeline registers can be used between the multiplier
stage and the summation block to speed up the multiplication. The
36 × 36-bit multiplier supports signed, unsigned as well as mixed sign
multiplication. Figure 6–9 shows the DSP block configured to implement
a 36-bit multiplier.
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January 2008
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Operational Modes
Figure 6–9. 36-Bit Multiplier
signa (1)
signb (1)
aclr
clock
ena
18
A[17..0]
D
Q
ENA
CLRN
Q
CLRN
18
B[17..0]
D
ENA
D
Q
ENA
CLRN
18
A[35..18]
D
Q
D
ENA
ENA
CLRN
B[35..18]
D
ENA
Q
36 × 36
Multiplier
Adder
CLRN
18
D
Q
Data Out
CLRN
Q
signa (2)
ENA
signb (2)
CLRN
18
A[35..18]
D
Q
ENA
CLRN
Q
CLRN
18
B[17..0]
D
ENA
D
Q
ENA
CLRN
18
A[17..0]
D
Q
ENA
CLRN
Q
CLRN
18
B[35..18]
D
ENA
D
Q
ENA
CLRN
Notes to Figure 6–9:
(1)
(2)
These signals are either not registered or registered once to match the pipeline.
These signals are either not registered, registered once, or registered twice to match the data path pipeline.
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January 2008
DSP Blocks in Stratix II and Stratix II GX Devices
The 36-bit multiplier is useful for applications requiring more than 18-bit
precision, for example, for mantissa multiplication of precision floatingpoint arithmetic applications.
Multiply Accumulate Mode
In multiply accumulate mode, the output of the multiplier stage feeds the
adder/output block which is configured as an accumulator or subtractor.
Figure 6–10 shows the DSP block configured to operate in multiply
accumulate mode.
Figure 6–10. Multiply Accumulate Mode
aclr[3..0]
clock[3..0]
ena[3..0]
Data A
accum_sload_upper_data (3)
accum_sload (3)
shiftina
shiftinb
D
Q
D
ENA
CLRN
D
Q1.15
Round/
Saturate
Q
ENA
Q1.15
Round/
Saturate
Q
Data Out
ENA
Accumulator
CLRN
CLRN
accum_is_saturated (4)
Data B
D
D
Q
ENA
Q
ENA
CLRN
D
Q
overflow
ENA
D
Q
ENA
shiftoutb
shiftouta
signb (1), (2)
signa (1), (2)
mult_round (2)
mult_saturate (2)
D
Q
ENA
mult_is_saturated (4)
addnsub (3)
signb (1), (3)
signa (1), (3)
accum_round (3)
accum_saturate (3)
Notes to Figure 6–10:
(1)
(2)
(3)
(4)
The signa and signb signals are the same in the multiplier stage and the adder/output block.
These signals are not registered or registered once to match the data path pipeline.
You can send these signals through either one or two pipeline registers.
These signals match the latency of the data path.
A single DSP block can implement up to two independent 18-bit
multiplier accumulators. The Quartus II software implements smaller
multiplier accumulators by tying the unused lower-order bits of the 18-bit
multiplier to ground.
The multiplier accumulator output can be up to 52-bits wide to account
for a 36-bit multiplier result with 16-bits of accumulation. In this mode,
the DSP block uses output registers and the accum_sload and overflow
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January 2008
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Operational Modes
signals. The accum_sload signal can be used to clear the accumulator so
that a new accumulation operation can begin without losing any clock
cycles. This signal can be unregistered or registered once or twice. The
accum_sload signal can also be used to preload the accumulator with a
value specified on the accum_sload_upper_data signal with a one
clock cycle penalty. The accum_sload_upper_data signal only loads
the upper 36-bits (bits [51..16] of the accumulator). To load the entire
accumulator, the value for the lower 16-bits (bits [15..0]) must be sent
through the multiplier feeding that accumulator with the multiplier set to
perform a multiplication by one. Bits [17..16] are overlapped by both
the accum_sload_upper_data signal and the multiplier output. Either
one of these signals can be used to load bits [17..16].
The overflow signal indicates an overflow or underflow in the
accumulator. This signal gets updated every clock cycle due to a new
accumulation operation every cycle. To preserve the signal, an external
latch can be used. The addnsub signal can be used to specify if an
accumulation or subtraction is performed dynamically.
1
The DSP block can implement just an accumulator (without
multiplication) by specifying a multiply by one at the multiplier
stage followed by an accumulator to force the Quartus II
software to implement the function within the DSP block.
Multiply Add Mode
In multiply add mode, the output of the multiplier stage feeds the
adder/output block which is configured as an adder or subtractor to sum
or subtract the outputs of two or more multipliers. The DSP block can be
configured to implement either a two-multiply add (where the outputs of
two multipliers are added/subtracted together) or a four-multiply add
function (where the outputs of four multipliers are added or subtracted
together).
1
The adder block within the DSP block can only be used if it
follows multiplication operations.
Two-Multiplier Adder
In the two-multiplier adder configuration, the DSP block can implement
four 9-bit or smaller multiplier adders or two 18-bit multiplier adders.
The adders can be configured to take the sum of both multiplier outputs
or the difference of both multiplier outputs. You have the option to vary
the summation/subtraction operation dynamically. These multiply add
functions are useful for applications such as FFTs and complex FIR filters.
Figure 6–11 shows the DSP block configured in the two-multiplier adder
mode.
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DSP Blocks in Stratix II and Stratix II GX Devices
Figure 6–11. Two-Multiplier Adder Mode
mult_round (1)
mult_saturate (1)
signa (1)
signb (1)
aclr[3..0]
clock[3..0]
ena[3..0]
shiftina
signb (2)
signa (2)
addnsub_round (2)
addnsub1 (2)
shiftinb
mult0_is_saturated (3)
D
Q
ENA
D
Q
ENA
D
Data A 1
Q
ENA
CLRN
D
Data B 1
D
Q1.15
Round/
Saturate
PRN
Q
ENA
CLRN
Q
ENA
Adder/
Subtractor/
Accumulator
1
CLRN
D
Data A 2
Q
ENA
CLRN
D
Data B 2
D
Q
ENA
Data Out 1
CLRN
PRN
Q
ENA
CLRN
Q
ENA
shiftoutb
D
Q1.15
Round/
Saturate
Q1.15
Rounding
mult1_is_saturated (3)
D
Q
ENA
D
Q
ENA
shiftouta
Notes to Figure 6–11:
(1)
(2)
(3)
These signals are not registered or registered once to match the data path pipeline.
You can send these signals through a pipeline register. The pipeline length can be set to 1 or 2.
These signals match the latency of the data path.
Complex Multiply
The DSP block can be configured to implement complex multipliers using
the two-multiplier adder mode. A single DSP block can implement one
18 × 18-bit complex multiplier or two 9 × 9-bit complex multipliers.
A complex multiplication can be written as:
(a + jb) × (c + jd) = ((a × c) – (b × d)) + j ((a × d) + (b × c))
To implement this complex multiplication within the DSP block, the real
part ((a × c) – (b × d)) is implemented using two multipliers feeding one
subtractor block while the imaginary part ((a × d) + (b × c)) is implemented
using another two multipliers feeding an adder block, for data up to
18-bits. Figure 6–12 shows an 18-bit complex multiplication. For data
widths up to 9-bits, a DSP block can perform two separate complex
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January 2008
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Operational Modes
multiplication operations using eight 9-bit multipliers feeding four
adder/subtractor/accumulator blocks. Resources external to the DSP
block must be used to route the correct real and imaginary input
components to the appropriate multiplier inputs to perform the correct
computation for the complex multiplication operation.
Figure 6–12. Complex Multiplier Using Two-Multiplier Adder Mode
DSP Block
18
18
A
36
18
18
C
18
37
Subtractor
18
B
(A × C) − (B × D)
(Real Part)
36
18
18
D
18
A
36
18
D
37
Adder
18
B
(A × D) + (B × C)
(Imaginary Part)
36
18
C
Four-Multiplier Adder
In the four-multiplier adder configuration, the DSP block can implement
one 18 × 18 or two individual 9 × 9 multiplier adders. These modes are
useful for implementing one-dimensional and two-dimensional filtering
applications. The four-multiplier adder is performed in two addition
stages. The outputs of two of the four multipliers are initially summed in
the two first-stage adder/subtractor/accumulator blocks. The results of
these two adder/subtractor/accumulator blocks are then summed in the
final stage summation block to produce the final four-multiplier adder
result. Figure 6–13 shows the DSP block configured in the four-multiplier
adder mode.
6–28
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
DSP Blocks in Stratix II and Stratix II GX Devices
Figure 6–13. Four-Multiplier Adder Mode
mult_round (1)
mult_saturate (1)
signa (1)
signb (1)
aclr[3..0]
clock[3..0]
ena[3..0]
shiftina
shiftinb
D
PRN
Q
D
ENA
CLRN
D
Data A 1
Q
ENA
CLRN
Q1.15
Round/
Saturate
(4)
D
Data B 1
D
PRN
Q
mult0_is_saturated (3)
ENA
CLRN
PRN
Q
ENA
CLRN
Q
ENA
Adder/
Subtractor/
Accumulator
1
CLRN
D
Data A 2
Q
ENA
CLRN
Q1.15
Round/
Saturate
(4)
D
Data B 2
D
Q1.15
Rounding
(4)
PRN
Q
D
ENA
CLRN
PRN
D
Q
ENA
CLRN
D
addnsub1 (2)
addnsub1/3_round (2)
signa (2)
signb (2)
addnsub3 (2)
Adder
Q
ENA
CLRN
Q1.15
Round/
Saturate
(4)
D
Data B 1
D
CLRN
Q1.15
Round/
Saturate
D
Q1.15
Rounding
(4)
PRN
Q
ENA
CLRN
Q
ENA
D
PRN
Q
ENA
CLRN
shiftoutb
mult0_is_saturated (3)
ENA
CLRN
Adder/
Subtractor/
Accumulator
1
(4)
D
PRN
Q
ENA
CLRN
Q
ENA
Data B 2
D
Q
CLRN
D
Data Out 1
CLRN
PRN
Q
ENA
Data A 2
D
Q
ENA
PRN
Q
ENA
CLRN
D
mult1_is_saturated (3)
ENA
CLRN
Q
ENA
Data A 1
PRN
Q
D
PRN
Q
mult1_is_saturated (3)
ENA
CLRN
shiftouta
Notes to Figure 6–13:
(1)
(2)
(3)
(4)
These signals are not registered or registered once to match the data path pipeline.
You should send these signals through the pipeline register to match the latency of the data path.
These signals match the latency of the data path.
The rounding and saturation is only supported in 18- × 18-bit signed multiplication for Q1.15 inputs.
Altera Corporation
January 2008
6–29
Stratix II Device Handbook, Volume 2
Operational Modes
FIR Filter
The four-multiplier adder mode can be used to implement FIR filter and
complex FIR filter applications. To do this, the DSP block is set up in a
four-multiplier adder mode with one set of input registers configured as
shift registers using the dedicated shift register chain. The set of input
registers configured as shift registers will contain the input data while the
inputs configured as regular inputs will hold the filter coefficients.
Figure 6–14 shows the DSP block configured in the four-multiplier adder
mode using input shift registers.
6–30
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
DSP Blocks in Stratix II and Stratix II GX Devices
Figure 6–14. FIR Filter Implemented Using the Four-Multiplier Adder Mode with Input Shift Registers
Data A
D
18
Q
ENA
CLRN
Coefficient 0
D
18
Q
D
ENA
Q
A[n] × Coefficient 0
(to Adder)
CLRN
ENA
CLRN
D
Q
ENA
CLRN
Coefficient 1
D
18
Q
D
ENA
Q
A[n − 1] × Coefficient 1
(to Adder)
CLRN
ENA
CLRN
D
Q
ENA
CLRN
Coefficient 2
D
18
Q
D
ENA
Q
A[n − 2] × Coefficient 2
(to Adder)
CLRN
ENA
CLRN
Altera Corporation
January 2008
6–31
Stratix II Device Handbook, Volume 2
Software Support
The built-in input shift register chain within the DSP block eliminates the
need for shift registers externally to the DSP block in logic elements (LEs).
This architecture feature simplifies the filter design and improves the
filter performance because all the filter circuitry is localized within the
DSP block.
1
Input shift registers for the 36-bit simple multiplier mode have
to be implemented using external registers to the DSP block.
A single DSP block can implement a four tap 18-bit FIR filter. For filters
larger than four taps, the DSP blocks can be cascaded with additional
adder stages implemented using LEs.
Software
Support
Altera provides two distinct methods for implementing various modes of
the DSP block in your design: instantiation and inference. Both methods
use the following three Quartus II megafunctions:
■
■
■
lpm_mult
altmult_add
altmult_accum
You can instantiate the megafunctions in the Quartus II software to use
the DSP block. Alternatively, with inference, you can create a HDL design
an synthesize it using a third-party synthesis tool like LeonardoSpectrum
or Synplify or Quartus II Native Synthesis that infers the appropriate
megafunction by recognizing multipliers, multiplier adders, and
multiplier accumulators. Using either method, the Quartus II software
maps the functionality to the DSP blocks during compilation.
Conclusion
f
See Quartus II On-Line Help for instructions on using the megafunctions
and the MegaWizard Plug-In Manager.
f
For more information, see the Synthesis section in Design and Synthesis
(volume 1) of the Quartus II Development Software Handbook.
The Stratix II and Stratix II GX device DSP blocks are optimized to
support DSP applications requiring high data throughput such as FIR
filters, FFT functions and encoders. These DSP blocks are flexible and can
be configured to implement one of several operational modes to suit a
particular application. The built-in shift register chain,
adder/subtractor/accumulator block and the summation block
minimizes the amount of external logic required to implement these
functions, resulting in efficient resource utilization and improved
performance and data throughput for DSP applications. The Quartus II
6–32
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
DSP Blocks in Stratix II and Stratix II GX Devices
software, together with the LeonardoSpectrum™ and Synplify software
provide a complete and easy-to-use flow for implementing these
multiplier functions in the DSP blocks.
Referenced
Documents
This chapter references the following documents:
■
■
■
■
■
■
Document
Revision History
AN 306: Implementing Multipliers in FPGA Devices
Design and Synthesis (volume 1) of the Quartus II Development Software
Handbook
Stratix II Architecture chapter in volume 1 of the Stratix II Device
Handbook
Stratix II GX Architecture chapter in volume 1 of the Stratix II GX
Device Handbook
Stratix II Device Family Data Sheet in volume 1 of the Stratix II Device
Handbook
Stratix II GX Device Family Data Sheet in volume 1 of the Stratix II GX
Device Handbook
Table 6–8 shows the revision history for this chapter.
Table 6–8. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
January 2008
v2.2
Added the “Referenced Documents” section.
—
Minor text edits.
—
No change
For the Stratix II GX Device Handbook only:
Formerly chapter 11. The chapter number changed
due to the addition of the Stratix II GX Dynamic
Reconfiguration chapter. No content change.
—
February 2007
v2.1
Added the “Document Revision History” section to
this chapter.
—
No change
Formerly chapter 10. Chapter number change only
due to chapter addition to Section I in
February 2006; no content change.
—
October 2005
v2.0
Added chapter to the Stratix II GX Device
Handbook.
—
Altera Corporation
January 2008
6–33
Stratix II Device Handbook, Volume 2
Document Revision History
6–34
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Section V. Configuration&
Remote System Upgrades
This section provides configuration information for all of the supported
configuration schemes for Stratix® II devices. These configuration
schemes use either a microprocessor, configuration device, or download
cable. There is detailed information on how to design with Altera
enhanced configuration devices which includes information on how to
manage multiple configuration files and access the on-chip FLASH
memory space. The last chapter shows designers how to perform remote
and local upgrades for their designs.
This section contains the following chapters:
Revision History
Altera Corporation
■
Chapter 7, Configuring Stratix II and Stratix II GX Devices
■
Chapter 8, Remote System Upgrades with Stratix II and Stratix II GX
Devices
■
Chapter 9, IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II
and Stratix II GX Devices
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section V–1
Preliminary
Configuration& Remote System Upgrades
Section V–2
Preliminary
Stratix II Device Handbook, Volume 2
Altera Corporation
7. Configuring Stratix II and
Stratix II GX Devices
SII52007-4.5
Introduction
Stratix® II and Stratix II GX devices use SRAM cells to store configuration
data. Because SRAM memory is volatile, configuration data must be
downloaded to Stratix II and Stratix II GX devices each time the device
powers up. Stratix II and Stratix II GX devices can be configured using
one of five configuration schemes: the fast passive parallel (FPP), active
serial (AS), passive serial (PS), passive parallel asynchronous (PPA), and
Joint Test Action Group (JTAG) configuration schemes. All configuration
schemes use either an external controller (for example, a MAX® II device
or microprocessor) or a configuration device.
Configuration Devices
The Altera enhanced configuration devices (EPC16, EPC8, and EPC4)
support a single-device configuration solution for high-density devices
and can be used in the FPP and PS configuration schemes. They are
ISP-capable through its JTAG interface. The enhanced configuration
devices are divided into two major blocks, the controller and the flash
memory.
f
For information on enhanced configuration devices, refer to the Enhanced
Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet in volume 2 of
the Configuration Handbook.
The Altera serial configuration devices (EPCS64, EPCS16, and EPCS4)
support a single-device configuration solution for Stratix II and
Stratix II GX devices and are used in the AS configuration scheme. Serial
configuration devices offer a low cost, low pin count configuration
solution.
f
For information on serial configuration devices, refer to the Serial
Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128)
Data Sheet chapter in volume 2 of the Configuration Handbook.
The EPC2 configuration devices provide configuration support for the PS
configuration scheme. The EPC2 device is ISP-capable through its JTAG
interface. The EPC2 device can be cascaded to hold large configuration
files.
f
Altera Corporation
January 2008
For more information on EPC2 configuration devices, refer to the
Configuration Devices for SRAM-Based LUT Devices Data Sheet chapter in
volume 2 of the Configuration Handbook.
7–1
Introduction
The configuration scheme is selected by driving the Stratix II or
Stratix II GX device MSEL pins either high or low as shown in Table 7–1.
The MSEL pins are powered by the VCCIO power supply of the bank they
reside in. The MSEL[3..0] pins have 9-k internal pull-down resistors
that are always active. During power-on reset (POR) and during
reconfiguration, the MSEL pins have to be at LVTTL VIL and VIH levels to
be considered a logic low and logic high.
1
To avoid any problems with detecting an incorrect configuration
scheme, hard-wire the MSEL[] pins to VCCPD and GND, without
any pull-up or pull-down resistors. Do not drive the MSEL[]
pins by a microprocessor or another device.
Table 7–1. Stratix II and Stratix II GX Configuration Schemes (Part 1 of 2)
Configuration Scheme
MSEL3
MSEL2
MSEL1
MSEL0
Fast passive parallel (FPP)
0
0
0
0
Passive parallel asynchronous (PPA)
0
0
0
1
Passive serial (PS)
0
0
1
0
Remote system upgrade FPP (1)
0
1
0
0
Remote system upgrade PPA (1)
0
1
0
1
Remote system upgrade PS (1)
0
1
1
0
Fast AS (40 MHz) (2)
1
0
0
0
Remote system upgrade fast AS (40 MHz) (2)
1
0
0
1
FPP with decompression and/or design security
feature enabled (3)
1
0
1
1
Remote system upgrade FPP with decompression
and/or design security feature enabled (1), (3)
1
1
0
0
AS (20 MHz) (2)
1
1
0
1
Remote system upgrade AS (20 MHz) (2)
1
1
1
0
(4)
(4)
(4)
(4)
JTAG-based configuration (5)
7–2
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Table 7–1. Stratix II and Stratix II GX Configuration Schemes (Part 2 of 2)
Configuration Scheme
MSEL3
MSEL2
MSEL1
MSEL0
Notes to Table 7–1:
(1)
(2)
(3)
(4)
(5)
These schemes require that you drive the RUnLU pin to specify either remote update or local update. For more
information about remote system upgrades in Stratix II devices, refer to the Remote System Upgrades With Stratix II
& Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Remote System Upgrades With
Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device Handbook.
Only the EPCS16 and EPCS64 devices support up to a 40 MHz DCLK. Other EPCS devices support up to a 20 MHz
DCLK. Refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet for more
information.
These modes are only supported when using a MAX II device or a microprocessor with flash memory for
configuration. In these modes, the host system must output a DCLK that is 4× the data rate.
Do not leave the MSEL pins floating. Connect them to VCCPD or ground. These pins support the non-JTAG
configuration scheme used in production. If only JTAG configuration is used, you should connect the MSEL pins to
ground.
JTAG-based configuration takes precedence over other configuration schemes, which means MSEL pin settings are
ignored.
Stratix II and Stratix II GX devices offer design security, decompression,
and remote system upgrade features. Design security using configuration
bitstream encryption is available in Stratix II and Stratix II GX devices,
which protects your designs. Stratix II and Stratix II GX devices can
receive a compressed configuration bit stream and decompress this data
in real-time, reducing storage requirements and configuration time. You
can make real-time system upgrades from remote locations of your
Stratix II and Stratix II GX designs with the remote system upgrade
feature.
Table 7–2 and Table 7–3 show the uncompressed configuration file sizes
for Stratix II and Stratix II GX devices, respectively.
Table 7–2. Stratix II Uncompressed .rbf Sizes
Device
Notes (1), (2)
Data Size (Bits)
Data Size (MBytes)
EP2S15
4,721,544
0.590
EP2S30
9,640,672
1.205
EP2S60
16,951,824
2.119
EP2S90
25,699,104
3.212
EP2S130
37,325,760
4.666
EP2S180
49,814,760
6.227
Notes to Table 7–2:
(1)
(2)
Altera Corporation
January 2008
These values are final.
.rbf: Raw Binary File.
7–3
Stratix II Device Handbook, Volume 2
Configuration Features
Table 7–3. Stratix II GX Uncompressed .rbf Sizes
Device
Note (1)
Data Size (Bits)
Data Size (MBytes)
EP2SGX30C
EP2SGX30D
9,640,672
1.205
EP2SGX60C
EP2SGX60D
EP2SGX60E
16,951,824
2.119
EP2SGX90E
EP2SGX90F
25,699,104
3.212
EP2SGX130G
37,325,760
4.666
Note to Table 7–3:
(1)
.rbf: Raw Binary File.
Use the data in Table 7–2 to estimate the file size before design
compilation. Different configuration file formats, such as a Hexidecimal
(.hex) or Tabular Text File (.ttf) format, will have different file sizes.
However, for any specific version of the Quartus® II software, any design
targeted for the same device will have the same uncompressed
configuration file size. If you are using compression, the file size can vary
after each compilation because the compression ratio is dependent on the
design.
This chapter explains the Stratix II and Stratix II GX device configuration
features and describes how to configure Stratix II and Stratix II GX
devices using the supported configuration schemes. This chapter
provides configuration pin descriptions and the Stratix II and
Stratix II GX device configuration file formats. In this chapter, the generic
term device(s) includes all Stratix II and Stratix II GX devices.
f
Configuration
Features
For more information on setting device configuration options or creating
configuration files, refer to Software Settings in volume 2 of the
Configuration Handbook.
Stratix II and Stratix II GX devices offer configuration data
decompression to reduce configuration file storage, design security using
data encryption to protect your designs, and remote system upgrades to
allow for remotely updating your Stratix II and Stratix II GX designs.
Table 7–4 summarizes which configuration features can be used in each
configuration scheme.
7–4
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Table 7–4. Stratix II and Stratix II GX Configuration Features
Configuration
Scheme
FPP
Configuration Method
MAX II device or a Microprocessor with
flash memory
Design Security Decompression
v (1)
v (1)
Remote System
Upgrade
v
v (2)
v
AS
Serial Configuration Device
v
v
v (3)
PS
MAX II device or a Microprocessor with
flash memory
v
v
v
Enhanced Configuration Device
v
v
v
Download cable
v
v
Enhanced Configuration Device
PPA
MAX II device or a Microprocessor with
flash memory
JTAG
MAX II device or a Microprocessor with
flash memory
v
Notes to Table 7–4:
(1)
(2)
(3)
In these modes, the host system must send a DCLK that is 4× the data rate.
The enhanced configuration device decompression feature is available, while the Stratix II and Stratix II GX
decompression feature is not available.
Only remote update mode is supported when using the AS configuration scheme. Local update mode is not
supported.
Configuration Data Decompression
Stratix II and Stratix II GX devices support configuration data
decompression, which saves configuration memory space and time. This
feature allows you to store compressed configuration data in
configuration devices or other memory and transmit this compressed bit
stream to Stratix II and Stratix II GX devices. During configuration,
Stratix II and Stratix II GX devices automatically recognize the
compressed file format and decompresses the bit stream in real time and
programs its SRAM cells.
1
Data indicates that compression typically reduces configuration
bit stream size by 35 to 55%.
Stratix II and Stratix II GX devices support decompression in the FPP
(when using a MAX II device/microprocessor + flash), AS, and PS
configuration schemes. Decompression is not supported in the PPA
configuration scheme nor in JTAG-based configuration.
Altera Corporation
January 2008
7–5
Stratix II Device Handbook, Volume 2
Configuration Features
1
When using FPP mode, the intelligent host must provide a DCLK
that is 4× the data rate. Therefore, the configuration data must be
valid for four DCLK cycles.
The decompression feature supported by Stratix II and Stratix II GX
devices is different from the decompression feature in enhanced
configuration devices (EPC16, EPC8, and EPC4 devices), although they
both use the same compression algorithm. The data decompression
feature in the enhanced configuration devices allows them to store
compressed data and decompress the bitstream before transmitting it to
the target devices. When using Stratix II and Stratix II GX devices in FPP
mode with enhanced configuration devices, the decompression feature is
available only in the enhanced configuration device, not the Stratix II or
Stratix II GX device.
In PS mode, use the Stratix II or Stratix II GX decompression feature
because sending compressed configuration data reduces configuration
time. Do not use both the Stratix II or Stratix II GX device and the
enhanced configuration device decompression features simultaneously.
The compression algorithm is not intended to be recursive and could
expand the configuration file instead of compressing it further.
When you enable compression, the Quartus II software generates
configuration files with compressed configuration data. This compressed
file reduces the storage requirements in the configuration device or flash
memory, and decreases the time needed to transmit the bitstream to the
Stratix II or Stratix II GX device. The time required by a Stratix II or
Stratix II GX device to decompress a configuration file is less than the
time needed to transmit the configuration data to the device.
There are two ways to enable compression for Stratix II and Stratix II GX
bitstreams: before design compilation (in the Compiler Settings menu)
and after design compilation (in the Convert Programming Files
window).
To enable compression in the project’s compiler settings, select Device
under the Assignments menu to bring up the Settings window. After
selecting your Stratix II or Stratix II GX device, open the Device & Pin
Options window, and in the General settings tab enable the check box for
Generate compressed bitstreams (as shown in Figure 7–1).
7–6
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Figure 7–1. Enabling Compression for Stratix II and Stratix II GX Bitstreams in
Compiler Settings
Compression can also be enabled when creating programming files from
the Convert Programming Files window.
Altera Corporation
January 2008
1.
Click Convert Programming Files (File menu).
2.
Select the programming file type (POF, SRAM HEXOUT, RBF, or
TTF).
3.
For POF output files, select a configuration device.
4.
In the Input files to convert box, select SOF Data.
5.
Select Add File and add a Stratix II or Stratix II GX device SOF(s).
7–7
Stratix II Device Handbook, Volume 2
Configuration Features
6.
Select the name of the file you added to the SOF Data area and click
Properties.
7.
Check the Compression check box.
When multiple Stratix II or Stratix II GX devices are cascaded, you can
selectively enable the compression feature for each device in the chain if
you are using a serial configuration scheme. Figure 7–2 depicts a chain of
two Stratix II or Stratix II GX devices. The first Stratix II or Stratix II GX
device has compression enabled and therefore receives a compressed bit
stream from the configuration device. The second Stratix II or
Stratix II GX device has the compression feature disabled and receives
uncompressed data.
In a multi-device FPP configuration chain all Stratix II or Stratix II GX
devices in the chain must either enable of disable the decompression
feature. You can not selectively enable the compression feature for each
device in the chain because of the DATA and DCLK relationship.
Figure 7–2. Compressed and Uncompressed Configuration Data in the Same
Configuration File
Serial Configuration Data
Serial or Enhanced
Configuration
Device
Uncompressed
Configuration
Data
Compressed
Configuration
Data
Decompression
Controller
Stratix II or
Stratix II GX
FPGA
nCE
nCEO
Stratix II or
Stratix II GX
FPGA
nCE
nCEO
N.C.
GND
You can generate programming files for this setup from the Convert
Programming Files window (File menu) in the Quartus II software.
Design Security Using Configuration Bitstream Encryption
Stratix II and Stratix II GX devices are the industry’s first devices with the
ability to decrypt a configuration bitstream using the Advanced
Encryption Standard (AES) algorithm—the most advanced encryption
algorithm available today. When using the design security feature, a
7–8
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
128-bit security key is stored in the Stratix II or Stratix II GX device. In
order to successfully configure a Stratix II or Stratix II GX device that has
the design security feature enabled, it must be configured with a
configuration file that was encrypted using the same 128-bit security key.
The security key can be stored in non-volatile memory inside the Stratix II
or Stratix II GX device. This non-volatile memory does not require any
external devices, such as a battery back-up, for storage.
1
When using a serial configuration scheme such as passive serial
(PS) or active serial (AS), configuration time is the same whether
or not the design security feature is enabled. If the fast passive
parallel (FPP) scheme is used with the design security or
decompression feature, a 4× DCLK is required. This results in a
slower configuration time when compared to the configuration
time of an FPGA that has neither the design security, nor
decompression feature enabled. For more information about
this feature, contact Altera Applications group.
Remote System Upgrade
Stratix II and Stratix II GX devices feature remote and local update.
f
For more information about this feature, refer to the Remote System
Upgrades With Stratix II & Stratix II GX Devices chapter in volume 2 of the
Stratix II Device Handbook or the Remote System Upgrades With Stratix II &
Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device
Handbook
Power-On Reset Circuit
The POR circuit keeps the entire system in reset until the power supply
voltage levels have stabilized on power-up. Upon power-up, the device
does not release nSTATUS until VCCINT, VCCPD, and VCCIO of banks 3, 4, 7,
and 8 are above the device’s POR trip point. On power down, VCCINT is
monitored for brown-out conditions.
The passive serial (PS) mode (MSEL[3,2,1,0] = 0010) and the Fast
passive parallel (FPP) mode (MSEL[3,2,1,0] = 0000) always set
bank 3 to use the lower POR trip point consistent with 1.8- and 1.5-V
signaling, regardless of the VCCSEL setting. For all other configuration
modes, VCCSEL selects the POR trip-point level. Refer to the section
“VCCSEL Pin” on page 7–10 for more details.
In Stratix II devices, a pin-selectable option PORSEL is provided that
allows you to select between a typical POR time setting of 12 ms or
100 ms. In both cases, you can extend the POR time by using an external
component to assert the nSTATUS pin low.
Altera Corporation
January 2008
7–9
Stratix II Device Handbook, Volume 2
Configuration Features
VCCPD Pins
Stratix II and Stratix II GX devices also offer a new power supply, VCCPD,
which must be connected to 3.3-V in order to power the 3.3-V/2.5-V
buffer available on the configuration input pins and JTAG pins. VCCPD
applies to all the JTAG input pins (TCK, TMS, TDI, and TRST) and the
configuration pins when VCCSEL is connected to ground. Refer to
Table 7–5 for information on the pins affected by VCCSEL.
1
VCCPD must ramp-up from 0-V to 3.3-V within 100 ms. If VCCPD
is not ramped up within this specified time, your Stratix II or
Stratix II GX device will not configure successfully. If your
system does not allow for a VCCPD ramp-up time of 100 ms or
less, you must hold nCONFIG low until all power supplies are
stable.
VCCSEL Pin
The VCCSEL pin selects the type of input buffer used on configuration
input pins and it selects the POR trip point voltage level for VCCIO bank 3
powered by VCCIO3 pins.
1
For more information, refer to Table 7–24 on page 7–105.
The configuration input pins and the PLL_ENA pin (Table 7–5) have a
dual buffer design. These pins have a 3.3-V/2.5-V input buffer and a
1.8-V/1.5-V input buffer. The VCCSEL input pin selects which input
buffer is used during configuration. The 3.3-V/2.5-V input buffer is
powered by VCCPD, while the 1.8-V/1.5-V input buffer is powered by
VCCIO. After configuration, the dual-purpose configuration pins are
powered by the VCCIO pins of the bank in which they reside. Table 7–5
shows the pins affected by VCCSEL.
7–10
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Table 7–5. Pins Affected by the Voltage Level at VCCSEL
VCCSEL = LOW (connected to GND) VCCSEL = HIGH (connected to VCCPD)
Pin
nSTATUS (when used as an
input)
nCONFIG
CONF_DONE (when used as an
input)
DATA[7..0]
nCE
DCLK (when used as an input)
CS
nWS
3.3/2.5-V input buffer is selected.
Input buffer is powered by VC C P D .
1.8/1.5-V input buffer is selected.
Input buffer is powered by VC C I O of
the I/O bank. These input buffers are
3.3 V tolerant.
nRS
nCS
CLKUSR
DEV_OE
DEV_CLRn
RUnLU
PLL_ENA
VCCSEL is sampled during power-up. Therefore, the VCCSEL setting
cannot change on the fly or during a reconfiguration. The VCCSEL input
buffer is powered by VCCINT and has an internal 5-kpull-down resistor
that is always active.
1
VCCSEL must be hardwired to VCCPD or GND.
A logic high selects the 1.8-V/1.5-V input buffer, and a logic low selects
the 3.3-V/2.5-V input buffer. VCCSEL should be set to comply with the
logic levels driven out of the configuration device or MAX II device or a
microprocessor with flash memory.
VCCSEL also sets the POR trip point for I/O bank 3 to ensure that this I/O
bank has powered up to the appropriate voltage levels before
configuration begins. For passive serial (PS) mode (MSEL[3..0] = 0010)
and for Fast passive parallel (FPP) mode (MSEL[3..0] = 0000) the POR
circuitry selects the trip point associated with 1.5-V/1.8-V signaling. For
all other configuration modes defined by MSEL[3..0] settings (other
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Configuration Features
than 00X0 (MSEL[1] = X, “don't care”), VCCSEL=GND selects the higher
I/O bank 3 POR trip point for 2.5-V/3.3-V signaling and VCCSEL=VCCPD
selects the lower I/O bank 3 POR trip point associated with 1.5-V/1.8-V
signaling.
For all configuration modes with MSEL[3..0] not equal to 00X0
(MSEL[1] = X, “don't care”), if VCCIO of configuration bank 3 is powered
by 1.8-V or 1.5-V and VCCSEL = GND, the voltage supplied to this I/O
bank(s) may never reach the POR trip point, which prevents the device
from beginning configuration.
If the VCCIO of I/O bank 3 is powered by 1.5- or 1.8-V and the
configuration signals used require 3.3- or 2.5-V signaling, you should set
VCCSEL to VCCPD to enable the 1.8-/1.5-V input buffers for configuration.
The 1.8-V/1.5-V input buffers are 3.3-V tolerant.
1
The fast passive parallel (FPP) and passive serial (PS) modes
always enable bank 3 to use the POR trip point to be consistent
with 1.8- and 1.5-V signaling, regardless of the VCCSEL setting.
Table 7–6 shows how you should set VCCSEL depending on the
configuration mode, the voltage level on VCCIO3 pins that power bank 3,
and the supported configuration input voltages.
Table 7–6. Supported VCCSEL Setting Based on Mode, VCCIO3, and Input
Configuration Voltage
VCCIO (Bank 3)
Supported Configuration
Input Voltages
All modes
3.3-V/2.5-V
3.3-V/2.5-V
GND
All modes
1.8-V/1.5-V
3.3-V/2.5-V
VCCPD (1)
All modes
1.8-V/1.5-V
1.8-V/1.5-V
VCCPD
—
3.3-V/2.5-V
1.8-V/1.5-V
Not Supported
Configuration
Mode
VCCSEL
Note to Table 7–6:
(1)
The VCCSEL pin can also be connected to GND for PS (MSEL[3..0]=0010) and
FPP (MSEL[3..0]=0000) modes.
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Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Table 7–7 shows the configuration mode support for banks 4, 7, and 8.
Table 7–7. Stratix II Configuration Mode Support for Banks 4, 7 and 8
Configuration Voltage/VC C I O Support for Banks 4, 7, and 8
Configuration Mode
3.3/3.3
1.8/1.8
3.3/1.8
VCCSEL = GND
VCCSEL = VCCPD
VCCSEL = GND
Fast passive parallel
Y
Y
Y
Passive parallel asynchronous
Y
Y
Y
Passive serial
Y
Y
Y
Remote system upgrade FPP
Y
Y
Y
Remote system upgrade PPA
Y
Y
Y
Remote system upgrade PS
Y
Y
Y
Fast AS (40 MHz)
Y
Y
Y
Remote system upgrade fast AS (40 MHz)
Y
Y
Y
FPP with decompression and/or design
security
Y
Y
Y
Remote system upgrade FPP with
decompression and/or design security
feature enabled
Y
Y
Y
AS (20 MHz)
Y
Y
Y
Remote system upgrade AS (20 MHz)
Y
Y
Y
Output Configuration Pins
You must verify that the configuration output pins for your chosen
configuration modes meet the VIH of the configuration device. Refer to
Table 7–22 on page 7–94 for a consolidated list of configuration output
pins.
The VIH of 3.3 V or 2.5 V configuration devices will not be met when the
VCCIO of the output configuration pins are 1.8 V or 1.5 V. Level shifters
will be required to meet the input high level voltage threshold VIH.
Note that AS mode is only applicable for 3.3-V configurations. If I/O
bank 3 is less than 3.3 V, level shifters are required on the output pins
(DCLK, nCSO, ASDO) from the Stratix II or Stratix II GX device back to the
EPCS device.
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January 2008
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Stratix II Device Handbook, Volume 2
Fast Passive Parallel Configuration
The key is to ensure the VCCIO voltage of bank 3 is high enough to trip
the VCCIO3 POR trip point on power-up. Also, to make sure the
configuration device meets the VIH for the configuration input pins based
on the selected input buffer.
Fast Passive
Parallel
Configuration
Fast passive parallel (FPP) configuration in Stratix II and Stratix II GX
devices is designed to meet the continuously increasing demand for
faster configuration times. Stratix II and Stratix II GX devices are
designed with the capability of receiving byte-wide configuration data
per clock cycle. Table 7–8 shows the MSEL pin settings when using the
FFP configuration scheme.
Table 7–8. Stratix II and Stratix II GX MSEL Pin Settings for FPP Configuration Schemes Notes (1), (2), and
(3)
Configuration Scheme
MSEL3 MSEL2 MSEL1 MSEL0
FPP when not using remote system upgrade or decompression and/or
design security feature
0
0
0
0
FPP when using remote system upgrade (4)
0
1
0
0
FPP with decompression and/or design security feature enabled (5)
1
0
1
1
FPP when using remote system upgrade and decompression and/or
design security feature (4), (5)
1
1
0
0
Notes to Table 7–8:
(1)
(2)
(3)
(4)
(5)
You must verify the configuration output pins for your chosen configuraiton modes meet the VIH of the
configuration device. Refer to Table 7–22 for a consolidated list of configuration output pins.
The VIH of 3.3-V or 2.5-V configuration devices will not be met when the VCCIO of the output configuration pins
is 1.8-V or 1.5-V. Level shifters will be required to meet the input high level voltage threshold VIH.
The VCCSEL signal does not control TDO or nCEO. During configuration, these pins drive out voltage levels
corresponding to the VCCIO supply voltage that powers the I/O bank containing the pin. For more information
about multi-volt support, including information about using TDO and nCEO in multi-volt systems, refer to the
Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
These schemes require that you drive the RUnLU pin to specify either remote update or local update. For more
information about remote system upgrade in Stratix II devices, refer to the Remote System Upgrades With Stratix II
& Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Remote System Upgrades With
Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device Handbook.
These modes are only supported when using a MAX II device or a microprocessor with flash memory for
configuration. In these modes, the host system must output a DCLK that is 4× the data rate.
FPP configuration of Stratix II and Stratix II GX devices can be performed
using an intelligent host, such as a MAX II device, a microprocessor, or an
Altera enhanced configuration device.
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Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
FPP Configuration Using a MAX II Device as an External Host
FPP configuration using compression and an external host provides the
fastest method to configure Stratix II and Stratix II GX devices. In the FPP
configuration scheme, a MAX II device can be used as an intelligent host
that controls the transfer of configuration data from a storage device, such
as flash memory, to the target Stratix II or Stratix II GX device.
Configuration data can be stored in RBF, HEX, or TTF format. When
using the MAX II devices as an intelligent host, a design that controls the
configuration process, such as fetching the data from flash memory and
sending it to the device, must be stored in the MAX II device.
1
If you are using the Stratix II or Stratix II GX decompression
and/or design security feature, the external host must be able to
send a DCLK frequency that is 4× the data rate.
The 4× DCLK signal does not require an additional pin and is sent on the
DCLK pin. The maximum DCLK frequency is 100 MHz, which results in a
maximum data rate of 200 Mbps. If you are not using the Stratix II or
Stratix II GX decompression or design security features, the data rate is
8× the DCLK frequency.
Figure 7–3 shows the configuration interface connections between the
Stratix II or Stratix II GX device and a MAX II device for single device
configuration.
Figure 7–3. Single Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
VCC (1)
10 kΩ
VCC (1)
10 kΩ
Stratix II Device
MSEL[3..0]
CONF_DONE
GND
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCE
nCEO
N.C.
GND
DATA[7..0]
nCONFIG
DCLK
Note to Figure 7–3:
(1)
Altera Corporation
January 2008
The pull-up resistor should be connected to a supply that provides an acceptable
input signal for the device. VCC should be high enough to meet the VIH
specification of the I/O on the device and the external host.
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Stratix II Device Handbook, Volume 2
Fast Passive Parallel Configuration
Upon power-up, the Stratix II and Stratix II GX devices go through a
Power-On Reset (POR). The POR delay is dependent on the PORSEL pin
setting; when PORSEL is driven low, the POR time is approximately
100 ms, if PORSEL is driven high, the POR time is approximately 12 ms.
During POR, the device resets, holds nSTATUS low, and tri-states all user
I/O pins. Once the device successfully exits POR, all user I/O pins
continue to be tri-stated. If nIO_pullup is driven low during power-up
and configuration, the user I/O pins and dual-purpose I/O pins have
weak pull-up resistors, which are on (after POR) before and during
configuration. If nIO_pullup is driven high, the weak pull-up resistors
are disabled.
1
f
You can hold nConfig low in order to stop device
configuration.
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the DC & Switching
Characteristics chapter in volume 1 of the Stratix II Device Handbook or the
DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Device Handbook.
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in the
reset stage. To initiate configuration, the MAX II device must drive the
nCONFIG pin from low-to-high.
1
VCCINT, VCCIO, and VCCPD of the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-k
pull-up resistor. Once nSTATUS is released, the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the MAX II device places the configuration data one byte at
a time on the DATA[7..0] pins.
1
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Stratix II Device Handbook, Volume 2
Stratix II and Stratix II GX devices receive configuration data on
the DATA[7..0] pins and the clock is received on the DCLK pin.
Data is latched into the device on the rising edge of DCLK. If you
are using the Stratix II or Stratix II GX decompression and/or
design security feature, configuration data is latched on the
rising edge of every fourth DCLK cycle. After the configuration
data is latched in, it is processed during the following three
DCLK cycles.
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Data is continuously clocked into the target device until CONF_DONE goes
high. The CONF_DONE pin goes high one byte early in parallel
configuration (FPP and PPA) modes. The last byte is required for serial
configuration (AS and PS) modes. After the device has received the next
to last byte of the configuration data successfully, it releases the
open-drain CONF_DONE pin, which is pulled high by an external 10-k
pull-up resistor. A low-to-high transition on CONF_DONE indicates
configuration is complete and initialization of the device can begin. The
CONF_DONE pin must have an external 10-k pull-up resistor in order for
the device to initialize.
In Stratix II and Stratix II GX devices, the initialization clock source is
either the internal oscillator (typically 10 MHz) or the optional CLKUSR
pin. By default, the internal oscillator is the clock source for initialization.
If the internal oscillator is used, the Stratix II or Stratix II GX device
provides itself with enough clock cycles for proper initialization.
Therefore, if the internal oscillator is the initialization clock source,
sending the entire configuration file to the device is sufficient to configure
and initialize the device. Driving DCLK to the device after configuration is
complete does not affect device operation.
You can also synchronize initialization of multiple devices or to delay
initialization with the CLKUSR option. The Enable user-supplied start-up
clock (CLKUSR) option can be turned on in the Quartus II software from
the General tab of the Device & Pin Options dialog box. Supplying a
clock on CLKUSR does not affect the configuration process. The
CONF_DONE pin goes high one byte early in parallel configuration (FPP
and PPA) modes. The last byte is required for serial configuration (AS and
PS) modes. After the CONF_DONE pin transitions high, CLKUSR is enabled
after the time specified as tCD2CU. After this time period elapses, Stratix II
and Stratix II GX devices require 299 clock cycles to initialize properly
and enter user mode. Stratix II and Stratix II GX devices support a
CLKUSR fMAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it is high because of an external 10-k
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high. The MAX II device must be
able to detect this low-to-high transition, which signals the device has
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January 2008
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Stratix II Device Handbook, Volume 2
Fast Passive Parallel Configuration
entered user mode. When initialization is complete, the device enters user
mode. In user-mode, the user I/O pins no longer have weak pull-up
resistors and function as assigned in your design.
To ensure DCLK and DATA[7..0] are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
whichever is convenient on your board. The DATA[7..0] pins are
available as user I/O pins after configuration. When you select the FPP
scheme in the Quartus II software, as a default, these I/O pins are
tri-stated in user mode. To change this default option in the Quartus II
software, select the Pins tab of the Device & Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
1
If you are using the Stratix II or Stratix II GX decompression
and/or design security feature and need to stop DCLK, it can
only be stopped three clock cycles after the last data byte was
latched into the Stratix II or Stratix II GX device.
By stopping DCLK, the configuration circuit allows enough clock cycles to
process the last byte of latched configuration data. When the clock
restarts, the MAX II device must provide data on the DATA[7..0] pins
prior to sending the first DCLK rising edge.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the MAX II device that there is an error. If the Auto-restart
configuration after error option (available in the Quartus II software
from the General tab of the Device & Pin Options (dialog box) is turned
on, the device releases nSTATUS after a reset time-out period (maximum
of 100 µs). After nSTATUS is released and pulled high by a pull-up
resistor, the MAX II device can try to reconfigure the target device
without needing to pulse nCONFIG low. If this option is turned off, the
MAX II device must generate a low-to-high transition (with a low pulse
of at least 2 µs) on nCONFIG to restart the configuration process.
The MAX II device can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the MAX II device to detect errors and determine when
programming completes. If all configuration data is sent, but the
CONF_DONE or INIT_DONE signals have not gone high, the MAX II
device will reconfigure the target device.
7–18
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
1
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, you need to
ensure CLKUSR continues toggling during the time nSTATUS is
low (maximum of 100 µs).
When the device is in user-mode, initiating a reconfiguration is done by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin should be
low for at least 2 µs. When nCONFIG is pulled low, the device also pulls
nSTATUS and CONF_DONE low and all I/O pins are tri-stated. Once
nCONFIG returns to a logic high level and nSTATUS is released by the
device, reconfiguration begins.
Figure 7–4 shows how to configure multiple devices using a MAX II
device. This circuit is similar to the FPP configuration circuit for a single
device, except the Stratix II or Stratix II GX devices are cascaded for
multi-device configuration.
Figure 7–4. Multi-Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
VCC (1) VCC (1)
10 kΩ
10 kΩ
Stratix II Device 1
Stratix II Device 2
MSEL[3..0]
MSEL[3..0]
CONF_DONE
CONF_DONE
GND
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCE
nCEO
GND
nSTATUS
nCE
nCEO
N.C.
GND
DATA[7..0]
DATA[7..0]
nCONFIG
nCONFIG
DCLK
DCLK
Note to Figure 7–4:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O standard on the device and the external
host.
In multi-device FPP configuration, the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle; therefore, the transfer of data destinations is transparent
to the MAX II device. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA[7..0], and CONF_DONE) are connected to every device in
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January 2008
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Stratix II Device Handbook, Volume 2
Fast Passive Parallel Configuration
the chain. The configuration signals may require buffering to ensure
signal integrity and prevent clock skew problems. Ensure that the DCLK
and DATA lines are buffered for every fourth device. Because all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
All nSTATUS and CONF_DONE pins are tied together and if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first device flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the
devices release their nSTATUS pins after a reset time-out period
(maximum of 100 µs). After all nSTATUS pins are released and pulled
high, the MAX II device can try to reconfigure the chain without pulsing
nCONFIG low. If this option is turned off, the MAX II device must
generate a low-to-high transition (with a low pulse of at least 2 µs) on
nCONFIG to restart the configuration process.
In a multi-device FPP configuration chain, all Stratix II or Stratix II GX
devices in the chain must either enable or disable the decompression
and/or design security feature. You can not selectively enable the
decompression and/or design security feature for each device in the
chain because of the DATA and DCLK relationship. If the chain contains
devices that do not support design security, you should use a serial
configuration scheme.
If a system has multiple devices that contain the same configuration data,
tie all device nCE inputs to GND, and leave nCEO pins floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. Configuration
signals may require buffering to ensure signal integrity and prevent clock
skew problems. Ensure that the DCLK and DATA lines are buffered for
every fourth device. Devices must be the same density and package. All
devices start and complete configuration at the same time. Figure 7–5
shows multi-device FPP configuration when both Stratix II or
Stratix II GX devices are receiving the same configuration data.
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Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Figure 7–5. Multiple-Device FPP Configuration Using an External Host When Both Devices Receive the Same
Data
Memory
ADDR DATA[7..0]
VCC (1) VCC (1)
10 kΩ
10 kΩ
Stratix II Device
Stratix II Device
MSEL[3..0]
CONF_DONE
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCE
MSEL[3..0]
CONF_DONE
GND
nCEO
GND
GND
nSTATUS
nCE
N.C. (2)
nCEO
N.C. (2)
GND
DATA[7..0]
DATA[7..0]
nCONFIG
nCONFIG
DCLK
DCLK
Notes to Figure 7–5:
(1)
(2)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O on the device and the external host.
The nCEO pins of both Stratix II or Stratix II GX devices are left unconnected when configuring the same
configuration data into multiple devices.
You can use a single configuration chain to configure Stratix II or
Stratix II GX devices with other Altera devices that support FPP
configuration, such as Stratix devices. To ensure that all devices in the
chain complete configuration at the same time or that an error flagged by
one device initiates reconfiguration in all devices, tie all of the device
CONF_DONE and nSTATUS pins together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, refer to Configuring Mixed Altera FPGA Chains in
volume 2 of the Configuration Handbook.
FPP Configuration Timing
Figure 7–6 shows the timing waveform for FPP configuration when using
a MAX II device as an external host. This waveform shows the timing
when the decompression and the design security feature are not enabled.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Fast Passive Parallel Configuration
Figure 7–6. FPP Configuration Timing Waveform
Notes (1), (2)
tCF2ST1
tCFG
nCONFIG
nSTATUS (3)
tCF2CK
tSTATUS
tCF2ST0
t
CLK
CONF_DONE (4)
tCF2CD
tST2CK
tCH tCL
(5)
DCLK
tDH
DATA[7..0]
(5)
Byte 0 Byte 1 Byte 2 Byte 3
Byte n
User Mode
tDSU
User I/O
High-Z
User Mode
INIT_DONE
tCD2UM
Notes to Figure 7–6:
(1)
(2)
(3)
(4)
(5)
(6)
This timing waveform should be used when the decompression and design security feature are not used.
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix II or Stratix II GX device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..0] are available as user I/O pins after configuration and the state of these pins depends on the
dual-purpose pin settings.
Table 7–9 defines the timing parameters for Stratix II and Stratix II GX
devices for FPP configuration when the decompression and the design
security features are not enabled.
Table 7–9. FPP Timing Parameters for Stratix II and Stratix II GX Devices (Part 1 of 2)
Symbol
Parameter
Min
Notes (1), (2)
Max
Units
800
ns
tCF2CD
nCONFIG low to CONF_DONE low
tCF2ST0
nCONFIG low to nSTATUS low
tCFG
nCONFIG low pulse width
2
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
tCF2CK
nCONFIG high to first rising edge on DCLK
100
µs
tST2CK
nSTATUS high to first rising edge of DCLK
2
µs
7–22
Stratix II Device Handbook, Volume 2
800
ns
µs
100 (3)
µs
100 (3)
µs
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Table 7–9. FPP Timing Parameters for Stratix II and Stratix II GX Devices (Part 2 of 2)
Symbol
Max
Notes (1), (2)
Parameter
Min
Units
tDSU
Data setup time before rising edge on DCLK
5
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCH
DCLK high time
4
ns
tCL
DCLK low time
4
ns
tCLK
DCLK period
10
ns
fMAX
DCLK frequency
tR
Input rise time
40
ns
tF
Input fall time
40
ns
tCD2UM
CONF_DONE high to user mode (4)
100
µs
tC D 2 C U
CONF_DONE high to CLKUSR enabled
tC D 2 U M C CONF_DONE high to user mode with
CLKUSR option on
100
20
MHz
4  maximum
DCLK period
tC D 2 C U  (299 
CLKUSR period)
Notes to Table 7–9:
(1)
(2)
(3)
(4)
This information is preliminary.
These timing parameters should be used when the decompression and design security feature are not used.
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device.
Altera Corporation
January 2008
7–23
Stratix II Device Handbook, Volume 2
Fast Passive Parallel Configuration
Figure 7–7 shows the timing waveform for FPP configuration when using
a MAX II device as an external host. This waveform shows the timing
when the decompression and/or the design security feature are enabled.
Figure 7–7. FPP Configuration Timing Waveform With Decompression or Design Security Feature
Enabled
Notes (1), (2)
tCF2ST1
tCFG
tCF2CK
nCONFIG
(3) nSTATUS
tSTATUS
tCF2ST0
(4) CONF_DONE
tCF2CD
DCLK
tCL
tST2CK
tCH
1
2
3
4
1
2
3
4
(6)
1
(6)
Byte 2
(5)
4
tCLK
DATA[7..0]
Byte 0
tDSU
User I/O
tDH
Byte 1
(5)
User Mode
Byte n
tDH
High-Z
User Mode
INIT_DONE
tCD2UM
Notes to Figure 7–7:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
This timing waveform should be used when the decompression and/or design security feature are used.
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix II or Stratix II GX device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[7..0] are available as user I/O pins after configuration and the state of these pins depends on the
dual-purpose pin settings.
If needed, DCLK can be paused by holding it low. When DCLK restarts, the external host must provide data on the
DATA[7..0] pins prior to sending the first DCLK rising edge.
7–24
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Table 7–10 defines the timing parameters for Stratix II and Stratix II GX
devices for FPP configuration when the decompression and/or the
design security feature are enabled.
Table 7–10. FPP Timing Parameters for Stratix II and Stratix II GX Devices With Decompression or Design
Security Feature Enabled
Note (1)
Symbol
Parameter
Min
tCF2CD
nCONFIG low to CONF_DONE low
tCF2ST0
nCONFIG low to nSTATUS low
tCFG
nCONFIG low pulse width
2
tSTATUS
nSTATUS low pulse width
10
Max
Units
800
ns
800
ns
µs
100 (2)
µs
100 (2)
µs
tCF2ST1
nCONFIG high to nSTATUS high
tCF2CK
nCONFIG high to first rising edge on DCLK
100
µs
tST2CK
nSTATUS high to first rising edge of DCLK
2
µs
tDSU
Data setup time before rising edge on DCLK
5
ns
tDH
Data hold time after rising edge on DCLK
30
ns
tCH
DCLK high time
4
ns
tCL
DCLK low time
4
ns
tCLK
DCLK period
10
fMAX
DCLK frequency
100
MHz
tD ATA
Data rate
200
Mbps
tR
Input rise time
40
ns
tF
Input fall time
40
ns
tCD2UM
CONF_DONE high to user mode (3)
100
µs
tC D 2 C U
CONF_DONE high to CLKUSR enabled
tC D 2 U M C CONF_DONE high to user mode with
CLKUSR option on
ns
20
4  maximum
DCLK period
tC D 2 C U + (299 
CLKUSR period)
Notes to Table 7–10:
(1)
(2)
(3)
These timing parameters should be used when the decompression and design security feature are used.
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device.
f
Altera Corporation
January 2008
Device configuration options and how to create configuration files are
discussed further in the Software Settings chapter in the Configuration
Handbook.
7–25
Stratix II Device Handbook, Volume 2
Fast Passive Parallel Configuration
FPP Configuration Using a Microprocessor
In the FPP configuration scheme, a microprocessor can control the
transfer of configuration data from a storage device, such as flash
memory, to the target Stratix II or Stratix II GX device.
1
All information in “FPP Configuration Using a MAX II Device
as an External Host” on page 7–15 is also applicable when using
a microprocessor as an external host. Refer to that section for all
configuration and timing information.
FPP Configuration Using an Enhanced Configuration Device
In the FPP configuration scheme, an enhanced configuration device sends
a byte of configuration data every DCLK cycle to the Stratix II or
Stratix II GX device. Configuration data is stored in the configuration
device.
1
When configuring your Stratix II or Stratix II GX device using
FPP mode and an enhanced configuration device, the enhanced
configuration device decompression feature is available while
the Stratix II and Stratix II GX decompression and design
security features are not.
Figure 7–8 shows the configuration interface connections between a
Stratix II or Stratix II GX device and the enhanced configuration device
for single device configuration.
1
f
The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the device.
For more information on the enhanced configuration device and flash
interface pins, such as PGM[2..0], EXCLK, PORSEL, A[20..0], and
DQ[15..0], refer to the Enhanced Configuration Devices (EPC4, EPC8 &
EPC16) Data Sheet in volume 2 of the Configuration Handbook.
7–26
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Figure 7–8. Single Device FPP Configuration Using an Enhanced Configuration
Device
VCC (1)
Stratix II Device
10 kΩ
(3) (3)
nCEO
GND
10 kΩ
Enhanced
Configuration
Device
DCLK
DATA[7..0]
OE (3)
nCS (3)
nINIT_CONF (2)
DCLK
DATA[7..0]
nSTATUS
CONF_DONE
nCONFIG
MSEL[3..0]
VCC (1)
N.C.
nCE
GND
Notes to Figure 7–8:
(1)
(2)
(3)
f
The pull-up resistor should be connected to the same supply voltage as the
configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an
internal pull-up resistor that is always active. This means an external pull-up
resistor should not be used on the nINIT_CONF-nCONFIG line. The nINIT_CONF
pin does not need to be connected if its functionality is not used. If nINIT_CONF
is not used, nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal
programmable pull-up resistors. If internal pull-up resistors are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up
resistors, check the Disable nCS and OE pull-ups on configuration device option
when generating programming files.
The value of the internal pull-up resistors on the enhanced configuration
devices can be found in the Enhanced Configuration Devices (EPC4, EPC8
& EPC16) Data Sheet in volume 2 of the Configuration Handbook.
When using enhanced configuration devices, you can connect the
device’s nCONFIG pin to nINIT_CONF pin of the enhanced configuration
device, which allows the INIT_CONF JTAG instruction to initiate device
configuration. The nINIT_CONF pin does not need to be connected if its
functionality is not used. If nINIT_CONF is not used, nCONFIG must be
pulled to VCC either directly or through a resistor. An internal pull-up
resistor on the nINIT_CONF pin is always active in the enhanced
configuration devices, which means an external pull-up resistor should
not be used if nCONFIG is tied to nINIT_CONF.
Upon power-up, the Stratix II or Stratix II GX device goes through a POR.
The POR delay is dependent on the PORSEL pin setting; when PORSEL is
driven low, the POR time is approximately 100 ms, if PORSEL is driven
high, the POR time is approximately 12 ms. During POR, the device will
reset, hold nSTATUS low, and tri-state all user I/O pins. The
Altera Corporation
January 2008
7–27
Stratix II Device Handbook, Volume 2
Fast Passive Parallel Configuration
configuration device also goes through a POR delay to allow the power
supply to stabilize. The POR time for enhanced configuration devices can
be set to either 100 ms or 2 ms, depending on its PORSEL pin setting. If the
PORSEL pin is connected to GND, the POR delay is 100 ms. If the PORSEL
pin is connected to VCC, the POR delay is 2 ms. During this time, the
configuration device drives its OE pin low. This low signal delays
configuration because the OE pin is connected to the target device’s
nSTATUS pin.
1
When selecting a POR time, you need to ensure that the device
completes power-up before the enhanced configuration device
exits POR. Altera recommends that you use a 12-ms POR time
for the Stratix II or Stratix II GX device, and use a 100-ms POR
time for the enhanced configuration device.
When both devices complete POR, they release their open-drain OE or
nSTATUS pin, which is then pulled high by a pull-up resistor. Once the
device successfully exits POR, all user I/O pins continue to be tri-stated.
If nIO_pullup is driven low during power-up and configuration, the
user I/O pins and dual-purpose I/O pins will have weak pull-up
resistors, which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Stratix II Device Handbook
or the Stratix II GX Device Handbook.
When the power supplies have reached the appropriate operating
voltages, the target device senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of
three stages: reset, configuration and initialization. While nCONFIG or
nSTATUS are low, the device is in reset. The beginning of configuration
can be delayed by holding the nCONFIG or nSTATUS pin low.
1
VCCINT, VCCIO and VCCPD of the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
nSTATUS pin, which is pulled high by a pull-up resistor. Enhanced
configuration devices have an optional internal pull-up resistor on the OE
pin. This option is available in the Quartus II software from the General
tab of the Device & Pin Options dialog box. If this internal pull-up
resistor is not used, an external 10-k pull-up resistor on the
OE-nSTATUS line is required. Once nSTATUS is released, the device is
ready to receive configuration data and the configuration stage begins.
7–28
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
When nSTATUS is pulled high, the configuration device’s OE pin also
goes high and the configuration device clocks data out to the device using
the Stratix II or Stratix II GX device’s internal oscillator. The Stratix II and
Stratix II GX devices receive configuration data on the DATA[7..0] pins
and the clock is received on the DCLK pin. A byte of data is latched into
the device on each rising edge of DCLK.
After the device has received all configuration data successfully, it
releases the open-drain CONF_DONE pin which is pulled high by a pull-up
resistor. Because CONF_DONE is tied to the configuration device’s nCS pin,
the configuration device is disabled when CONF_DONE goes high.
Enhanced configuration devices have an optional internal pull-up
resistor on the nCS pin. This option is available in the Quartus II software
from the General tab of the Device & Pin Options dialog box. If this
internal pull-up resistor is not used, an external 10-k pull-up resistor on
the nCS-CONF_DONE line is required. A low to high transition on
CONF_DONE indicates configuration is complete and initialization of the
device can begin.
In Stratix II and Stratix II GX devices, the initialization clock source is
either the internal oscillator (typically 10 MHz) or the optional CLKUSR
pin. By default, the internal oscillator is the clock source for initialization.
If the internal oscillator is used, the Stratix II or Stratix II GX device
provides itself with enough clock cycles for proper initialization. You also
have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. The Enable user-supplied
start-up clock (CLKUSR) option can be turned on in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
Supplying a clock on CLKUSR will not affect the configuration process.
After all configuration data has been accepted and CONF_DONE goes high,
CLKUSR will be enabled after the time specified as tCD2CU. After this time
period elapses, Stratix II and Stratix II GX devices require 299 clock cycles
to initialize properly and enter user mode. Stratix II and Stratix II GX
devices support a CLKUSR fMAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it will be high due to an external 10-k
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. In user-mode, the user
Altera Corporation
January 2008
7–29
Stratix II Device Handbook, Volume 2
Fast Passive Parallel Configuration
I/O pins will no longer have weak pull-up resistors and will function as
assigned in your design. The enhanced configuration device will drive
DCLK low and DATA[7..0] high at the end of configuration.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. Since the nSTATUS pin is tied to OE, the
configuration device will also be reset. If the Auto-restart configuration
after error option (available in the Quartus II software from the General
tab of the Device & Pin Options dialog box) is turned on, the device will
automatically initiate reconfiguration if an error occurs. The Stratix II or
Stratix II GX device releases its nSTATUS pin after a reset time-out period
(maximum of 100 µs). When the nSTATUS pin is released and pulled high
by a pull-up resistor, the configuration device reconfigures the chain. If
this option is turned off, the external system must monitor nSTATUS for
errors and then pulse nCONFIG low for at least 2 µs to restart
configuration. The external system can pulse nCONFIG if nCONFIG is
under system control rather than tied to VCC.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONE has not gone high, it recognizes that the device
has not configured successfully. Enhanced configuration devices wait for
64 DCLK cycles after the last configuration bit was sent for CONF_DONE to
reach a high state. In this case, the configuration device pulls its OE pin
low, which in turn drives the target device’s nSTATUS pin low. If the
Auto-restart configuration after error option is set in the software, the
target device resets and then releases its nSTATUS pin after a reset
time-out period (maximum of 100 µs). When nSTATUS returns to a logic
high level, the configuration device will try to reconfigure the device.
When CONF_DONE is sensed low after configuration, the configuration
device recognizes that the target device has not configured successfully.
Therefore, your system should not pull CONF_DONE low to delay
initialization. Instead, you should use the CLKUSR option to synchronize
the initialization of multiple devices that are not in the same
configuration chain. Devices in the same configuration chain will
initialize together if their CONF_DONE pins are tied together.
1
If the optional CLKUSR pin is used and nCONFIG is pulled low
to restart configuration during device initialization, ensure
CLKUSR continues toggling during the time nSTATUS is low
(maximum of 100 µs).
When the device is in user-mode, a reconfiguration can be initiated by
pulling the nCONFIG pin low. The nCONFIG pin should be low for at least
2 µs. When nCONFIG is pulled low, the device also pulls nSTATUS and
CONF_DONE low and all I/O pins are tri-stated. Because CONF_DONE is
7–30
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
pulled low, this activates the configuration device because it sees its nCS
pin drive low. Once nCONFIG returns to a logic high level and nSTATUS
is released by the device, reconfiguration begins.
Figure 7–9 shows how to configure multiple Stratix II or Stratix II GX
devices with an enhanced configuration device. This circuit is similar to
the configuration device circuit for a single device, except the Stratix II or
Stratix II GX devices are cascaded for multi-device configuration.
Figure 7–9. Multi-Device FPP Configuration Using an Enhanced Configuration Device
VCC (1)
VCC (1)
10 kΩ
(3)
(3)
Stratix II Device 2
N.C.
nCEO
MSEL[3..0]
DATA[7..0]
DATA[7..0]
OE (3)
nCS (3)
nSTATUS
GND
CONF_DONE
CONF_DONE
nCONFIG
nCONFIG
nCE
DCLK
DCLK
DATA[7..0]
nSTATUS
GND
Enhanced
Configuration Device
Stratix II Device 1
DCLK
MSEL[3..0]
nCEO
10 kΩ
nINIT_CONF (2)
nCE
GND
Notes to Figure 7–9:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor should not be used on the nINIT_CONF-nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-up resistors on configuration device option when generating programming files.
1
Enhanced configuration devices cannot be cascaded.
When performing multi-device configuration, you must generate the
configuration device’s POF from each project’s SOF. You can combine
multiple SOFs using the Convert Programming Files window in the
Quartus II software.
f
Altera Corporation
January 2008
For more information on how to create configuration files for
multi-device configuration chains, refer to Software Settings in volume 2
of the Configuration Handbook.
7–31
Stratix II Device Handbook, Volume 2
Fast Passive Parallel Configuration
In multi-device FPP configuration, the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. All other configuration pins (nCONFIG, nSTATUS, DCLK,
DATA[7..0], and CONF_DONE) are connected to every device in the
chain. Pay special attention to the configuration signals because they may
require buffering to ensure signal integrity and prevent clock skew
problems. Ensure that the DCLK and DATA lines are buffered for every
fourth device.
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. Similarly, since all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first device flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This low
signal drives the OE pin low on the enhanced configuration device and
drives nSTATUS low on all devices, which causes them to enter a reset
state. This behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the
devices will automatically initiate reconfiguration if an error occurs. The
devices will release their nSTATUS pins after a reset time-out period
(maximum of 100 µs). When all the nSTATUS pins are released and pulled
high, the configuration device tries to reconfigure the chain. If the
Auto-restart configuration after error option is turned off, the external
system must monitor nSTATUS for errors and then pulse nCONFIG low
for at least 2 µs to restart configuration. The external system can pulse
nCONFIG if nCONFIG is under system control rather than tied to VCC.
Your system may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA[7..0], and
CONF_DONE) are connected to every device in the chain. Configuration
signals may require buffering to ensure signal integrity and prevent clock
skew problems. Ensure that the DCLK and DATA lines are buffered for
every fourth device. Devices must be the same density and package. All
devices will start and complete configuration at the same time.
Figure 7–10 shows multi-device FPP configuration when both Stratix II or
Stratix II GX devices are receiving the same configuration data.
7–32
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Figure 7–10. Multiple-Device FPP Configuration Using an Enhanced Configuration Device When Both
devices Receive the Same Data
VCC (1)
VCC (1)
10 kΩ
(3)
(3)
Stratix II Device
(4) N.C.
nCEO
DCLK
DCLK
MSEL[3..0]
DATA[7..0]
nSTATUS
GND
Enhanced
Configuration Device
Stratix II Device
DCLK
MSEL[3..0]
DATA[7..0]
CONF_DONE
CONF_DONE
nCONFIG
nCONFIG
(4) N.C.
nCE
GND
DATA[7..0]
OE (3)
nSTATUS
GND
nCEO
10 kΩ
nCS (3)
nINIT_CONF (2)
nCE
GND
Notes to Figure 7–10:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor should not be used on the nINIT_CONF-nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single enhanced configuration chain to configure multiple
Stratix II or Stratix II GX devices with other Altera devices that support
FPP configuration, such as Stratix and Stratix GX devices. To ensure that
all devices in the chain complete configuration at the same time or that an
error flagged by one device initiates reconfiguration in all devices, all of
the device CONF_DONE and nSTATUS pins must be tied together.
f
Altera Corporation
January 2008
For more information on configuring multiple Altera devices in the same
configuration chain, refer to Configuring Mixed Altera FPGA Chains in the
Configuration Handbook.
7–33
Stratix II Device Handbook, Volume 2
Active Serial Configuration (Serial Configuration Devices)
Figure 7–11 shows the timing waveform for the FPP configuration
scheme using an enhanced configuration device.
Figure 7–11. Stratix II and Stratix II GX FPP Configuration Using an Enhanced Configuration Device Timing
Waveform
nINIT_CONF or
VCC/nCONFIG
tLOE
OE/nSTATUS
nCS/CONF_DONE
tHC
tCE
tLC
DCLK
DATA[7..0]
byte
1
Driven High
byte
2
byte
n
tOE
User I/O
Tri-State
User Mode
Tri-State
INIT_DONE
tCD2UM (1)
Note to Figure 7–11:
(1)
The initialization clock can come from the Stratix II or Stratix II GX device’s internal oscillator or the CLKUSR pin.
f
For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8 & EPC16) Data Sheet in volume 2 of the Configuration
Handbook.
f
Device configuration options and how to create configuration files are
discussed further in the Software Settings section in volume 2 of the
Configuration Handbook.
Active Serial
Configuration
(Serial
Configuration
Devices)
In the AS configuration scheme, Stratix II and Stratix II GX devices are
configured using a serial configuration device. These configuration
devices are low-cost devices with non-volatile memory that feature a
simple four-pin interface and a small form factor. These features make
serial configuration devices an ideal low-cost configuration solution.
Note that AS mode is only applicable for 3.3-V configurations. If I/O
bank 3 is less than 3.3 V, level shifters are required on the output pins
(DCLK, nCSO, ASDO) from the Stratix II or Stratix II GX device back to the
EPCS device.
1
7–34
Stratix II Device Handbook, Volume 2
If VCCIO in bank 3 is set to 1.8 V, an external voltage level
translator is needed to meet the VIH of the EPCS device (3.3 V).
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
f
For more information on serial configuration devices, refer to the Serial
Configuration Devices (EPCS1, EPCS16, EPCS64, and EPCS128) Data Sheet
in volume 2 of the Configuration Handbook.
Serial configuration devices provide a serial interface to access
configuration data. During device configuration, Stratix II and
Stratix II GX devices read configuration data via the serial interface,
decompress data if necessary, and configure their SRAM cells. This
scheme is referred to as the AS configuration scheme because the device
controls the configuration interface. This scheme contrasts with the PS
configuration scheme, where the configuration device controls the
interface.
1
The Stratix II and Stratix II GX decompression and design
security features are fully available when configuring your
Stratix II or Stratix II GX device using AS mode.
Table 7–11 shows the MSEL pin settings when using the AS configuration
scheme.
Table 7–11. Stratix II and Stratix II GX MSEL Pin Settings for AS
Configuration Schemes Note (2)
Configuration Scheme
MSEL3 MSEL2 MSEL1 MSEL0
Fast AS (40 MHz) (1)
1
0
0
0
Remote system upgrade fast AS (40 MHz)
(1)
1
0
0
1
AS (20 MHz) (1)
1
1
0
1
Remote system upgrade AS (20 MHz) (1)
1
1
1
0
Notes to Table 7–11:
(1)
(2)
Only the EPCS16 and EPCS64 devices support a DCLK up to 40 MHz clock; other
EPCS devices support a DCLK up to 20 MHz. Refer to the Serial Configuration
Devices (EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128) Data Sheet in volume 2 of
the Configuration Handbook for more information.
Note that AS mode is only applicable for 3.3-V configuration. If I/O bank 3 is less
than 3.3-V, level shifters are required on the output pins (DCLK,nCSO, and
ASDO) from the Stratix II or Stratix II GX device back to the EPCS device.
Serial configuration devices have a four-pin interface: serial clock input
(DCLK), serial data output (DATA), AS data input (ASDI), and an
active-low chip select (nCS). This four-pin interface connects to Stratix II
and Stratix II GX device pins, as shown in Figure 7–12.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Active Serial Configuration (Serial Configuration Devices)
Figure 7–12. Single Device AS Configuration
VCC (1)
VCC (1)
10 kΩ
10 kΩ
VCC (1)
10 kΩ
Serial Configuration
Device
Stratix II or Stratix II GX FPGA
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
VCC
GND
DATA
DATA0
(3) MSEL3
DCLK
DCLK
(3) MSEL2
nCS
nCSO
(3) MSEL1
ASDI
ASDO
(3) MSEL0
(2)
N.C.
GND
Notes to Figure 7–12:
(1)
(2)
(3)
Connect the pull-up resistors to a 3.3-V supply.
Stratix II and Stratix II GX devices use the ASDO to ASDI path to control the
configuration device.
If using an EPCS4 device, MSEL[3..0] should be set to 1101. Refer to Table 7–11
for more details.
Upon power-up, the Stratix II and Stratix II GX devices go through a
POR. The POR delay is dependent on the PORSEL pin setting. When
PORSEL is driven low, the POR time is approximately 100 ms. If PORSEL
is driven high, the POR time is approximately 12 ms. During POR, the
device will reset, hold nSTATUS and CONF_DONE low, and tri-state all
user I/O pins. Once the device successfully exits POR, all user I/O pins
continue to be tri-stated. If nIO_pullup is driven low during power-up
and configuration, the user I/O pins and dual-purpose I/O pins will
have weak pull-up resistors which are on (after POR) before and during
configuration. If nIO_pullup is driven high, the weak pull-up resistors
are disabled.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the DC & Switching
Characteristics chapter in volume 1 of the Stratix II Device Handbook and
the DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Device Handbook.
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
After POR, the Stratix II and Stratix II GX devices release nSTATUS,
which is pulled high by an external 10-k pull-up resistor, and enters
configuration mode.
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Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
1
To begin configuration, power the VCCINT, VCCIO, and VCCPD
voltages (for the banks where the configuration and JTAG pins
reside) to the appropriate voltage levels.
The serial clock (DCLK) generated by the Stratix II and Stratix II GX
devices controls the entire configuration cycle and provides the timing for
the serial interface. Stratix II and Stratix II GX devices use an internal
oscillator to generate DCLK. Using the MSEL[] pins, you can select to use
either a 40- or 20-MHz oscillator.
1
Only the EPCS16 and EPCS64 devices support a DCLK up to
40-MHz clock; other EPCS devices support a DCLK up to
20-MHz. Refer to the Serial Configuration Devices Data Sheet for
more information. The EPCS4 device only supports the smallest
Stratix II (EP2S15) device, which is when the SOF compression
is enabled. Because of its insufficient memory capacity, the
EPCS1 device does not support any Stratix II devices.
Table 7–12 shows the active serial DCLK output frequencies.
Table 7–12. Active Serial DCLK Output Frequency
Oscillator
Minimum
Typical
Maximum
Units
40 MHz (1)
20
26
40
MHz
20 MHz
10
13
20
MHz
Note to Table 7–12:
(1)
Only the EPCS16 and EPCS64 devices support a DCLK up to 40-MHz clock; other
EPCS devices support a DCLK up to 20-MHz. Refer to the Serial Configuration
Devices (EPCS1, EPCS4, EPCS16, EPCS16, and EPCS128) Data Sheet chapter in
volume 2 of the Configuration Handbook for more information.
In both AS and fast AS configuration schemes, the serial configuration
device latches input and control signals on the rising edge of DCLK and
drives out configuration data on the falling edge. Stratix II and
Stratix II GX devices drive out control signals on the falling edge of DCLK
and latch configuration data on the falling edge of DCLK.
In configuration mode, Stratix II and Stratix II GX devices enable the
serial configuration device by driving the nCSO output pin low, which
connects to the chip select (nCS) pin of the configuration device. The
Stratix II and Stratix II GX devices use the serial clock (DCLK) and serial
data output (ASDO) pins to send operation commands and/or read
address signals to the serial configuration device. The configuration
device provides data on its serial data output (DATA) pin, which connects
to the DATA0 input of the Stratix II and Stratix II GX devices.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Active Serial Configuration (Serial Configuration Devices)
After all configuration bits are received by the Stratix II or Stratix II GX
device, it releases the open-drain CONF_DONE pin, which is pulled high
by an external 10-k resistor. Initialization begins only after the
CONF_DONE signal reaches a logic high level. All AS configuration pins,
DATA0, DCLK, nCSO, and ASDO, have weak internal pull-up resistors that
are always active. After configuration, these pins are set as input
tri-stated and are driven high by the weak internal pull-up resistors. The
CONF_DONE pin must have an external 10-k pull-up resistor in order for
the device to initialize.
In Stratix II and Stratix II GX devices, the initialization clock source is
either the 10-MHz (typical) internal oscillator (separate from the active
serial internal oscillator) or the optional CLKUSR pin. By default, the
internal oscillator is the clock source for initialization. If the internal
oscillator is used, the Stratix II or Stratix II GX device provides itself with
enough clock cycles for proper initialization. You also have the flexibility
to synchronize initialization of multiple devices or to delay initialization
with the CLKUSR option. The Enable user-supplied start-up clock
(CLKUSR) option can be turned on in the Quartus II software from the
General tab of the Device & Pin Options dialog box. When you Enable
the user supplied start-up clock option, the CLKUSR pin is the
initialization clock source. Supplying a clock on CLKUSR will not affect
the configuration process. After all configuration data has been accepted
and CONF_DONE goes high, CLKUSR is enabled after 600 ns. After this
time period elapses, Stratix II and Stratix II GX devices require 299 clock
cycles to initialize properly and enter user mode. Stratix II and
Stratix II GX devices support a CLKUSR fMAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used, it will be high due to an external 10-k
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high. This low-to-high transition
signals that the device has entered user mode. When initialization is
complete, the device enters user mode. In user mode, the user I/O pins
no longer have weak pull-up resistors and function as assigned in your
design.
If an error occurs during configuration, Stratix II and Stratix II GX devices
assert the nSTATUS signal low, indicating a data frame error, and the
CONF_DONE signal stays low. If the Auto-restart configuration after error
option (available in the Quartus II software from the General tab of the
7–38
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Device & Pin Options dialog box) is turned on, the Stratix II or
Stratix II GX device resets the configuration device by pulsing nCSO,
releases nSTATUS after a reset time-out period (maximum of 100 µs), and
retries configuration. If this option is turned off, the system must monitor
nSTATUS for errors and then pulse nCONFIG low for at least 2 µs to restart
configuration.
When the Stratix II or Stratix II GX device is in user mode, you can initiate
reconfiguration by pulling the nCONFIG pin low. The nCONFIG pin
should be low for at least 2 µs. When nCONFIG is pulled low, the device
also pulls nSTATUS and CONF_DONE low and all I/O pins are tri-stated.
Once nCONFIG returns to a logic high level and nSTATUS is released by
the Stratix II or Stratix II GX device, reconfiguration begins.
You can configure multiple Stratix II or Stratix II GX devices using a
single serial configuration device. You can cascade multiple Stratix II or
Stratix II GX devices using the chip-enable (nCE) and chip-enable-out
(nCEO) pins. The first device in the chain must have its nCE pin connected
to ground. You must connect its nCEO pin to the nCE pin of the next
device in the chain. When the first device captures all of its configuration
data from the bit stream, it drives the nCEO pin low, enabling the next
device in the chain. You must leave the nCEO pin of the last device
unconnected. The nCONFIG, nSTATUS, CONF_DONE, DCLK, and DATA0
pins of each device in the chain are connected (refer to Figure 7–13).
This first Stratix II or Stratix II GX device in the chain is the configuration
master and controls configuration of the entire chain. You must connect
its MSEL pins to select the AS configuration scheme. The remaining
Stratix II or Stratix II GX devices are configuration slaves and you must
connect their MSEL pins to select the PS configuration scheme. Any other
Altera device that supports PS configuration can also be part of the chain
as a configuration slave. Figure 7–13 shows the pin connections for this
setup.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Active Serial Configuration (Serial Configuration Devices)
Figure 7–13. Multi-Device AS Configuration
VCC (1)
VCC (1)
10 kΩ
10 kΩ
VCC (1)
10 kΩ
Serial Configuration
Device
Stratix II or Stratix II GX
FPGA Master
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
DATA
DATA0
DCLK
DCLK
nCS
nCSO
ASDI
ASDO
VCC
(2) MSEL3
Stratix II or Stratix II GX
FPGA Slave
nSTATUS
CONF_DONE
nCEO
nCONFIG
nCE
DATA0
(2) MSEL2
DCLK
(2) MSEL1
(2) MSEL0
N.C.
MSEL3
VCC
MSEL2
MSEL1
MSEL0
GND
GND
Notes to Figure 7–13:
(1)
(2)
Connect the pull-up resistors to a 3.3-V supply.
If using an EPCS4 device, MSEL[3..0] should be set to 1101. Refer to Table 7–11 for more details.
As shown in Figure 7–13, the nSTATUS and CONF_DONE pins on all target
devices are connected together with external pull-up resistors. These pins
are open-drain bidirectional pins on the devices. When the first device
asserts nCEO (after receiving all of its configuration data), it releases its
CONF_DONE pin. But the subsequent devices in the chain keep this shared
CONF_DONE line low until they have received their configuration data.
When all target devices in the chain have received their configuration
data and have released CONF_DONE, the pull-up resistor drives a high
level on this line and all devices simultaneously enter initialization mode.
If an error occurs at any point during configuration, the nSTATUS line is
driven low by the failing device. If you enable the Auto-restart
configuration after error option, reconfiguration of the entire chain begins
after a reset time-out period (a maximum of 100 µs). If the Auto-restart
configuration after error option is turned off, the external system must
monitor nSTATUS for errors and then pulse nCONFIG low to restart
configuration. The external system can pulse nCONFIG if it is under
system control rather than tied to VCC.
1
7–40
Stratix II Device Handbook, Volume 2
While you can cascade Stratix II or Stratix II GX devices, serial
configuration devices cannot be cascaded or chained together.
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
If the configuration bit stream size exceeds the capacity of a serial
configuration device, you must select a larger configuration device
and/or enable the compression feature. When configuring multiple
devices, the size of the bitstream is the sum of the individual devices’
configuration bitstreams.
A system may have multiple devices that contain the same configuration
data. In active serial chains, this can be implemented by storing two
copies of the SOF in the serial configuration device. The first copy would
configure the master Stratix II or Stratix II GX device, and the second
copy would configure all remaining slave devices concurrently. All slave
devices must be the same density and package. The setup is similar to
Figure 7–13, where the master is set up in active serial mode and the slave
devices are set up in passive serial mode.
To configure four identical Stratix II or Stratix II GX devices with the
same SOF, you could set up the chain similar to the example shown in
Figure 7–14. The first device is the master device and its MSEL pins should
be set to select AS configuration. The other three slave devices are set up
for concurrent configuration and its MSEL pins should be set to select PS
configuration. The nCEO pin from the master device drives the nCE input
pins on all three slave devices, and the DATA and DCLK pins connect in
parallel to all four devices. During the first configuration cycle, the master
device reads its configuration data from the serial configuration device
while holding nCEO high. After completing its configuration cycle, the
master drives nCE low and transmits the second copy of the configuration
data to all three slave devices, configuring them simultaneously.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Active Serial Configuration (Serial Configuration Devices)
Figure 7–14. Multi-Device AS Configuration When devices Receive the Same Data
Stratix II FPGA Slave
nSTATUS
CONF_DONE
nCONFIG
nCE
VCC (1)
VCC (1)
10 kΩ
N.C.
VCC (1)
(2) MSEL3
DATA0
10 kΩ
nCEO
10 kΩ
VCC
(2) MSEL2
DCLK
(2) MSEL1
(2) MSEL0
GND
Serial Configuration
Device
Stratix II FPGA Slave
Stratix II FPGA Master
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
GND
DATA
DATA0
DCLK
DCLK
nCS
nCSO
ASDI
ASDO
VCC
(2) MSEL3
nSTATUS
CONF_DONE
nCONFIG
nCE
VCC
(2) MSEL2
DCLK
(2) MSEL1
N.C.
(2) MSEL3
DATA0
(2) MSEL2
nCEO
(2) MSEL1
(2) MSEL0
(2) MSEL0
GND
GND
Stratix II FPGA Slave
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA0
DCLK
nCEO
N.C.
(2) MSEL3
VCC
(2) MSEL2
(2) MSEL1
(2) MSEL0
GND
Notes to Figure 7–14:
(1)
(2)
Connect the pull-up resistors to a 3.3-V supply.
If using an EPCS4 device, MSEL[3..0] should be set to 1101. Refer to Table 7–11 for more details.
7–42
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Estimating Active Serial Configuration Time
Active serial configuration time is dominated by the time it takes to
transfer data from the serial configuration device to the Stratix II device.
This serial interface is clocked by the Stratix II DCLK output (generated
from an internal oscillator). As listed in Table 7–12 on page 7–37, the DCLK
minimum frequency when choosing to use the 40-MHz oscillator is
20 MHz (50 ns). Therefore, the maximum configuration time estimate for
an EP2S15 device (5 MBits of uncompressed data) is:
RBF Size (minimum DCLK period / 1 bit per DCLK cycle) = estimated
maximum configuration time
5 Mbits × (50 ns / 1 bit) = 250 ms
To estimate the typical configuration time, use the typical DCLK period as
listed in Table 7–12. With a typical DCLK period of 38.46 ns, the typical
configuration time is 192 ms. Enabling compression reduces the amount
of configuration data that is transmitted to the Stratix II or Stratix II GX
device, which also reduces configuration time. On average, compression
reduces configuration time by 50%.
Programming Serial Configuration Devices
Serial configuration devices are non-volatile, flash-memory-based
devices. You can program these devices in-system using the USB-Blaster™
or ByteBlaster™ II download cable. Alternatively, you can program them
using the Altera Programming Unit (APU), supported third-party
programmers, or a microprocessor with the SRunner software driver.
You can perform in-system programming of serial configuration devices
via the AS programming interface. During in-system programming, the
download cable disables device access to the AS interface by driving the
nCE pin high. Stratix II and Stratix II GX devices are also held in reset by
a low level on nCONFIG. After programming is complete, the download
cable releases nCE and nCONFIG, allowing the pull-down and pull-up
resistors to drive GND and VCC, respectively. Figure 7–15 shows the
download cable connections to the serial configuration device.
f
Altera Corporation
January 2008
For more information on the USB Blaster download cable, refer to the
USB-Blaster Download Cable User Guide. For more information on the
ByteBlaster II cable, refer to the ByteBlaster II Download Cable User Guide.
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Stratix II Device Handbook, Volume 2
Active Serial Configuration (Serial Configuration Devices)
Figure 7–15. In-System Programming of Serial Configuration Devices
VCC (1)
10 kΩ
VCC (1)
10 kΩ
VCC (1)
10 kΩ
Stratix II FPGA
CONF_DONE
nSTATUS
Serial
Configuration
Device
nCEO
N.C.
nCONFIG
nCE
10 kΩ
VCC
DATA
DATA0
(3) MSEL3
DCLK
DCLK
nCS
nCSO
(3) MSEL1
ASDI
ASDO
(3) MSEL0
(3) MSEL2
GND
Pin 1
VCC (2)
USB Blaster or ByteBlaser II
10-Pin Male Header
Notes to Figure 7–15:
(1)
(2)
(3)
Connect these pull-up resistors to 3.3-V supply.
Power up the ByteBlaster II cable's VCC with a 3.3-V supply.
If using an EPCS4 device, MSEL[3..0] should be set to 1101. Refer to Table 7–11
for more details.
You can program serial configuration devices with the Quartus II
software with the Altera programming hardware (APU) and the
appropriate configuration device programming adapter. The EPCS1 and
EPCS4 devices are offered in an eight-pin small outline integrated circuit
(SOIC) package.
In production environments, serial configuration devices can be
programmed using multiple methods. Altera programming hardware or
other third-party programming hardware can be used to program blank
serial configuration devices before they are mounted onto printed circuit
boards (PCBs). Alternatively, you can use an on-board microprocessor to
program the serial configuration device in-system using C-based
software drivers provided by Altera.
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Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
A serial configuration device can be programmed in-system by an
external microprocessor using SRunner. SRunner is a software driver
developed for embedded serial configuration device programming,
which can be easily customized to fit in different embedded systems.
SRunner is able to read a raw programming data (.rpd) file and write to
the serial configuration devices. The serial configuration device
programming time using SRunner is comparable to the programming
time with the Quartus II software.
f
For more information about SRunner, refer to AN 418: SRunner: An
Embedded Solution for Serial Configuration Device Programming and the
source code on the Altera web site at www.altera.com.
f
For more information on programming serial configuration devices,
refer to the Serial Configuration Devices (EPCS1, EPCS4, EPCS16, EPCS64,
and EPCS128) Data Sheet in the Configuration Handbook.
Figure 7–16 shows the timing waveform for the AS configuration scheme
using a serial configuration device.
Figure 7–16. AS Configuration Timing
tCF2ST1
nCONFIG
nSTATUS
CONF_DONE
nCSO
tCL
DCLK
tCH
tDH
ASDO
Read Address
tDSU
DATA0
bit N
bit N − 1
bit 1
bit 0
tCD2UM (1)
INIT_DONE
User I/O
User Mode
Note to Figure 7–16:
(1)
The initialization clock can come from the Stratix II or Stratix II GX device’s internal oscillator or the CLKUSR pin.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Passive Serial Configuration
Table 7–13 shows the AS timing parameters for Stratix II devices.
Table 7–13. AS Timing Parameters for Stratix II Devices
Symbol
Parameter
Condition
Minimum
tC F 2 S T 1
nCONFIG high to nSTATUS high
tD S U
Data setup time before falling edge
on DCLK
7
tD H
Data hold time after falling edge on
0
Typical
Maximum
100
DCLK
tC H
DCLK high time
10
tC L
DCLK low time
10
tC D 2 U M
CONF_DONE high to user mode
20
Passive Serial
Configuration
100
PS configuration of Stratix II and Stratix II GX devices can be performed
using an intelligent host, such as a MAX II device or microprocessor with
flash memory, an Altera configuration device, or a download cable. In the
PS scheme, an external host (MAX II device, embedded processor,
configuration device, or host PC) controls configuration. Configuration
data is clocked into the target Stratix II or Stratix II GX device via the
DATA0 pin at each rising edge of DCLK.
1
The Stratix II and Stratix II GX decompression and design
security features are fully available when configuring your
Stratix II or Stratix II GX device using PS mode.
Table 7–14 shows the MSEL pin settings when using the PS configuration
scheme.
Table 7–14. Stratix II and Stratix II GX MSEL Pin Settings for PS
Configuration Schemes
Configuration Scheme
MSEL3 MSEL2 MSEL1 MSEL0
PS
0
0
1
0
PS when using Remote System Upgrade (1)
0
1
1
0
Note to Table 7–14:
(1)
This scheme requires that you drive the RUnLU pin to specify either remote
update or local update. For more information about remote system upgrade in
Stratix II devices, refer to the Remote System Upgrades With Stratix II &
Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the
Remote System Upgrades With Stratix II & Stratix II GX Devices chapter in volume 2
of the Stratix II GX Device Handbook.
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Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
PS Configuration Using a MAX II Device as an External Host
In the PS configuration scheme, a MAX II device can be used as an
intelligent host that controls the transfer of configuration data from a
storage device, such as flash memory, to the target Stratix II or
Stratix II GX device. Configuration data can be stored in RBF, HEX, or
TTF format. Figure 7–17 shows the configuration interface connections
between a Stratix II or Stratix II GX device and a MAX II device for single
device configuration.
Figure 7–17. Single Device PS Configuration Using an External Host
Memory
ADDR
DATA0
(1) VCC
10 k Ω
VCC (1)
Stratix II Device
10 k Ω
CONF_DONE
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCEO
nCE
N.C.
MSEL3
GND
DATA0
MSEL2
nCONFIG
MSEL1
DCLK
VCC
MSEL0
GND
Note to Figure 7–17:
(1)
Connect the pull-up resistor to a supply that provides an acceptable input signal for the device. VCC should be high
enough to meet the VIH specification of the I/O on the device and the external host.
Upon power-up, Stratix II and Stratix II GX devices go through a POR.
The POR delay is dependent on the PORSEL pin setting; when PORSEL is
driven low, the POR time is approximately 100 ms, if PORSEL is driven
high, the POR time is approximately 12 ms. During POR, the device
resets, holds nSTATUS low, and tri-states all user I/O pins. Once the
device successfully exits POR, all user I/O pins continue to be tri-stated.
If nIO_pullup is driven low during power-up and configuration, the
user I/O pins and dual-purpose I/O pins will have weak pull-up
resistors which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
1
Altera Corporation
January 2008
You can hold nConfig low in order to stop device
configuration.
7–47
Stratix II Device Handbook, Volume 2
Passive Serial Configuration
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the Stratix II Device Handbook
or the Stratix II GX Device Handbook.
The configuration cycle consists of three stages: reset, configuration, and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the MAX II device must generate a low-to-high
transition on the nCONFIG pin.
1
VCCINT, VCCIO, and VCCPD of the banks where the configuration
and JTAG pins reside need to be fully powered to the
appropriate voltage levels in order to begin the configuration
process.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-k
pull-up resistor. Once nSTATUS is released, the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the MAX II device should place the configuration data one
bit at a time on the DATA0 pin. If you are using configuration data in RBF,
HEX, or TTF format, you must send the least significant bit (LSB) of each
data byte first. For example, if the RBF contains the byte sequence 02 1B
EE 01 FA, the serial bitstream you should transmit to the device is
0100-0000 1101-1000 0111-0111 1000-0000 0101-1111.
The Stratix II and Stratix II GX devices receive configuration data on the
DATA0 pin and the clock is received on the DCLK pin. Data is latched into
the device on the rising edge of DCLK. Data is continuously clocked into
the target device until CONF_DONE goes high. After the device has
received all configuration data successfully, it releases the open-drain
CONF_DONE pin, which is pulled high by an external 10-k pull-up
resistor. A low-to-high transition on CONF_DONE indicates configuration
is complete and initialization of the device can begin. The CONF_DONE
pin must have an external 10-k pull-up resistor in order for the device to
initialize.
In Stratix II and Stratix II GX devices, the initialization clock source is
either the internal oscillator (typically 10 MHz) or the optional CLKUSR
pin. By default, the internal oscillator is the clock source for initialization.
If the internal oscillator is used, the Stratix II or Stratix II GX device
provides itself with enough clock cycles for proper initialization.
Therefore, if the internal oscillator is the initialization clock source,
sending the entire configuration file to the device is sufficient to configure
and initialize the device. Driving DCLK to the device after configuration is
complete does not affect device operation.
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January 2008
Configuring Stratix II and Stratix II GX Devices
You also have the flexibility to synchronize initialization of multiple
devices or to delay initialization with the CLKUSR option. The Enable
user-supplied start-up clock (CLKUSR) option can be turned on in the
Quartus II software from the General tab of the Device & Pin Options
dialog box. Supplying a clock on CLKUSR will not affect the configuration
process. After all configuration data has been accepted and CONF_DONE
goes high, CLKUSR will be enabled after the time specified as tCD2CU. After
this time period elapses, Stratix II and Stratix II GX devices require 299
clock cycles to initialize properly and enter user mode. Stratix II and
Stratix II GX devices support a CLKUSR fMAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it will be high due to an external 10-k
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin will go low. When initialization is complete, the
INIT_DONE pin will be released and pulled high. The MAX II device
must be able to detect this low-to-high transition which signals the device
has entered user mode. When initialization is complete, the device enters
user mode. In user-mode, the user I/O pins will no longer have weak
pull-up resistors and will function as assigned in your design.
To ensure DCLK and DATA0 are not left floating at the end of
configuration, the MAX II device must drive them either high or low,
whichever is convenient on your board. The DATA[0] pin is available as
a user I/O pin after configuration. When the PS scheme is chosen in the
Quartus II software, as a default this I/O pin is tri-stated in user mode
and should be driven by the MAX II device. To change this default option
in the Quartus II software, select the Dual-Purpose Pins tab of the Device
& Pin Options dialog box.
The configuration clock (DCLK) speed must be below the specified
frequency to ensure correct configuration. No maximum DCLK period
exists, which means you can pause configuration by halting DCLK for an
indefinite amount of time.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the MAX II device that there is an error. If the Auto-restart
configuration after error option (available in the Quartus II software
from the General tab of the Device & Pin Options dialog box) is turned
on, the Stratix II or Stratix II GX device releases nSTATUS after a reset
time-out period (maximum of 100 µs). After nSTATUS is released and
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January 2008
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Stratix II Device Handbook, Volume 2
Passive Serial Configuration
pulled high by a pull-up resistor, the MAX II device can try to reconfigure
the target device without needing to pulse nCONFIG low. If this option is
turned off, the MAX II device must generate a low-to-high transition
(with a low pulse of at least 2 µs) on nCONFIG to restart the configuration
process.
The MAX II device can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. The CONF_DONE pin must be
monitored by the MAX II device to detect errors and determine when
programming completes. If all configuration data is sent, but CONF_DONE
or INIT_DONE have not gone high, the MAX II device must reconfigure
the target device.
1
If the optional CLKUSR pin is being used and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 100 µs).
When the device is in user-mode, you can initiate a reconfiguration by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin must be
low for at least 2 µs. When nCONFIG is pulled low, the device also pulls
nSTATUS and CONF_DONE low and all I/O pins are tri-stated. Once
nCONFIG returns to a logic high level and nSTATUS is released by the
device, reconfiguration begins.
Figure 7–18 shows how to configure multiple devices using a MAX II
device. This circuit is similar to the PS configuration circuit for a single
device, except Stratix II or Stratix II GX devices are cascaded for
multi-device configuration.
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January 2008
Configuring Stratix II and Stratix II GX Devices
Figure 7–18. Multi-Device PS Configuration Using an External Host
Memory
ADDR
DATA0
VCC (1)
10 k Ω
VCC (1)
10 k Ω
Stratix II or Stratix II GX
Device 1
Stratix II or Stratix II GX
Device 2
CONF_DONE
CONF_DONE
nSTATUS
External Host
(MAX II Device or
Microprocessor)
nCE
nSTATUS
nCE
nCEO
MSEL3
GND
DATA0
DATA0
VCC
MSEL2
nCONFIG
MSEL1
nCONFIG
MSEL1
DCLK
MSEL0
DCLK
MSEL0
GND
N.C.
MSEL3
VCC
MSEL2
nCEO
GND
Note to Figure 7–18:
(1)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O on the device and the external host.
In multi-device PS configuration the first device’s nCE pin is connected to
GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device's nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device's nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle. Therefore, the transfer of data destinations is transparent
to the MAX II device. All other configuration pins (nCONFIG, nSTATUS,
DCLK, DATA0, and CONF_DONE) are connected to every device in the
chain. Configuration signals can require buffering to ensure signal
integrity and prevent clock skew problems. Ensure that the DCLK and
DATA lines are buffered for every fourth device. Because all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first device flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single device detecting an error.
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January 2008
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Passive Serial Configuration
If the Auto-restart configuration after error option is turned on, the
devices release their nSTATUS pins after a reset time-out period
(maximum of 100 µs). After all nSTATUS pins are released and pulled
high, the MAX II device can try to reconfigure the chain without needing
to pulse nCONFIG low. If this option is turned off, the MAX II device must
generate a low-to-high transition (with a low pulse of at least 2 µs) on
nCONFIG to restart the configuration process.
In your system, you can have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE)
are connected to every device in the chain. Configuration signals can
require buffering to ensure signal integrity and prevent clock skew
problems. Ensure that the DCLK and DATA lines are buffered for every
fourth device. Devices must be the same density and package. All devices
will start and complete configuration at the same time. Figure 7–19 shows
multi-device PS configuration when both Stratix II or Stratix II GX
devices are receiving the same configuration data.
Figure 7–19. Multiple-Device PS Configuration When Both devices Receive the Same Data
Memory
ADDR
DATA0
VCC (1)
10 k Ω
VCC (1)
10 k Ω
Stratix II Device
Stratix II Device
CONF_DONE
CONF_DONE
nSTATUS
nCE
External Host
(MAX II Device or
Microprocessor)
nCEO
MSEL3
GND
DATA0
nSTATUS
nCE
N.C. (2)
VCC
MSEL2
nCEO
MSEL3
GND
DATA0
VCC
MSEL2
nCONFIG
MSEL1
nCONFIG
MSEL1
DCLK
MSEL0
DCLK
MSEL0
GND
N.C. (2)
GND
Notes to Figure 7–19:
(1)
(2)
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O on the device and the external host.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single configuration chain to configure Stratix II or
Stratix II GX devices with other Altera devices. To ensure that all devices
in the chain complete configuration at the same time or that an error
flagged by one device initiates reconfiguration in all devices, all of the
device CONF_DONE and nSTATUS pins must be tied together.
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January 2008
Configuring Stratix II and Stratix II GX Devices
f
For more information on configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera FPGA Chains
chapter in volume 2 of the Configuration Handbook.
PS Configuration Timing
Figure 7–20 shows the timing waveform for PS configuration when using
a MAX II device as an external host.
Figure 7–20. PS Configuration Timing Waveform
Note (1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
t
CLK
CONF_DONE (3)
tCF2CD
tST2CK
tCH tCL
(4)
DCLK
tDH
DATA
Bit 0 Bit 1 Bit 2 Bit 3
Bit n
(4)
tDSU
User I/O
High-Z
User Mode
INIT_DONE
tCD2UM
Notes to Figure 7–20:
(1)
(2)
(3)
(4)
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Stratix II or Stratix II GX device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[0] is available as a user I/O pin after configuration and the state of this pin depends on the dual-purpose pin
settings.
Table 7–15 defines the timing parameters for Stratix II and Stratix II GX
devices for PS configuration.
Table 7–15. PS Timing Parameters for Stratix II and Stratix II GX Devices (Part 1 of 2)
Symbol
tCF2CD
tCF2ST0
Parameter
Max
Units
nCONFIG low to CONF_DONE low
800
ns
nCONFIG low to nSTATUS low
800
ns
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January 2008
Min
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Passive Serial Configuration
Table 7–15. PS Timing Parameters for Stratix II and Stratix II GX Devices (Part 2 of 2)
Symbol
Parameter
Min
tCFG
nCONFIG low pulse width
2
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
tCF2CK
Max
Units
µs
100 (1)
µs
100 (1)
µs
nCONFIG high to first rising edge on DCLK
100
µs
tST2CK
nSTATUS high to first rising edge of DCLK
2
µs
tDSU
Data setup time before rising edge on DCLK
5
ns
tDH
Data hold time after rising edge on DCLK
0
ns
tCH
DCLK high time
4
ns
tCL
DCLK low time
4
ns
tCLK
DCLK period
10
fMAX
DCLK frequency
100
MHz
tR
Input rise time
40
ns
tF
Input fall time
tCD2UM
CONF_DONE high to user mode (2)
tC D 2 C U
CONF_DONE high to CLKUSR enabled
tC D 2 U M C CONF_DONE high to user mode with
CLKUSR option on
20
ns
40
ns
100
µs
4  maximum
DCLK period
tC D 2 C U + (299 
CLKUSR period)
Notes to Table 7–15:
(1)
(2)
This value is applicable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
the device.
f
Device configuration options and how to create configuration files are
discussed further in Software Settings in volume 2 of the Configuration
Handbook.
An example PS design that uses a MAX II device as the external host for
configuration will be available when devices are available.
PS Configuration Using a Microprocessor
In the PS configuration scheme, a microprocessor can control the transfer
of configuration data from a storage device, such as flash memory, to the
target Stratix II or Stratix II GX device.
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January 2008
Configuring Stratix II and Stratix II GX Devices
1
All information in the “PS Configuration Using a MAX II Device
as an External Host” section is also applicable when using a
microprocessor as an external host. Refer to that section for all
configuration and timing information.
PS Configuration Using a Configuration Device
You can use an Altera configuration device, such as an enhanced
configuration device, to configure Stratix II and Stratix II GX devices
using a serial configuration bitstream. Configuration data is stored in the
configuration device. Figure 7–21 shows the configuration interface
connections between a Stratix II or Stratix II GX device and a
configuration device.
1
f
Altera Corporation
January 2008
The figures in this chapter only show the configuration-related
pins and the configuration pin connections between the
configuration device and the device.
For more information on the enhanced configuration device and flash
interface pins (such as PGM[2..0], EXCLK, PORSEL, A[20..0], and
DQ[15..0]), refer to the Enhanced Configuration Devices (EPC4, EPC8,
EPC16, EPCS64, and EPCS128) Data Sheet chapter in volume 2 of the
Configuration Handbook.
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Passive Serial Configuration
Figure 7–21. Single Device PS Configuration Using an Enhanced Configuration Device
VCC (1)
Stratix II Device
MSEL2
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL1
nCEO
MSEL0
nCE
MSEL3
VCC
10 kΩ
(3)
VCC (1)
10 kΩ
(3)
Enhanced
Configuration
Device
DCLK
DATA
OE (3)
nCS (3)
nINIT_CONF (2)
N.C.
GND
GND
Notes to Figure 7–21:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active, meaning an external pull-up resistor should not be used on the nINIT_CONF-nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
f
The value of the internal pull-up resistors on the enhanced configuration
devices can be found in the Operating Conditions table of the Enhanced
Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet chapter in
volume 2 of the Configuration Handbook or the Configuration Devices for
SRAM-based LUT Devices Data Sheet chapter in volume 2 of the
Configuration Handbook.
When using enhanced configuration devices, nCONFIG of the device can
be connected to nINIT_CONF of the configuration device, which allows
the INIT_CONF JTAG instruction to initiate device configuration. The
nINIT_CONF pin does not need to be connected if its functionality is not
used. An internal pull-up resistor on the nINIT_CONF pin is always
active in enhanced configuration devices, which means an external
pull-up resistor should not be used if nCONFIG is tied to nINIT_CONF.
Upon power-up, the Stratix II and Stratix II GX devices go through a
POR. The POR delay is dependent on the PORSEL pin setting. When
PORSEL is driven low, the POR time is approximately 100 ms. If PORSEL
is driven high, the POR time is approximately 12 ms. During POR, the
device will reset, hold nSTATUS low, and tri-state all user I/O pins. The
configuration device also goes through a POR delay to allow the power
supply to stabilize. The POR time for EPC2 devices is 200 ms (maximum).
The POR time for enhanced configuration devices can be set to either
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January 2008
Configuring Stratix II and Stratix II GX Devices
100 ms or 2 ms, depending on its PORSEL pin setting. If the PORSEL pin
is connected to GND, the POR delay is 100 ms. If the PORSEL pin is
connected to VCC, the POR delay is 2 ms. During this time, the
configuration device drives its OE pin low. This low signal delays
configuration because the OE pin is connected to the target device’s
nSTATUS pin.
1
When selecting a POR time, you need to ensure that the device
completes power-up before the enhanced configuration device
exits POR. Altera recommends that you choose a POR time for
the Stratix II or Stratix II GX device of 12 ms, while selecting a
POR time for the enhanced configuration device of 100 ms.
When both devices complete POR, they release their open-drain OE or
nSTATUS pin, which is then pulled high by a pull-up resistor. Once the
device successfully exits POR, all user I/O pins continue to be tri-stated.
If nIO_pullup is driven low during power-up and configuration, the
user I/O pins and dual-purpose I/O pins will have weak pull-up
resistors which are on (after POR) before and during configuration. If
nIO_pullup is driven high, the weak pull-up resistors are disabled.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the DC & Switching
Characteristics chapter in volume 2 of the Stratix II Device Handbook or the
DC & Switching Characteristics chapter in volume 2 of the Stratix II GX
Device Handbook.
When the power supplies have reached the appropriate operating
voltages, the target device senses the low-to-high transition on nCONFIG
and initiates the configuration cycle. The configuration cycle consists of
three stages: reset, configuration, and initialization. While nCONFIG or
nSTATUS are low, the device is in reset. The beginning of configuration
can be delayed by holding the nCONFIG or nSTATUS pin low.
1
To begin configuration, power the VCCINT, VCCIO, and VCCPD
voltages (for the banks where the configuration and JTAG pins
reside) to the appropriate voltage levels.
When nCONFIG goes high, the device comes out of reset and releases the
nSTATUS pin, which is pulled high by a pull-up resistor. Enhanced
configuration and EPC2 devices have an optional internal pull-up resistor
on the OE pin. This option is available in the Quartus II software from the
General tab of the Device & Pin Options dialog box. If this internal
pull-up resistor is not used, an external 10-k pull-up resistor on the
OE-nSTATUS line is required. Once nSTATUS is released, the device is
ready to receive configuration data and the configuration stage begins.
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January 2008
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Passive Serial Configuration
When nSTATUS is pulled high, OE of the configuration device also goes
high and the configuration device clocks data out serially to the device
using the Stratix II or Stratix II GX device’s internal oscillator. The
Stratix II and Stratix II GX devices receive configuration data on the
DATA0 pin and the clock is received on the DCLK pin. Data is latched into
the device on the rising edge of DCLK.
After the device has received all configuration data successfully, it
releases the open-drain CONF_DONE pin, which is pulled high by a
pull-up resistor. Since CONF_DONE is tied to the configuration device’s
nCS pin, the configuration device is disabled when CONF_DONE goes
high. Enhanced configuration and EPC2 devices have an optional
internal pull-up resistor on the nCS pin. This option is available in the
Quartus II software from the General tab of the Device & Pin Options
dialog box. If this internal pull-up resistor is not used, an external 10-k
pull-up resistor on the nCS-CONF_DONE line is required. A low-to-high
transition on CONF_DONE indicates configuration is complete and
initialization of the device can begin.
In Stratix II and Stratix II GX devices, the initialization clock source is
either the internal oscillator (typically 10 MHz) or the optional CLKUSR
pin. By default, the internal oscillator is the clock source for initialization.
If you are using internal oscillator, the Stratix II or Stratix II GX device
supplies itself with enough clock cycles for proper initialization. You also
have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. You can turn on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
Supplying a clock on CLKUSR will not affect the configuration process.
After all configuration data has been accepted and CONF_DONE goes high,
CLKUSR will be enabled after the time specified as tCD2CU. After this time
period elapses, the Stratix II and Stratix II GX devices require 299 clock
cycles to initialize properly and enter user mode. Stratix II and
Stratix II GX devices support a CLKUSR fMAX of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
The Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If you are using the INIT_DONE pin, it will be high due to an external
10-k pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high. This low-to-high transition
signals that the device has entered user mode. In user-mode, the user I/O
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Configuring Stratix II and Stratix II GX Devices
pins will no longer have weak pull-up resistors and will function as
assigned in your design. Enhanced configuration devices and EPC2
devices drive DCLK low and DATA0 high at the end of configuration.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. Since the nSTATUS pin is tied to OE, the
configuration device will also be reset. If the Auto-restart configuration
after error option, available in the Quartus II software, from the General
tab of the Device & Pin Options dialog box is turned on, the device
automatically initiates reconfiguration if an error occurs. The Stratix II
and Stratix II GX devices release the nSTATUS pin after a reset time-out
period (maximum of 100 µs). When the nSTATUS pin is released and
pulled high by a pull-up resistor, the configuration device reconfigures
the chain. If this option is turned off, the external system must monitor
nSTATUS for errors and then pulse nCONFIG low for at least 2 µs to restart
configuration. The external system can pulse nCONFIG if nCONFIG is
under system control rather than tied to VCC.
In addition, if the configuration device sends all of its data and then
detects that CONF_DONE has not gone high, it recognizes that the device
has not configured successfully. Enhanced configuration devices wait for
64 DCLK cycles after the last configuration bit was sent for CONF_DONE to
reach a high state. EPC2 devices wait for 16 DCLK cycles. In this case, the
configuration device pulls its OE pin low, driving the target device’s
nSTATUS pin low. If the Auto-restart configuration after error option is
set in the software, the target device resets and then releases its nSTATUS
pin after a reset time-out period (maximum of 100 µs). When nSTATUS
returns to a logic high level, the configuration device tries to reconfigure
the device.
When CONF_DONE is sensed low after configuration, the configuration
device recognizes that the target device has not configured successfully.
Therefore, your system should not pull CONF_DONE low to delay
initialization. Instead, use the CLKUSR option to synchronize the
initialization of multiple devices that are not in the same configuration
chain. Devices in the same configuration chain will initialize together if
their CONF_DONE pins are tied together.
1
If you are using the optional CLKUSR pin and nCONFIG is pulled
low to restart configuration during device initialization, you
need to ensure that CLKUSR continues toggling during the time
nSTATUS is low (maximum of 100 µs).
When the device is in user-mode, pulling the nCONFIG pin low initiates
a reconfiguration. The nCONFIG pin should be low for at least 2 µs. When
nCONFIG is pulled low, the device also pulls nSTATUS and CONF_DONE
low and all I/O pins are tri-stated. Because CONF_DONE is pulled low, this
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activates the configuration device because it sees its nCS pin drive low.
Once nCONFIG returns to a logic high level and nSTATUS is released by
the device, reconfiguration begins.
Figure 7–22 shows how to configure multiple devices with an enhanced
configuration device. This circuit is similar to the configuration device
circuit for a single device, except Stratix II or Stratix II GX devices are
cascaded for multi-device configuration.
Figure 7–22. Multi-Device PS Configuration Using an Enhanced Configuration Device
VCC (1)
10 kΩ
Stratix II or Stratix II GX
Device 2
MSEL3
VCC
MSEL2
MSEL1
MSEL0
N.C.
nCEO
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL3
MSEL2
MSEL1
MSEL0
nCEO
nCE
10 kΩ
(3)
Enhanced
Configuration
Device
Stratix II or Stratix II GX
Device 1
VCC
(3)
VCC (1)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
DCLK
DATA
OE (3)
nCS (3)
nINIT_CONF (2)
nCE
GND
GND
GND
Notes to Figure 7–22:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active, meaning an external pull-up resistor should not be used on the nINIT_CONF-nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
1
Enhanced configuration devices cannot be cascaded.
When performing multi-device configuration, you must generate the
configuration device's POF from each project’s SOF. You can combine
multiple SOFs using the Convert Programming Files window in the
Quartus II software.
f
For more information on how to create configuration files for
multi-device configuration chains, refer to the Software Settings chapter
of the Configuration Handbook.
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January 2008
Configuring Stratix II and Stratix II GX Devices
In multi-device PS configuration, the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, prompting the second device to begin
configuration. All other configuration pins (nCONFIG, nSTATUS, DCLK,
DATA0, and CONF_DONE) are connected to every device in the chain.
Configuration signals can require buffering to ensure signal integrity and
prevent clock skew problems. Ensure that the DCLK and DATA lines are
buffered for every fourth device.
When configuring multiple devices, configuration does not begin until all
devices release their OE or nSTATUS pins. Similarly, since all device
CONF_DONE pins are tied together, all devices initialize and enter user
mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first device flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This low
signal drives the OE pin low on the enhanced configuration device and
drives nSTATUS low on all devices, causing them to enter a reset state.
This behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the
devices will automatically initiate reconfiguration if an error occurs. The
devices will release their nSTATUS pins after a reset time-out period
(maximum of 100 µs). When all the nSTATUS pins are released and pulled
high, the configuration device tries to reconfigure the chain. If the
Auto-restart configuration after error option is turned off, the external
system must monitor nSTATUS for errors and then pulse nCONFIG low
for at least 2 µs to restart configuration. The external system can pulse
nCONFIG if nCONFIG is under system control rather than tied to VCC.
The enhanced configuration devices also support parallel configuration
of up to eight devices. The n-bit (n = 1, 2, 4, or 8) PS configuration mode
allows enhanced configuration devices to concurrently configure devices
or a chain of devices. In addition, these devices do not have to be the same
device family or density as they can be any combination of Altera devices.
An individual enhanced configuration device DATA line is available for
each targeted device. Each DATA line can also feed a daisy chain of
devices. Figure 7–23 shows how to concurrently configure multiple
devices using an enhanced configuration device.
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January 2008
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Passive Serial Configuration
Figure 7–23. Concurrent PS Configuration of Multiple Devices Using an
Enhanced Configuration Device
(1) VCC
Stratix II Device 1
N.C.
(3)
(3)
10 kΩ
Enhanced
Configuration
Device
DCLK
DATA0
DCLK
DATA0
DATA1
MSEL1
nSTATUS
CONF_DONE
nCONFIG
MSEL0
nCE
OE (3)
nCEO
MSEL3
VCC
10 kΩ
VCC (1)
MSEL2
DATA[2..6]
nCS (3)
GND
N.C.
VCC
Stratix II Device 2
nCEO
DCLK
DATA0
MSEL3
nSTATUS
MSEL2 CONF_DONE
nCONFIG
MSEL1
nCE
MSEL0
GND
nINIT_CONF (2)
DATA 7
GND
GND
Stratix II Device 8
N.C.
nCEO
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
nCE
MSEL3
VCC
MSEL2
GND
GND
Notes to Figure 7–23:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the
configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an
internal pull-up resistor that is always active, meaning an external pull-up resistor
should not be used on the nINIT_CONF-nCONFIG line. The nINIT_CONF pin does
not need to be connected if its functionality is not used. If nINIT_CONF is not used,
nCONFIG must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal
programmable pull-up resistors. If internal pull-up resistors are used, external
pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up
resistors, check the Disable nCS and OE pull-ups on configuration device option
when generating programming files.
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January 2008
Configuring Stratix II and Stratix II GX Devices
The Quartus II software only allows the selection of n-bit PS
configuration modes, where n must be 1, 2, 4, or 8. However, you can use
these modes to configure any number of devices from 1 to 8. When
configuring SRAM-based devices using n-bit PS modes, use Table 7–16 to
select the appropriate configuration mode for the fastest configuration
times.
Table 7–16. Recommended Configuration Using n-Bit PS Modes
Number of Devices (1)
Recommended Configuration Mode
1
1-bit PS
2
2-bit PS
3
4-bit PS
4
4-bit PS
5
8-bit PS
6
8-bit PS
7
8-bit PS
8
8-bit PS
Note to Table 7–16:
(1)
Assume that each DATA line is only configuring one device, not a daisy chain of
devices.
For example, if you configure three devices, you would use the 4-bit PS
mode. For the DATA0, DATA1, and DATA2 lines, the corresponding SOF
data is transmitted from the configuration device to the device. For
DATA3, you can leave the corresponding Bit3 line blank in the Quartus II
software. On the PCB, leave the DATA3 line from the enhanced
configuration device unconnected.
Alternatively, you can daisy chain two devices to one DATA line while the
other DATA lines drive one device each. For example, you could use the
2-bit PS mode to drive two devices with DATA Bit0 (two EP2S15 devices)
and the third device (EP2S30 device) with DATA Bit1. This 2-bit PS
configuration scheme requires less space in the configuration flash
memory, but can increase the total system configuration time.
A system may have multiple devices that contain the same configuration
data. To support this configuration scheme, all device nCE inputs are tied
to GND, while nCEO pins are left floating. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE) are connected to
every device in the chain. Configuration signals can require buffering to
ensure signal integrity and prevent clock skew problems. Ensure that the
DCLK and DATA lines are buffered for every fourth device. Devices must
be the same density and package. All devices will start and complete
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January 2008
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Passive Serial Configuration
configuration at the same time. Figure 7–24 shows multi-device PS
configuration when the Stratix II or Stratix II GX devices are receiving the
same configuration data.
Figure 7–24. Multiple-Device PS Configuration Using an Enhanced Configuration Device When devices
Receive the Same Data
(1) VCC
Stratix II or Stratix II GX
10 KΩ
Device 1
(4) N.C.
nCEO
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
nCE
MSEL3
VCC
MSEL2
GND
(4) N.C.
(3)
10 KΩ
Enhanced
Configuration
Device
DCLK
DATA0
OE (3)
nCS (3)
nINIT_CONF (2)
Stratix II or Stratix II GX GND
Device 2
nCEO
MSEL3
VCC
(3)
VCC (1)
MSEL2
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
MSEL0
GND
GND
Last Stratix II or Stratix II GX
Device
(4) N.C.
nCEO
MSEL1
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
MSEL0
nCE
MSEL3
VCC
MSEL2
GND
GND
Notes to Figure 7–24:
(1)
(2)
(3)
(4)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active, meaning an external pull-up resistor should not be used on the nINIT_CONF-nCONFIG line. The
nINIT_CONF pin does not need to be connected if its functionality is not used. If nINIT_CONF is not used, nCONFIG
must be pulled to VCC either directly or through a resistor.
The enhanced configuration devices’ OE and nCS pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the Disable nCS and
OE pull-ups on configuration device option when generating programming files.
The nCEO pins of all devices are left unconnected when configuring the same configuration data into multiple
devices.
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Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
You can cascade several EPC2 devices to configure multiple Stratix II or
Stratix II GX devices. The first configuration device in the chain is the
master configuration device, while the subsequent devices are the slave
devices. The master configuration device sends DCLK to the Stratix II or
Stratix II GX devices and to the slave configuration devices. The first EPC
device’s nCS pin is connected to the CONF_DONE pins of the devices,
while its nCASC pin is connected to nCS of the next configuration device
in the chain. The last device’s nCS input comes from the previous device,
while its nCASC pin is left floating. When all data from the first
configuration device is sent, it drives nCASC low, which in turn drives
nCS on the next configuration device. A configuration device requires
less than one clock cycle to activate a subsequent configuration device, so
the data stream is uninterrupted.
1
Enhanced configuration devices cannot be cascaded.
Because all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, the master configuration device stops configuration for
the entire chain and the entire chain must be reconfigured. For example,
if the master configuration device does not detect CONF_DONE going high
at the end of configuration, it resets the entire chain by pulling its OE pin
low. This low signal drives the OE pin low on the slave configuration
device(s) and drives nSTATUS low on all devices, causing them to enter a
reset state. This behavior is similar to the device detecting an error in the
configuration data.
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January 2008
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Passive Serial Configuration
Figure 7–25 shows how to configure multiple devices using cascaded
EPC2 devices.
Figure 7–25. Multi-Device PS Configuration Using Cascaded EPC2 Devices
VCC (1)
VCC (1)
VCC (1)
(3) 10 kΩ
Stratix II Device 2
MSEL3
VCC
MSEL2
MSEL1
MSEL0
GND
N.C.
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCEO
10 kΩ
MSEL3
MSEL2
MSEL1
MSEL0
nCEO
nCE
GND
10 kΩ (3)
EPC2/EPC1
Device 1
Stratix II Device 1
VCC
(2)
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
EPC2/EPC1
Device 2
DCLK
DATA
OE (3)
nCS (3)
nCASC
nINIT_CONF (2)
DCLK
DATA
nCS
OE
nINIT_CONF
nCE
GND
Notes to Figure 7–25:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active, meaning an external pull-up resistor should not be used on the
nINIT_CONF-nCONFIG line. The nINIT_CONF pin does not need to be connected if its functionality is not used.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. External 10-kpull-up resistors should be used. To turn off the internal pull-up resistors, check the
Disable nCS and OE pull-ups on configuration device option when generating programming files.
When using enhanced configuration devices or EPC2 devices, nCONFIG
of the device can be connected to nINIT_CONF of the configuration
device, allowing the INIT_CONF JTAG instruction to initiate device
configuration. The nINIT_CONF pin does not need to be connected if its
functionality is not used. An internal pull-up resistor on the nINIT_CONF
pin is always active in the enhanced configuration devices and the EPC2
devices, which means that you shouldn’t be using an external pull-up
resistor if nCONFIG is tied to nINIT_CONF. If you are using multiple
EPC2 devices to configure a Stratix II or Stratix II GX device(s), only the
first EPC2 has its nINIT_CONF pin tied to the device’s nCONFIG pin.
You can use a single configuration chain to configure Stratix II or
Stratix II GX devices with other Altera devices. To ensure that all devices
in the chain complete configuration at the same time or that an error
flagged by one device initiates reconfiguration in all devices, all of the
device CONF_DONE and nSTATUS pins must be tied together.
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January 2008
Configuring Stratix II and Stratix II GX Devices
f
For more information on configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera FPGA Chains
chapter in the Configuration Handbook.
Figure 7–26 shows the timing waveform for the PS configuration scheme
using a configuration device.
Figure 7–26. Stratix II and Stratix II GX PS Configuration Using a Configuration Device Timing Waveform
nINIT_CONF or VCC/nCONFIG
tPOR
OE/nSTATUS
nCS/CONF_DONE
DCLK
DATA
tDSU
tCL
D0
D1
tCH
tDH
tOEZX
D2
D3
Dn
tCO
User I/O
Tri-State
User Mode
Tri-State
INIT_DONE
(1)
Note to Figure 7–26:
(1)
The initialization clock can come from the Stratix II or Stratix II GX device’s internal oscillator or the CLKUSR pin.
f
For timing information, refer to the Enhanced Configuration Devices
(EPC4, EPC8 & EPC16) Data Sheet chapter in volume 2 of the
Configuration Handbook or the Configuration Devices for SRAM-Based LUT
Devices Data Sheet chapter in volume 2 of the Configuration Handbook.
f
Device configuration options and how to create configuration files are
discussed further in the Software Settings chapter in volume 2 of the
Configuration Handbook.
PS Configuration Using a Download Cable
In this section, the generic term “download cable” includes the Altera
USB-Blaster™ universal serial bus (USB) port download cable,
MasterBlaster™ serial/USB communications cable, ByteBlaster™ II
parallel port download cable, and the ByteBlaster MV parallel port
download cable.
In PS configuration with a download cable, an intelligent host (such as a
PC) transfers data from a storage device to the device via the USB Blaster,
MasterBlaster, ByteBlaster II, or ByteBlasterMV cable.
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Passive Serial Configuration
Upon power-up, the Stratix II and Stratix II GX devices go through a
POR. The POR delay is dependent on the PORSEL pin setting. When
PORSEL is driven low, the POR time is approximately 100 ms. If PORSEL
is driven high, the POR time is approximately 12 ms. During POR, the
device will reset, hold nSTATUS low, and tri-state all user I/O pins. Once
the device successfully exits POR, all user I/O pins continue to be
tri-stated. If nIO_pullup is driven low during power-up and
configuration, the user I/O pins and dual-purpose I/O pins will have
weak pull-up resistors which are on (after POR) before and during
configuration. If nIO_pullup is driven high, the weak pull-up resistors
are disabled.
f
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the DC & Switching
Characteristics chapter in volume 1 of the Stratix II Device Handbook and
the DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Device Handbook.
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration in this scheme, the download cable generates a
low-to-high transition on the nCONFIG pin.
1
To begin configuration, power the VCCINT, VCCIO, and VCCPD
voltages (for the banks where the configuration and JTAG pins
reside) to the appropriate voltage levels.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-k
pull-up resistor. Once nSTATUS is released the device is ready to receive
configuration data and the configuration stage begins. The programming
hardware or download cable then places the configuration data one bit at
a time on the device’s DATA0 pin. The configuration data is clocked into
the target device until CONF_DONE goes high. The CONF_DONE pin must
have an external 10-k pull-up resistor in order for the device to initialize.
When using a download cable, setting the Auto-restart configuration
after error option does not affect the configuration cycle because you
must manually restart configuration in the Quartus II software when an
error occurs. Additionally, the Enable user-supplied start-up clock
(CLKUSR) option has no affect on the device initialization since this
option is disabled in the SOF when programming the device using the
Quartus II programmer and download cable. Therefore, if you turn on
the CLKUSR option, you do not need to provide a clock on CLKUSR when
you are configuring the device with the Quartus II programmer and a
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January 2008
Configuring Stratix II and Stratix II GX Devices
download cable. Figure 7–27 shows PS configuration for Stratix II or
Stratix II GX devices using a USB Blaster, MasterBlaster, ByteBlaster II, or
ByteBlasterMV cable.
Figure 7–27. PS Configuration Using a USB Blaster, MasterBlaster, ByteBlaster II or ByteBlasterMV Cable
VCC (1)
VCC (1)
VCC (1)
10 kΩ
(2)
Stratix II or Stratix II GX
Device
10 kΩ
VCC (1)
MSEL3
VCC
MSEL2
10 kΩ
VCC (1)
10 kΩ
CONF_DONE
nSTATUS
MSEL1
10 kΩ
(2)
MSEL0
GND
nCE
GND
DCLK
DATA0
nCONFIG
nCEO
N.C.
Download Cable
10-Pin Male Header
(PS Mode)
Pin 1
VCC
GND
VIO (3)
Shield
GND
Notes to Figure 7–27:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II or ByteBlasterMV cable.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme
used on your board. This ensures that DATA0 and DCLK are not left floating after configuration. For example, if you
are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable User Guide for this value. In the ByteBlasterMV
cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cables, this pin is connected to nCE when it is
used for active serial programming, otherwise it is a no connect.
You can use a download cable to configure multiple Stratix II or
Stratix II GX devices by connecting each device’s nCEO pin to the
subsequent device’s nCE pin. The first device’s nCE pin is connected to
GND while its nCEO pin is connected to the nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. All other configuration pins, nCONFIG,
nSTATUS, DCLK, DATA0, and CONF_DONE are connected to every device
in the chain. Because all CONF_DONE pins are tied together, all devices in
the chain initialize and enter user mode at the same time.
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Passive Serial Configuration
In addition, because the nSTATUS pins are tied together, the entire chain
halts configuration if any device detects an error. The Auto-restart
configuration after error option does not affect the configuration cycle
because you must manually restart configuration in the Quartus II
software when an error occurs.
Figure 7–28 shows how to configure multiple Stratix II or Stratix II GX
devices with a download cable.
Figure 7–28. Multi-Device PS Configuration using a USB Blaster, MasterBlaster, ByteBlaster II or
ByteBlasterMV Cable
VCC (1)
VCC (1)
10 kΩ
VCC
Stratix II or Stratix II GX
Device 1
MSEL3
MSEL2
MSEL1
MSEL0
(2)
VCC (1)
VCC
VCC (1)
10 kΩ
(2)
Pin 1
VCC
GND
VIO (3)
nCEO
nCE
GND
10 kΩ
CONF_DONE
nSTATUS
DCLK
GND
10 kΩ
10 kΩ
Download Cable
10-Pin Male Header
(PS Mode)
VCC (1)
DATA0
nCONFIG
GND
Stratix II or Stratix II GX
Device 2
MSEL3
MSEL2
MSEL1
MSEL0
CONF_DONE
nSTATUS
DCLK
GND
nCEO
N.C.
nCE
DATA0
nCONFIG
Notes to Figure 7–28:
(1)
(2)
(3)
The pull-up resistor should be connected to the same supply voltage as the USB Blaster, MasterBlaster (VIO pin),
ByteBlaster II or ByteBlasterMV cable.
The pull-up resistors on DATA0 and DCLK are only needed if the download cable is the only configuration scheme
used on your board. This is to ensure that DATA0 and DCLK are not left floating after configuration. For example, if
you are also using a configuration device, the pull-up resistors on DATA0 and DCLK are not needed.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable User Guide for this value. In the ByteBlasterMV
cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cables, this pin is connected to nCE when it is
used for active serial programming, otherwise it is a no connect.
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January 2008
Configuring Stratix II and Stratix II GX Devices
If you are using a download cable to configure device(s) on a board that
also has configuration devices, electrically isolate the configuration
device from the target device(s) and cable. One way of isolating the
configuration device is to add logic, such as a multiplexer, that can select
between the configuration device and the cable. The multiplexer chip
allows bidirectional transfers on the nSTATUS and CONF_DONE signals.
Another option is to add switches to the five common signals (nCONFIG,
nSTATUS, DCLK, DATA0, and CONF_DONE) between the cable and the
configuration device. The last option is to remove the configuration
device from the board when configuring the device with the cable.
Figure 7–29 shows a combination of a configuration device and a
download cable to configure an device.
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January 2008
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Passive Serial Configuration
Figure 7–29. PS Configuration with a Download Cable and Configuration Device Circuit
VCC (1)
10 kΩ
VCC (1)
10 kΩ
VCC
Stratix II or Stratix II GX
Device
(4)
MSEL3
MSEL2
MSEL1
MSEL0
Download Cable
10-Pin Male Header
(PS Mode)
VCC (1)
(5)
10 kΩ
Pin 1
CONF_DONE
nSTATUS
DCLK
VCC
GND
VIO (2)
GND
nCE
GND
(5)
DATA0
nCONFIG
nCEO
N.C.
(3)
(3)
(3)
GND
Configuration
Device
(3)
DCLK
DATA
OE (5)
nCS (5)
(3)
nINIT_CONF (4)
Notes to Figure 7–29:
(1)
(2)
(3)
(4)
(5)
The pull-up resistor should be connected to the same supply voltage as the configuration device.
Pin 6 of the header is a VIO reference voltage for the MasterBlaster output driver. VIO should match the device’s
VCCIO. Refer to the MasterBlaster Serial/USB Communications Cable User Guide for this value. In the ByteBlasterMV
cable, this pin is a no connect. In the USB Blaster and ByteBlaster II cables, this pin is connected to nCE when it is
used for active serial programming, otherwise it is a no connect.
You should not attempt configuration with a download cable while a configuration device is connected to a Stratix II
or Stratix II GX device. Instead, you should either remove the configuration device from its socket when using the
download cable or place a switch on the five common signals between the download cable and the configuration
device.
The nINIT_CONF pin (available on enhanced configuration devices and EPC2 devices only) has an internal pull-up
resistor that is always active. This means an external pull-up resistor should not be used on the
nINIT_CONF-nCONFIG line. The nINIT_CONF pin does not need to be connected if its functionality is not used.
The enhanced configuration devices’ and EPC2 devices’ OE and nCS pins have internal programmable pull-up
resistors. If internal pull-up resistors are used, external pull-up resistors should not be used on these pins. The
internal pull-up resistors are used by default in the Quartus II software. To turn off the internal pull-up resistors,
check the Disable nCS and OE pull-up resistors on configuration device option when generating programming
files.
f
For more information on how to use the USB Blaster, MasterBlaster,
ByteBlaster II or ByteBlasterMV cables, refer to the following data sheets:
■
■
■
■
USB Blaster Download Cable User Guide
MasterBlaster Serial/USB Communications Cable User Guide
ByteBlaster II Download Cable User Guide
ByteBlasterMV Download Cable User Guide
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January 2008
Configuring Stratix II and Stratix II GX Devices
Passive Parallel
Asynchronous
Configuration
Passive parallel asynchronous (PPA) configuration uses an intelligent
host, such as a microprocessor, to transfer configuration data from a
storage device, such as flash memory, to the target Stratix II or
Stratix II GX device.
Configuration data can be stored in RBF, HEX, or TTF format. The host
system outputs byte-wide data and the accompanying strobe signals to
the device. When using PPA, pull the DCLK pin high through a 10-k pullup resistor to prevent unused configuration input pins from floating.
1
You cannot use the Stratix II or Stratix II GX decompression and
design security features if you are configuring your Stratix II or
Stratix II GX device using PPA mode.
Table 7–17 shows the MSEL pin settings when using the PS configuration
scheme.
Table 7–17. Stratix II and Stratix II GX MSEL Pin Settings for PPA
Configuration Schemes
Configuration Scheme
MSEL3
MSEL2
MSEL1
MSEL0
PPA
0
0
0
1
Remote System Upgrade PPA (1)
0
1
0
1
Note to Table 7–17:
(1)
This scheme requires that you drive the RUnLU pin to specify either remote
update or local update. For more information about remote system upgrades in
Stratix II and Stratix II GX devices, refer to the Remote System Upgrades With
Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II Device
Handbook or the Remote System Upgrades With Stratix II & Stratix II GX Devices
chapter in volume 2 of the Stratix II GX Device Handbook.
Figure 7–30 shows the configuration interface connections between the
device and a microprocessor for single device PPA configuration. The
microprocessor or an optional address decoder can control the device’s
chip select pins, nCS and CS. The address decoder allows the
microprocessor to select the Stratix II or Stratix II GX device by accessing
a particular address, which simplifies the configuration process. Hold the
nCS and CS pins active during configuration and initialization.
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January 2008
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Passive Parallel Asynchronous Configuration
Figure 7–30. Single Device PPA Configuration Using a Microprocessor
Address Decoder
ADDR
VCC (2)
Memory
10 kΩ
VCC (2)
ADDR DATA[7..0]
10 k Ω
Stratix II or Stratix II GX
Device
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCE
Microprocessor
GND
DATA[7..0]
nWS
nRS
nCONFIG
RDYnBSY
MSEL3
MSEL2
MSEL1
MSEL0
nCEO
VCC
N.C.
GND
VCC (2)
10 kΩ
DCLK
Notes to Figure 7–30:
(1)
(2)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for the device. VCC
should be high enough to meet the VIH specification of the I/O on the device and the external host.
During PPA configuration, it is only required to use either the nCS or CS
pin. Therefore, if you are using only one chip-select input, the other must
be tied to the active state. For example, nCS can be tied to ground while
CS is toggled to control configuration. The device’s nCS or CS pins can be
toggled during PPA configuration if the design meets the specifications
set for tCSSU, tWSP, and tCSH listed in Table 7–18.
Upon power-up, the Stratix II and Stratix II GX devices go through a
POR. The POR delay is dependent on the PORSEL pin setting. When
PORSEL is driven low, the POR time is approximately 100 ms. If PORSEL
is driven high, the POR time is approximately 12 ms. During POR, the
device will reset, hold nSTATUS low, and tri-state all user I/O pins. Once
the device successfully exits POR, all user I/O pins continue to be
tri-stated. If nIO_pullup is driven low during power-up and
configuration, the user I/O pins and dual-purpose I/O pins will have
weak pull-up resistors which are on (after POR) before and during
configuration. If nIO_pullup is driven high, the weak pull-up resistors
are disabled.
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January 2008
Configuring Stratix II and Stratix II GX Devices
1
f
You can hold nConfig low in order to stop device
configuration.
The value of the weak pull-up resistors on the I/O pins that are on before
and during configuration can be found in the DC & Switching
Characteristics chapter in volume 1 of the Stratix II Device Handbook and
the DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Device Handbook.
The configuration cycle consists of three stages: reset, configuration and
initialization. While nCONFIG or nSTATUS are low, the device is in reset.
To initiate configuration, the microprocessor must generate a low-to-high
transition on the nCONFIG pin.
1
To begin configuration, power the VCCINT, VCCIO, and VCCPD
voltages (for the banks where the configuration and JTAG pins
reside) to the appropriate voltage levels.
When nCONFIG goes high, the device comes out of reset and releases the
open-drain nSTATUS pin, which is then pulled high by an external 10-k
pull-up resistor. Once nSTATUS is released the device is ready to receive
configuration data and the configuration stage begins. When nSTATUS is
pulled high, the microprocessor should then assert the target device’s
nCS pin low and/or CS pin high. Next, the microprocessor places an 8-bit
configuration word (one byte) on the target device’s DATA[7..0] pins
and pulses the nWS pin low.
On the rising edge of nWS, the target device latches in a byte of
configuration data and drives its RDYnBSY signal low, which indicates it
is processing the byte of configuration data. The microprocessor can then
perform other system functions while the Stratix II or Stratix II GX device
is processing the byte of configuration data.
During the time RDYnBSY is low, the Stratix II or Stratix II GX device
internally processes the configuration data using its internal oscillator
(typically 100 MHz). When the device is ready for the next byte of
configuration data, it will drive RDYnBSY high. If the microprocessor
senses a high signal when it polls RDYnBSY, the microprocessor sends the
next byte of configuration data to the device.
Alternatively, the nRS signal can be strobed low, causing the RDYnBSY
signal to appear on DATA7. Because RDYnBSY does not need to be
monitored, this pin doesn’t need to be connected to the microprocessor.
Do not drive data onto the data bus while nRS is low because it will cause
contention on the DATA7 pin. If you are not using the nRS pin to monitor
configuration, it should be tied high.
Altera Corporation
January 2008
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Passive Parallel Asynchronous Configuration
To simplify configuration and save an I/O port, the microprocessor can
wait for the total time of tBUSY (max) + tRDY2WS + tW2SB before sending the
next data byte. In this set-up, nRS should be tied high and RDYnBSY does
not need to be connected to the microprocessor. The tBUSY, tRDY2WS, and
tW2SB timing specifications are listed in Table 7–18 on page 7–82.
Next, the microprocessor checks nSTATUS and CONF_DONE. If nSTATUS
is not low and CONF_DONE is not high, the microprocessor sends the next
data byte. However, if nSTATUS is not low and all the configuration data
has been received, the device is ready for initialization. The CONF_DONE
pin will go high one byte early in parallel configuration (FPP and PPA)
modes. The last byte is required for serial configuration (AS and PS)
modes. A low-to-high transition on CONF_DONE indicates configuration
is complete and initialization of the device can begin. The open-drain
CONF_DONE pin is pulled high by an external 10-kpull-up resistor. The
CONF_DONE pin must have an external 10-k pull-up resistor in order for
the device to initialize.
In Stratix II and Stratix II GX devices, the initialization clock source is
either the internal oscillator (typically 10 MHz) or the optional CLKUSR
pin. By default, the internal oscillator is the clock source for initialization.
If the internal oscillator is used, the Stratix II or Stratix II GX device
provides itself with enough clock cycles for proper initialization.
Therefore, if the internal oscillator is the initialization clock source,
sending the entire configuration file to the device is sufficient to configure
and initialize the device.
You also have the flexibility to synchronize initialization of multiple
devices or to delay initialization with the CLKUSR option. The Enable
user-supplied start-up clock (CLKUSR) option can be turned on in the
Quartus II software from the General tab of the Device & Pin Options
dialog box. Supplying a clock on CLKUSR does not affect the
configuration process. After CONF_DONE goes high, CLKUSR is enabled
after the time specified as tCD2CU. After this time period elapses, the
Stratix II and Stratix II GX devices require 299 clock cycles to initialize
properly and enter user mode. Stratix II devices support a CLKUSR fMAX
of 100 MHz.
An optional INIT_DONE pin is available, which signals the end of
initialization and the start of user-mode with a low-to-high transition.
This Enable INIT_DONE Output option is available in the Quartus II
software from the General tab of the Device & Pin Options dialog box.
If the INIT_DONE pin is used it is high because of an external 10-k
pull-up resistor when nCONFIG is low and during the beginning of
configuration. Once the option bit to enable INIT_DONE is programmed
into the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
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January 2008
Configuring Stratix II and Stratix II GX Devices
INIT_DONE pin is released and pulled high. The microprocessor must be
able to detect this low-to-high transition that signals the device has
entered user mode. When initialization is complete, the device enters user
mode. In user-mode, the user I/O pins no longer have weak pull-up
resistors and function as assigned in your design.
To ensure DATA[7..0] is not left floating at the end of configuration, the
microprocessor must drive them either high or low, whichever is
convenient on your board. After configuration, the nCS, CS, nRS, nWS,
RDYnBSY, and DATA[7..0] pins can be used as user I/O pins. When
choosing the PPA scheme in the Quartus II software as a default, these
I/O pins are tri-stated in user mode and should be driven by the
microprocessor. To change this default option in the Quartus II software,
select the Dual-Purpose Pins tab of the Device & Pin Options dialog box.
If an error occurs during configuration, the device drives its nSTATUS pin
low, resetting itself internally. The low signal on the nSTATUS pin also
alerts the microprocessor that there is an error. If the Auto-restart
configuration after error option-available in the Quartus II software from
the General tab of the Device & Pin Options dialog box-is turned on, the
device releases nSTATUS after a reset time-out period (maximum of
100 µs). After nSTATUS is released and pulled high by a pull-up resistor,
the microprocessor can try to reconfigure the target device without
needing to pulse nCONFIG low. If this option is turned off, the
microprocessor must generate a low-to-high transition (with a low pulse
of at least 2 µs) on nCONFIG to restart the configuration process.
The microprocessor can also monitor the CONF_DONE and INIT_DONE
pins to ensure successful configuration. To detect errors and determine
when programming completes, monitor the CONF_DONE pin with the
microprocessor. If the microprocessor sends all configuration data but
CONF_DONE or INIT_DONE has not gone high, the microprocessor must
reconfigure the target device.
1
If you are using the optional CLKUSR pin and nCONFIG is pulled
low to restart configuration during device initialization, ensure
CLKUSR continues toggling during the time nSTATUS is low
(maximum of 100 µs).
When the device is in user-mode, a reconfiguration can be initiated by
transitioning the nCONFIG pin low-to-high. The nCONFIG pin should go
low for at least 2 µs. When nCONFIG is pulled low, the device also pulls
nSTATUS and CONF_DONE low and all I/O pins are tri-stated. Once
nCONFIG returns to a logic high level and nSTATUS is released by the
device, reconfiguration begins.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Passive Parallel Asynchronous Configuration
Figure 7–31 shows how to configure multiple Stratix II or Stratix II GX
devices using a microprocessor. This circuit is similar to the PPA
configuration circuit for a single device, except the devices are cascaded
for multi-device configuration.
Figure 7–31. Multi-Device PPA Configuration Using a Microprocessor
VCC (2)
VCC (2)
10 kΩ
(2) VCC
10 kΩ
10 kΩ
Address Decoder
VCC (2)
ADDR
Memory
10 kΩ
ADDR DATA[7..0]
Stratix II Device 1
DATA[7..0]
nCS (1)
CS (1)
CONF_DONE
nSTATUS
Microprocessor
Stratix II Device 2
nCE
GND
DCLK
nCEO
nWS
nRS
nCONFIG
RDYnBSY
MSEL3
MSEL2
MSEL1
MSEL0
VCC
GND
DATA[7..0]
DCLK
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCEO
nCE
nWS
MSEL3
nRS
MSEL2
nCONFIG
MSEL1
RDYnBSY
MSEL0
N.C.
VCC
GND
Notes to Figure 7–31:
(1)
(2)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O on the device and the external host.
In multi-device PPA configuration the first device’s nCE pin is connected
to GND while its nCEO pin is connected to nCE of the next device in the
chain. The last device’s nCE input comes from the previous device, while
its nCEO pin is left floating. After the first device completes configuration
in a multi-device configuration chain, its nCEO pin drives low to activate
the second device’s nCE pin, which prompts the second device to begin
configuration. The second device in the chain begins configuration within
one clock cycle. Therefore, the transfer of data destinations is transparent
to the microprocessor.
Each device’s RDYnBSY pin can have a separate input to the
microprocessor. Alternatively, if the microprocessor is pin limited, all the
RDYnBSY pins can feed an AND gate and the output of the AND gate can
feed the microprocessor. For example, if you have two devices in a PPA
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January 2008
Configuring Stratix II and Stratix II GX Devices
configuration chain, the second device’s RDYnBSY pin will be high during
the time that the first device is being configured. When the first device has
been successfully configured, it will drive nCEO low to activate the next
device in the chain and drive its RDYnBSY pin high. Therefore, since
RDYnBSY signal is driven high before configuration and after
configuration before entering user-mode, the device being configured
will govern the output of the AND gate.
The nRS signal can be used in multi-device PPA chain because the
Stratix II and Stratix II GX devices tri-state the DATA[7..0] pins before
configuration and after configuration before entering user-mode to avoid
contention. Therefore, only the device that is currently being configured
responds to the nRS strobe by asserting DATA7.
All other configuration pins (nCONFIG, nSTATUS, DATA[7..0], nCS,
CS, nWS, nRS and CONF_DONE) are connected to every device in the chain.
It is not necessary to tie nCS and CS together for every device in the chain,
as each device’s nCS and CS input can be driven by a separate source.
Configuration signals may require buffering to ensure signal integrity
and prevent clock skew problems. Ensure that the DATA lines are buffered
for every fourth device. Because all device CONF_DONE pins are tied
together, all devices initialize and enter user mode at the same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device
detects an error, configuration stops for the entire chain and the entire
chain must be reconfigured. For example, if the first device flags an error
on nSTATUS, it resets the chain by pulling its nSTATUS pin low. This
behavior is similar to a single device detecting an error.
If the Auto-restart configuration after error option is turned on, the
devices release their nSTATUS pins after a reset time-out period
(maximum of 100 µs). After all nSTATUS pins are released and pulled
high, the microprocessor can try to reconfigure the chain without needing
to pulse nCONFIG low. If this option is turned off, the microprocessor
must generate a low-to-high transition (with a low pulse of at least 2 µs)
on nCONFIG to restart the configuration process.
In your system, you may have multiple devices that contain the same
configuration data. To support this configuration scheme, all device nCE
inputs are tied to GND, while nCEO pins are left floating. All other
configuration pins (nCONFIG, nSTATUS, DATA[7..0], nCS, CS, nWS,
nRS and CONF_DONE) are connected to every device in the chain.
Configuration signals may require buffering to ensure signal integrity
and prevent clock skew problems. Ensure that the DATA lines are buffered
for every fourth device. Devices must be the same density and package.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Passive Parallel Asynchronous Configuration
All devices start and complete configuration at the same time.
Figure 7–32 shows multi-device PPA configuration when both devices are
receiving the same configuration data.
Figure 7–32. Multiple-Device PPA Configuration Using a Microprocessor When Both devices Receive the
Same Data
VCC (2)
VCC (2)
10 kΩ
(2) VCC
10 kΩ
10 kΩ
Address Decoder
VCC (2)
ADDR
Memory
10 kΩ
ADDR DATA[7..0]
Stratix II Device
DATA[7..0]
nCS (1)
CS (1)
CONF_DONE
nSTATUS
Stratix II Device
nCE
GND
DCLK
nCEO
Microprocessor
nWS
nRS
nCONFIG
RDYnBSY
MSEL3
MSEL2
MSEL1
MSEL0
N.C. (3)
VCC
GND
GND
DATA[7..0]
DCLK
nCS (1)
CS (1)
CONF_DONE
nSTATUS
nCEO
nCE
nWS
MSEL3
nRS
MSEL2
nCONFIG
MSEL1
RDYnBSY
MSEL0
N.C. (3)
VCC
GND
Notes to Figure 7–32:
(1)
(2)
(3)
If not used, the CS pin can be connected to VCC directly. If not used, the nCS pin can be connected to GND directly.
The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in the
chain. VCC should be high enough to meet the VIH specification of the I/O on the device and the external host.
The nCEO pins of both devices are left unconnected when configuring the same configuration data into multiple
devices.
You can use a single configuration chain to configure Stratix II or
Stratix II GX devices with other Altera devices that support PPA
configuration, such as Stratix, Mercury™, APEX™ 20K, ACEX® 1K, and
FLEX® 10KE devices. To ensure that all devices in the chain complete
configuration at the same time or that an error flagged by one device
initiates reconfiguration in all devices, all of the device CONF_DONE and
nSTATUS pins must be tied together.
f
For more information on configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera FPGA Chains
chapter in volume 2 of the Configuration Handbook.
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Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
PPA Configuration Timing
Figure 7–33 shows the timing waveform for the PPA configuration
scheme using a microprocessor.
Figure 7–33. Stratix II and Stratix II GX PPA Configuration Timing Waveform Using nWS
tCFG
Note (1)
tCF2ST1
nCONFIG
nSTATUS (2)
CONF_DONE (3)
Byte 0
DATA[7..0]
Byte 1
Byte n − 1
Byte n
(5)
tCSH
(5)
tDSU
(4) CS
tCF2WS
tCSSU
tDH
(5)
(4) nCS
tWSP
(5)
nWS
tRDY2WS
(5)
RDYnBSY
tWS2B
tSTATUS
tBUSY
tCF2ST0
tCF2CD
User I/Os
tCD2UM
High-Z
High-Z
User-Mode
INIT_DONE
Notes to Figure 7–33:
(1)
(2)
(3)
(4)
(5)
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, Stratix II and Stratix II GX devices hold nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
The user can toggle nCS or CS during configuration if the design meets the specification for tCSSU, tWSP, and tCSH.
DATA[7..0], CS, nCS, nWS, nRS, and RDYnBSY are available as user I/O pins after configuration and the state of
theses pins depends on the dual-purpose pin settings.
Altera Corporation
January 2008
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Stratix II Device Handbook, Volume 2
Passive Parallel Asynchronous Configuration
Figure 7–34 shows the timing waveform for the PPA configuration
scheme when using a strobed nRS and nWS signal.
Figure 7–34. Stratix II and Stratix II GX PPA Configuration Timing Waveform Using nRS and nWS Note (1)
tCF2ST1
tCFG
nCONFIG
(2) nSTATUS
tSTATUS
tCF2SCD
(3) CONF_DONE
tCSSU
(5)
(4) nCS
tCSH
(5)
(4) CS
tDH
Byte 0
DATA[7..0]
(5)
Byte n
Byte 1
tDSU
(5)
nWS
tWSP
tRS2WS
tWS2RS
tCF2WS
nRS
(5)
tWS2RS
tRSD7
INIT_DONE
tRDY2WS
User I/O
High-Z
User-Mode
tWS2B
(5)
(6) DATA7/RDYnBSY
tCD2UM
tBUSY
Notes to Figure 7–34:
(1)
(2)
(3)
(4)
(5)
(6)
The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, Stratix II and Stratix II GX devices hold nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
The user can toggle nCS or CS during configuration if the design meets the specification for tCSSU, tWSP, and tCSH.
DATA[7..0], CS, nCS, nWS, nRS, and RDYnBSY are available as user I/O pins after configuration and the state of
theses pins depends on the dual-purpose pin settings.
DATA7 is a bidirectional pin. It is an input for configuration data input, but it is an output to show the status of
RDYnBSY.
Table 7–18 defines the timing parameters for Stratix II and Stratix II GX
devices for PPA configuration.
Table 7–18. PPA Timing Parameters for Stratix II and Stratix II GX Devices (Part 1 of 2)
Max
Units
tCF2CD
Symbol
nCONFIG low to CONF_DONE low
Parameter
800
ns
tCF2ST0
nCONFIG low to nSTATUS low
800
ns
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Min
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
Table 7–18. PPA Timing Parameters for Stratix II and Stratix II GX Devices (Part 2 of 2)
Symbol
Parameter
Min
Max
Units
tCFG
nCONFIG low pulse width
2
tSTATUS
nSTATUS low pulse width
10
tCF2ST1
nCONFIG high to nSTATUS high
tCSSU
Chip select setup time before rising edge
on nWS
10
ns
tCSH
Chip select hold time after rising edge on
0
ns
µs
100 (1)
µs
100 (1)
µs
nWS
nCONFIG high to first rising edge on nWS
100
µs
tST2WS
nSTATUS high to first rising edge on nWS
2
µs
tDSU
Data setup time before rising edge on nWS
10
ns
tDH
Data hold time after rising edge on nWS
0
ns
tWSP
nWS low pulse width
15
tWS2B
nWS rising edge to RDYnBSY low
tBUSY
RDYnBSY low pulse width
7
tCF2WS
ns
20
ns
45
ns
tRDY2WS
RDYnBSY rising edge to nWS rising edge
15
ns
tWS2RS
nWS rising edge to nRS falling edge
15
ns
tRS2WS
nRS rising edge to nWS rising edge
15
ns
tRSD7
nRS falling edge to DATA7 valid with
20
ns
RDYnBSY signal
tR
Input rise time
40
ns
tF
Input fall time
40
ns
tCD2UM
CONF_DONE high to user mode (2)
20
100
µs
tC D 2 C U
CONF_DONE high to CLKUSR enabled
40
tC D 2 U M C CONF_DONE high to user mode with
CLKUSR option on
ns
tC D 2 C U + (299 
CLKUSR period)
Notes to Table 7–18:
(1)
(2)
This value is obtainable if users do not delay configuration by extending the nCONFIG or nSTATUS low pulse
width.
The minimum and maximum numbers apply only if the internal oscillator is chosen as the clock source for starting
up the device.
f
Altera Corporation
January 2008
Device configuration options and how to create configuration files are
discussed further in the Software Settings chapter in volume 2 the
Configuration Handbook.
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Stratix II Device Handbook, Volume 2
JTAG Configuration
JTAG
Configuration
f
The JTAG has developed a specification for boundary-scan testing. This
boundary-scan test (BST) architecture offers the capability to efficiently
test components on PCBs with tight lead spacing. The BST architecture
can test pin connections without using physical test probes and capture
functional data while a device is operating normally. The JTAG circuitry
can also be used to shift configuration data into the device. The Quartus II
software automatically generates SOFs that can be used for JTAG
configuration with a download cable in the Quartus II software
programmer.
For more information on JTAG boundary-scan testing, refer to the
following documents:
■
■
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II GX Device Handbook
Jam Programming Support - JTAG Technologies
Stratix II and Stratix II GX devices are designed such that JTAG
instructions have precedence over any device configuration modes.
Therefore, JTAG configuration can take place without waiting for other
configuration modes to complete. For example, if you attempt JTAG
configuration of Stratix II or Stratix II GX devices during PS
configuration, PS configuration is terminated and JTAG configuration
begins.
1
You cannot use the Stratix II and Stratix II GX decompression or
design security features if you are configuring your Stratix II or
Stratix II GX device when using JTAG-based configuration.
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS,
and TCK, and one optional pin, TRST. The TCK pin has an internal weak
pull-down resistor, while the TDI, TMS, and TRST pins have weak
internal pull-up resistors (typically 25 k). The TDO output pin is
powered by VCCIO in I/O bank 4. All of the JTAG input pins are powered
by the 3.3-V VCCPD pin. All user I/O pins are tri-stated during JTAG
configuration. Table 7–19 explains each JTAG pin’s function.
1
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The TDO output is powered by the VCCIO power supply of I/O
bank 4.
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
f
For recommendations on how to connect a JTAG chain with multiple
voltages across the devices in the ch