NSC DM54LS191J Synchronous 4-bit up/down counters with mode control Datasheet

DM54LS190/DM74LS190, DM54LS191/DM74LS191
Synchronous 4-Bit Up/Down Counters with Mode Control
General Description
These circuits are synchronous, reversible, up/down counters. The LS191 is a 4-bit binary counter and the LS190 is a
BCD counter. Synchronous operation is provided by having
all flip-flops clocked simultaneously, so that the outputs
change simultaneously when so instructed by the steering
logic. This mode of operation eliminates the output counting
spikes normally associated with asynchronous (ripple clock)
counters.
The outputs of the four master-slave flip-flops are triggered
on a low-to-high level transition of the clock input, if the
enable input is low. A high at the enable input inhibits counting. Level changes at either the enable input or the down/
up input should be made only when the clock input is high.
The direction of the count is determined by the level of the
down/up input. When low, the counter counts up and when
high, it counts down.
These counters are fully programmable; that is, the outputs
may be preset to either level by placing a low on the load
input and entering the desired data at the data inputs. The
output will change independent of the level of the clock input. This feature allows the counters to be used as moduloN dividers by simply modifying the count length with the
preset inputs.
The clock, down/up, and load inputs are buffered to lower
the drive requirement; which significantly reduces the number of clock drivers, etc., required for long parallel words.
Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum count.
The latter output produces a high-level output pulse with a
duration approximately equal to one complete cycle of the
clock when the counter overflows or underflows. The ripple
clock output produces a low-level output pulse equal in
width to the low-level portion of the clock input when an
overflow or underflow condition exists. The counters can be
easily cascaded by feeding the ripple clock output to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. The
maximum/minimum count output can be used to accomplish look-ahead for high-speed operation.
Features
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Counts 8-4-2-1 BCD or binary
Single down/up count control line
Count enable control input
Ripple clock output for cascading
Asynchronously presettable with load control
Parallel outputs
Cascadable for n-bit applications
Average propagation delay 20 ns
Typical clock frequency 25 MHz
Typical power dissipation 100 mW
Connection Diagram
Dual-In-Line-Package
TL/F/6405-1
Order Number DM54LS190J, DM54LS191J, DM54LS190W,
DM54LS191W, DM74LS190M, DM74LS191M, DM74LS190N, or DM74LS191N
See NS Package Number
J16A, M16A, N16A or W16A
C1995 National Semiconductor Corporation
TL/F/6405
RRD-B30M105/Printed in U. S. A.
DM54LS190/DM74LS190, DM54LS191/DM74LS191
Synchronous 4-Bit Up/Down Counters with Mode Control
May 1989
Absolute Maximum Ratings (Note)
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage
7V
Input Voltage
7V
Operating Free Air Temperature Range
b 55§ C to a 125§ C
DM54LS
DM74LS
0§ C to a 70§ C
b 65§ C to a 150§ C
Storage Temperature Range
Recommended Operating Conditions
Symbol
DM54LS190, LS191
Parameter
DM74LS190, LS191
Units
Min
Nom
Max
Min
Nom
Max
4.5
5
5.5
4.75
5
5.25
VCC
Supply Voltage
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IOH
High Level Output Current
IOL
Low Level Output Current
fCLK
Clock Frequency (Note 4)
0
tW
Pulse Width
(Note 4)
Clock
25
25
Load
35
35
2
2
V
V
0.7
0.8
V
b 0.4
b 0.4
mA
4
20
0
8
mA
20
MHz
ns
tSU
Data Setup Time (Note 4)
20
20
ns
tH
Data Hold Time (Note 4)
0
0
ns
tEN
Enable Time to Clock (Note 4)
30
30
TA
Free Air Operating Temperature
b 55
125
ns
0
70
§C
Max
Units
b 1.5
V
’LS190 and ’LS191 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
VI
Parameter
Conditions
Min
Typ
(Note 1)
Input Clamp Voltage
VCC e Min, II e b 18 mA
VOH
High Level Output
Voltage
VCC e Min, IOH e Max
VIL e Max, VIH e Min
DM54
2.5
DM74
2.7
VOL
Low Level Output
Voltage
VCC e Min, IOL e Max
VIL e Max, VIH e Min
DM54
0.25
0.4
DM74
0.35
0.5
IOL e 4 mA, VCC e Min
DM74
0.25
0.4
Input Current @ Max
Input Voltage
VCC e Max
VI e 7V
Enable
0.3
Others
0.1
High Level Input
Current
VCC e Max
VI e 2.7V
Enable
60
Others
20
Low Level Input
Current
VCC e Max
VI e 0.4V
Enable
b 1.08
Others
b 0.4
Short Circuit
Output Current
VCC e Max
(Note 2)
DM54
b 20
b 100
DM74
b 20
b 100
Supply Current
VCC e Max (Note 3)
II
IIH
IIL
IOS
ICC
3.4
3.4
20
Note 1: All typicals are at VCC e 5V, TA e 25§ C.
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: ICC is measured with all inputs grounded and all outputs open.
Note 4: TA e 25§ C and VCC e 5V.
2
V
35
V
mA
mA
mA
mA
mA
’LS190 and ’LS191 Switching Characteristics
at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
RL e 2 kX
From (Input)
To (Output)
CL e 15 pF
Min
Max
CL e 50 pF
Min
Units
Max
fMAX
Maximum Clock
Frequency
tPLH
Propagation Delay Time
Low to High Level Output
Load to
Any Q
33
43
ns
tPHL
Propagation Delay Time
High to Low Level Output
Load to
Any Q
50
59
ns
tPLH
Propagation Delay Time
Low to High Level Output
Data to
Any Q
22
26
ns
tPHL
Propagation Delay Time
High to Low Level Output
Data to
Any Q
50
62
ns
tPLH
Propagation Delay Time
Low to High Level Output
Clock to
Ripple Clock
20
24
ns
tPHL
Propagation Delay Time
High to Low Level Output
Clock to
Ripple Clock
24
33
ns
tPLH
Propagation Delay Time
Low to High Level Output
Clock to
Any Q
24
29
ns
tPHL
Propagation Delay Time
High to Low Level Output
Clock to
Any Q
36
45
ns
tPLH
Propagation Delay Time
Low to High Level Output
Clock to
Max/Min
42
47
ns
tPHL
Propagation Delay Time
High to Low Level Output
Clock to
Max/Min
52
65
ns
tPLH
Propagation Delay Time
Low to High Level Output
Up/Down to
Ripple Clock
45
50
ns
tPHL
Propagation Delay Time
High to Low Level Output
Up/Down to
Ripple Clock
45
54
ns
tPLH
Propagation Delay Time
Low to High Level Output
Down/Up to
Max/Min
33
36
ns
tPHL
Propagation Delay Time
High to Low Level Output
Down/Up to
Max/Min
33
42
ns
tPLH
Propagation Delay Time
Low to High Level Output
Enable to
Ripple Clock
33
36
ns
tPHL
Propagation Delay Time
High to Low Level Output
Enable to
Ripple Clock
33
42
ns
20
3
20
MHz
Logic Diagrams
LS190 Decade Counters
Pin (16) e VCC, Pin (8) e GND
TL/F/6405 – 2
4
Logic Diagrams (Continued)
LS191 Binary Counters
TL/F/6405 – 3
5
Pin (16) e VCC, Pin (8) e GND
Timing Diagrams
LS190 Decade Counters
Typical Load, Count, and Inhibit Sequences
TL/F/6405 – 4
LS191 Binary Counters
Typical Load, Count, and Inhibit Sequences
TL/F/6405 – 5
6
Physical Dimensions inches (millimeters)
16-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54LS190J, DM54LS191J
NS Package Number J16A
16-Lead Small Outline Molded Package (M)
Order Number DM74LS190M, DM74LS191M
NS Package Number M16A
7
DM54LS190/DM74LS190, DM54LS191/DM74LS191
Synchronous 4-Bit Up/Down Counters with Mode Control
Physical Dimensions inches (millimeters) (Continued)
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS190N, DM74LS191N
NS Package Number N16E
16-Lead Ceramic Flat Package (W)
Order Number DM54LS190W or DM54LS191W
NS Package Number W16A
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