August 1999 NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface General Description: continuously reliable non-volatile solution for all markets. The NM24C65U is a 64K (65,536) bit serial interface CMOS EEPROM (Electrically Erasable Programmable Read-Only Memory). This device fully conforms to the Extended I2C™ 2-wire protocol which uses Clock (SCL) and Data I/O (SDA) pins to synchronously clock data between the "master" (for example a microprocessor) and the "slave" (the EEPROM device). In addition, the serial interface allows a minimal pin count packaging designed to simplify PC board layout requirements and offers the designer a variety of low voltage and low power options. Functions NM24C65U incorporates a hardware "Write Protect" feature, by which the upper half of the memory can be disabled against programming by connecting the WP pin to VCC. This section of memory then effectively becomes a ROM (Read-Only Memory) and can no longer be programmed as long as WP pin is connected to VCC. ■ Memory "Upper Block" Write Protect pin ■ I2C™ compatible interface ■ 65,536 bits organized as 8,192 x 8 ■ 100 KHz or 400 KHz operation ■ Extended 2.7V – 5.5V operating voltage ■ Self timed programming cycle (6ms typical) ■ "Programming complete" indicated by ACK polling Features ■ The I2C™ interface allows the smallest I/O pincount of any EEPROM interface ■ 32 byte page write mode to minimize total write time per byte ■ Low VCC programming lockout (3.8V) — "H" option (Standard VCC range) parts only Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption for a ■ Typical 200µA active current (ICCA) ■ Typical 1µA standby current (ISB) for "L" devices and 0.1µA standby current for "LZ" devices ■ Endurance: Up to 1,000,000 data changes ■ Data retention greater than 40 years Block Diagram WRITE LOCKOUT VCC WP START CYCLE H.V. GENERATION TIMING &CONTROL START STOP LOGIC SDA CONTROL LOGIC SLAVE ADDRESS REGISTER & COMPARATOR SCL XDEC LOAD A2 A1 A0 E2PROM ARRAY INC WORD ADDRESS COUNTER R/W YDEC CK DATA REGISTER DIN DS800012-1 I2C™ is a registered trademark of Philips Electronics N.V. © 1999 Fairchild Semiconductor Corporation NM24C65U Rev. B.1 DOUT 1 www.fairchildsemi.com NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface PRELIMINARY Dual-In-Line Package (N) and 8-Pin SO Package (M8) A0 1 A1 2 8 VCC 7 WP NM24C65U A2 3 6 SCL VSS 4 5 SDA DS800012-2 Top View See Package Number N08E and M08A Pin Names A0, A1, A2 Device Address Input VSS Ground SDA Data I/O SCL Clock Input WP Write Protect VCC Power Supply Ordering Information NM 24 C XX U F LZ E XX Letter Description N M8 8-Pin DIP 8-Pin SOIC Temp. Range None V E 0 to 70°C -40 to +125°C -40 to +85°C Voltage Operating Range Blank L LZ H 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V and <1µA Standby Current 4.5V to 5.5V and VCC Lockout Blank F 100KHz 400KHz Package SCL Clock Frequency Density Interface 2 NM24C65U Rev. B.1 Ultralite CS100UL Process 65 64K with Write Protect C CMOS 24 IIC NM Fairchild Non-Volatile Memory www.fairchildsemi.com NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface Connection Diagram Operating Conditions Absolute Maximum Ratings Ambient Storage Temperature Ambient Operating Temperature NM24C65U NM24C65UE NM24C65UV –65°C to +150°C All Input or Output Voltages with Respect to Ground 6.5V to –0.3V Lead Temperature (Soldering, 10 seconds) +300°C ESD Rating 0°C to +70°C -40°C to +85°C -40°C to +125°C Positive Power Supply NM24C65U/NM24C65UH NM24C65UL NM24C65ULZ 2000V min. 4.5V to 5.5V 2.7V to 5.5V 2.7V to 5.5V Standard VCC (4.5V to 5.5V) DC Electrical Characteristics Symbol Parameter Test Conditions Min Limits Typ (Note 1) Max Units ICCA Active Power Supply Current fSCL = 400 kHz fSCL = 100 kHz 0.2 1.0 mA ISB Standby Current VIN = GND or VCC 10 50 µA ILI Input Leakage Current VIN = GND to VCC 0.1 1 µA ILO Output Leakage Current VOUT = GND to VCC 0.1 1 µA VIL Input Low Voltage –0.3 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V VOL Output Low Voltage 0.4 V IOL = 3 mA Low VCC (2.7V to 5.5V) DC Electrical Characteristics Symbol Parameter Test Conditions Min Limits Typ (Note 1) Max Units ICCA Active Power Supply Current fSCL = 400 KHz fSCL = 100 KHz 0.2 1.0 mA ISB Standby Current VIN = GND or VCC 1 0.1 10 10 1 50 µA µA µA ILI Input Leakage Current VIN = GND to VCC 0.1 1 µA ILO Output Leakage Current VOUT = GND to VCC 0.1 1 µA VIL Input Low Voltage –0.3 VCC x 0.3 V VIH Input High Voltage VCC x 0.7 VCC + 0.5 V VOL Output Low Voltage 0.4 V VCC = 2.7V - 4.5V VCC = 2.7V - 4.5V VCC = 4.5V - 5.5V IOL = 3 mA Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2) Symbol Test Conditions Max Units CI/O Input/Output Capacitance (SDA) VI/O = 0V 8 pF CIN Input Capacitance (A0, A1, A2, SCL) VIN = 0V 6 pF Note 1: Typical values are for TA = 25°C and nominal supply voltage (5V). Note 2: This parameter is periodically sampled and not 100% tested. 3 NM24C65U Rev. B.1 www.fairchildsemi.com NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface Product Specifications Input Pulse Levels VCC x 0.1 to VCC x 0.9 Input Rise and Fall Times 10 ns Input & Output Timing Levels VCC x 0.5 Output Load 1 TTL Gate and CL = 100 pF Read and Write Cycle Limits (Standard and Low VCC Range - 2.7V-5.5V) Symbol fSCL TI Parameter 100 KHz Min Max 400 KHz Min Max Units SCL Clock Frequency 100 400 KHz Noise Suppression Time Constant at SCL, SDA Inputs (Minimum VIN Pulse width) 100 50 ns 0.9 µs tAA SCL Low to SDA Data Out Valid 0.3 tBUF Time the Bus Must Be Free before a New Transmission Can Start 4.7 1.3 µs Start Condition Hold Time 4.0 0.6 µs tLOW Clock Low Period 4.7 1.5 µs tHIGH Clock High Period 4.0 0.6 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 0.6 µs tHD:DAT Data in Hold Time 0 0 µs tSU:DAT Data in Setup Time 250 100 ns tHD:STA 3.5 0.1 tR SDA and SCL Rise Time 1 0.3 µs tF SDA and SCL Fall Time 300 300 ns tSU:STO tDH tWR (Note 3) Stop Condition Setup Time 4.7 0.6 µs Data Out Hold Time 300 50 ns Write Cycle Time - NM24C65U - NM24C65UL, NM24C65ULZ 10 15 10 15 ms Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the NM24C65U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address 4 NM24C65U Rev. B.1 www.fairchildsemi.com NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface AC Conditions of Test tR tF tHIGH tLOW tLOW SCL ;; tSU:STA SDA tHD:STA tHD:DAT tSU:DAT tSU:STO IN tBUF tAA tDH SDA OUT DS800012-3 Pin Description BACKGROUND INFORMATION (IIC Bus) As mentioned, the IIC bus allows synchronous bidirectional communication between Transmitter/Receiver using the SCL (clock) and SDA (Data I/O) lines. All communication must be started with a valid START condition, concluded with a STOP condition and acknowledged by the Receiver with an ACKNOWLEDGE condition. SERIAL CLOCK (SCL) The SCL input is used to clock all data into and out of the device. SERIAL DATA (SDA) SDA is a biderectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. In addition, since the IIC bus is designed to support other devices such as RAM, EPROM, etc., the device type identifier string, or slave address, must follow the START condition. For EEPROMs, the first 4-bits of the slave address is '1010'. This is then followed by the device selection bits A2, A1 and A0.The final bit in the slave address determines the type of operation performed (READ/ WRITE). A "1" signifies a READ while a "0" signifies a WRITE. The slave address is then followed by two bytes that define the word address, which is then followed by the data byte. Device Address Inputs (A0, A1, A2) Device address pins A0, A1, and A2 are connected to VCC or VSS to configure the EEPROM address for multiple device configuration. A total of eight different devices can be attached to the same SDA bus. Write Protection (WP) The EEPROMs on the IIC bus may be configured in any manner required, providing the total memory addressed does not exceed 4M bits in the Extended IIC protocol. EEPROM memory addressing is controlled by hardware configuring the A2, A1, and A0 pins (Device Address pins) with pull-up or pull-down resistors. ALL UNUSED PINS MUST BE GROUNDED (tied to VSS). If WP is tied to VCC, program WRITE operations onto the upper half of the memory will not be executed. READ operations are always available. If WP is tied to VSS, normal memory operation is enabled, READ/ WRITE over the entire bit memory array. This feature allows the user to assign the upper half of the memory as ROM which can be protected against accidental programming writes. When WRITE is disabled, slave address and word address will be acknowledged but data will not be acknowledged. Addressing an EEPROM memory location involves sending a command string with the following information: [DEVICE TYPE]-[DEVICE ADDRESS]-[PAGE BLOCK ADDRESS]-[BYTE ADDRESS] Device Operation Definitions Word 8 bits (byte) of data Page 32 sequential addresses (one byte each) that may be programmed during a "Page Write" programming cycle. Master Any IIC device CONTROLLING the transfer of data (such as a microcontroller). Slave Device being controlled (EEPROMS are always considered Slaves). Transmitter Device currently SENDING data on the bus (may be either a Master or Slave). Receiver Device currently RECEIVING data on the bus (Master or Slave). The NM24C65Uxxx supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter and the receiving devices as the receiver. The device controlling the transfer is the master and the device that is controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the NM24C65Uxxx is considered a slave in all applications. CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH and reserved for indicating start and stop conditions. Refer to Figures 2 and 3. START CONDITION All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is HIGH. The NM24C65Uxxx continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. STOP CONDITION All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the NM24C65Uxxx to place the device in the standby power mode. 5 NM24C65U Rev. B.1 www.fairchildsemi.com NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface Bus Timing both the device and a WRITE operation have been selected, the NM24C65Uxxx will respond with an acknowledge after the receipt of each subsequent eight bit word. ACKNOWLEDGE Acknowledge is a hardware convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data. Refer to Figure 4. In the READ mode the NM24C65Uxxx slave will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to the standby power mode. The NM24C65Uxxx device will always respond with an acknowledge after recognition of a start condition and its slave address. If Write Cycle Timing (Figure 1) SCL SDA 8th BIT ACK WORD n tWR START CONDITION STOP CONDITION DS800012-4 Data Validity (Figure 2) SCL SDA DATA STABLE DATA CHANGE DS800012-5 Definition of Start and Stop (Figure 3) SCL SDA START CONDITION STOP CONDITION DS800012-6 Acknowledge Response from Receiver (Figure 4) SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE 6 NM24C65U Rev. B.1 DS800012-7 www.fairchildsemi.com NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface Write Cycle Timing Following a start condition the master must output the address of the slave it is accessing. The most significant four bits of the slave address are those of the device type identifier. This is fixed as 1010 for all EEPROM devices. The next three bits identifies the device address. Address from 000 to 111 are acceptable thus allowing up to eight devices to be connected to the IIC bus. PAGE WRITE The NM24C65Uxxx is capable of thirty-two byte page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data word is transfered, the master can transmit up to thirty-one more words. After the receipt of each word, the device responds with an acknowledge. The last bit of the slave address defines whether a write or read condition is requested by the master. A "1" indicates that a READ operation is to be executed and a "0" initiates the WRITE mode. A simple review: After the NM24C65Uxxx recognizes the start condition, the devices interfaced to the IIC bus wait for a slave address to be transmitted over the SDA line. If the transmitted slave address matches an address of one of the devices, the designated slave pulls the line LOW with an acknowledge signal and awaits further transmissions. After the receipt of each word, the internal address counter increments to the next address and the next SDA data is accepted. If the master should transmit more than thirty-two words prior to generating the stop condition, the address counter will "roll over" and the previous written data will be overwritten. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer Figure 6 for the Page Write sequence. Write Operations BYTE WRITE For a WRITE operation, two additional address bytes, with 13 active bits, are required after the SLAVE acknowledge to address the full memory array. The first byte indicates the high-order byte of the word address. Only the five least signicant bits can be changed, the other bits are pre-assigned the value "0". Following the acknowledgement from the first word address, the next byte indicates the low-order byte of the word address. Upon receipt of the word address, the NM24C65Uxxx responds with another acknowledge and waits for the next eight bits of data, again, Acknowledge Polling Once the stop condition is isssued to indicate the end of the host's write operation, the NM24C65Uxxx initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the NM24C65Uxxx is still busy with the write operation, no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. Byte Write (Figure 5) S T Bus Activity: A Master R T SDA Line Bus Activity SLAVE ADDRESS WORD ADDRESS (1) 1 0 1 0 WORD ADDRESS (0) S T O P DATA 0 0 0 A C K A C K A C K A C K DS800012-8 7 NM24C65U Rev. B.1 www.fairchildsemi.com NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the NM24C65Uxxx begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress, the device's inputs are disabled and the device will not respond to any requests from the master. Refer Figure 5 for the Byte Write sequence. DEVICE ADDRESSING Programming of the upper half of memory will not take place if the WP pin is connected to VCC. The device will accept slave and word addresses; but if the memory accessed is write protected by the WP pin, the NM24C65Uxxx will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the stop condition is asserted. RANDOM READ Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to "1", the master must first perform a "dummy" write operation. The master issues a start condition, slave address with the R/W bit set to "0" and then the word address it is to read from. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to "1". This will be followed by an acknowledge from the NM24C65Uxxx and then by the eight bit data. The master will not acknowledge the transfer but does generate the stop condition, and therefore the NM24C65Uxxx discontinues transmission. Refer Figure 8 for the Random Read sequence. Low VCC Lockout NM24C65UxHx (H option) protects against data corruption during programming by preventing any programming operations if VCC drops below approximately 3.8V (VCC Lockout trip level). This is accomplished by monitoring the "READ/WRITE" (R/W) bit in the SLAVE address and if the R/W bit is "0," indicating a programming operation, the VCC Lockout is activated. At that point, if the VCC drops below the trip level, programming is inhibited and the device does not issue an ACK (the output stays high). To restate, the VCC Lockout feature is active from the time a WRITE bit is received up to the time that the Master's STOP condition is received (the STOP condition turns on the VPP internal high voltage). Once programming has begun, the programming cycle cannot be interrupted except by removal of VCC, which could result in data corruption. SEQUENTIAL READ Sequential reads can be initiated as either a current address read or random access read. The first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. The NM24C65Uxxx continues to output data for each acknowledge received. The read operation is terminated by the master not responding with an acknowledge or by generating a stop condition. Read Operation Read operations are initiated in the same manner as write operations, with the exception that the R/W bit of the slave address is set to "1". There are three basic read operations: current address read, random read and sequential read. The data output is sequential, with the data from address n, followed by the data n+1. The address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. After the entire memory has been read, the counter "rolls over" and the NM24C65Uxxx continues to output data for each acknowledge received. Refer Figure 9 for the Sequential Read sequence. CURRENT ADDRESS READ Internally the NM24C65Uxxx contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n+1. Upon receipt of the slave address with R/W set to one, the NM24C65Uxxx issues an acknowledge and transmits the Page Write (Figure 6) S T Bus Activity: A Master R T SDA Line Bus Activity SLAVE ADDRESS WORD ADDRESS (1) 1 0 1 0 WORD ADDRESS (0) DATA n S T O P DATA n+31 0 0 0 A C K A C K A C K A C K DS800012-9 8 NM24C65U Rev. B.1 www.fairchildsemi.com NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface eight bit word. The master will not acknowledge acknowledge the transfer but does generate a stop condition, and therefore discontinues transmission. Refer Figure 7 for the Current Address Read sequence. Write Protection S T A R SLAVE ADDRESS T S T O P DATA 1 0 1 0 A C K NO A C K DS800012-10 Random Read (Figure 8) S T A Bus Activity: R Master T SDA Line SLAVE ADDRESS 1 0 1 0 WORD ADDRESS (1) 0 WORD ADDRESS (0) 0 0 0 SLAVE ADDRESS 1 0 1 0 A C K Bus Activity S T A R T A C K A C K DATA n S T O P 1 A C K NO A C K DS800012-11 Sequential Read (Figure 9) S T Bus Activity: A Master R T SDA Line Bus Activity SLAVE ADDRESS DATA n DATA n + 1 DATA n + x S T O P 1 0 1 0 A C K A C K A C K A C K NO A C K DS800012-12 9 NM24C65U Rev. B.1 www.fairchildsemi.com NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface Current Address Read (Figure 7) NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface Physical Dimensions inches (millimeters) unless otherwise noted 0.189 - 0.197 (4.800 - 5.004) 8 7 6 5 0.228 - 0.244 (5.791 - 6.198) 1 2 3 4 Lead #1 IDENT 0.010 - 0.020 x 45° (0.254 - 0.508) 0.0075 - 0.0098 (0.190 - 0.249) Typ. All Leads 0.150 - 0.157 (3.810 - 3.988) 8° Max, Typ. All leads 0.04 (0.102) All lead tips 0.053 - 0.069 (1.346 - 1.753) 0.004 - 0.010 (0.102 - 0.254) Seating Plane 0.014 (0.356) 0.016 - 0.050 (0.406 - 1.270) Typ. All Leads 0.050 (1.270) Typ 0.014 - 0.020 Typ. (0.356 - 0.508) Molded Small Out-Line Package (M8) Order Number NM24C65UxxxM8 or NM24C65UxxxEM8 Package Number M08A 10 NM24C65U Rev. B.1 www.fairchildsemi.com 0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) 8 0.092 DIA (2.337) 7 6 0.250 - 0.005 + Pin #1 IDENT 8 0.032 ± 0.005 (6.35 ± 0.127) Pin #1 IDENT 1 Option 1 1 0.280 MIN (7.112) 2 3 0.040 Typ. (1.016) 0.300 - 0.320 (7.62 - 8.128) 7 (0.813 ± 0.127) RAD 5 0.030 MAX (0.762) 20° ± 1° 4 Option 2 0.145 - 0.200 0.039 (0.991) (3.683 - 5.080) 0.130 ± 0.005 (3.302 ± 0.127) 95° ± 5° 0.009 - 0.015 (0.229 - 0.381) +0.040 0.325 -0.015 +1.016 8.255 -0.381 0.125 (3.175) DIA NOM 0.125 - 0.140 (3.175 - 3.556) 0.065 (1.651) 90° ± 4° Typ 0.018 ± 0.003 (0.457 ± 0.076) 0.100 ± 0.010 (2.540 ± 0.254) 0.045 ± 0.015 (1.143 ± 0.381) 0.020 (0.508) Min 0.060 (1.524) 0.050 (1.270) Molded Dual-In-Line Package (N) Order Number NM24C65UxxxN or NM24C65UxxxEN Package Number N08E Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Fairchild Semiconductor Europe Fax: +44 (0) 1793-856858 Deutsch Tel: +49 (0) 8141-6102-0 English Tel: +44 (0) 1793-856856 Français Tel: +33 (0) 1-6930-3696 Italiano Tel: +39 (0) 2-249111-1 Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre 68 Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383 Fairchild Semiconductor Japan Ltd. 4F, Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 11 NM24C65U Rev. B.1 www.fairchildsemi.com NM24C65U 64K-Bit Serial EEPROM with Write Protect 2-Wire Bus Interface Physical Dimensions inches (millimeters) unless otherwise noted