16-Bit 1 MSPS PulSAR Unipolar ADC with Reference AD7653 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM Throughput: 1 MSPS (Warp mode) 800 kSPS (Normal mode) 666 kSPS (Impulse mode) 16-bit resolution Analog input voltage range: 0 V to 2.5 V No pipeline delay Parallel and serial 5 V/3 V interface SPI®/QSPITM/MICROWIRETM/DSP compatible Single 5 V supply operation Power dissipation 92 mW typ @ 666 kSPS, 138 µW @ 1 kSPS without REF 128 mW typ @ 1 MSPS with REF 48-lead LQFP and 48-lead LFCSP packages Pin-to-pin compatible with PulSAR ADCs APPLICATIONS AGND AVDD The AD7653 is a 16-bit, 1 MSPS, charge redistribution SAR analog-to-digital converter that operates from a single 5 V power supply. The part contains a high speed 16-bit sampling ADC, internal conversion clock, internal reference, error correction circuits, and both serial and parallel system interface ports. It features a very high sampling rate mode (Warp), a fast mode (Normal) for asynchronous conversion rate applications, and a reduced power mode (Impulse) for low power applications where power is scaled with the throughput. The AD7653 is fabricated using Analog Devices’ high performance, 0.6 micron CMOS process, with correspondingly low cost. It is available in a 48-lead LQFP and a tiny 48-lead LFCSP with operation specified from –40°C to +85°C. DGND OVDD IN 16 SWITCHED CAP DAC INGND OGND SERIAL PORT REF PARALLEL INTERFACE PDREF PDBUF CLOCK PD RESET DATA[15:0] BUSY RD CS CONTROL LOGIC AND CALIBRATION CIRCUITRY SER/PAR OB/2C BYTESWAP WARP IMPULSE CNVST 02966-0-001 Figure 1. Table 1. PulSAR™ Selection True Bipolar True Differential 18-Bit Multichannel/ Simultaneous GENERAL DESCRIPTION DVDD AD7653 Type/kSPS PseudoDifferential Data acquisition Instrumentation Digital signal processing Spectrum analysis Medical instruments Battery-powered systems Process control Rev. C REFBUFIN REF REFGND 100–250 AD7651 AD7660/AD7661 AD7663 AD7675 500–570 AD7650/AD7652 AD7664/AD7666 AD7666 AD7676 AD7678 AD7679 AD7654 AD7655 800– 1000 AD7653 AD7667 AD7671 AD7677 AD7674 PRODUCT HIGHTLIGHTS 1. 2. 3. 4. Fast Throughput. The AD7653 is a 1 MSPS, charge redistribution, 16-bit SAR ADC with internal error correction circuitry. Internal Reference. The AD7653 has an internal reference with a typical temperature drift of 7 ppm/°C. Single-Supply Operation. The AD7653 operates from a single 5 V supply. In Impulse mode, its power dissipation decreases with the throughput. Serial or Parallel Interface. Versatile parallel or 2-wire serial interface arrangement is compatible with both 3 V and 5 V logic. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2003–2017 Analog Devices, Inc. All rights reserved. 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AD7653 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Connection Diagram ................................................... 17 Applications ....................................................................................... 1 Power Dissipation vs. Throughput .......................................... 19 General Description ......................................................................... 1 Conversion Control ................................................................... 19 Functional Block Diagram .............................................................. 1 Digital Interface .......................................................................... 20 Product Hightlights .......................................................................... 1 Parallel Interface ......................................................................... 20 Revision History ............................................................................... 2 Serial Interface ............................................................................ 20 Specifications..................................................................................... 3 Master Serial Interface ............................................................... 21 Timing Specifications....................................................................... 5 Slave Serial Interface .................................................................. 22 Absolute Maximum Ratings............................................................ 7 Microprocessor Interfacing ....................................................... 24 ESD Caution .................................................................................. 7 Application Hints ........................................................................... 25 Pin Configuration and Function Descriptions ............................. 8 Bipolar and Wider Input Ranges .............................................. 25 Definitions of Specifications ......................................................... 11 Layout .......................................................................................... 25 Typical Performance Characteristics ........................................... 12 Outline Dimensions ....................................................................... 26 Circuit Information ........................................................................ 15 Ordering Guide .......................................................................... 26 Converter Operation .................................................................. 15 REVISION HISTORY 12/2017—Rev. B to Rev. C Changes to Figure 4 .......................................................................... 8 Updated Outline Dimensions ....................................................... 26 Changes to Ordering Guide .......................................................... 26 9/2016—Rev. A to Rev. B. Changes to Figure 4 and Table 6 ..................................................... 8 Changes to Microprocessor Interface Section, SPI Interface (ADSP-2191M) Section, and Figure 37 ....................................... 24 Deleted Evaluating the AD7653’s Performance Section............ 25 Updated Outline Dimensions ............................................................... 26 Changes to Ordering Guide................................................................... 26 9/2003—Rev. 0 to Rev. A. Change to Product Highlights .........................................................1 Changes to Specifications .................................................................3 Changes to Absolute Maximum Ratings ........................................7 Changes to Figure 15...................................................................... 13 Changes to Figure 22...................................................................... 16 Changes to Voltage Reference Input section .............................. 18 Changes to Figure 31...................................................................... 20 8/2003—Revision 0: Initial Version Rev. C | Page 2 of 26 Data Sheet AD7653 SPECIFICATIONS Table 2. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance 1 THROUGHPUT SPEED Complete Cycle Throughput Rate Time between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error No Missing Codes Differential Linearity Error Transition Noise Unipolar Zero Error, TMIN to TMAX 3 Unipolar Zero Error Temperature Drift Full-Scale Error, TMIN to TMAX3 Full-Scale Error Temperature Drift Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) –3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response REFERENCE Internal Reference Voltage Internal Reference Temperature Drift Line Regulation Turn-On Settling Time Temperature Pin Voltage Output @ 25°C Temperature Sensitivity Output Resistance External Reference Voltage Range External Reference Current Drain Conditions Min 16 VIN – VINGND VIN 0 –0.1 VINGND fIN = 10 kHz 1 MSPS Throughput –0.1 In Warp Mode In Warp Mode In Warp Mode In Normal Mode In Normal Mode In Impulse Mode In Impulse Mode Typ Max Unit Bits VREF +3 V V +0.5 V dB µA 1 1000 1 1.25 800 1.5 666 µs kSPS ms µs kSPS µs kSPS +6 ±0.4 ±2 LSB 2 Bits LSB LSB LSB ppm/°C % of FSR ppm/°C LSB 86 98 –98 –96 86 30 12 dB 4 dB dB dB dB dB MHz 2 5 ns ps rms ns 65 12 1 0 0 –6 15 –2 +3 0.7 ±25 ±0.2 REF = 2.5 V ±0.12 AVDD = 5 V ± 5%, with REF fIN = 100 kHz fIN = 100 kHz fIN = 45 kHz fIN = 100 kHz fIN = 100 kHz –60 dB Input, fIN = 100 kHz Full-Scale Step 250 VREF @ 25°C –40°C to +85°C AVDD = 5 V ± 5% CREF = 10 µF 2.48 2.3 1 MSPS Throughput Rev. C | Page 3 of 26 2.50 ±7 ±24 5 300 1 4.3 2.5 300 2.52 AVDD – 1.85 V ppm/°C ppm/V ms mV mV/°C kΩ V µA AD7653 Parameter DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format 5 Pipeline Delay 6 VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current 8 AVDD 9 AVDD 10 DVDD 11 OVDD11 Power Dissipation without REF Power Dissipation with REF TEMPERATURE RANGE 12 Specified Performance Data Sheet Conditions Min Typ –0.3 2.0 –1 –1 ISINK = 1.6 mA ISOURCE = –500 µA Unit +0.8 DVDD + 0.3 +1 +1 V V µA µA 0.4 V V 5.25 5.25 5.25 7 V V V OVDD – 0.6 4.75 4.75 2.7 1 MSPS Throughput With Reference and Buffer Reference and Buffer Alone 5 5 18.7 3 6.7 200 92 138 128 666 kSPS Throughput11 1 kSPS Throughput11 1 MSPS Throughput8 TMIN to TMAX Max –40 145 mA mA mA µA mW µW mW +85 °C 115 See Analog Input section. LSB means least significant bit. With the 0 V to 2.5 V input range, 1 LSB is 38.15 µV. 3 See Definitions of Specifications section. These specifications do not include the error contribution from the external reference. 4 All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 5 Parallel or serial 16-bit. 6 Conversion results are available immediately after completed conversion. 7 The max should be the minimum of 5.25 V and DVDD + 0.3 V. 8 In Warp mode. 9 With REF, PDREF and PDBUF are LOW; without REF, PDREF and PDBUF are HIGH. 10 With PDREF, PDBUF LOW and PD HIGH. 11 Impulse Mode. Tested in Parallel Reading mode. 12 Consult factory for extended temperature range. 1 2 Rev. C | Page 4 of 26 Data Sheet AD7653 TIMING SPECIFICATIONS Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted Parameter Refer to Figure 26 and Figure 27 Convert Pulse Width Time between Conversions (Warp Mode/Normal Mode/Impulse Mode) 1 CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except Master Serial Read after Convert (Warp Mode/Normal Mode/Impulse Mode) Aperture Delay End of Conversion to BUSY LOW Delay Conversion Time (Warp Mode/Normal Mode/Impulse Mode) Acquisition Time RESET Pulse Width Refer to Figure 28, Figure 29, and Figure 30 (Parallel Interface Modes) CNVST LOW to DATA Valid Delay (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY LOW Delay Bus Access Request to DATA Valid Bus Relinquish Time Refer to Figure 32 and Figure 33 (Master Serial Interface Modes) 2 CS LOW to SYNC Valid Delay CS LOW to Internal SCLK Valid Delay2 CS LOW to SDOUT Delay CNVST LOW to SYNC Delay (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay Internal SCLK Period 3 Internal SCLK HIGH3 Internal SCLK LOW3 SDOUT Valid Setup Time3 SDOUT Valid Hold Time3 SCLK Last Edge to SYNC Delay3 CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read after Convert3 (Warp Mode/Normal Mode/Impulse Mode) CNVST LOW to SYNC Asserted Delay (Warp Mode/Normal Mode/Impulse Mode) SYNC Deasserted to BUSY LOW Delay Refer to Figure 34 and Figure 35 (Slave Serial Interface Modes) 2 External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW Symbol Min t1 t2 t3 10 1/1.25/1.5 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 Typ Unit 35 ns µs ns 0.75/1/1.25 2 10 0.75/1/1.25 250 10 0.75/1/1.25 12 45 15 5 10 10 10 25/275/525 3 25 12 7 4 2 3 40 10 10 10 t28 See Table 4 t29 t30 0.75/1/1.25 25 t31 t32 t33 t34 t35 t36 t37 Max 5 3 5 5 25 10 10 2 Rev. C | Page 5 of 26 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns 18 In Warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 3 In Serial Master Read during Convert Mode. See Table 4 for Serial Master Read after Convert mode. 1 µs ns ns µs ns ns ns ns ns ns ns ns ns AD7653 Data Sheet Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum BUSY HIGH Width Maximum (Warp) BUSY HIGH Width Maximum (Normal) BUSY HIGH Width Maximum (Impulse) Symbol t18 t19 t19 t20 t21 t22 t23 t24 t28 t28 t28 Rev. C | Page 6 of 26 0 0 3 25 40 12 7 4 2 3 1.5 1.75 2 0 1 17 50 70 22 21 18 4 55 2 2.25 2.5 1 0 17 100 140 50 49 18 30 130 3 3.25 3.5 1 1 17 200 280 100 99 18 80 290 5.25 5.55 5.75 Unit ns ns ns ns ns ns ns ns µs µs µs Data Sheet AD7653 ABSOLUTE MAXIMUM RATINGS 1.6mA Table 5. AD7653 Absolute Maximum Ratings Parameter IN1, TEMP1,REF, REFBUFIN, INGND, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD, OVDD AVDD to DVDD, AVDD to OVDD DVDD to OVDD Digital Inputs PDREF, PDBUF2 Internal Power Dissipation3 Internal Power Dissipation4 Junction Temperature Storage Temperature Range Lead Temperature Range (Soldering 10 sec) Rating AVDD + 0.3 V to AGND – 0.3 V TO OUTPUT PIN IOL 1.4V CL 60pF* 500µA ±0.3 V IOH * IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM. –0.3 V to +7 V ±7 V –0.3 V to +7 V –0.3 V to DVDD + 0.3 V ±20 mA 700 mW 2.5 W 150°C –65°C to +150°C 300°C 02966-0-006 Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs CL = 10 pF 2V 0.8V tDELAY tDELAY 2V 0.8V 2V 0.8V 02966-0-007 Figure 3. Voltage Reference Levels for Timing See Analog Input section. 2 See Voltage Reference Input section. 3 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W 4 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. 1 ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. C | Page 7 of 26 AD7653 Data Sheet 48 47 46 45 44 43 42 41 40 39 38 37 PDBUF PDREF REFBUFIN TEMP AVDD IN AGND AGND NC INGND REFGND REF PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD7653 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 AGND CNVST PD RESET CS RD DGND BUSY D15 D14 D13 D12 D4/EXT/INT D5/INVSYNC D6/INVSCLK D7/RDC/SDIN OGND OVDD DVDD DGND D8/SDOUT D9/SCLK D10/SYNC D11/RDERROR 13 14 15 16 17 18 19 20 21 22 23 24 AGND 1 AVDD 2 NC 3 BYTESWAP 4 OB/2C 5 WARP 6 IMPULSE 7 SER/PAR 8 D0 9 D1 10 D2/DIVSCLK0 11 D3/DIVSCLK1 12 NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE LFCSP PACKAGE HAS AN EXPOSED PAD. THIS EPAD CAN BE CONNECTED AGND. THIS CONNECTION IS NOT REQUIRED TO MEET ELECTRICAL PERFORMANCE SPECIFICATIONS. 02966-0-002 Figure 4. 48-Lead LQFP (ST-48) and 48-Lead LFCSP (CP-48-1) Table 6. Pin Function Descriptions Pin No. 0 Mnemonic EPAD Type 1 1, 36, 41, 42 2, 44 3, 40 4 AGND P AVDD NC BYTESWAP P 5 OB/2C DI 6 WARP DI 7 IMPULSE DI 8 SER/PAR DI 9, 10 D[0:1] DO 11, 12 D[2:3]or DIVSCLK[0:1] DI/O DI Description Exposed Pad. The LFCSP package has an exposed pad. This EPAD can be connected to AGND. This connection is not required to meet electrical performance specifications. Analog Power Ground Pin. Input Analog Power Pin. Nominally 5 V. No Connect. Parallel Mode Selection (8-/16-bit). When LOW, the LSB is output on D[7:0] and the MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0]. Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. Mode Selection. When this pin is HIGH and the IMPULSE pin is LOW, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of the minimum conversion rate. Mode Selection. When IMPULSE is HIGH and WARP is LOW, this input selects a reduced power mode. In this mode, the power dissipation is approximately proportional to the sampling rate. Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the serial interface mode is selected and some bits of the DATA bus are used as a serial port. Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these outputs are in high impedance. When SER/PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus. When SER/PAR is HIGH, EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In other serial modes, these pins are not used. Rev. C | Page 8 of 26 Data Sheet AD7653 Pin No. 13 Mnemonic D4 or EXT/INT Type 1 DI/O 14 D5 or INVSYNC DI/O 15 D6 or INVSCLK DI/O 16 D7 or RDC/SDIN DI/O 17 18 OGND OVDD P P 19 20 21 DVDD DGND D8 or SDOUT P P DO 22 D9 or SCLK DI/O 23 D10 or SYNC DO 24 D11 or RDERROR DO 25–28 D[12:15] DO 29 BUSY DO 30 31 DGND RD P DI Description When SER/PAR is LOW, this output is used as Bit 4 of the parallel port data output bus. When SER/PAR is HIGH, this input, part of the serial port, is used as a digital select input for choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. When SER/PAR is LOW, this output is used as Bit 5 of the parallel port data output bus. When SER/PAR is HIGH, this input, part of the serial port, is used to select the active state of the SYNC signal. It is active in both master and slave modes. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus. When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave modes. When SER/PAR is LOW, this output is used as Bit 7 of the parallel port data output bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. Input/Output Interface Digital Power Ground. Input/Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Digital Power. Nominally at 5 V. Digital Power Ground. When SER/PAR is LOW, this output is used as Bit 8 of the parallel port data output bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7653 provides the conversion result, MSB first, from its internal shift register. The DATA format is determined by the logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode when EXT/INT is HIGH, if INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge. When SER/PAR is LOW, this output is used as Bit 9 of the parallel port data or SCLK output bus. When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. When SER/PAR is LOW, this output is used as Bit 10 of the parallel port data output bus. When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while the SDOUT output is valid. When SER/PAR is LOW, this output is used as Bit 11 of the parallel port data output bus. When SER/PAR and EXT/INT are HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed HIGH. Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the state of SER/PAR. Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. Must Be Tied to Digital Ground. Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. Rev. C | Page 9 of 26 AD7653 Data Sheet Pin No. 32 Mnemonic CS Type 1 DI 33 RESET DI 34 PD DI 35 CNVST DI 37 38 39 43 45 46 47 REF REFGND INGND IN TEMP REFBUFIN PDREF AI/O AI AI AI AO AI/O DI 48 PDBUF DI 1 Description Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. Reset Input. When set to a logic HIGH, this pin resets the AD7653 and the current conversion, if any, is aborted. If not used, this pin could be tied to DGND. Power-Down Input. When set to logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. Start Conversion. A falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. In Impulse mode (IMPULSE HIGH, WARP LOW), if CNVST is held LOW when the acquisition phase (t8) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. Reference Input Voltage. On-chip reference output voltage. Reference Input Analog Ground. Analog Input Ground. Primary Analog Input with a Range of 0 V to 2.5 V. Temperature Sensor Voltage Output. Reference Input Voltage. The reference output and the reference buffer input. This pin allows the choice of internal or external voltage references. When LOW, the on-chip reference is turned on. When HIGH, the internal reference is switched off and an external reference must be used. This pin allows the choice of buffering an internal or external reference with the internal buffer. When LOW, the buffer is selected. When HIGH, the buffer is switched off. AI = Analog Input; AI/O = Bidirectional Analog; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power. Rev. C | Page 10 of 26 Data Sheet AD7653 DEFINITIONS OF SPECIFICATIONS Integral Nonlinearity Error (INL) Signal-to-Noise Ratio (SNR) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Full-Scale Error The last transition (from 011…10 to 011…11 in twos complement coding) should occur for an analog voltage 1½ LSB below the nominal full scale (2.49994278 V for the 0 V to 2.5 V range). The full-scale error is the deviation of the actual level of the last transition from the ideal level. Unipolar Zero Error The first transition should occur at a level ½ LSB above analog ground (19.073 µV for the 0 V to 2.5 V range). Unipolar zero error is the deviation of the actual transition from that point. Spurious-Free Dynamic Range (SFDR) Signal-to-(Noise + Distortion) Ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels. Aperture Delay Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Transient Response Transient response is the time required for the AD7653 to achieve its rated accuracy after a full-scale step function is applied to its input. Overvoltage Recovery Overvoltage recovery is the time required for the ADC to recover to full accuracy after an analog input signal 150% of the full-scale value is reduced to 50% of the full-scale value. Reference Voltage Temperature Coefficient SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Reference voltage temperature coefficient is the change of internal reference voltage output voltage V over the operating temperature range and normalized by the output voltage at 25°C, expressed in ppm/°C. The equation follows: Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula: TCV ( ppm / °C ) = ENOB = (S/[N+D]dB – 1.76)/6.02 and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal, and is expressed in decibels. V (T 2) – V (T 1) × 106 V (25°C) × (T 2 – T 1) where: V(25°C) = V at +25°C. V(T2) = V at Temperature 2 (+85°C). V(T1) = V at Temperature 1 (–40°C). Rev. C | Page 11 of 26 AD7653 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 2.0 4 3 1.5 2 1.0 DNL (LSB) INL (LSB) 1 0 –1 0.5 0 –2 –0.5 –3 –4 16384 0 49152 32768 CODE –1.0 65536 16384 0 02966-0-023 65536 02966-0-026 Figure 8. Differential Nonlinearity vs. Code Figure 5. Integral Nonlinearity vs. Code 160000 140000 114641 112516 120000 49152 32768 CODE 146148 140000 120000 100000 COUNTS 60000 60000 40000 15906 0 0 17001 679 0 0 0 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 CODE IN HEX 02966-0-027 0 –60 –80 –100 –120 SNR, S/[N+D] (dB) SNR = 86.0dB THD = 90.3dB SFDR = 91.5dB S/[N+D] = 84.8dB –40 0 53 2856 7FFC 7FFD 7FFE 7FFF 8000 8001 CODE IN HEX 3099 8002 9 0 8003 8004 02966-0-028 Figure 9. Histogram of 261,120 Conversions of a DC Input at the Code Center fS = 1000kSPS fIN = 101kHz –20 AMPLITUDE (dB of Full Scale) 54473 20000 377 Figure 6. Histogram of 261,120 Conversions of a DC Input at the Code Transition 90 15.0 87 14.5 SNR 84 81 14.0 S/[N+D] 13.5 13.0 78 ENOB –140 12.5 75 –160 –180 54482 40000 20000 0 80000 0 100 300 200 FREQUENCY (kHz) 400 72 500 02966-0-029 1 10 100 FREQUENCY (kHz) 12.0 1000 02966-0-030 Figure 10. SNR, S/(N+D), and ENOB vs. Frequency Figure 7. FFT Plot Rev. C | Page 12 of 26 ENOB (Bits) COUNTS 100000 80000 Data Sheet AD7653 SFDR –70 80 –80 60 –90 THD –100 40 THIRD HARMONIC –110 THIRD HARMONIC –115 –125 –55 0 1000 10 100 FREQUENCY (kHz) 5 25 45 65 85 125 105 02966-0-034 Figure 14. THD and Harmonics vs. Temperature 100000 91 10000 90 89 SNR S/[N+D] 86 85 84 AVDD, WARP/NORMAL DVDD, WARP/NORMAL 1000 OPERATING CURRENT (µA) SNR, S/[N+D] REFERRED TO FULL SCALE (dB) –15 02966-0-031 92 87 –35 TEMPERATURE (°C) Figure 11. THD, Harmonics, and SFDR vs. Frequency 88 SECOND HARMONIC THD –105 20 SECOND HARMONIC 1 THD, HARMONICS (dB) 100 SFDR (dB) THD, HARMONICS (dB) –60 –120 –95 120 –50 100 10 DVDD, IMPULSE AVDD, IMPULSE 1 OVDD, ALL MODES 0.1 0.01 83 82 –60 –50 –40 –30 –20 –10 INPUT LEVEL (dB) PDREF = PDBUF = HIGH 0.001 10 0 1000 100 100000 SAMPLE RATE (SPS) 02966-A-032 Figure 12. SNR and S/(N+D) vs. Input Level (Referred to Full Scale) 1000000 02966-0-036 Figure 15. Operating Current vs. Sample Rate 6 14.75 89 10000 14.50 SNR S[N+D] 87 14.25 ENOB ENOB (Bits) SNR, S/[N+D] (dB) 88 14.00 86 ZERO ERROR, FULL SCALE (LSB) 5 4 3 2 FULL SCALE 1 0 –1 ZERO ERROR –2 –3 –4 –5 85 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 –6 –55 13.75 125 –35 –15 5 25 45 65 TEMPERATURE (°C) 02966-0-033 85 105 125 02966-0-040 Figure 16. Zero Error, Full Scale with Reference vs. Temperature Figure 13. SNR, S/(N+D), and ENOB vs. Temperature Rev. C | Page 13 of 26 AD7653 Data Sheet 2.5020 50 OVDD = 2.7V @ 85°C 2.5019 2.5018 40 2.5017 t12 DELAY (ns) VREF (V) 2.5016 2.5015 2.5014 2.5013 2.5012 2.5011 OVDD = 2.7V @ 25°C 30 OVDD = 5V @ 85°C 20 OVDD = 5V @ 25°C 10 2.5010 2.5009 2.5008 –40 –20 0 20 40 80 60 TEMPERATURE (°C) 100 0 120 Figure 17. Typical Reference Output Voltage vs. Temperature 80 NUMBER OF UNITS 70 60 50 40 30 20 10 –30 –26 –22 –18 –14 –10 –6 –2 2 6 10 14 18 22 26 30 REFERENCE DRIFT (ppm/°C) 50 100 150 Figure 19. Typical Delay vs. Load Capacitance CL 90 0 0 CL (pF) 02966-0-038 02966-0-039 Figure 18. Reference Voltage Temperature Coefficient Distribution (335 Units) Rev. C | Page 14 of 26 200 02966-0-035 Data Sheet AD7653 CIRCUIT INFORMATION IN REF REFGND MSB 32,768C 16,384C LSB 4C 2C C SWA SWITCHES CONTROL C BUSY COMP INGND CONTROL LOGIC OUTPUT CODE 65,536C SWB CNVST 02966-0-005 Figure 20. ADC Simplified Schematic The AD7653 is a very fast, low power, single supply, precise 16-bit analog-to-digital converter (ADC). The AD7653 features different modes to optimize performance according to the application. In Warp mode, the part can convert 1 million samples per second. The AD7653 provides the user with an on-chip track/hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7653 can be operated from a single 5 V supply and can be interfaced to either 5 V or 3 V digital logic. It is housed in either a 48-lead LQFP or a 48-lead LFCSP that saves space and allows flexible configurations as either a serial or a parallel interface. The AD7653 is a pin-to-pin compatible upgrade of the AD7651/AD7652. CONVERTER OPERATION The AD7653 is a successive approximation ADC based on a charge redistribution DAC. Figure 20 shows a simplified schematic of the ADC. The capacitive DAC consists of an array of 16 binary weighted capacitors and an additional LSB capacitor. The comparator’s negative input is connected to a dummy capacitor of the same value as the capacitive DAC array. During the acquisition phase, the common terminal of the array tied to the comparator’s positive input is connected to AGND via SWA. All independent switches are connected to the analog input IN. Thus, the capacitor array is used as a sampling capacitor and acquires the analog signal on IN. Similarly, the dummy capacitor acquires the analog signal on INGND. When CNVST goes LOW, a conversion phase is initiated. When the conversion phase begins, SWA and SWB are opened. The capacitor array and dummy capacitor are then disconnected from the inputs and connected to REFGND. Therefore, the differential voltage between IN and INGND captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4, …VREF/65536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After this process is completed, the control logic generates the ADC output code and brings the BUSY output LOW. Modes of Operation The AD7653 features three modes of operations: Warp, Normal, and Impulse. Each mode is best suited for specific applications. Warp mode allows the fastest conversion rate up to 1 MSPS. However in this mode and this mode only, the full specified accuracy is guaranteed only when the time between conversions does not exceed 1 ms. If the time between two consecutive conversions is longer than 1 ms (e.g., after power-up), the first conversion result should be ignored. This mode makes the AD7653 ideal for applications where both high accuracy and fast sample rate are required. Normal mode is the fastest mode (800 kSPS) without any limitations on the time between conversions. This mode makes the AD7653 ideal for asynchronous applications such as data acquisition systems, where both high accuracy and fast sample rate are required. Impulse mode, the lowest power dissipation mode, allows power saving between conversions. When operating at 1 kSPS, for example, it typically consumes only 138 µW. This feature makes the AD7653 ideal for battery-powered applications. Rev. C | Page 15 of 26 AD7653 Data Sheet Transfer Functions Table 7. Output Codes and Ideal Input Voltages Using the OB/2C digital input, the AD7653 offers two output codings: straight binary and twos complement. The LSB size is VREF/65536, which is about 38.15 µV. The AD7653’s ideal transfer characteristic is shown in Figure 21 and Table 7. Description FSR – 1 LSB FSR – 2 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 1 LSB = V REF /65536 ADC CODE (Straight Binary) Analog Input 2.499962 V 2.499923 V 1.250038 V 1.25 V 1.249962 V 38 µV 0V 111...111 111...110 111...101 Digital Output Code (Hex) Straight Twos Binary Complement FFFF 1 7FFF1 FFFE 7FFE 8001 0001 8000 0000 7FFF FFFF 0001 8001 0000 2 80002 This is also the code for overrange analog input (VIN – VINGND above VREF – VREFGND). 2 This is also the code for underrange analog input (VIN below VINGND). 1 000...010 000...001 000...000 0V 1 LSB 0.5 LSB VREF – 1 LSB VREF – 1.5 LSB ANALOG INPUT 02966-0-003 Figure 21. ADC Ideal Transfer Function 20Ω ANALOG SUPPLY (5V) + + 100nF 10µF AVDD 10µF DGND GND 100nF 100nF DVDD OVDD + DIGITAL SUPPLY (3.3V OR 5V) 10µF OGND SERIAL PORT SCLK REF CR4 100nF SDOUT REFBUFIN1 REFGND AD7653 ANALOG INPUT (0V TO 2.5V) 15Ω U12 CC CNVST IN D3 OB/2C SER/PAR WARP BYTESWAP 2.7nF INGND PDREF µC/µP/DSP BUSY DVDD IMPULSE PD PDBUF RESET CS RD CLOCK NOTES 1THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE AND INTERNAL BUFFER. 2THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 3OPTIONAL LOW JITTER. 4A 10µF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M). SEE VOLTAGE REFERENCE INPUT SECTION. Figure 22. Typical Connection Diagram Rev. C | Page 16 of 26 02966-A-004 Data Sheet AD7653 TYPICAL CONNECTION DIAGRAM Figure 22 shows a typical connection diagram for the AD7653. Analog Input Figure 23 shows an equivalent circuit of the input structure of the AD7653. The two diodes, D1 and D2, provide ESD protection for the analog inputs IN and INGND. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V. This will cause these diodes to become forward-biased and start conducting current. These diodes can handle a forward-biased current of 100 mA maximum. For instance, these conditions could eventually occur when the input buffer’s (U1) supplies are different from AVDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. During the conversion phase, when the switches are opened, the input impedance is limited to C1. R1 and C2 make a 1-pole low-pass filter that reduces undesirable aliasing effects and limits the noise. When the source impedance of the driving circuit is low, the AD7653 can be driven directly. Large source impedances will significantly affect the ac performance, especially total harmonic distortion. Driver Amplifier Choice Although the AD7653 is easy to drive, the driver amplifier needs to meet the following requirements: • AVDD IN OR INGND D1 C1 R1 C2 D2 AGND • 02966-0-008 Figure 23. Equivalent Analog Input Circuit This analog input structure allows the sampling of the differenttial signal between IN and INGND. Unlike other converters, INGND is sampled at the same time as IN. By using this differential input, small signals common to both inputs are rejected. For instance, by using INGND to sense a remote signal ground, ground potential differences between the sensor and the local ADC ground are eliminated. During the acquisition phase, the impedance of the analog input IN can be modeled as a parallel combination of capacitor C1 and the network formed by the series connection of R1 and C2. C1 is primarily the pin capacitance. R1 is typically 168 Ω and is a lumped component made up of some serial resistors and the on resistance of the switches. C2 is typically 60 pF and is mainly the ADC sampling capacitor. • The driver amplifier and the AD7653 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier’s data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection. The tiny op amp AD8021, which combines ultralow noise and high gain-bandwidth, meets this settling time requirement even when used with gains up to 13. The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7653. The noise coming from the driver is filtered by the AD7653 analog input circuit 1-pole low-pass filter made by R1 and C2 or by the external filter, if one is used. The driver needs to have a THD performance suitable to that of the AD7653. The AD8021 meets these requirements and is appropriate for almost all applications. The AD8021 needs a 10 pF external compensation capacitor that should have good linearity as an NPO ceramic or mica type. The AD8022 could also be used if a dual version is needed and gain of 1 is present. The AD829 is an alternative in applications where high frequency (above 100 kHz) performance is not required. In gain of 1 applications, it requires an 82 pF compensation capacitor. The AD8610 is an option when low bias current is needed in low frequency applications. Rev. C | Page 17 of 26 AD7653 Data Sheet Voltage Reference Input The AD7653 allows the choice of either a very low temperature drift internal voltage reference or an external 2.5 V reference. For applications that use multiple AD7653s, it is more effective to use the internal buffer to buffer the reference voltage. Unlike many ADCs with internal references, the internal reference of the AD7653 provides excellent performance and can be used in almost all applications. Care should be taken with the voltage reference’s temperature coefficient, which directly affects the full-scale accuracy, if this parameter matters. For instance, a ±15 ppm/°C temperature coefficient of the reference changes full scale by ±1 LSB/°C. To use the internal reference along with the internal buffer, PDREF and PDBUF should both be LOW. This will produce a 1.207 V voltage on REFBUFIN which, amplified by the buffer, will result in a 2.5 V reference on the REF pin. Note that VREF can be increased to AVDD – 1.85 V. Since the input range is defined in terms of VREF, this would essentially increase the range to 0 V to 3 V with an AVDD above 4.85 V. The AD780 can be selected with a 3 V reference voltage. The output impedance of REFBUFIN is 11 kΩ (minimum) when the reference is enabled. It is useful to decouple REFBUFIN with a 100 nF ceramic capacitor. Thus, the 100 nF capacitor provides an RC filter for noise reduction. The TEMP pin, which measures the temperature of the AD7653, can be used as shown in Figure 24. The output of the TEMP pin is applied to one of the inputs of the analog switch (e.g., ADG779), and the ADC itself is used to measure its own temperature. This configuration is very useful for improving the calibration accuracy over the temperature range. To use an external reference along with the internal buffer, PDREF should be HIGH and PDBUF should be LOW. This powers down the internal reference and allows the 2.5 V reference to be applied to REFBUFIN. TEMP ADG779 To use an external reference directly on the REF pin, PDREF and PDBUF should both be HIGH. PDREF and PDBUF, respectively, power down the internal reference and the internal reference. Note that the PDREF and PDBUF input current should never exceed 20 mA. This could eventually occur when input voltage is above AVDD (for instance at power-up). In this case, a 100 Ω series resistor is recommended. The internal reference is temperature compensated to 2.5 V ± 20 mV. The reference is trimmed to provide a typical drift of 7 ppm/°C. This typical drift characteristic is shown in Figure 17. For improved drift performance, an external reference such as the AD780 can be used. The AD7653 voltage reference input REF has a dynamic input impedance; it should, therefore, be driven by a low impedance source with efficient decoupling between the REF and REFGND inputs. This decoupling depends on the choice of the voltage reference, but usually consists of a low ESR capacitor connected to REF and REFGND with minimum parasitic inductance. A 10 μF (X5R, 1206 size) ceramic chip capacitor (or 47 μF tantalum capacitor) is appropriate when using either the internal reference or one of these recommended reference voltages: The low noise, low temperature drift ADR421 and AD780 The low power ADR291 The low cost AD1582 IN ANALOG INPUT (UNIPOLAR) AD8021 CC TEMPERATURE SENSOR AD7653 02966-0-024 Figure 24. Temperature Sensor Connection Diagram Power Supply The AD7653 uses three power supply pins: an analog 5 V supply AVDD, a digital 5 V core supply DVDD, and a digital input/output interface supply OVDD. OVDD allows direct interface with any logic between 2.7 V and DVDD + 0.3 V. To reduce the supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply, as shown in Figure 22. The AD7653 is independent of power supply sequencing once OVDD does not exceed DVDD by more than 0.3 V, and is thus free of supply voltage induced latch-up. Rev. C | Page 18 of 26 Data Sheet AD7653 POWER DISSIPATION VS. THROUGHPUT Operating currents are very low during the acquisition phase, allowing significant power savings when the conversion rate is reduced (see Figure 25). This power savings depends on the mode used. In Impulse mode, the AD7653 automatically reduces power consumption at the end of each conversion phase. This makes the part ideal for very low power battery applications. The digital interface and the reference remain active even during the acquisition phase. To reduce operating digital supply currents even further, digital inputs need to be driven close to the power supply rails (i.e., DVDD or DGND), and OVDD should not exceed DVDD by more than 0.3 V. POWER DISSIPATION (µW) 1000000 100000 The CNVST trace should be shielded with ground and a low value serial resistor (i.e., 50 Ω) termination should be added close to the output of the component that drives this line. For applications where SNR is critical, the CNVST signal should have very low jitter. This may be achieved by using a dedicated oscillator for CNVST generation, or to clock CNVST with a high frequency, low jitter clock, as shown in Figure 22. t2 t1 CNVST BUSY t4 t3 WARP MODE POWER t6 t5 MODE ACQUIRE CONVERT 10000 ACQUIRE t7 CONVERT t8 02966-0-011 Figure 26. Basic Conversion Timing 1000 t9 IMPULSE MODE POWER 100 10 10 RESET PDREF = PDBUF = HIGH 100 1000 10000 100000 SAMPLE RATE (SPS) 1000000 BUSY 02966-0-041 DATA Figure 25. Power Dissipation vs. Sampling Rate t8 CONVERSION CONTROL CNVST Figure 26 shows the detailed timing diagrams of the conversion process. The AD7653 is controlled by the CNVST signal, which initiates conversion. Once initiated, it cannot be restarted or aborted, even by the power-down input PD, until the conversion is complete. CNVST operates independently of CS and RD. In Impulse mode, conversions can be automatically initiated. If CNVST is held LOW when BUSY is LOW, the AD7653 controls the acquisition phase and automatically initiates a new conversion. By keeping CNVST LOW, the AD7653 keeps the conversion process running by itself. It should be noted that the analog input must be settled when BUSY goes low. Also, at power-up, CNVST should be brought LOW once to initiate the conversion process. In this mode, the AD7653 can run slightly faster than the guaranteed 666 kSPS limits in Impulse mode. This feature does not exist in Warp and Normal modes. 02966-0-011 Figure 27. RESET Timing CS = RD = 0 t1 CNVST t10 BUSY t3 DATA BUS t4 t11 PREVIOUS CONVERSION DATA NEW DATA 02966-0-012 Figure 28. Master Parallel Data Timing for Reading (Continuous Read) Although CNVST is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot and undershoot or ringing. Rev. C | Page 19 of 26 AD7653 Data Sheet DIGITAL INTERFACE CS The AD7653 has a versatile digital interface; it can be interfaced with the host system by using either a serial or a parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7653 digital interface also accommodates both 3 V and 5 V logic by simply connecting the OVDD supply pin of the AD7653 to the host system interface digital supply. Finally, by using the OB/2C input pin, both twos complement and straight binary coding can be used. The two signals, CS and RD, control the interface. CS and RD have a similar effect because they are OR’d together internally. When at least one of these signals is HIGH, the interface outputs are in high impedance. Usually CS allows the selection of each AD7653 in multicircuit applications and is held LOW in a single AD7653 design. RD is generally used to enable the conversion result on the data bus. RD BUSY DATA BUS CURRENT CONVERSION t12 02966-0-013 Figure 29. Slave Parallel Data Timing for Reading (Read after Convert Mode) CS = 0 t1 CNVST, RD PARALLEL INTERFACE The AD7653 is configured to use the parallel interface when SER/PAR is held LOW. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in Figure 29 and Figure 30, respectively. When the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. BUSY The AD7653 is configured to use the serial interface when SER/PAR is held HIGH. The AD7653 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edges of the data clock. t4 t3 DATA BUS PREVIOUS CONVERSION t12 t13 02966-0-014 Figure 30. Slave Parallel Data Timing for Reading (Read during Convert Mode) The BYTESWAP pin allows a glueless interface to an 8-bit bus. As shown in Figure 31, the LSB byte is output on D[7:0] and the MSB is output on D[15:8] when BYTESWAP is LOW. When BYTESWAP is HIGH, the LSB and MSB bytes are swapped and the LSB is output on D[15:8] and the MSB is output on D[7:0]. By connecting BYTESWAP to an address line, the 16-bit data can be read in two bytes on either D[15:8] or D[7:0]. SERIAL INTERFACE t13 CS RD BYTESWAP PINS D[15:8] PINS D[7:0] HI-Z HI-Z HIGH BYTE t12 LOW BYTE LOW BYTE t12 HIGH BYTE HI-Z t13 HI-Z 02966-A-025 Figure 31. 8-Bit Parallel Interface Rev. C | Page 20 of 26 Data Sheet AD7653 Usually, because the AD7653 is used with a fast throughput, the Master Read During Conversion mode is the most recommended serial mode. In this mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions. MASTER SERIAL INTERFACE Internal Clock The AD7653 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held LOW. The AD7653 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted, if desired. Depending on the RDC/SDIN input, the data can be read after each conversion or during the following conversion. Figure 32 and Figure 33 show the detailed timing diagrams of these two modes. RDC/SDIN = 0 EXT/INT = 0 CS, RD In Read After Conversion mode, it should be noted that unlike in other modes, the BUSY signal returns LOW after the 16 data bits are pulsed out and not at the end of the conversion phase, which results in a longer BUSY width. INVSCLK = INVSYNC = 0 t3 CNVST t28 BUSY t30 t29 t25 SYNC t14 t18 t19 t20 SCLK t24 t21 1 2 D15 D14 3 14 15 t26 16 t15 t27 SDOUT X t16 D2 D1 D0 t23 t22 02966-0-015 Figure 32. Master Serial Data Timing for Reading (Read after Convert) EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 CS, RD t1 CNVST t3 BUSY t17 t25 SYNC t14 t19 t20 t21 t15 SCLK 1 t24 2 3 14 15 t18 SDOUT X t16 t22 t26 16 t27 D15 D14 D2 D1 D0 t23 02966-0-016 Figure 33. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. C | Page 21 of 26 AD7653 Data Sheet SLAVE SERIAL INTERFACE External Clock The AD7653 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held HIGH. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both LOW, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or a discontinuous clock. A discontinuous clock can be either normally HIGH or normally LOW when inactive. Figure 34 and Figure 35 show the detailed timing diagrams of these methods. EXT/INT = 1 RD While the AD7653 is performing a bit decision, it is important that voltage transients be avoided on digital input/output pins, or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the AD7653 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that is toggling only when BUSY is LOW, or, more importantly, that it does not transition during the latter half of BUSY HIGH. RD = 0 INVSCLK = 0 BUSY t36 SCLK t35 t37 1 2 t31 3 14 15 16 17 18 t32 X SDOUT D15 t16 D14 D13 D1 D0 X15 X14 X14 X13 X1 X0 Y15 Y14 t 34 SDIN X15 t33 02966-0-017 Figure 34. Slave Serial Data Timing for Reading (Read after Convert) EXT/INT = 1 CS RD = 0 INVSCLK = 0 CNVST BUSY t3 t35 t36 t 37 SCLK 1 2 t31 14 15 16 t32 X SDOUT 3 D15 D14 D13 D1 D0 t 16 02966-0-018 Figure 35. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. C | Page 22 of 26 Data Sheet AD7653 External Clock Data Read During Conversion External Discontinuous Clock Data Read After Conversion Though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. Figure 34 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning LOW, the conversion’s result can be read while both CS and RD are LOW. Data is shifted out MSB first with 16 clock pulses and is valid on the rising and falling edges of the clock. Among the advantages of this method is the fact that conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Another advantage is the ability to read the data at any speed up to 40 MHz, which accommodates both the slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7653 provides a daisy-chain feature using the RDC/SDIN pin for cascading multiple converters together. This feature is useful for reducing component count and wiring connections when desired, as, for instance, in isolated multiconverter applications. Figure 35 shows the detailed timing diagrams of this method. During a conversion, while both CS and RD are both LOW, the result of the previous conversion can be read. The data is shifted out MSB first with 16 clock pulses, and is valid on both the rising and falling edges of the clock. The 16 bits must be read before the current conversion is complete; otherwise, RDERROR is pulsed HIGH and can be used to interrupt the host interface to prevent incomplete data reading. There is no daisy-chain feature in this mode, and the RDC/SDIN input should always be tied either HIGH or LOW. To reduce performance degradation due to digital activity, a fast discontinuous clock (at least 18 MHz when Impulse mode is used, 25 MHz when Normal mode is used, or 40 MHz when Warp mode is used) is recommended to ensure that all the bits are read during the first half of the conversion phase. It is also possible to begin to read data after conversion and continue to read the last bits after a new conversion has been initiated. This allows the use of a slower clock speed like 14 MHz in Impulse mode, 18 MHz in Normal mode, and 25 MHz in Warp mode. The concatenation of two devices is shown in Figure 36. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the edge of SCLK opposite the one used to shift out the data on SDOUT. Thus, the MSB of the upstream converter follows the LSB of the downstream converter on the next SCLK cycle. BUSY OUT BUSY BUSY AD7653 AD7653 #1 (DOWNSTREAM) #2 (UPSTREAM) RDC/SDIN SDOUT CNVST RDC/SDIN SDOUT DATA OUT CNVST CS CS SCLK SCLK SCLK IN CS IN CNVST IN 02966-0-019 Figure 36. Two AD7653s in a Daisy-Chain Configuration Rev. C | Page 23 of 26 AD7653 Data Sheet MICROPROCESSOR INTERFACING The AD7653 is ideally suited for traditional dc measurement applications supporting a microprocessor, and for ac signal processing applications interfacing to a digital signal processor. The AD7653 is designed to interface either with a parallel 8-bit or 16-bit wide interface, or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7653 to prevent digital noise from coupling into the ADC. The following section discusses the use of an AD7653 with an SPI equipped DSP, the ADSP-2191M. face (SPI) on the ADSP-2191M is configured for master mode—(MSTR) = 1, Clock Polarity bit (CPOL) = 0, Clock Phase bit (CPHA) = 1, and SPI Interrupt Enable (TIMOD) = 00—by writing to the SPI control register (SPICLTx). To meet all timing requirements, the SPI clock should be limited to 17 Mbps, which allows it to read an ADC result in less than 1 µs. When a higher sampling rate is desired, use of one of the parallel interface modes is recommended. DVDD AD7653* ADSP-2191M* SER/PAR SPI Interface (ADSP-2191M) Figure 37 shows an interface diagram between the AD7653 and the SPI equipped ADSP-2191M. To accommodate the slower speed of the DSP, the AD7653 acts as a slave device and data must be read after conversion. This mode also allows the daisychain feature. The convert command can be initiated in response to an internal timer interrupt. The reading process can be initiated in response to the end-of-conversion signal (BUSY going LOW) using an interrupt line of the DSP. The serial inter- Rev. C | Page 24 of 26 EXT/INT BUSY RD INVSCLK CS SDOUT SCLK CNVST PFx SPIxSEL (PFx) MISOx SCKx PFx or TFSx * ADDITIONAL PINS OMITTED FOR CLARITY 02966-0-021 Figure 37. Interfacing the AD7653 to an SPI Interface Data Sheet AD7653 APPLICATION HINTS BIPOLAR AND WIDER INPUT RANGES In some applications, it is desirable to use a bipolar or wider analog input range such as ±10 V, ±5 V, or 0 V to 5 V. Although the AD7653 has only one unipolar range, simple modifications of input driver circuitry allow bipolar and wider input ranges to be used without any performance degradation. Figure 38 shows a connection diagram that allows this. Component values required and resulting full-scale ranges are shown in Table 8. When desired, accurate gain and offset can be calibrated by acquiring a ground and voltage reference using an analog multiplexer (U2) as shown in Figure 38. The power supply lines to the AD7653 should use as large a trace as possible to provide low impedance paths and to reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supply’s impedance presented to the AD7653, and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed on each power supply pin—AVDD, DVDD, and OVDD—close to, and ideally right up against these pins and their corresponding ground pins. Additionally, low ESR 10 µF capacitors should be located near the ADC to further reduce low frequency ripple. CF R1 R2 ANALOG INPUT 15Ω U1 IN 2.7nF AD7653 U2 R3 R4 100nF INGND REF CREF REFGND 02966-0-022 Figure 38. Using the AD7653 in 16-Bit Bipolar and/or Wider Input Ranges Table 8. Component Values and Input Ranges Input Range ±10 V ±5 V 0 V to –5 V R1 (Ω) 500 500 500 R2 (kΩ) 4 2 1 R3 (kΩ) 2.5 2.5 None Running digital lines under the device should be avoided since these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7653 to avoid noise coupling. Fast switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other to will reduce the effect of crosstalk through the board. R4 (kΩ) 2 1.67 0 LAYOUT The AD7653 has very good immunity to noise on the power supplies. However, care should still be taken with regard to grounding layout. The printed circuit board that houses the AD7653 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be separated easily. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7653, or as close as possible to the AD7653. If the AD7653 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close as possible to the AD7653. The DVDD supply of the AD7653 can be a separate supply or can come from the analog supply AVDD or the digital interface supply OVDD. When the system digital supply is noisy or when fast switching digital signals are present, if no separate supply is available, the user should connect DVDD to AVDD through an RC filter (see Figure 22), and the system supply to OVDD and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. The AD7653 has five different ground pins: INGND, REFGND, AGND, DGND, and OGND. INGND is used to sense the analog input signal. REFGND senses the reference voltage and, because it carries pulsed currents, should be a low impedance return to the reference. AGND is the ground to which most internal ADC analog signals are referenced; it must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. Rev. C | Page 25 of 26 AD7653 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 9.20 9.00 SQ 8.80 1.60 MAX 37 48 36 1 PIN 1 0.15 0.05 7.20 7.00 SQ 6.80 TOP VIEW 1.45 1.40 1.35 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY SEATING PLANE (PINS DOWN) 25 12 13 24 0.27 0.22 0.17 VIEW A 0.50 BSC LEAD PITCH 051706-A VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 39. 48-Lead Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 0.30 0.23 0.18 0.60 MAX 0.60 MAX 37 48 1 36 PIN 1 INDICATOR 6.85 6.75 SQ 6.65 0.50 REF 5.25 5.10 SQ 4.95 EXPOSED PAD 12 25 0.50 0.40 0.30 TOP VIEW 1.00 0.85 0.80 12° MAX SIDE VIEW PKG-001049 13 24 BOTTOM VIEW 0.20 MIN 5.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 11-13-2017-B 7.10 7.00 SQ 6.90 Figure 40. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.85 mm Package Height (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model1 AD7653ASTZ AD7653ASTZRL AD7653ACPZ AD7653ACPZRL Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 48-Lead Quad Flat Package [LQFP] 48-Lead Quad Flat Package [LQFP] 48-Lead Lead Frame Chip Scale Package [LFCSP] 48-Lead Lead Frame Chip Scale Package [LFCSP] 1 Z = RoHS Compliant Part. ©2003–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02966-0-12/17(C) Rev. C | Page 26 of 26 Package Option ST-48 ST-48 CP-48-1 CP-48-1