Features • Fast Read Access Time – 45 ns • Low-Power CMOS Operation • • • • • • • • • – 100 µA Max Standby – 30 mA Max Active at 5 MHz JEDEC Standard Packages – 40-lead PDIP – 44-lead PLCC – 40-lead VSOP Direct Upgrade from 512K (AT27C516) EPROM 5V ± 10% Power Supply High-Reliability CMOS Technology – 2000V ESD Protection – 200 mA Latchup Immunity Rapid Programming Algorithm – 100 µs/Word (Typical) CMOS and TTL Compatible Inputs and Outputs Integrated Product Identification Code Industrial and Automotive Temperature Ranges Green (Pb/Halide-free) Packaging Option 1-Megabit (64K x 16) OTP EPROM AT27C1024 1. Description The AT27C1024 is a low-power, high-performance 1,048,576 bit one-time programmable read-only memory (OTP EPROM) organized 64K by 16 bits. It requires only one 5V power supply in normal read mode operation. Any word can be accessed in less than 45 ns, eliminating the need for speed reducing WAIT states. The by-16 organization make this part ideal for high-performance 16- and 32-bit microprocessor systems. In read mode, the AT27C1024 typically consumes 15 mA. Standby mode supply current is typically less than 10 µA. The AT27C1024 is available in industry-standard JEDEC-approved one-time programmable (OTP) plastic PDIP, PLCC, and VSOP packages. The device features two-line control (CE, OE) to eliminate bus contention in high-speed systems. With high density 64K word storage capability, the AT27C1024 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. Atmel’s AT27C1024 have additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/word. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages. 0019M–EPROM–12/07 2. Pin Configurations Pin Name Function A0 - A15 Addresses O0 - O15 Outputs CE Chip Enable OE Output Enable PGM Program Strobe NC No Connect 40-lead PDIP Top View 2.2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC PGM NC A15 A14 A13 A12 A11 A10 A9 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 O12 O11 O10 O9 O8 GND NC O7 O6 O5 O4 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5 40-lead VSOP Top View – Type 1 A9 A10 A11 A12 A13 A14 A15 NC PGM VCC VPP CE O15 O14 O13 O12 O11 O10 O9 O8 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 44-lead PLCC Top View O3 O2 O1 O0 OE NC A0 A1 A2 A3 A4 VPP CE O15 O14 O13 O12 O11 O10 O9 O8 GND O7 O6 O5 O4 O3 O2 O1 O0 OE 2.3 O13 O14 O15 CE VPP NC VCC PGM NC A15 A14 2.1 6 5 4 3 2 1 44 43 42 41 40 Both GND pins must be connected. 18 19 20 21 22 23 24 25 26 27 28 Note: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 OE O0 O1 A2 O3 O4 O5 O6 O7 GND AT27C1024 0019M–EPROM–12/07 AT27C1024 3. System Considerations Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. 4. Block Diagram 5. Absolute Maximum Ratings* Temperature Under Bias.............................. -55° C to + 125° C Storage Temperature ................................... -65° C to + 150° C Voltage on Any Pin with Respect to Ground ........................................-2.0V to + 7.0V(1) Voltage on A9 with Respect to Ground .....................................-2.0V to + 14.0V(1) *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. VPP Supply Voltage with Respect to Ground ......................................-2.0V to + 14.0V(1) Note: 1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns. 3 0019M–EPROM–12/07 6. Operating Modes Mode/Pin CE OE PGM Ai VPP Outputs (1) Read VIL VIL X Ai X DOUT Output Disable X VIH X X X High Z Standby VIH X X X X(5) High Z Rapid Program(2) VIL VIH VIL Ai VPP DIN PGM Verify VIL VIL VIH Ai VPP DOUT PGM Inhibit VIH X X X VPP High Z Product Identification(4) VIL VIL X A9 = VH(3) A0 = VIH or VIL A1 - A15 = VIL VCC Identification Code Notes: 1. X can be VIL or VIH. 2. Refer to Programming Characteristics. 3. VH = 12.0 ± 0.5V. 4. Two identifier words may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled low (VIL) to select the Manufacturer’s Identification word and high (VIH) to select the Device Code word. 5. Standby VCC current (ISB) is specified with VPP = VCC. VCC > VPP will cause a slight increase in ISB. 7. DC and AC Operating Conditions for Read Operation AT27C1024 Operating Temp. (Case) Ind. -45 -70 -40° C - 85° C -40° C - 85° C 5V ± 10% 5V ± 10% Auto. VCC Power Supply 8. DC and Operating Characteristics for Read Operation Symbol Parameter Condition ILI Input Load Current VIN = 0V to VCC ILO Output Leakage Current IPP1 (2) VPP(1)) Read/Standby Current Max Units Ind. ±1 µA Auto. ±5 µA Ind. ±5 µA Auto. ±10 µA VPP = VCC 10 µA ISB1 (CMOS), CE = VCC ± 0.3V 100 µA ISB2 (TTL), CE = 2.0 to VCC + 0.5V 1 mA f = 5 MHz, IOUT = 0 mA, CE = VIL 30 mA VOUT = 0V to VCC Min ISB VCC(1) Standby Current ICC VCC Active Current VIL Input Low Voltage -0.6 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V VOL Output Low Voltage IOL = 2.1 mA 0.4 V VOH Output High Voltage IOH = -400 µA Notes: 2.4 V 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP.. 2. VPP may be connected directly to VCC, except during programming. The supply current would then be the sum of ICC and IPP.. 4 AT27C1024 0019M–EPROM–12/07 AT27C1024 9. AC Characteristics for Read Operation AT27C1024 -45 Symbol Parameter Condition tACC(1) Address to Output Delay CE = OE = VIL tCE(1) CE to Output Delay tOE(1) OE to Output Delay tDF(1) OE or CE High to Output Float, Whichever Occurred First tOH Output Hold from Address, CE or OE, Whichever Occurred First Note: Min -70 Max Max Units 45 70 ns OE = VIL 45 70 ns CE = VIL 20 25 ns 20 25 ns 7 Min 7 ns 1. See AC Waveforms for Read Operation. 10. AC Waveforms for Read Operation(1) Notes: 1. Timing measurement reference level is 1.5V for -45. Input AC drive levels are VIL = 0.0V and VIH = 3.0V. Timing measurement reference levels for all other speed grades are VOL = 0.8V and VOH = 2.0V. Input AC drive levels are VIL = 0.45V and VIH = 2.4V. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE. 3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC. 4. This parameter is only sampled and is not 100% tested. 5. Output float is defined as the point when data is no longer driven. 5 0019M–EPROM–12/07 11. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol CIN COUT Note: Typ Max Units Conditions 4 10 pF VIN = 0V 8 12 pF VOUT = 0V 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. 12. Input Test Waveforms and Measurement Levels For -45 devices only: tR, tF < 5 ns (10% to 90%) For -70 devices only: tR, tF < 20 ns (10% to 90%) 13. Output Test Load Note: 6 1. CL = 100 pF including jig capacitance except -45 devices, where CL = 30 pF. AT27C1024 0019M–EPROM–12/07 AT27C1024 14. Programming Waveforms(1) Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH. 2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer. 3. When programming the AT27C1024 a 0.1 µF capacitor is required across VPP and ground to suppress sputious voltage transients. 15. DC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V Limits Symbol Parameter Test Conditions ILI Input Load Current VIN = VIL, VIH VIL Input Low Level VIH Input High Level VOL Output Low Voltage IOL = 2.1 mA VOH Output High Voltage IOH = -400 µA ICC2 VCC Supply Current (Program and Verify) IPP2 VPP Supply Current VID A9 Product Identification Voltage Min Max Units ±10 µA -0.6 0.8 V 2.0 VCC + 0.1 V 0.4 V 2.4 CE = PGM = VIL 11.5 V 50 mA 30 mA 12.5 V 7 0019M–EPROM–12/07 16. AC Programming Characteristics TA = 25 ± 5° C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V Limits Test Conditions(1) Symbol Parameter tAS Address Setup Time 2 µs tCES CE Setup Time 2 µs tOES OE Setup Time 2 µs tDS Data Setup Time 2 µs tAH Address Hold Time 0 µs tDH Data Hold Time 2 µs Input Rise and Fall Times (10% to 90%) 20 ns Input Pulse Levels 0.45V to 2.4V OE High to Output Float Delay tDFP tVPS VPP Setup Time tVCS VCC Setup Time (2) Output Timing Reference Level 0.8V to 2.0V (3) PGM Program Pulse Width tOE Data Valid from OE tPRT VPP Pulse Rise Time During Programming Max 0 Input Timing Reference Level 0.8V to 2.0V tPW Notes: Min Units 130 ns 2 µs 2 µs 95 105 µs 150 ns 50 ns 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven – see timing diagram. 3. Program Pulse width tolerance is 100 µsec ± 5%. 17. Atmel’s AT27C1024 Integrated Product Identification Code Pins A0 O15-O8 O7 O6 O5 O4 O3 O2 O1 O0 Hex Data Manufacturer 0 0 0 0 0 1 1 1 1 0 001E Device Type 1 0 1 1 1 1 0 0 0 1 00F1 Codes 8 AT27C1024 0019M–EPROM–12/07 AT27C1024 18. Rapid Programming Algorithm A 100 µs PGM pulse width is used to program. The address is set to the first location. VCC is raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 100 µs PGM pulse without verification. Then a verification/reprogramming loop is executed for each address. In the event a word fails to pass verification, up to 10 successive 100 µs pulses are applied with a verification after each pulse. If the word fails to verify after 10 pulses have been applied, the part is considered failed. After the word verifies properly, the next address is selected until all have been checked. VPP is then lowered to 5.0V and VCC to 5.0V. All words are read again and compared with the original data to determine if the device passes or fails. 9 0019M–EPROM–12/07 19. Ordering Information 19.1 Standard Package ICC (mA) tACC (ns) Active Standby 45 30 70 30 Note: 19.2 tACC (ns) Ordering Code Package 0.1 AT27C1024-45JI AT27C1024-45PI AT27C1024-45VI 44J 40P6 40V(1) Industrial (-40° C to 85° C) 0.1 AT27C1024-70JI AT27C1024-70PI AT27C1024-70VI 44J 40P6 40V(1) Industrial (-40° C to 85° C) Not recommended for new designs. Use Green package option. Green Package (Pb/Halide-free) ICC (mA) Active Standby Ordering Code Package 44J 40P6 Industrial (-40° C to 85° C) 44J 40P6 Industrial (-40° C to 85° C) 45 30 0.1 AT27C1024-45JU AT27C1024-45PU 70 30 0.1 AT27C1024-70JU AT27C1024-70PU Note: Operation Range Operation Range 1. The 40-lead VSOP package is not recommended for new designs. Package Type 44J 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 40V 40-Lead, Plastic Thin Small Outline Package (VSOP) 10 x 14 mm 10 AT27C1024 0019M–EPROM–12/07 AT27C1024 20. Packaging Information 20.1 44J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) IDENTIFIER E1 D2/E2 B1 E B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. SYMBOL MIN NOM MAX A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 17.399 – 17.653 D1 16.510 – 16.662 E 17.399 – 17.653 E1 16.510 – 16.662 D2/E2 14.986 – 16.002 B 0.660 – 0.813 B1 0.330 – 0.533 e NOTE Note 2 Note 2 1.270 TYP 10/04/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. REV. 44J B 11 0019M–EPROM–12/07 20.2 40P6 – PDIP D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 SYMBOL eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). e NOTE Note 2 Note 2 2.540 TYP 09/28/01 R 12 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B AT27C1024 0019M–EPROM–12/07 AT27C1024 20.3 40V – VSOP PIN 1 0º ~ 8º c Pin 1 Identifier D1 D L b e L1 A2 E A GAGE PLANE SEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) A1 MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 13.80 14.00 14.20 D1 12.30 12.40 12.50 Note 2 E 9.90 10.00 10.10 Note 2 L 0.50 0.60 0.70 SYMBOL Notes: 1. This package conforms to JEDEC reference MO-142, Variation CA. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e NOTE 0.50 BASIC 10/18/01 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 40V, 40-lead (10 x 14 mm Package) Plastic Thin Small Outline Package, Type I (VSOP) DRAWING NO. REV. 40V B 13 0019M–EPROM–12/07 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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