Cypress CY29351AXI 2.5v or 3.3v, 200 mhz, 9-output zero delay Datasheet

PRELIMINARY
CY29351
2.5V or 3.3V, 200 MHz,
9-Output Zero Delay
Features
Functional Description
■
Output frequency range: 25 MHz to 200 MHz
■
Input frequency range: 25 MHz to 200 MHz
The CY29351 is a low voltage high performance 200 MHz
PLL-based zero delay buffer designed for high speed clock distribution applications.
■
2.5V or 3.3V operation
■
Split 2.5V/3.3V outputs
■
±2.5% max Output duty cycle variation
■
9 clock outputs: Drive up to 18 clock lines
■
Two reference clock inputs: LVPECL or LVCMOS
■
150-ps max output-output skew
■
Phase-locked loop (PLL) bypass mode
■
Spread Aware™
■
Output enable/disable
■
Pin-compatible with MPC9351
■
Industrial temperature range: –40°C to +85°C
■
32-pin 1.0-mm TQFP package
The CY29351 features LVPECL and LVCMOS reference clock
inputs and provides 9 outputs partitioned in four banks of one,
one, two, and five outputs. Bank A divides the VCO output by two
or four while the other banks divide by four or eight per SEL(A:D)
settings (Table 3, “Function Table,” on page 3). These dividers
allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each
LVCMOS compatible output can drive 50Ω series or parallel
terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the
device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range of
output frequencies from 25 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO is running at multiples of
the input reference clock set by the feedback divider (Table 2,
“Frequency Table,” on page 3).
When PLL_EN# is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
SELA
PLL_EN
REF_SEL
TCLK
PECL_CLK
Phase
Detector
VCO
200 500 MHz
LPF
FB_IN
SELB
÷2 / ÷4
QA
÷4 / ÷8
QB
÷4 / ÷8
QC0
QC1
SELC
OE#
÷4 / ÷8
QD0
QD1
SELD
QD2
QD3
QD4
Cypress Semiconductor Corporation
Document Number: 38-07475 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 21, 2008
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PRELIMINARY
CY29351
Pinouts
REF_SEL
PLL_EN
TCLK
VSS
QA
VDDQB
QB
VSS
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
9
10
11
12
13
14
15
16
OE#
VDD
QD4
VSS
QD3
VDDQD
QD2
C Y29351
PECL_CLK#
A VD D
F B _IN
SE LA
SE LB
SELC
SELD
AVSS
PEC L_C LK
32
Figure 1. Pin Diagram - 32 Pin TQFP Package
QC0
VD D Q C
QC1
VSS
QD0
VD D Q D
QD1
VSS
Table 1. Pin Definitions - 32 Pin TQFP Package
Pin[1]
Name
IO
Type
I, PU
Description
8
PECL_CLK
9
PECL_CLK# I, PU/PD
LVPECL LVPECL reference clock input. Weak pull up to VDD/2.
30
TCLK
LVCMOS LVCMOS/LVTTL reference clock input
28
QA
I, PD
O
LVPECL LVPECL reference clock input
LVCMOS Clock output bank A
26
QB
O
LVCMOS Clock output bank B
22, 24
QC(1,0)
O
LVCMOS Clock output bank C
12, 14, 16, 18, 20 QD(4:0)
O
LVCMOS Clock output bank D
2
FB_IN
I, PD
LVCMOS Feedback clock input. Connect to an output for normal operation. This
input should be at the same voltage rail as input reference clock
10
OE#
I, PD
LVCMOS Output enable/disable input
31
PLL_EN
I, PU
LVCMOS PLL enable/disable input
32
REF_SEL
I, PD
LVCMOS Reference select input
3, 4, 5, 6
SEL(A:D)
I, PD
LVCMOS Frequency select input, bank (A:D)
27
VDDQB
Supply
VDD
2.5V or 3.3V power supply for bank B output clock[2,3]
23
VDDQC
Supply
VDD
2.5V or 3.3V power supply for bank C output clocks[2,3]
15, 19
VDDQD
Supply
VDD
2.5V or 3.3V power supply for bank D output clocks[2,3]
1
AVDD
Supply
VDD
2.5V or 3.3V power supply for PLL[5,6]
11
VDD
Supply
VDD
2.5V or 3.3V power supply for core, inputs, and bank A output clock[2,3]
7
AVSS
Supply
Ground
Analog ground
Supply
Ground
Common ground
13, 17, 21, 25, 29 VSS
Notes
1. PU = Internal pull up, PD = Internal pull down.
2. A 0.1-μF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins, the
high-frequency filtering characteristics are cancelled by the lead inductance of the traces.
3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD power supply pins.
4. VCMR (DC) is the crossing point of the differential input signal. Normal operation is obtained when the crossing point is within the VCMR range and the input swing
is within the VPP (DC) specification.
5. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50 Ω series terminated transmission
lines.
6. Inputs have pull up or pull down resistors that affect the input current.
Document Number: 38-07475 Rev. *B
Page 2 of 10
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PRELIMINARY
CY29351
Table 2. Frequency Table
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
Feedback Output Divider
VCO
÷2
Input Clock * 2
100 MHz to 200 MHz
100 MHz to 190 MHz
÷4
Input Clock * 4
50 MHz to 125 MHz
50 MHz to 95 MHz
÷8
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 47.5 MHz
Table 3. Function Table
Control
Default
0
1
REF_SEL
0
PCLK
TCLK
PLL_EN
1
Bypass mode, PLL disabled. The input clock
connects to the output dividers
PLL enabled. The VCO output connects to the output
dividers
OE#
0
Outputs enabled
Outputs disabled (three-state), VCO running at its
minimum frequency
SELA
0
÷ 2 (bank A)
÷ 4 (bank A)
SELB
0
÷ 4 (bank B)
÷ 8 (bank B)
SELC
0
÷ 4 (bank C)
÷ 8 (bank C)
SELD
0
÷ 4 (bank D)
÷ 8 (bank D)
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
DC supply voltage
–0.3
5.5
V
VDD
DC operating voltage
Functional
2.375
3.465
V
VIN
DC input voltage
Relative to VSS
–0.3
VDD + 0.3
V
DC output voltage
Relative to VSS
–0.3
VDD + 0.3
V
–
VDD ÷ 2
V
Functional
200
–
mA
VOUT
VTT
Output termination voltage
LU
Latch-up immunity
RPS
Power supply ripple
Ripple frequency < 100 kHz
–
150
mVp-p
TS
Temperature, storage
Non Functional
–65
+150
°C
TA
Temperature, operating ambient
Functional
–40
+85
°C
TJ
Temperature, junction
Functional
–
+150
°C
ØJC
Dissipation, junction to case
Functional
42
°C/W
ØJA
Dissipation, junction to ambient
Functional
105
°C/W
ESDH
FIT
ESD protection (human body model)
Failure in time
Document Number: 38-07475 Rev. *B
2000
Manufacturing test
–
10
Volts
ppm
Page 3 of 10
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PRELIMINARY
CY29351
DC Electrical Specifications
(VDD = 2.5V ± 5%, TA = –40°C to +85°C)
Parameter
Description
Condition
VIL
Input voltage, low
LVCMOS
Min
Typ.
Max
Unit
–
–
0.7
V
VIH
Input voltage, high
LVCMOS
1.7
–
VDD+0.3
V
VPP
Peak-Peak input voltage
LVPECL
250
–
1000
mV
VCMR
Common mode range[4]
LVPECL
1.0
–
VDD – 0.6
V
VOL
Output voltage, low[5]
IOL = 15mA
–
–
0.6
V
VOH
Output voltage, high[5]
IOH = –15mA
1.8
–
–
V
IIL
Input current, low[6]
VIL = VSS
–
–
–100
μA
IIH
Input current, high[6]
VIL = VDD
–
–
100
μA
IDDA
PLL supply current
AVDD only
–
5
10
mA
IDDQ
Quiescent supply current
All VDD pins except AVDD
–
–
7
mA
IDD
Dynamic supply current
Outputs loaded at 100 MHz
–
180
–
mA
Outputs loaded at 200 MHz
–
210
–
CIN
Input pin capacitance
–
4
–
pF
Output impedance
14
18
22
Ω
Min
Typ.
Max
Unit
–
–
0.8
V
ZOUT
DC Electrical Specifications
(VDD = 3.3V ± 5%, TA = –40°C to +85°C)
Parameter
Description
VIL
Input voltage, low
Condition
LVCMOS
VIH
Input voltage, high
LVCMOS
2.0
–
VDD + 0.3
V
VPP
Peak-Peak input voltage
LVPECL
250
–
1000
mV
VCMR
Common mode range[4]
LVPECL
1.0
–
VDD – 0.6
V
VOL
Output Voltage, Low[5]
IOL = 24 mA
–
–
0.55
V
VOH
Output voltage, high[5]
IOL = 12 mA
IOH = –24 mA
–
–
0.30
2.4
–
–
V
IIL
Input current,
VIL = VSS
–
–
–100
μA
IIH
Input current, high[6]
VIL = VDD
–
–
100
μA
IDDA
PLL supply current
AVDD only
–
5
10
mA
IDDQ
Quiescent supply current
All VDD pins except AVDD
–
–
7
mA
Dynamic supply current
Outputs loaded at 100 MHz
–
270
–
mA
Outputs loaded at 200 MHz
–
300
–
IDD
CIN
ZOUT
low[6]
Input pin capacitance
–
4
–
pF
Output impedance
12
15
18
Ω
Document Number: 38-07475 Rev. *B
Page 4 of 10
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PRELIMINARY
CY29351
AC Electrical Specifications
(VDD = 2.5V ± 5%, TA = –40°C to +85°C)[7]
Parameter
Description
fVCO
VCO frequency
fin
Input frequency
Condition
Min
Typ.
Max
Unit
200
–
380
MHz
÷2 feedback
100
–
190
MHz
÷4 feedback
50
–
95
÷8 feedback
25
–
47.5
Bypass mode (PLL_EN = 0)
0
–
200
frefDC
Input duty cycle
25
–
75
%
VPP
Peak-Peak input voltage
LVPECL
500
–
1000
mV
VCMR
Common mode range[8]
LVPECL
1.2
–
VDD – 0.6
V
tr , tf
TCLK input rise/fall time
0.7V to 1.7V
–
–
1.0
ns
fMAX
Maximum output frequency
÷2 output
100
–
190
MHz
÷4 output
50
–
95
÷8 output
DC
Output duty cycle
tr , tf
Output rise/fall times
t(φ)
fMAX < 100 MHz
25
–
47.5
47.5
–
52.5
%
fMAX > 100 MHz
45
–
55
0.6V to 1.8V
0.1
–
1.0
ns
Propagation delay (static phase offset) TCLK to FB_IN
–100
–
100
ps
PCLK to FB_IN
–100
–
100
tsk(O)
Output-to-Output skew
–
–
150
ps
tPLZ, HZ
Output disable time
–
–
10
ns
tPZL, ZH
Output enable time
BW
PLL closed loop bandwidth (–3dB)
tJIT(CC)
tJIT(PER)
Cycle-to-Cycle jitter
Period jitter
–
–
10
ns
÷2 feedback
–
2.2
–
MHz
÷4 feedback
–
0.85
–
÷8 feedback
–
0.6
–
Same frequency
–
–
150
Multiple frequencies
–
–
250
Same frequency
–
–
100
Multiple frequencies
–
–
175
ps
ps
tJIT(φ)
IO phase jitter
–
175
–
ps
tLOCK
Maximum PLL lock time
–
–
1
ms
Notes
7. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.
8. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies
within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(φ).
Document Number: 38-07475 Rev. *B
Page 5 of 10
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PRELIMINARY
CY29351
AC Electrical Specifications
(VDD = 3.3V ± 5%, TA = –40°C to +85°C)[7]
Parameter
Description
fVCO
VCO frequency
fin
Input frequency
Condition
Min
Typ.
Max
Unit
200
–
500
MHz
MHz
÷2 feedback
100
–
200
÷4 feedback
50
–
125
÷8 feedback
25
–
62.5
Bypass mode (PLL_EN = 0)
0
–
200
frefDC
Input duty cycle
25
–
75
%
VPP
Peak-Peak input voltage
LVPECL
500
–
1000
mV
VCMR
Common mode range[8]
LVPECL
1.2
–
VDD – 0.9
V
tr , tf
TCLK input rise/fall time
0.8V to 2.0V
–
–
1.0
ns
fMAX
Maximum output frequency
÷2 output
100
–
200
MHz
÷4 output
50
–
125
÷8 output
fMAX < 100 MHz
25
–
62.5
47.5
–
52.5
DC
Output duty cycle
fMAX > 100 MHz
45
–
55
tr , tf
Output rise/fall times
0.8V to 2.4V
0.1
–
1.0
ns
t(φ)
Propagation delay (static phase
offset)
TCLK to FB_IN, same VDD
–100
–
100
ps
PCLK to FB_IN, same VDD
–100
–
100
%
tsk(O)
Output-to-Output skew
Banks at same voltage
–
–
150
ps
tsk(B)
Bank-to-Bank skew
Banks at different voltages
–
–
350
ps
tPLZ, HZ
Output disable time
–
–
10
ns
tPZL, ZH
Output enable time
–
–
10
ns
BW
PLL closed loop bandwidth (–3dB)
MHz
÷2 feedback
–
2.2
–
÷4 feedback
–
0.85
–
÷8 feedback
–
0.6
–
tJIT(CC)
Cycle-to-Cycle jitter
Same frequency
–
–
150
Multiple frequencies
–
–
250
tJIT(PER)
Period jitter
Same frequency
–
–
100
Multiple frequencies
–
–
150
tJIT(φ)
IO phase jitter
IO same VDD
–
175
–
ps
tLOCK
Maximum PLL lock time
–
–
1
ms
Document Number: 38-07475 Rev. *B
ps
ps
Page 6 of 10
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PRELIMINARY
CY29351
Figure 2. LVCMOS_CLK AC Test Reference for VDD = 3.3V / 2.5V
Zo = 50 ohm
P u ls e
G e n e ra to r
Z = 50 ohm
Zo = 50 ohm
R T = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 3. PECL_CLK AC Test Reference for VDD = 3.3V / 2.5V
Zo = 50 ohm
D iffe re n tia l
P u ls e
G e n e ra to r
Z = 50 ohm
Zo = 50 ohm
Zo = 50 ohm
R T = 50 ohm
VTT
R T = 50 ohm
VTT
Figure 4. LVPECL Propagation Delay t(f), static phase offset
PECL_CLK
VPP
PECL_CLK
VCMR
VDD
FB_IN
VDD/2
t(φ)
GND
Figure 5. LVCMOS Propagation Delay t(φ), static phase offset
VDD
LVCMOS_CLK
VDD/2
GND
VDD
FB_IN
VDD/2
t(φ)
Document Number: 38-07475 Rev. *B
GND
Page 7 of 10
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PRELIMINARY
CY29351
Figure 6. Output Duty Cycle (DC)
VDD
VDD/2
tP
GND
T0
DC = tP / T0 x 100%
Figure 7. Output-to-Output Skew, tsk(O)
VDD
VDD/2
GND
VDD
VDD/2
tSK(O)
GND
Ordering Information
Part Number
Package Type
Product Flow
Pb-free
CY29351AXI
32-pin TQFP
Industrial, –40°C to 85°C
CY29351AXIT
32-pin TQFP – tape and reel
Industrial, –40°C to 85°C
Document Number: 38-07475 Rev. *B
Page 8 of 10
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PRELIMINARY
CY29351
Package Drawing and Dimension
Figure 8. 32-Pin Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm
51-85063-*B
Document Number: 38-07475 Rev. *B
Page 9 of 10
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PRELIMINARY
CY29351
Document History Page
Document Title: CY29351 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer
Document Number: 38-0747
REV.
ECN No.
Issue Date
Orig. of Change
**
128152
07/07/03
RGL
New Data Sheet
*A
245448
See ECN
RGL
Re-worded Select Function Descriptions in table 2.
*B
2001108
See ECN
Description of Change
Corrected package thickness in Figure 7 from 1.4mm to 1.0mm. In Ordering
PYG/KVM/AESA
Information, removed leaded and added Pb-free parts.
© Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-07475 Rev. *B
Revised January 21, 2008
Page 10 of 10
Spread Aware™ is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders.
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