4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA and AC Excitation AD7195 FEATURES Chromatography PLC/DCS analog input modules Data acquisition Medical and scientific instrumentation AC or DC sensor excitation RMS noise: 8.5 nV at 4.7 Hz (gain = 128) 16 noise-free bits at 2.4 kHz (gain = 128) Up to 22.5 noise-free bits (gain = 1) Offset drift: 5 nV/°C Gain drift: 1 ppm/°C Specified drift over time 2 differential/4 pseudo differential input channels Automatic channel sequencer Programmable gain (1 to 128) Output data rate: 4.7 Hz to 4.8 kHz Internal or external clock Simultaneous 50 Hz/60 Hz rejection Power supply AVDD: 4.75 V to 5.25 V DVDD: 2.7 V to 5.25 V Current: 6 mA Temperature range: –40°C to +105°C Package: 32-lead LFCSP GENERAL DESCRIPTION The AD7195 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC. The AD7195 contains ac excitation, which is used to remove dc-induced offsets from bridge sensors. The device can be configured to have two differential inputs or four pseudo differential inputs. The on-chip channel sequencer allows several channels to be enabled, and the AD7195 sequentially converts on each enabled channel. This simplifies communication with the part. The on-chip 4.92 MHz clock can be used as the clock source to the ADC or, alternatively, an external clock or crystal can be used. The output data rate from the part can be varied from 4.7 Hz to 4.8 kHz. INTERFACE The device has two digital filter options. The choice of filter affects the rms noise/noise-free resolution at the programmed output data rate, the settling time, and the 50 Hz/60 Hz rejection. For applications that require all conversions to be settled, the AD7195 includes a zero latency feature. 3-wire serial SPI, QSPI™, MICROWIRE™, and DSP compatible Schmitt trigger on SCLK APPLICATIONS Weigh scales Strain gage transducers Pressure measurement Temperature measurement The part operates with a 5 V analog power supply and a digital power supply from 2.7 V to 5.25 V. It consumes a current of 6 mA. It is housed in a 32-lead LFCSP package. FUNCTIONAL BLOCK DIAGRAM AVDD AGND DVDD DGND REFIN(+) REFIN(–) REFERENCE DETECT AIN1 AIN2 AIN3 AIN4 AVDD MUX PGA AINCOM SERIAL INTERFACE AND CONTROL LOGIC Σ-Δ ADC DOUT/RDY DIN SCLK CS SYNC BPDSW AGND AC EXCITATION CLOCK AD7195 ACX1 ACX1 CLOCK CIRCUITRY ACX2 ACX2 MCLK1 MCLK2 08771-001 TEMP SENSOR Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. AD7195* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS TOOLS AND SIMULATIONS View a parametric search of comparable parts. • Download the Active Functional Model to evaluate and debug AD719x EVALUATION KITS • AD7195 Evaluation Board REFERENCE MATERIALS Tutorials DOCUMENTATION Application Notes • AN-1069: Zero Latency for the AD7190, AD7192, AD7193, AD7194, and AD7195 • Tutorial on Technical and Performance Benefits of AD719x Family DESIGN RESOURCES • AN-1084: Channel Switching: AD7190, AD7192, AD7193, AD7194, AD7195 • AD7195 Material Declaration • AN-1131: Chopping on the AD7190, AD7192, AD7193, AD7194, and AD7195 • Quality And Reliability • AN-1264: Precision Signal Conditioning for High Resolution Industrial Applications Data Sheet • AD7195: 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA and AC Excitation User Guides • UG-257: Evaluation Board for the AD7195, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC SOFTWARE AND SYSTEMS REQUIREMENTS • AD7190 - Microcontroller No-OS Driver • AD7192 IIO High Precision ADC Linux Driver • PCN-PDN Information • Symbols and Footprints DISCUSSIONS View all AD7195 EngineerZone Discussions. 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AD7195 TABLE OF CONTENTS Features .............................................................................................. 1 Overview ..................................................................................... 25 Interface ............................................................................................. 1 Analog Input Channel ............................................................... 26 Applications ....................................................................................... 1 PGA .............................................................................................. 26 General Description ......................................................................... 1 Reference ..................................................................................... 26 Functional Block Diagram .............................................................. 1 Reference Detect ......................................................................... 26 Revision History ............................................................................... 2 Bipolar/Unipolar Configuration .............................................. 27 Specifications..................................................................................... 3 Data Output Coding .................................................................. 27 Timing Characteristics ................................................................ 6 Burnout Currents ....................................................................... 27 Absolute Maximum Ratings............................................................ 8 AC Excitation .............................................................................. 27 Thermal Resistance ...................................................................... 8 Channel Sequencer .................................................................... 28 ESD Caution .................................................................................. 8 Digital Interface .......................................................................... 28 Pin Configuration and Function Descriptions ............................. 9 Reset ............................................................................................. 32 Typical Performance Characteristics ........................................... 11 System Synchronization ............................................................ 32 RMS Noise and Resolution............................................................ 13 Clock ............................................................................................ 32 4 Enable Parity ............................................................................... 32 3 Temperature Sensor ................................................................... 32 4 Bridge Power-Down Switch ...................................................... 33 3 Sinc Chop Enabled .................................................................... 16 Calibration................................................................................... 33 On-Chip Registers .......................................................................... 17 Digital Filter ................................................................................ 34 Communications Register ......................................................... 18 Sinc4 Filter (Chop Disabled) ..................................................... 34 Status Register ............................................................................. 19 Sinc3 Filter (Chop Disabled) ..................................................... 36 Mode Register ............................................................................. 19 Chop Enabled (Sinc4 Filter) ...................................................... 38 Configuration Register .............................................................. 21 Chop Enabled (Sinc3 Filter) ...................................................... 40 Data Register ............................................................................... 23 Summary of Filter Options ....................................................... 41 ID Register ................................................................................... 23 Grounding and Layout .............................................................. 42 GPOCON Register ..................................................................... 23 Applications Information .............................................................. 43 Offset Register ............................................................................. 24 Weigh Scales ................................................................................ 43 Full-Scale Register ...................................................................... 24 Outline Dimensions ....................................................................... 44 ADC Circuit Information .............................................................. 25 Ordering Guide .......................................................................... 44 Sinc Chop Disabled ................................................................... 13 Sinc Chop Disabled ................................................................... 14 Sinc Chop Enabled .................................................................... 15 REVISION HISTORY 1/10—Revision 0: Initial Version Rev. 0 | Page 2 of 44 AD7195 SPECIFICATIONS AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFIN(+) = AVDD, REFIN(−) = AGND, MCLK = 4.92 MHz, TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter ADC Output Data Rate No Missing Codes 2 Min Typ 4.7 1.17 1.56 24 24 Resolution RMS Noise and Output Data Rates Integral Nonlinearity Gain = 12 Gain > 1 Offset Error 4 , 5 ±1 ±5 ±75/gain ±0.5 ±100/gain Offset Error Drift vs. Temperature Offset Error Drift vs. Time ±5 ±5 25 Gain Error4 ±0.001 Gain Drift vs. Temperature Gain Drift vs. Time ±0.006 ±1 10 Power Supply Rejection 98 100 Common-Mode Rejection @ DC2 @ DC @ 50 Hz, 60 Hz2 @ 50 Hz, 60 Hz2 Normal Mode Rejection2 Sinc4 Filter Internal Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz Sinc3 Filter Internal Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz 100 115 120 120 Max Unit Test Conditions/Comments 1 4800 1200 1600 Hz Hz Hz Bits Bits Chop disabled Chop enabled, sinc4 filter Chop enabled, sinc3 filter FS > 1, sinc4 filter 3 FS > 4, sinc3 filter3 See the RMS Noise and Resolution section See the RMS Noise and Resolution section ±5 ±15 ppm of FSR ppm of FSR μV μV nV/°C ±0.005 nV/°C nV/°C nV/1000 hours % max % ppm/°C ppm/1000 hours dB 95 103 110 dB 115 140 Chop disabled Chop enabled Gain = 1 to 16; chop disabled Gain = 32 to 128; chop disabled Chop enabled Gain > 32 AVDD = 5 V, gain = 1, TA = 25°C (factory calibration conditions) Gain > 1, post internal full-scale calibration Gain = 1 Gain = 1, VIN = 1 V Gain = 8, VIN = 1 V/gain Gain > 8, VIN = 1 V/gain dB min dB min dB dB Gain = 1, VIN = 1 V Gain > 1, VIN = 1 V/gain 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 50 ± 1 Hz (50 Hz output data rate), 60 ± 1 Hz (60 Hz output data rate) 100 74 dB dB 96 97 dB dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 50 Hz output data rate, REJ60 6 = 1, 50 ± 1 Hz, 60 ± 1 Hz 50 Hz output data rate, 50 ± 1 Hz 60 Hz output data rate, 60 ± 1 Hz 120 82 120 120 dB dB dB dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz 50 Hz output data rate, 50 ± 1 Hz 60 Hz output data rate, 60 ± 1 Hz 75 60 70 70 dB dB dB dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz 50 Hz output data rate, 50 ± 1 Hz 60 Hz output data rate, 60 ± 1 Hz Rev. 0 | Page 3 of 44 AD7195 Parameter External Clock @ 50 Hz, 60 Hz @ 50 Hz @ 60 Hz ANALOG INPUTS Differential Input Voltage Ranges Min Typ 100 67 95 95 ±VREF/gain −(AVDD − 1.25 V)/gain Absolute AIN Voltage Limits2 Unbuffered Mode Buffered Mode Analog Input Current Buffered Mode Input Current2 Output High Voltage, VOH2 Output Low Voltage, VOL2 INTERNAL/EXTERNAL CLOCK Internal Clock Frequency Duty Cycle External Clock/Crystal2 Frequency Input Low Voltage VINL Input High Voltage, VINH Input Current dB dB dB dB 10 Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz 50 Hz output data rate, REJ606 = 1, 50 ± 1 Hz, 60 ± 1 Hz 50 Hz output data rate, 50 ± 1 Hz 60 Hz output data rate, 60 ± 1 Hz V VREF = REFIN(+) − REFIN(−), gain = 1 to 128 V Gain > 1 V V −2 −4.5 +2 +4.5 Gain = 1 Gain > 1 ±5 nA nA pA/°C ±5 ±1 ±0.05 ±1.6 μA/V μA/V nA/V/°C nA/V/°C Gain = 1, input current varies with input voltage Gain > 1 External clock Internal clock AVDD V REFIN = REFIN(+) − REFIN(−). The differential input must be limited to ±(AVDD − 1.25 V)/gain when gain > 1 AVDD + 0.05 V 1 AVDD GND − 0.05 Normal Mode Rejection2 Common-Mode Rejection Reference Detect Levels TEMPERATURE SENSOR Accuracy Sensitivity BRIDGE POWER-DOWN SWITCH RON Allowable Current2 BURNOUT CURRENTS AIN Current DIGITAL OUTPUTS (ACXx, ACXx ) Test Conditions/Comments 1 AVDD + 0.05 AVDD − 0.25 Input Current Drift Absolute REFIN Voltage Limits2 Average Reference Input Current Average Reference Input Current Drift +(AVDD − 1.25 V)/gain Unit AGND − 0.05 AGND + 0.25 Input Current Drift Unbuffered Mode Input Current REFERENCE INPUT REFIN Voltage Max 7 μA/V ±0.03 nA/V/°C External clock ±1.3 Same as for analog inputs 95 nA/V/°C Internal clock 0.3 dB V 0.6 ±2 2815 10 30 500 4 0.4 4.72 2.5 3.5 −10 4.9152 Applies after user calibration at 25°C Bipolar mode Ω mA Continuous current nA Analog inputs must be buffered and chop disabled V V AVDD = 5 V, ISOURCE = 200 μA AVDD = 5 V, ISINK = 800 μA 5.12 MHz % 5.12 0.8 0.4 MHz V V V V μA 50:50 2.4576 °C Codes/°C +10 Rev. 0 | Page 4 of 44 DVDD = 5 V DVDD = 3 V DVDD = 3 V DVDD = 5 V AD7195 Parameter LOGIC INPUTS Input High Voltage, VINH2 Input Low Voltage, VINL2 Hysteresis2 Input Currents LOGIC OUTPUT (DOUT/RDY) Output High Voltage, VOH2 Output Low Voltage, VOL2 Output High Voltage, VOH2 Output Low Voltage, VOL2 Floating-State Leakage Current Floating-State Output Capacitance Data Output Coding SYSTEM CALIBRATION2 Full-Scale Calibration Limit Zero-Scale Calibration Limit Input Span POWER REQUIREMENTS 7 Power Supply Voltage AVDD − AGND DVDD − DGND Power Supply Currents AIDD Current DIDD Current IDD (Power-Down Mode) Min Typ Max Unit 0.8 0.25 +10 V V V μA 2 0.1 −10 DVDD − 0.6 0.4 4 0.4 +10 −10 10 V V V V μA Test Conditions/Comments 1 DVDD = 3 V, ISOURCE = 100 μA DVDD = 3 V, ISINK = 100 μA DVDD = 5 V, ISOURCE = 200 μA DVDD = 5 V, ISINK = 1.6 mA pF Offset binary −1.05 × FS 0.8 × FS 1.05 × FS 2.1 × FS V V V 4.75 2.7 5.25 5.25 V V 1 1.3 4.5 5 6.4 6.9 0.4 0.6 mA mA mA mA mA mA mA mA mA μA 0.85 1.1 3.5 4 5 5.5 0.35 0.5 1.5 2 1 gain = 1, buffer off gain = 1, buffer on gain = 8, buffer off gain = 8, buffer on gain = 16 to 128, buffer off gain = 16 to 128, buffer on DVDD = 3 V DVDD = 5 V External crystal used Temperature range: −40°C to +105°C. Specification is not production tested, but is supported by characterization data at initial product release. FS is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 4 Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system fullscale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate. 5 The analog inputs are configured for differential mode. 6 REJ60 is a bit in the mode register. When the output data rate is set to 50 Hz, setting REJ60 to 1 places a notch at 60 Hz, allowing simultaneous 50 Hz/60 Hz rejection. 7 Digital inputs equal to DVDD or DGND. 2 3 Rev. 0 | Page 5 of 44 AD7195 TIMING CHARACTERISTICS AVDD = 4.75 V to 5.25 V, DVDD = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = DVDD, unless otherwise noted. Table 2. Parameter READ AND WRITE OPERATIONS t3 t4 READ OPERATION t1 t2 3 t5 5, 6 t6 t7 WRITE OPERATION t8 t9 t10 t11 Limit at TMIN, TMAX (B Version) Unit Conditions/Comments 1, 2 100 100 ns min ns min SCLK high pulse width SCLK low pulse width 0 60 80 0 60 80 10 80 0 10 ns min ns max ns max ns min ns max ns max ns min ns max ns min ns min CS falling edge to DOUT/RDY active time DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V SCLK active edge to data valid delay 4 DVDD = 4.75 V to 5.25 V DVDD = 2.7 V to 3.6 V Bus relinquish time after CS inactive edge 0 30 25 0 ns min ns min ns min ns min CS falling edge to SCLK active edge setup time4 Data valid to SCLK edge setup time Data valid to SCLK edge hold time CS rising edge to SCLK edge hold time 1 SCLK inactive edge to CS inactive edge SCLK inactive edge to DOUT/RDY high Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.6 V. See Figure 3 and Figure 4. 3 These numbers are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit shown in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading capacitances. 6 RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high, although care should be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. 2 Rev. 0 | Page 6 of 44 AD7195 Circuit and Timing Diagram ISINK (1.6mA WITH DVDD = 5V, 100µA WITH DVDD = 3V) TO OUTPUT PIN 1.6V ISOURCE (200µA WITH DVDD = 5V, 100µA WITH DVDD = 3V) 08771-002 50pF Figure 2. Load Circuit for Timing Characterization CS (I) t6 t1 t5 MSB DOUT/RDY (O) LSB t7 t2 t3 08771-003 SCLK (I) t4 I = INPUT, O = OUTPUT Figure 3. Read Cycle Timing Diagram CS (I) t11 t8 SCLK (I) t9 t10 MSB LSB I = INPUT, O = OUTPUT Figure 4. Write Cycle Timing Diagram Rev. 0 | Page 7 of 44 08771-004 DIN (I) AD7195 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 3. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter AVDD to AGND DVDD to AGND AGND to DGND Analog Input Voltage to AGND Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND AIN/Digital Input Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Lead Temperature, Soldering Reflow Rating −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V 10 mA −40°C to +105°C −65°C to +150°C 150°C Table 4. Thermal Resistance Package Type 32-Lead LFCSP_WQ ESD CAUTION 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 8 of 44 θJA 32.5 θJC 32.71 Unit °C/W AD7195 32 31 30 29 28 27 26 25 CS SCLK MCLK2 MCLK1 DIN DOUT/RDY NC SYNC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD7195 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 DVDD AVDD DGND AGND BPDSW NC REFIN(–) REFIN(+) NOTES 1. NC = NO CONNECT. 2. CONNECT EXPOSED PAD TO AGND. 08771-005 AIN1 AIN2 NC NC NC NC AIN3 AIN4 9 10 11 12 13 14 15 16 ACX2 ACX2 ACX1 ACX1 AVDD AGND NC AINCOM Figure 5.Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 Mnemonic ACX2 2 ACX2 3 ACX1 4 ACX1 5 6 7 8 9 AVDD AGND NC AINCOM AIN1 10 AIN2 11 12 13 14 15 NC NC NC NC AIN3 16 AIN4 17 REFIN(+) 18 19 REFIN(−) NC Description Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac excited bridge applications. In ac mode, ACX2 toggles in anti-phase with ACX1. If the ACX bit equals zero (ac excitation turned off), the ACX2 output remains low. When toggling, it is guaranteed to be nonoverlapping with ACX1. The nonoverlap interval between ACX1 and ACX2 is 1/(master clock) which is equal to 200 ns when a 4.92 MHz clock is used. Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac excited bridge applications. This output is the inverse of ACX2. If the ACX bit equals zero (ac excitation turned off), the ACX2 output remains high. Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac excited bridge applications. When ACX1 is high, the bridge excitation is taken as normal and when ACX1 is low, the bridge excitation is reversed (chopped). If the Bit ACX equals zero (ac excitation turned off), the ACX1 output remains high. Digital Output. Provides a signal that can be used to control the reversing of the bridge excitation in ac excited bridge applications. This output is the inverse of ACX1. When ACX1 is low, the bridge excitation is taken as normal and when ACX1 is high, the bridge excitation is reversed (chopped). If the ACX bit equals zero (ac excitation turned off), the ACX1 output remains low. Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD. Analog Ground Reference Point. No Connect. This pin should be tied to AGND. Analog inputs AIN1 to AIN4 are referenced to this input when configured for pseudo differential operation. Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN2 or as a pseudo differential input when used with AINCOM. Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN1 or as a pseudo differential input when used with AINCOM. No Connect. This pin should be tied to AGND. No Connect. This pin should be tied to AGND. No Connect. This pin should be tied to AGND. No Connect. This pin should be tied to AGND. Analog Input. This pin can be configured as the positive input of a fully differential input pair when used with AIN4 or as a pseudo differential input when used with AINCOM. Analog Input. This pin can be configured as the negative input of a fully differential input pair when used with AIN3 or as a pseudo differential input when used with AINCOM. Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(−). REFIN(+) can lie anywhere between AVDD and AGND + 1 V. The nominal reference voltage, (REFIN(+) − REFIN(−)), is AVDD, but the part functions with a reference from 1 V to AVDD. Negative Reference Input. This reference input can lie anywhere between AGND and AVDD − 1 V. No Connect. This pin should be tied to AGND. Rev. 0 | Page 9 of 44 AD7195 Pin No. 20 21 22 23 24 25 Mnemonic BPDSW AGND DGND AVDD DVDD SYNC 26 27 NC DOUT/RDY 28 DIN 29 MCLK1 30 MCLK2 31 SCLK 32 CS Description Bridge Power-Down Switch to AGND. Analog Ground Reference Point. Digital Ground Reference Point. Analog Supply Voltage, 4.75 V to 5.25 V. AVDD is independent of DVDD. Digital Supply Voltage, 2.7 V to 5.25 V. DVDD is independent of AVDD. Logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7195 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low. SYNC has a pull-up resistor internally to DVDD. No Connect. This pin should be tied to AGND. Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. It functions as a serial data output pin to access the output shift register of the ADC. The output shift register can contain data from any of the on-chip data or control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used as an interrupt to a processor, indicating that valid data is available. With an external serial clock, the data can be read using the DOUT/RDY pin. With CS low, the data-/control-word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the control registers in the ADC, with the register selection bits of the communications register identifying the appropriate register. When the master clock for the device is provided externally by a crystal, the crystal is connected between MCLK1 and MCLK2. Master Clock Signal for the Device. The AD7195 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7195 can be provided externally also in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected. Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK has a Schmitttriggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information transmitted to or from the ADC in smaller batches of data. Chip Select Input. This is an active low logic input used to select the ADC. CS can be used to select the ADC in systems with more than one device on the serial bus or as a frame synchronization signal in communicating with the device. CS can be hardwired low, allowing the ADC to operate in 3-wire mode with SCLK, DIN, and DOUT used to interface with the device. Rev. 0 | Page 10 of 44 AD7195 TYPICAL PERFORMANCE CHARACTERISTICS 8,388,760 30 8,388,758 25 8,388,756 FREQUENCY CODE 20 8,388,754 8,388,752 15 10 8,388,750 0 200 400 600 800 1000 SAMPLE 0 8,388,490 08771-006 8,388,746 8,388,576 8,388,662 8,388,748 CODE 8,388,834 8,388,920 08771-009 5 8,388,748 Figure 9. Noise Distribution Histogram (VREF = 5 V, Output Data Rate = 4800 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) Figure 6. Noise (VREF = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) 250 8,388,820 8,388,800 8,388,780 200 150 8,388,740 CODE FREQUENCY 8,388,760 8,388,720 8,388,700 100 8,388,680 50 8,388,660 CODE 0 100 200 300 400 500 600 700 800 900 08771-010 8,388,620 08771-007 8,388,760 8,388,758 8,388,756 8,388,754 8,388,752 8,388,750 8,388,746 8,388,748 8,388,640 0 1000 SAMPLES Figure 10. Noise (VREF = 5 V, Output Data Rate = 4800 Hz, Gain = 1, Chop Disabled, Sinc4 Filter) Figure 7. Noise Distribution Histogram (VREF = 5 V, Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) 80 8,388,950 8,388,900 70 8,388,850 60 FREQUENCY 8,388,800 8,388,700 8,388,650 50 40 30 8,388,600 20 8,388,550 8,388,450 0 100 200 300 400 500 600 700 800 900 1000 SAMPLES Figure 8. Noise (VREF = 5 V, Output Data Rate = 4800 Hz, Gain = 128, Chop Disabled, Sinc4 Filter) 0 8,388,620 8,388,660 8,388,700 8,388,740 CODE 8,388,780 8,388,820 Figure 11. Noise Distribution Histogram (VREF = 5 V, Output Data Rate = 4800 Hz, Gain = 1, Chop Disabled, Sinc4 Filter) Rev. 0 | Page 11 of 44 08771-011 10 8,388,500 08771-008 CODE 8,388,750 AD7195 0 3.0 –0.1 2.0 OFFSET (µV) INL (ppm of FSR) –0.2 1.0 0 –0.3 –0.4 –1.0 –0.5 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 VIN (V) –0.7 –60 –40 –20 0 20 40 60 80 100 120 TEMERATURE (°C) Figure 12. INL (Gain = 1) 08771-015 –2.0 08771-012 –3.0 –2.5 –0.6 Figure 15. Offset Error (Gain = 128, Chop Disabled) 1.000008 6 1.000007 4 1.000005 GAIN INL (ppm of FSR) 1.000006 2 0 1.000004 1.000003 –2 1.000002 –4 0 0.005 0.010 0.015 0.020 VIN (V) 1.000000 –60 08771-013 –6 –0.020 –0.015 –0.010 –0.005 –20 0 20 40 60 80 100 120 100 120 TEMPERATURE (°C) Figure 16. Gain Error (Gain = 1, Chop Disabled) Figure 13. INL (Gain = 128) 128.003 66 128.002 64 128.001 GAIN 62 60 128.000 127.999 58 127.998 56 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) 140 Figure 14. Offset Error (Gain = 1, Chop Disabled) 127.996 –60 –40 –20 0 20 40 60 80 TEMPERATURE (°C) Figure 17. Gain Error (Gain = 128, Chop Disabled) Rev. 0 | Page 12 of 44 08771-017 54 –60 127.997 08771-014 OUTPUT VOLTAGE (µV) –40 08771-016 1.000001 AD7195 RMS NOISE AND RESOLUTION The tables in this section show the rms noise, peak-to-peak noise, effective resolution, and noise-free (peak-to-peak) resolution of the AD7195 for various output data rates and gain settings, with chop disabled and chop enabled for the sinc4 and sinc3 filters. The numbers given are for the bipolar input range with the external 5 V reference. These numbers are typical and are generated with a differential input voltage of 0 V when the ADC is continuously converting on a single channel. It is important to note that the effective resolution is calculated using the rms noise, whereas the peak-to-peak resolution is calculated based on peak-to-peak noise. The peak-to-peak resolution represents the resolution for which there is no code flicker. SINC4 CHOP DISABLED Table 6. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 852.5 533 400 80 66.7 26.7 13.3 4.17 1.67 0.83 Gain of 1 280 390 470 1000 1100 1460 1900 3000 5000 14,300 Gain of 8 96 120 130 150 170 220 285 480 780 1920 Gain of 16 50 54 56 78 88 125 170 280 440 1000 Gain of 32 22 28 31 45 52 75 100 175 280 550 Gain of 64 10 12 14 33 36 55 75 140 220 380 Gain of 128 8.5 10.5 11.5 28 31 48 67 121 198 295 Gain of 16 250 290 300 450 480 750 1000 1800 2800 6000 Gain of 32 130 150 190 280 300 410 600 1100 1700 3500 Gain of 64 65 80 100 180 220 340 440 810 1400 2400 Gain of 128 56 65 70 170 190 310 430 710 1200 1900 Gain of 641 23.6 (21.2) 23.4 (20.9) 23.3 (20.6) 22.2 (19.7) 22.1 (19.4) 21.5 (18.8) 21 (18.4) 20.2 (17.6) 19.5 (16.8) 18.8 (16) Gain of 1281 23.1 (20.4) 22.8 (20.2) 22.7 (20.1) 21.4 (18.8) 21.3 (18.6) 20.6 (17.9) 20.1 (17.5) 19.3 (16.7) 18.6 (16) 18 (15.3) Table 7. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 852.5 533 400 80 66.7 26.7 13.3 4.17 1.67 0.83 Gain of 1 1600 2200 3000 6000 7200 8300 11,000 20,000 32,000 86,000 Gain of 8 500 650 670 900 1100 1500 1700 3000 5100 13,000 Table 8. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 852.5 533 400 80 66.7 26.7 13.3 4.17 1.67 0.83 Gain of 1 1 24 (22.6) 24 (22.1) 24 (21.7) 23.3 (20.7) 23.1 (20.4) 22.7 (20.2) 22.3 (19.8) 21.7 (18.9) 20.9 (18.3) 19.4 (16.8) Gain of 81 23.6 (21.3) 23.4 (20.9) 23.3 (20.8) 23 (20.4) 22.8 (20.1) 22.4 (19.7) 22.1 (19.5) 21.3 (18.7) 20.6 (17.9) 19.3 (16.6) Gain of 161 23.6 (21.3) 23.4 (20.9) 23.3 (20.8) 22.9 (20.4) 22.8 (20) 22.3 (19.7) 21.8 (19.3) 21.1 (18.4) 20.4 (17.7) 19.3 (16.4) The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. 0 | Page 13 of 44 Gain of 321 23.6 (21.2) 23.4 (20.9) 23.3 (20.8) 22.7 (20.1) 22.5 (20 ) 22 (19.5) 21.6 (19) 20.8 (18.1) 20.1 (17.5) 19.1 (16.4) AD7195 SINC3 CHOP DISABLED Table 9. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 20 10 3.13 1.25 0.625 Gain of 1 290 470 610 1100 1200 1500 1950 4000 56,600 442,000 Gain of 8 125 135 145 160 170 230 308 590 7000 55,000 Gain of 16 53 56 58 86 95 130 175 330 3500 28,000 Gain of 32 24 29 32 50 55 80 110 200 1800 14,000 Gain of 64 10.5 13 16 35 40 58 83 150 900 7000 Gain of 128 9 11.5 12.5 29 32 50 73 133 490 3450 Gain of 16 260 340 360 480 600 710 1000 2200 22,000 170,000 Gain of 32 140 150 200 290 300 470 670 1200 12,000 79,000 Gain of 64 65 84 100 200 240 360 470 850 5600 41,000 Gain of 128 56 60 70 180 200 310 500 800 3100 24,000 Table 10. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 20 10 3.13 1.25 0.625 Gain of 1 1700 2400 3000 6600 6800 8900 13,000 25,000 310,000 2,600,000 Gain of 8 750 800 900 1000 1100 1400 2000 3400 41,000 300,000 Table 11. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 1 Output Data Rate (Hz) 4.7 7.5 10 50 60 150 300 960 2400 4800 Settling Time (ms) 639.4 400 300 60 50 20 10 3.13 1.25 0.625 Gain of 1 1 24 (22.5) 24 (22) 24 (22) 23.1 (20.5) 23 (20.5) 22.7 (20) 22.3 (19.5) 21.3 (18.5) 17.4 (14.9) 14.5 (11.9) Gain of 81 23.5 (21) 23.3 (20.8) 23.2 (20.5) 22.9 (20.3) 22.8 (20.1) 22.4 (19.8) 22 (19.3) 21 (18.5) 17.4 (14.9) 14.5 (11.9) Gain of 161 23.5 (21) 23.3 (20.8) 23.2 (20.5) 22.8 (20.3) 22.6 (20) 22.2 (19.7) 21.8 (19.3) 20.9 (18.1) 17.4 (14.8) 14.4 (11.8) The output peak-to-peak (p-p) resolution is listed in parentheses. Rev. 0 | Page 14 of 44 Gain of 321 23.5 (21) 23.3 (20.8) 23.2 (20.5) 22.6 (20) 22.4 (20) 21.9 (19.3) 21.4 (18.8) 20.6 (18) 17.4 (14.7) 14.4 (11.8) Gain of 641 23.5 (21) 23.3 (20.8) 23.2 (20.5) 22.1 (19.6) 21.9 (19.3) 21.4 (18.7) 20.8 (18.3) 20 (17.5) 17.4 (14.7) 14.4 (11.8) Gain of 1281 23 (20.4) 22.7 (20.3) 22.6 (20.1) 21.4 (18.7) 21.2 (18.6) 20.6 (17.9) 20 (17.3) 19.2 (16.6) 17.3 (14.6) 14.4 (11.7) AD7195 SINC4 CHOP ENABLED Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 1.175 1.875 2.5 12.5 15 37.5 75 240 600 1200 Settling Time (ms) 1702 1067 800 160 133 53.3 26.7 8.33 3.33 1.67 Gain of 1 198 276 332 707 778 990 1344 2192 3606 9900 Gain of 8 85 92 99 127 141 156 191 325 523 1345 Gain of 16 41 45 46 61 62 85 106 184 297 680 Gain of 32 18 22 23 34 35 51 67 120 191 368 Gain of 64 7 8.5 10 23 24 38 51 92 148 248 Gain of 128 6 7 8 18 21 33 45 78 134 200 Gain of 16 212 248 255 368 424 530 707 1273 1980 4950 Gain of 32 92 106 134 198 212 290 424 778 1202 2475 Gain of 64 46 57 71 127 156 240 311 573 990 1697 Gain of 128 40 46 50 120 134 219 304 502 850 1345 Gain of 641 24 (21.7) 23.9 (21.4) 23.8 (21.1) 22.7 (20.2) 22.6 (19.9) 22 (19.3) 21.5 (18.9) 20.7 (18.1) 20 (17.3) 19.3 (16.5) Gain of 1281 23.6 (20.9) 23.3 (20.7) 23.2 (20.6) 21.9 (19.3) 21.8 (19.1) 21.1 (18.4) 20.6 (18) 19.8 (17.2) 19.1 (16.5) 18.5 (15.8) Table 13. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 1.175 1.875 2.5 12.5 15 37.5 75 240 600 1200 Settling Time (ms) 1702 1067 800 160 133 53.3 26.7 8.33 3.33 1.67 Gain of 1 1131 1556 2121 4243 5091 5870 7780 14,142 22,627 60,800 Gain of 8 474 495 530 707 849 1061 1202 2121 3606 9192 Table 14. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 1 Output Data Rate (Hz) 1.175 1.875 2.5 12.5 15 37.5 75 240 600 1200 Settling Time (ms) 1702 1067 800 160 133 53.3 26.7 8.33 3.33 1.67 Gain of 1 1 24 (23.1) 24 (22.6) 24 (22.2) 23.8 (21.2) 23.6 (20.9) 23.2 (20.7) 22.8 (20.3) 22.2 (19.4) 21.4 (18.8) 19.9 (17.3) Gain of 81 24 (21.8) 23.9 (21.4) 23.8 (21.3) 23.5 (20.9) 23.3 (20.6) 22.9 (20.2) 22.6 (20) 21.8 (19.2) 21.1 (18.4) 19.8 (17.1) Gain of 161 24 (21.8) 23.9 (21.4) 23.8 (21.3) 23.4 (20.9) 23.3 (20.5) 22.8 (20.2) 22.3 (19.8) 21.6 (18.9) 20.9 (18.2) 19.8 (16.9) Gain of 321 24 (21.7) 23.9 (21.4) 23.8 (21.3) 23.2 (20.6) 23 (20.5) 22.5 (20) 22.1 (19.5) 21.3 (18.6) 20.6 (18) 19.6 (16.9) The output peak-to-peak (p-p) resolution is listed in parentheses. When ac excitation is enabled, the rms noise and resolution is the same as for chop enabled mode. Rev. 0 | Page 15 of 44 AD7195 SINC3 CHOP ENABLED Table 15. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 1.56 2.5 3.33 16.6 20 50 100 320 800 1600 Settling Time (ms) 1282 800 600 120 100 40 20 6.25 2.5 1.25 Gain of 1 205 332 431 778 849 1061 1379 2828 40,022 312,540 Gain of 8 88 95 103 113 120 163 218 417 4950 38,890 Gain of 16 37 40 41 61 67 92 124 233 2475 19,800 Gain of 32 17 21 23 35 39 57 78 141 1273 9900 Gain of 64 7.5 9 11.5 25 28 41 59 106 636 4950 Gain of 128 6.5 8 9 21 23 35 52 94 346 2440 Gain of 16 184 240 255 318 424 474 707 1556 15,560 120,200 Gain of 32 92 120 141 198 205 382 474 849 8485 55,870 Gain of 64 46 59 71 141 170 255 332 601 3960 29,000 Gain of 128 40 42 49 127 141 219 354 566 2192 16,970 Gain of 641 24 (21.5) 23.8 (21.3) 23.7 (21) 22.6 (20.1) 22.4 (19.8) 21.9 (19.2) 21.3 (18.8) 20.5 (18) 17.9 (15.2) 14.9 (12.3) Gain of 1281 23.5 (20.9) 23.2 (20.8) 23.1 (20.6) 21.9 (19.2) 21.7 (19.1) 21.1 (18.4) 20.5 (17.8) 19.7 (17.1) 17.8 (15.1) 14.9 (12.2) Table 16. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 Output Data Rate (Hz) 1.56 2.5 3.33 16.6 20 50 100 320 800 1600 Settling Time (ms) 1282 800 600 120 100 40 20 6.25 2.5 1.25 Gain of 1 1202 1697 2121 4667 4808 6293 9192 17,680 219,200 1,838,500 Gain of 8 530 566 636 686 707 990 1414 2404 29,000 212,200 Table 17. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate Filter Word (Decimal) 1023 640 480 96 80 32 16 5 2 1 1 Output Data Rate (Hz) 1.56 2.5 3.33 16.6 20 320 100 320 800 1600 Settling Time (ms) 1282 800 600 120 100 40 20 6.25 2.5 1.25 Gain of 1 1 24 (23) 24 (22.5) 24 (22.5) 23.6 (21) 23.5 (21) 23.2 (20.5) 22.8 (20) 21.8 (19) 17.9 (15.4) 15 (12.4) Gain of 81 24 (21.5) 23.8 (21.3) 23.7 (21) 23.4 (20.8) 23.3 (20.6) 22.9 (20.3) 22.5 (19.8) 21.5 (19) 17.9 (15.4) 15 (12.4) Gain of 161 24 (21.5) 23.8 (21.3) 23.7 (21) 23.3 (20.8) 23.1 (20.5) 22.7 (20.2) 22.3 (19.8) 21.4 (18.6) 17.9 (15.3) 14.9 (12.3) Gain of 321 24 (21.5) 23.8 (21.3) 23.7 (21) 23.1 (20.5) 22.9 (20.5) 22.4 (19.8) 21.9 (19.3) 21.1 (18.5) 17.9 (15.2) 14.9 (12.3) The output peak-to-peak (p-p) resolution is listed in parentheses. When ac excitation is enabled, the rms noise and resolution is the same as for chop enabled mode. Rev. 0 | Page 16 of 44 AD7195 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers described on the following pages. In the following descriptions, the term set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. Table 18. Register Summary Register Communications Addr. 00 Dir. W Default 00 Bit 7 WEN Bit 6 R/W Status Mode 00 R 80 RDY ERR 01 R/W 080060 Mode select SINC3 0 FS7 FS6 Chop (MSB) ACX CH7 CH6 BURN REFDET D23 (MSB) D15 D7 1 0 OF23 (MSB) OF15 OF7 FS23 (MSB) FS15 FS7 Configuration 02 R/W 000117 Data 03 R 000000 ID GPOCON Offset 04 05 06 R R/W R/W A6 00 800000 Full Scale 07 R/W 5XXXX0 D22 D14 D6 0 BPDSW OF22 OF14 OF6 FS22 FS14 FS6 Bit 5 Bit 4 Bit 3 Register address NOREF PARITY 0 Bit 2 CREAD Bit 1 0 Bit 0 0 CHD2 CHD1 CHD0 ENPAR FS5 0 CH5 0 DAT_STA 0 FS4 0 CH4 BUF CLK1 SINGLE FS3 0 CH3 U/B CLK0 REJ60 FS2 0 CH2 G2 0 FS9 FS1 0 CH1 G1 0 FS8 FS0 (LSB) 0 CH0 G0 (LSB) D21 D13 D5 1 0 OF21 OF13 OF5 FS21 FS13 FS5 D20 D12 D4 0 0 OF20 OF12 OF4 FS20 FS12 FS4 D19 D11 D3 0 0 OF19 OF11 OF3 FS19 FS11 FS3 D18 D10 D2 1 0 OF18 OF10 OF2 FS18 FS10 FS2 D17 D9 D1 1 0 OF17 OF9 OF1 FS17 FS9 FS1 D16 D8 D0 (LSB) 0 0 OF16 OF8 OF0 (LSB) FS16 FS8 FS0 (LSB) Rev. 0 | Page 17 of 44 AD7195 COMMUNICATIONS REGISTER (RS2, RS1, RS0 = 0, 0, 0) The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or a write operation and in which register this operation takes place. For read or write operations, when the subsequent read or write operation to the selected register is complete, the interface returns to where it expects a write operation to the communications register. This is the default CR7 WEN(0) CR6 R/W(0) CR5 RS2(0) CR4 RS1(0) state of the interface and, on power-up or after a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the interface sequence is lost, a write operation of at least 40 serial clock cycles with DIN high returns the ADC to this default state by resetting the entire part. Table 19 outlines the bit designations for the communications register. CR0 through CR7 indicate the bit location, CR denoting that the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. CR3 RS0(0) CR2 CREAD(0) CR1 0 CR0 0 Table 19. Communications Register Bit Designations Bit Location CR7 Bit Name WEN CR6 R/W CR5 to CR3 RS2 to RS0 CR2 CREAD CR1 to CR0 0 Description Write enable bit. For a write to the communications register to occur, 0 must be written to this bit. If a 1 is the first bit written, the part does not clock on to subsequent bits in the register; rather, it stays at this bit location until a 0 is written to this bit. After a 0 is written to the WEN bit, the next seven bits are loaded to the communications register. Idling the DIN pin high between data transfers minimizes the effects of spurious SCLK pulses on the serial interface. A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position indicates that the next operation is a read from the designated register. Register address bits. These address bits are used to select which registers of the ADC are selected during the serial interface communication (see Table 20). Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial interface is configured so that the data register can be continuously read; that is, the contents of the data register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin goes low to indicate that a conversion is complete. The communications register does not have to be written to for subsequent data reads. To enable continuous read, the Instruction 01011100 must be written to the communications register. To disable continuous read, the Instruction 01011000 must be written to the communications register while the RDY pin is low. While continuous read is enabled, the ADC monitors activity on the DIN line so that it can receive the instruction to disable continuous read. Additionally, a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, hold DIN low until an instruction is written to the device. These bits must be programmed to Logic 0 for correct operation. Table 20. Register Selection RS2 0 0 0 0 0 1 1 1 1 RS1 0 0 0 1 1 0 0 1 1 RS0 0 0 1 0 1 0 1 0 1 Register Communications register during a write operation Status register during a read operation Mode register Configuration register Data register/data register plus status information ID register GPOCON register Offset register Full-scale register Rev. 0 | Page 18 of 44 Register Size 8 bits 8 bits 24 bits 24 bits 24 bits/32 bits 8 bits 8 bits 24 bits 24 bits AD7195 STATUS REGISTER (RS2, RS1, RS0 = 0, 0, 0; Power-On/Reset = 0x80) The status register is an 8-bit read-only register. To access the ADC status register, the user must write to the communications register, select the next operation to be a read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 21 outlines the bit designations for the status register. SR0 through SR7 indicate the bit locations, SR denoting that the bits are in the status register. SR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. SR7 RDY(1) SR6 ERR(0) SR5 NOREF(0) SR4 PARITY(0) SR3 0 SR2 CHD2(0) SR1 CHD1(0) SR0 CHD0(0) Table 21. Status Register Bit Designations Bit Location SR7 Bit Name RDY SR6 ERR SR5 NOREF SR4 PARITY SR3 SR2 to SR0 0 CHD2 to CHD0 Description Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set automatically after the ADC data register is read, or a period of time before the data register is updated, with a new conversion result to indicate to the user that the conversion data should not be read. It is also set when the part is placed in power-down mode or idle mode or when SYNC is taken low. The end of a conversion is also indicated by the DOUT/RDY pin. This pin can be used as an alternative to the status register for monitoring the ADC for conversion data. ADC error bit. This bit is written to at the same time as the RDY bit. This bit is set to indicate that the result written to the ADC data register is clamped to all 0s or all 1s. Error sources include overrange or underrange, or the absence of a reference voltage. This bit is cleared when the result written to the data register is within the allowed analog input range again. No external reference bit. This bit is set to indicate that the reference is at a voltage that is below a specified threshold. When set, conversion results are clamped to all 1s. This bit is cleared to indicate that a valid reference is applied to the selected reference pins. The NOREF bit is enabled by setting the REFDET bit in the configuration register to 1. Parity check of the data register. If the ENPAR bit in the mode register is set, the PARITY bit is set if there is an odd number of 1s in the data register. It is cleared if there is an even number of 1s in the data register. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. This bit is set to 0. These bits indicate which channel corresponds to the data register contents. They do not indicate which channel is presently being converted but indicate which channel was selected when the conversion contained in the data register was generated. MODE REGISTER (RS2, RS1, RS0 = 0, 0, 1; Power-On/Reset = 0x080060) The mode register is a 24-bit register from which data can be read or to which data can be written. This register is used to select the operating mode, the output data rate, and the clock source. Table 22 outlines the bit designations for the mode register. MR0 through MR23 indicate the bit locations, MR denoting that the bits are in the mode register. MR23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. Any write to the mode register resets the modulator and filter and sets the RDY bit. MR23 MD2(0) MR15 SINC3(0) MR7 FS7(0) MR22 MD1(0) MR14 0 MR6 FS6(1) MR21 MD0(0) MR13 ENPAR(0) MR5 FS5(1) MR20 DAT_STA(0) MR12 0 MR4 FS4(0) MR19 CLK1(1) MR11 SINGLE(0) MR3 FS3(0) Rev. 0 | Page 19 of 44 MR18 CLK0(0) MR10 REJ60(0) MR2 FS2(0) MR17 0 MR9 FS9(0) MR1 FS1(0) MR16 0 MR8 FS8(0) MR0 FS0(0) AD7195 Table 22. Mode Register Bit Designations Bit Location MR23 to MR21 MR20 Bit Name MD2 to MD0 DAT_STA MR19, MR18 CLK1, CLK0 MR17, MR16 MR15 0 SINC3 MR14 MR13 0 ENPAR MR12 MR11 0 SINGLE MR10 REJ60 MR9 to MR0 FS9 to FS0 Description Mode select bits. These bits select the operating mode of the AD7195 (see Table 23). This bit enables the transmission of status register contents after each data register read. When DAT_STA is set, the contents of the status register are transmitted along with each data register read. This function is useful when several channels are selected because the status register identifies the channel to which the data register value corresponds. These bits select the clock source for the AD7195. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7195 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7195. CLK1 CLK0 ADC Clock Source 0 0 External crystal. The external crystal is connected from MCLK1 to MCLK2. 0 1 External clock. The external clock is applied to the MCLK2 pin. 1 0 Internal 4.92 MHz clock. Pin MCLK2 is tristated. 1 1 Internal 4.92 MHz clock. The internal clock is available on MCLK2. These bits must be programmed with a Logic 0 for correct operation. Sinc3 filter select bit. When this bit is cleared, the sinc4 filter is used (default value). When this bit is set, the sinc3 filter is used. The benefit of the sinc3 filter compared to the sinc4 filter is its lower settling time. For a given output data rate, fADC, the sinc3 filter has a settling time of 3/fADC while the sinc4 filter has a settling time of 4/fADC when chop is disabled. The sinc4 filter, due to its deeper notches, gives better 50 Hz/60 Hz rejection. At low output data rates, both filters give similar rms noise and similar no missing codes for a given output data rate. At higher output data rates (FS values less than 5), the sinc4 filter gives better performance than the sinc3 filter for rms noise and no missing codes. This bit must be programmed with a Logic 0 for correct operation. Enable parity bit. When ENPAR is set, parity checking on the data register is enabled. The DAT_STA bit in the mode register should be set when the parity check is used. When the DAT_STA bit is set, the contents of the status register are transmitted along with the data for each data register read. This bit must be programmed with a Logic 0 for correct operation. Single cycle conversion enable bit. When this bit is set, the AD7195 settles in one conversion cycle so that it functions as a zero-latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected. This bit enables a notch at 60 Hz when the first notch of the sinc filter is at 50 Hz. When REJ60 is set, a filter notch is placed at 60 Hz when the sinc filter first notch is at 50 Hz. This allows simultaneous 50 Hz/ 60 Hz rejection. Filter output data rate select bits. The 10 bits of data programmed into these bits determine the filter cut-off frequency, the position of the first notch of the filter, and the output data rate for the part. In association with the gain selection, they also determine the output noise (and, therefore, the effective resolution) of the device (see Table 6 through Table 17). When chop is disabled and continuous conversion mode is selected, Output Data Rate = (MCLK/1024)/FS where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in an output data rate from 4.69 Hz to 4.8 kHz. With chop disabled, the first notch frequency is equal to the output data rate when converting on a single channel. When chop is enabled, Output Data Rate = (MCLK/1024)/(N × FS) where FS is the decimal equivalent of the code in Bit FS0 to Bit FS9 and is in the range 1 to 1023, and MCLK is the master clock frequency. With a nominal MCLK of 4.92 MHz, this results in a conversion rate from 4.69/N Hz to 4.8/N kHz, where N is the order of the sinc filter. The sinc filter’s first notch frequency is equal to N × output data rate. The chopping introduces notches at odd integer multiples of (output data rate/2). Rev. 0 | Page 20 of 44 AD7195 Table 23. Operating Modes MD2 0 MD1 0 MD0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Mode Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places the result in the data register. The DOUT/RDY pin and the RDY bit in the status register go low when a conversion is complete. The user can read these conversions by setting the CREAD bit in the communications register to 1, which enables continuous read. When continuous read is enabled, the conversions are automatically placed on the DOUT line when SCLK pulses are applied. Alternatively, the user can instruct the ADC to output each conversion by writing to the communications register. After power-on, a reset, or a reconfiguration of the ADC, the complete settling time of the filter is required to generate the first valid conversion. Subsequent conversions are available at the selected output data rate, which is dependent on filter choice. Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the selected channel. The internal clock requires up to 1 ms to power up and settle. The ADC then performs the conversion, which requires the complete settling time of the filter. The conversion result is placed in the data register. RDY goes low, and the ADC returns to power-down mode. The conversion remains in the data register until another conversion is performed. RDY remains active (low) until the data is read or another conversion is performed. Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks are still provided. Power-down mode. In power-down mode, all AD7195 circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7195 for settling reasons. The external crystal, if selected, remains active. Internal zero-scale calibration. An internal short is automatically connected to the input. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. Internal full-scale calibration. A full-scale input voltage is automatically connected to the input for this calibration. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed to minimize the fullscale error. System zero-scale calibration. The user should connect the system zero-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A system zero-scale calibration is required each time the gain of a channel is changed. System full-scale calibration. The user should connect the system full-scale input to the channel input pins as selected by the CH7 to CH0 bits in the configuration register. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration. The measured full-scale coefficient is placed in the full-scale register of the selected channel. A full-scale calibration is required each time the gain of a channel is changed. CONFIGURATION REGISTER (RS2, RS1, RS0 = 0, 1, 0; Power-On/Reset = 0x000117) The configuration register is a 24-bit register from which data can be read or to which data can be written. This register is used to configure the ADC for unipolar or bipolar mode, to enable or disable the buffer, to enable or disable the burnout currents, to select the gain, and to select the analog input channel. Table 24 outlines the bit designations for the filter register. CON0 through CON23 indicate the bit locations. CON denotes that the bits are in the configuration register. CON23 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. CON23 CHOP(0) CON15 CH7(0) CON7 BURN(0) CON22 ACX(0) CON14 CH6(0) CON6 REFDET(0) CON21 0 CON13 CH5(0) CON5 0 CON20 0 CON12 CH4(0) CON4 BUF(1) CON19 0 CON11 CH3(0) CON3 U/B (0) Rev. 0 | Page 21 of 44 CON18 0 CON10 CH2(0) CON2 G2(1) CON17 0 CON9 CH1(0) CON1 G1(1) CON16 0 CON8 CH0(1) CON0 G0(1) AD7195 Table 24. Configuration Register Bit Designations Bit Location CON23 Bit Name CHOP CON22 ACX CON21 to CON16 CON15 to CON8 0 CH7 to CH0 CON7 BURN CON6 REFDET CON5 CON4 0 BUF CON3 U/B CON2 to CON0 G2 to G0 Description Chop enable bit. When the CHOP bit is cleared, chop is disabled. When the CHOP bit is set, chop is enabled. When chop is enabled, the offset and offset drift of the ADC are continuously removed. However, this increases the conversion time and settling time of the ADC. For example, when FS = 96 decimal and the sinc4 filter is selected, the conversion time with chop enabled equals 80 ms and the settling time equals 160 ms. With chop disabled, higher conversion rates are allowed. For an FS word of 96 decimal and the sinc4 filter selected, the conversion time is 20 ms and the settling time is 80 ms. However, at low gains, periodic calibrations may be required to remove the offset and offset drift. When ax excitation is enabled, chop must be enabled also. AC excitation enable bit. If the signal source to the AD7195 is ac excited, this bit must be set to 1. For dc-excited inputs, this bit must be 0. With the ACX bit at 1, the AD7195 assumes that the voltage at the AIN(+)/AIN(–) and REFIN(+)/REFIN(–) input terminals are reversed on alternate input sampling cycles (that is, chopped). Note that when the AD7195 is performing internal zero-scale or full-scale calibrations, the ACX bit is treated as a 0, that is, the device performs these self-calibrations with dc excitation. TheBitCHOP must be set to 1 when ac excitation is enabled. These bits must be programmed with a Logic 0 for correct operation. Channel select bits. These bits are used to select which channels are enabled on the AD7195 (see Table 25). Several channels can be selected, and the AD7195 automatically sequences them. The conversion on each channel requires the complete settling time. When performing calibrations or when accessing the calibration registers, only one channel can be selected. When this bit is set to 1, the 500 nA current sources in the signal path are enabled. When BURN = 0, the burnout currents are disabled. The burnout currents can be enabled only when the buffer is active and when chop is disabled. Enables the reference detect function. When set, the NOREF bit in the status register indicates when the external reference being used by the ADC is open circuit or less than 0.6 V maximum. The reference detect circuitry operates only when the ADC is active. This bit must be programmed with a Logic 0 for correct operation. Enables the buffer on the analog inputs. If cleared, the analog inputs are unbuffered, lowering the power consumption of the device. If this bit is set, the analog inputs are buffered, allowing the user to place source impedances on the front end without contributing gain errors to the system. With the buffer disabled, the voltage on the analog input pins can be from 50 mV below AGND to 50 mV above AVDD. When the buffer is enabled, it requires some headroom; therefore, the voltage on any input pin must be limited to 250 mV within the power supply rails. Polarity select bit. When this bit is set, unipolar operation is selected. When this bit is cleared, bipolar operation is selected. Gain select bits. These bits are written by the user to select the ADC input range as follows: G2 G1 G0 Gain ADC Input Range (5 V Reference) 0 0 0 1 ±5 V 0 0 1 Reserved 0 1 0 Reserved 0 1 1 8 ±625 mV 1 0 0 16 ±312.5 mV 1 0 1 32 ±156.2 mV 1 1 0 64 ±78.125 mV 1 1 1 128 ±39.06 mV Rev. 0 | Page 22 of 44 AD7195 Table 25. Channel Selection Channel Enable Bits in the Configuration Register CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 1 1 1 1 1 1 1 1 Channel Enabled Positive Input Negative Input AIN(+) AIN(−) AIN1 AIN2 AIN3 AIN4 Temperature sensor AIN2 AIN2 AIN1 AINCOM AIN2 AINCOM AIN3 AINCOM AIN4 AINCOM Status Register Bits CHD[2:0] 000 001 010 011 100 101 110 111 Calibration Register Pair 0 1 None 0 0 1 2 3 DATA REGISTER (RS2, RS1, RS0 = 0, 1, 1; Power-On/Reset = 0x000000) The conversion result from the ADC is stored in this data register. This is a read-only, 24-bit register. On completion of a read operation from this register, the RDY pin/bit is set. When the DAT_STA bit in the mode register is set to 1, the contents of the status register are appended to each 24-bit conversion. This is advisable when several analog input channels are enabled because the three LSBs of the status register (CHD2 to CHD0) identify the channel from which the conversion originated. ID REGISTER (RS2, RS1, RS0 = 1, 0, 0; Power-On/Reset = 0xA6) The identification number for the AD7195 is stored in the ID register. This is a read-only register. GPOCON REGISTER (RS2, RS1, RS0 = 1, 0, 1; Power-On/Reset = 0x00) The GPOCON register is an 8-bit register from which data can be read or to which data can be written. This register is used to enable the general-purpose digital outputs. Table 26 outlines the bit designations for the GPOCON register. GP0 through GP7 indicate the bit locations. GP denotes that the bits are in the GPOCON register. GP7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. GP7 0 GP6 BPDSW(0) GP5 0 GP4 0 GP3 0 GP2 0 GP1 0 GP0 0 Table 26. Register Bit Designations Bit Location GP7 GP 6 Bit Name 0 BPDSW GP5 to GP0 0 Description This bit must be programmed with a Logic 0 for correct operation. Bridge power-down switch control bit. This bit is set by the user to close the bridge power-down switch BPDSW to AGND. The switch can sink up to 30 mA. The bit is cleared by the user to open the bridge powerdown switch. When the ADC is placed in power-down mode, the bridge power-down switch remains active. These bits must be programmed with a Logic 0 for correct operation. Rev. 0 | Page 23 of 44 AD7195 FULL-SCALE REGISTER OFFSET REGISTER (RS2, RS1, RS0 = 1, 1, 1; Power-On/Reset = 0x5XXXX0) (RS2, RS1, RS0 = 1, 1, 0; Power-On/Reset = 0x800000) The offset register holds the offset calibration coefficient for the ADC. The power-on reset value of the offset register is 0x800000. The AD7195 has four offset registers; therefore, each channel has a dedicated offset register (see Table 25). Each of these registers is a 24-bit read/write register. This register is used in conjunction with its associated full-scale register to form a register pair. The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7195 must be placed in powerdown mode or idle mode when writing to the offset register. The full-scale register is a 24-bit register that holds the full-scale calibration coefficient for the ADC. The AD7195 has four fullscale registers; therefore, each channel has a dedicated full-scale register (see Table 25). The full-scale registers are read/write registers. However, when writing to the full-scale registers, the ADC must be placed in power-down mode or idle mode. These registers are configured at power-on with factory-calibrated full-scale calibration coefficients, the calibration being performed at gain = 1. Therefore, every device has different default coefficients. The default value is automatically overwritten if an internal or system full-scale calibration is initiated by the user or if the full-scale register is written to. Rev. 0 | Page 24 of 44 AD7195 ADC CIRCUIT INFORMATION AVDD AGND DVDD DGND REFIN(+) REFIN(–) REFERENCE DETECT AIN1 AIN2 AIN3 AIN4 AVDD MUX PGA AINCOM SERIAL INTERFACE AND CONTROL LOGIC Σ-Δ ADC DOUT/RDY DIN SCLK CS SYNC BPDSW AGND AC EXCITATION CLOCK AD7195 ACX1 ACX1 CLOCK CIRCUITRY ACX2 ACX2 MCLK1 MCLK2 08771-001 TEMP SENSOR Figure 18. Block Diagram Σ-Δ ADC and Filter OVERVIEW The AD7195 is an ultralow noise ADC that incorporates a Σ-Δ modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals, such as those in pressure transducers, weigh scales, and strain gage applications. Figure 18 shows the block diagram for the part. Analog Inputs The device can be configured to have two differential or four pseudo differential analog inputs. The analog inputs can be buffered or unbuffered. Multiplexer The AD7195 contains a fourth-order Σ-Δ modulator followed by a digital filter. The device offers the following filter options: • • • • Sinc4 Sinc3 Chop enabled/disabled Zero latency AC Excitation The AD7195 supports ac excitation of load cells. It provides the four logic outputs needed to control the transistors in an ac excited load cell design. The on-chip multiplexer increases the channel count of the device. Because the multiplexer is included on chip, any channel changes are synchronized with the conversion process. Serial Interface PGA Clock The analog input signal can be amplified using the PGA. The PGA allows gains of 1, 8, 16, 32, 64, and 128. The AD7195 has an internal 4.92 MHz clock. Either this clock or an external clock can be used as the clock source to the AD7195. The internal clock can also be made available on a pin if a clock source is required for external circuitry. Reference Detect The AD7195 is capable of monitoring the external reference. If the reference is not present, a flag is set in the status register of the device. Burnout Currents Two 500 nA burnout currents are included on-chip to detect the presence of the external sensor. The AD7195 has a 4-wire SPI. The on-chip registers are accessed via the serial interface. Temperature Sensor The on-chip temperature sensor monitors the die temperature. Calibration Both internal and system calibration are included on chip; thus, the user has the option of removing offset/gain errors internal to the AD7195 only, or removing the offset/gain errors of the complete end system. Rev. 0 | Page 25 of 44 AD7195 The AD7195 has two differential/four pseudo differential analog input channels, which can be buffered or unbuffered. In buffered mode (the BUF bit in the configuration register is set to 1), the input channel feeds into a high impedance input stage of the buffer amplifier. Therefore, the input can tolerate significant source impedances and is tailored for direct connection to external resistive-type sensors such as strain gages or resistance temperature detectors (RTDs). When BUF = 0, the part operates in unbuffered mode. This results in a higher analog input current. Note that this unbuffered input path provides a dynamic load to the driving source. Therefore, resistor/capacitor combinations on the input pins can cause gain errors, depending on the output impedance of the source that is driving the ADC input. Table 27 shows the allowable external resistance/capacitance values for unbuffered mode at a gain of 1 such that no gain error at the 20-bit level is introduced. Table 27. External R-C Combination for No 20-Bit Gain Error C (pF) R (Ω) 50 1.4 k 100 850 500 300 1000 230 5000 30 The absolute input voltage range in buffered mode is restricted to a range between AGND + 250 mV and AVDD − 250 mV. Care must be taken in setting up the common-mode voltage so that these limits are not exceeded. Otherwise, linearity and noise performance degrades. AD7195 is 0 to 3.75 V/gain in unipolar mode or ±3.75 V/gain in bipolar mode. REFERENCE The ADC has a fully differential input capability for the reference channel. The common-mode range for these differential inputs is from AGND to AVDD. The reference voltage REFIN (REFIN(+) − REFIN(−)) is AVDD nominal, but the AD7195 is functional with reference voltages from 1 V to AVDD. In applications where the excitation (voltage or current) for the transducer on the analog input also drives the reference voltage for the part, the effect of the low frequency noise in the excitation source is removed because the application is ratiometric. If the AD7195 is used in a nonratiometric application, a low noise reference should be used. The reference input is unbuffered; therefore, excessive R-C source impedances introduce gain errors. R-C values similar to those in Table 27 are recommended for the reference inputs. Deriving the reference input voltage across an external resistor means that the reference input sees significant external source impedance. External decoupling on the REFINx pins is not recommended in this type of circuit configuration. Conversely, if large decoupling capacitors are used on the reference inputs, there should be no resistors in series with the reference inputs. Recommended 2.5 V reference voltage sources for the AD7195 include the ADR421 and ADR431, which are low noise references. These references tolerate decoupling capacitors on REFIN(+) without introducing gain errors in the system. Figure 19 shows the recommended connections between the ADR421 and the AD7195. 2 The absolute input voltage in unbuffered mode includes the range between AGND − 50 mV and AVDD + 50 mV. The negative absolute input voltage limit does allow the possibility of monitoring small true bipolar signals with respect to AGND. 0.1µF VIN VOUT 6 10µF REFINx(+) 4.7µF 4 PGA AD7195 ADR421 AVDD GND TRIM 5 REFINx(–) 08771-037 ANALOG INPUT CHANNEL Figure 19. ADR421 to AD7195 Connections When the gain stage is enabled, the output from the buffer is applied to the input of the PGA. The presence of the PGA means that signals of small amplitude can be gained within the AD7195 while still maintaining excellent noise performance. For example, when the gain is set to 128, the rms noise is 8.5 nV, typically, when the output data rate is 4.7 Hz, which is equivalent to 23 bits of effective resolution or 20.5 bits of noise-free resolution. The AD7195 can be programmed to have a gain of 1, 8, 16, 32, 64, and 128 using Bit G2 to Bit G0 in the configuration register. Therefore, with an external 2.5 V reference, the unipolar ranges are from 0 mV to 19.53 mV to 0 V to 2.5 V and the bipolar ranges are from ±19.53 mV to ±2.5 V. The analog input range must be limited to ±(AVDD − 1.25 V)/gain because the PGA requires some headroom. Therefore, if AVDD = 5 V, the maximum analog input that can be applied to the REFERENCE DETECT The AD7195 includes on-chip circuitry to detect whether the part has a valid reference for conversions or calibrations. This feature is enabled when the REFDET bit in the configuration register is set to 1. If the voltage between the REFIN(+) and REFIN(−) pins is between 0.3 V and 0.6 V, the AD7195 detects that it no longer has a valid reference. In this case, the NOREF bit of the status register is set to 1. If the AD7195 is performing normal conversions and the NOREF bit becomes active, the conversion result is all 1s. Therefore, it is not necessary to continuously monitor the status of the NOREF bit when performing conversions. It is only necessary to verify its status if the conversion result read from the ADC data register is all 1s. If the AD7195 is performing either an offset or full-scale calibration and the NOREF bit becomes active, the updating of the respective calibration Rev. 0 | Page 26 of 44 AD7195 registers is inhibited to avoid loading incorrect coefficients to these registers, and the ERR bit in the status register is set. If the user is concerned about verifying that a valid reference is in place every time a calibration is performed, the status of the ERR bit should be checked at the end of the calibration cycle. turned on, they flow in the external transducer circuit, and a measurement of the input voltage on the analog input channel can be taken. It will take some time for the burnout currents to detect an open circuit condition as the currents will need to charge any external capacitors BIPOLAR/UNIPOLAR CONFIGURATION There are several reasons why a fault condition might be detected. The front-end sensor may be open circuit. The frontend sensor may be overloaded, or the reference may be absent and the NOREF bit in the status register is set, thus clamping the data to all 1s. Check these possibilities first. If the voltage measured is 0 V, it may indicate that the transducer has short circuited. The current sources work over the normal absolute input voltage range specifications when the analog inputs are buffered and chop is disabled. The analog input to the AD7195 can accept either unipolar or bipolar input voltage ranges. A bipolar input range does not imply that the part can tolerate negative voltages with respect to system AGND. In pseudo differential mode, signals are referenced to AINCOM while in differential mode, signals are referenced to the negative input of the differential pair. For example, if AINCOM is 2.5 V and the AD7195 AIN1 analog input is configured for unipolar mode with a gain of 2, the input voltage range on the AIN1 pin is 2.5 V to 3.75 V when a 2.5 V reference is used. If AINCOM is 2.5 V and the AD7195 AIN1 analog input is configured for bipolar mode with a gain of 2, the analog input range on AIN1 is 1.25 V to 3.75 V. The bipolar/unipolar option is chosen by programming the U/B bit in the configuration register. DATA OUTPUT CODING When the ADC is configured for unipolar operation, the output code is natural (straight) binary with a zero differential input voltage resulting in a code of 00...00, a midscale voltage resulting in a code of 100...000, and a full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as Code = (2N × AIN × Gain)/VREF When the ADC is configured for bipolar operation, the output code is offset binary with a negative full-scale voltage resulting in a code of 000...000, a zero differential input voltage resulting in a code of 100...000, and a positive full-scale input voltage resulting in a code of 111...111. The output code for any analog input voltage can be represented as Code = 2N – 1 × [(AIN × Gain/VREF) + 1] where: N = 24. AIN is the analog input voltage. Gain is the PGA setting (1 to 128). BURNOUT CURRENTS The AD7195 contains two 500 nA constant current generators, one sourcing current from AVDD to AIN(+) and one sinking current from AIN(−) to AGND, where AIN(+) is the positive analog input terminal and AIN(−) is the negative analog input terminal in differential mode and AINCOM in pseudo differential mode. The currents are switched to the selected analog input pair. Both currents are either on or off, depending on the burnout current enable (BURN) bit in the configuration register. These currents can be used to verify that an external transducer remains operational before attempting to take measurements on that channel. After the burnout currents are AC EXCITATION AC excitation of the bridge addresses many of the concerns with thermocouple, offset, and drift effects encountered in dc excited applications. In ac excitation, the polarity of the excitation voltage to the bridge is reversed on alternate cycles. The result is the elimination of dc errors at the expense of a more complex system design. Figure 50 outlines the connections for an ac excited bridge application based on the AD7195. The excitation voltage to the bridge must be switched on alternate cycles. Transistor T1 to Transistor T4 in Figure 50 perform the switching of the excitation voltage. These transistors can be discrete matched bipolar or MOS transistors, or a dedicated bridge driver chip, such as the MIC4427 available from Micrel Components, can be used to perform the task. Since the analog input voltage and the reference voltage are reversed on alternate cycles, the AD7195 must be synchronized with this reversing of the excitation voltage. To allow the AD7195 to synchronize itself with this switching, it provides the logic control signals for the switching of the excitation voltage. These signals are the nonoverlapping CMOS outputs ACX1/ACX1 and ACX2/ACX2. One of the problems encountered with ac excitation is the settling time associated with the analog input signals after the excitation voltage is switched. This is particularly true in applications where there are long lead lengths from the bridge to the AD7195. It means that the converter could encounter errors because it is processing signals that are not fully settled. The AD7195 includes a delay between the switching of the ac excitation signals and the processing of data at the analog inputs. The delay equals 100 μs when FS[9:0] equals 1 and equals 200 μs for all other output data rates. The AD7195 also scales the ac excitation switching frequency in accordance with the output data rate. This avoids situations where the bridge is switched at an unnecessarily faster rate than the system requires. The fact that the AD7195 can handle reference voltages, which are the same as the excitation voltages, is particularly useful Rev. 0 | Page 27 of 44 AD7195 in ac excitation where resistor divider arrangements on the reference input add to the settling time associated with the switching. When the ACX bit in the configuration register is set to 0, the digital outputs ACX1 and ACX2 are high, while outputs ACX2 and ACX1 are low. Therefore, the bridge is dc excited with the T2 and T4 transistors turned on and the T1 and T3 transistors turned off. When the AD7195 is in power-down mode, outputs ACX1 and ACX2 are low and outputs ACX1 and ACX2 are high so that the excitation voltage is disconnected from the bridge. CHANNEL SEQUENCER The AD7195 includes a channel sequencer, which simplifies communications with the device in multichannel applications. The sequencer also optimizes the channel throughput of the device because the sequencer switches channels at the optimum rate rather than waiting for instructions via the SPI interface. When several channels are enabled, the ADC must allow the complete settling time to generate a valid conversion each time that the channel is changed. The AD7195 takes care of this: when a channel is selected, the modulator and filter are reset, and the RDY pin is taken high. The AD7195 then allows the complete settling time to generate the first conversion. RDY goes low only when a valid conversion is available. The AD7195 then selects the next enabled channel and converts on that channel. The user can then read the data register while the ADC is performing the conversion on the next channel. The time required to read a valid conversion from all enabled channels is equal to tSETTLE × number of enabled channels For example, if the sinc4 filter is selected, chop is disabled, and zero latency is disabled, the settling time for each channel is equal to tSETTLE = 4/fADC Bit CH0 to Bit CH7 in the configuration register are used to enable the required channels. In continuous conversion mode, the ADC selects each of the enabled channels in sequence and performs a conversion on the channel. The RDY pin goes low when a valid conversion is available on each channel. When several channels are enabled, the contents of the status register should be attached to the 24-bit word so that the user can identify the channel that corresponds to each conversion. To attach the status register value to the conversion, Bit DAT_STA in the mode register should be set to 1. where fADC is the output data rate when continuously converting on a single channel. The time required to sample N channels is DIGITAL INTERFACE The DOUT/RDY pin functions as a data ready signal also; the line goes low when a new data-word is available in the output register. It is reset high when a read operation from the data register is complete. It also goes high prior to the updating of the data register to indicate when not to read from the device to ensure that a data read is not attempted while the register is being updated. CS is used to select a device. It can be used to decode the AD7195 in systems where several components are connected to the serial bus. As indicated in the On-Chip Registers section, the programmable functions of the AD7195 are controlled using a set of on-chip registers. Data is written to these registers via the serial interface of the part. Read access to the on-chip registers is also provided by this interface. All communication with the part must start with a write to the communications register. After power-on or reset, the device expects a write to its communications register. The data written to this register determines whether the next operation is a read operation or a write operation and determines to which register this read or write operation occurs. Therefore, write access to any of the other registers on the part begins with a write operation to the communications register, followed by a write to the selected register. A read operation from any other register (except when continuous read mode is selected) starts with a write to the communications register, followed by a read operation from the selected register. The serial interface of the AD7195 consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The DIN line is used to transfer data into the on-chip registers and DOUT/RDY is used for accessing data from the on-chip registers. SCLK is the serial clock input for the device, and all data transfers (either on DIN or DOUT/RDY) occur with respect to the SCLK signal. 4/(fADC× N) RDY CHANNEL A CHANNEL B CHANNEL C 1/fADC 08771-028 CONVERSIONS Figure 20. Channel Sequencer Figure 3 and Figure 4 show timing diagrams for interfacing to the AD7195, with CS being used to decode the part. Figure 3 shows the timing for a read operation from the output shift register of the AD7195, and Figure 4 shows the timing for a write operation to the input shift register. It is possible to read the same word from the data register several times even though the DOUT/RDY line returns high after the first read operation. However, care must be taken to ensure that the read operations are completed before the next output update occurs. In continuous read mode, the data register can be read only once. Rev. 0 | Page 28 of 44 AD7195 The serial interface can operate in 3-wire mode by tying CS low. In this case, the SCLK, DIN, and DOUT/RDY lines are used to communicate with the AD7195. The end of the conversion can be monitored using the RDY bit or pin. This scheme is suitable for interfacing to microcontrollers. If CS is required as a decoding signal, it can be generated from a port pin. For microcontroller interfaces, it is recommended that SCLK idle high between data transfers. The AD7195 can be operated with CS used as a frame synchronization signal. This scheme is useful for DSP interfaces. In this case, the first bit (MSB) is effectively clocked out by CS because CS normally occurs after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers, provided the timing numbers are obeyed. The serial interface can be reset by writing a series of 1s to the DIN input. If a Logic 1 is written to the AD7195 DIN line for at least 40 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system. Reset returns the interface to the state in which it expects a write to the communications register. This operation resets the contents of all registers to their power-on values. Following a reset, the user should allow a period of 500 μs before addressing the serial interface. The AD7195 can be configured to continuously convert or to perform a single conversion (see Figure 21 through Figure 23). Single Conversion Mode In single conversion mode, the AD7195 is placed in powerdown mode after conversions. When a single conversion is initiated by setting MD2, MD1, and MD0 to 0, 0, 1, respectively, in the mode register, the AD7195 powers up, performs a single conversion, and then returns to power-down mode. The onchip oscillator requires 1 ms, approximately, to power up. DOUT/RDY goes low to indicate the completion of a conversion. When the data-word has been read from the data register, DOUT/RDY goes high. If CS is low, DOUT/RDY remains high until another conversion is initiated and completed. The data register can be read several times, if required, even when DOUT/RDY has gone high. If several channels are enabled, the ADC sequences through the enabled channels and performs a conversion on each channel. When a conversion is started, DOUT/RDY goes high and remains high until a valid conversion is available. As soon as the conversion is available, DOUT/RDY goes low. The ADC then selects the next channel and begins a conversion. The user can read the present conversion while the next conversion is being performed. As soon as the next conversion is complete, the data register is updated; therefore, the user has a limited period in which to read the conversion. When the ADC has performed a single conversion on each of the selected channels, it returns to power-down mode. If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. The four LSBs of the status register indicate the channel to which the conversion corresponds. CS 0x08 0x280060 0x58 DIN DATA 08771-029 DOUT/RDY SCLK Figure 21. Single Conversion Rev. 0 | Page 29 of 44 AD7195 Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7195 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion is completed. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register. When the data-word has been read from the data register, DOUT/RDY goes high. The user can read this register additional times, if required. However, the user must ensure that the data register is not being accessed at the completion of the next conversion or else the new conversion word is lost. When several channels are enabled, the ADC continuously loops through the enabled channels, performing one conversion on each channel per loop. The data register is updated as soon as each conversion is available. The DOUT/RDY pin pulses low each time a conversion is available. The user can then read the conversion while the ADC converts on the next enabled channel. If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion each time that the data read is performed. The status register indicates the channel to which the conversion corresponds. CS 0x58 0x58 DIN DATA DATA 08771-030 DOUT/RDY SCLK Figure 22. Continuous Conversion Rev. 0 | Page 30 of 44 AD7195 Continuous Read conversion is complete, and the new conversion is placed in the output serial register. Rather than write to the communications register each time a conversion is complete to access the data, the AD7195 can be configured so that the conversions are placed on the DOUT/RDY line automatically. By writing 01011100 to the communications register, the user need only apply the appropriate number of SCLK cycles to the ADC, and the conversion word is automatically placed on the DOUT/RDY line when a conversion is complete. The ADC should be configured for continuous conversion mode. To exit the continuous read mode, Instruction 01011000 must be written to the communications register while the RDY pin is low. While in continuous read mode, the ADC monitors activity on the DIN line so that it can receive the instruction to exit the continuous read mode. Additionally, a reset occurs if 40 consecutive 1s are seen on DIN. Therefore, DIN should be held low in continuous read mode until an instruction is to be written to the device. When several channels are enabled, the ADC continuously steps through the enabled channels and performs one conversion on each channel each time that it is selected. DOUT/ RDY pulses low when a conversion is available. When the user applies sufficient SCLK pulses, the data is automatically placed on the DOUT/RDY pin. If the DAT_STA bit in the mode register is set to 1, the contents of the status register are output along with the conversion. The status register indicates the channel to which the conversion corresponds. When DOUT/RDY goes low to indicate the end of a conversion, sufficient SCLK cycles must be applied to the ADC; the data conversion is then placed on the DOUT/RDY line. When the conversion is read, DOUT/RDY returns high until the next conversion is available. In this mode, the data can be read only once. Also, the user must ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion, or if insufficient serial clocks are applied to the AD7195 to read the word, the serial output register is reset when the next CS 0x5C DIN DATA DATA DATA 08771-031 DOUT/RDY SCLK Figure 23. Continuous Read Rev. 0 | Page 31 of 44 AD7195 RESET The circuitry and serial interface of the AD7195 can be reset by writing consecutive 1s to the device; 40 consecutive 1s are required to perform the reset. This resets the logic, the digital filter, and the analog modulator, whereas all on-chip registers are reset to their default values. A reset is automatically performed on power-up. When a reset is initiated, the user must allow a period of 500 μs before accessing any of the on-chip registers. A reset is useful if the serial interface loses synchronization due to noise on the SCLK line. SYSTEM SYNCHRONIZATION The SYNC input allows the user to reset the modulator and the digital filter without affecting any of the setup conditions on the part. This allows the user to start gathering samples of the analog input from a known point in time, that is, the rising edge of SYNC. SYNC needs to be taken low for at least four master clock cycles to implement the synchronization function. If multiple AD7195 devices operate from a common master clock, they can be synchronized so that their data registers are updated simultaneously. A falling edge on the SYNC pin resets the digital filter and the analog modulator and places the AD7195 into a consistent, known state. While the SYNC pin is low, the AD7195 is maintained in this state. On the SYNC rising edge, the modulator and filter are taken out of this reset state and, on the next clock edge, the part starts to gather input samples again. In a system using multiple AD7195 devices, a common signal to their SYNC pins synchronizes their operation. This is normally done after each AD7195 has performed its own calibration or has calibration coefficients loaded into its calibration registers. The conversions from the AD7195s are then synchronized. The part is taken out of reset on the master clock falling edge following the SYNC low to high transition. Therefore, when multiple devices are being synchronized, the SYNC pin should be taken high on the master clock rising edge to ensure that all devices begin sampling on the master clock falling edge. If the SYNC pin is not taken high in sufficient time, a difference of one master clock cycle may result between the devices; that is, the instant at which conversions are available differs from part to part by a maximum of one master clock cycle. The SYNC pin can also be used as a start conversion command. In this mode, the rising edge of SYNC starts conversion, and the falling edge of RDY indicates when the conversion is complete. The settling time of the filter has to be allowed for each data register update. For example, if the ADC is configured to use the sinc4 filter, zero latency is disabled, and chop is disabled, the settling time equals 4/fADC where fADC is the output data rate when continuously converting on a single channel. CLOCK The AD7195 includes an internal 4.92 MHz clock on-chip. This internal clock has a tolerance of ±4%. Either the internal clock or an external crystal/clock can be used as the clock source to the AD7195. The clock source is selected using the CLK1 and CLK0 bits in the mode register. When an external crystal is used, it must be connected across the MCLK1 and MCLK2 pins. The crystal manufacturer recommends the load capacitances required for the crystal. The MCLK1 and MCLK2 pins of the AD7195 have a capacitance of 15 pF, typically. If an external clock source is used, the clock source must be connected to the MCLK2 pin, and the MCLK1 pin can be left floating. The internal clock can also be made available at the MCLK2 pin. This is useful when several ADCs are used in an application and the devices must be synchronized. The internal clock from one device can be used as the clock source for all ADCs in the system. Using a common clock, the devices can be synchronized by applying a common reset to all devices, or the SYNC pin can be pulsed. ENABLE PARITY The AD7195 also has an on-chip parity check function that detects 1-bit errors in the serial communications between the ADC and the microprocessor. When the ENPAR bit in the mode register is set to 1, parity is enabled. The contents of the status register must be transmitted along with each 24-bit conversion when the parity function is enabled. To append the contents of the status register to each conversion read, the DAT_STA bit in the mode register should be set to 1. For each conversion read, the parity bit in the status register is programmed so that the overall number of 1s transmitted in the 24-bit data-word is even. Therefore, for example, if the 24-bit conversion contains eleven 1s (binary format), the parity bit is set to 1 so that the total number of 1s in the serial transmission is even. If the microprocessor receives an odd number of 1s, it knows that the data received has been corrupted. The parity function only detects 1-bit errors. For example, two bits of corrupt data can result in the microprocessor receiving an even number of 1s. Therefore, an error condition is not detected. TEMPERATURE SENSOR Embedded in the AD7195 is a temperature sensor. This is selected using the CH2 bit in the configuration register. When the CH2 bit is set to 1, the temperature sensor is enabled. When the temperature sensor is selected and bipolar mode is selected, the device should return a code of 0x800000 when the temperature is 0 K. A one-point calibration is needed to get the optimum performance from the sensor. Therefore, a conversion at 25°C should be recorded and the sensitivity calculated. The sensitivity is approximately 2815 codes/°C. The equation for the temperature sensor is Temp (K) = (Conversion − 0x800000)/2815 K Temp (°C) = Temp (K) − 273 Following the one point calibration, the internal temperature sensor has an accuracy of ±2 °C, typically. Rev. 0 | Page 32 of 44 AD7195 BRIDGE POWER-DOWN SWITCH In bridge applications, such as strain gauges and load cells, the bridge itself consumes the majority of the current in the system. For example, a 350 Ω load cell requires 15 mA of current when excited with a 5 V supply. To minimize the current consumption of the system, the bridge can be disconnected (when it is not being used) using the bridge power-down switch. Figure 50 shows how the bridge power-down switch is used. The switch can withstand 30 mA of continuous current, and it has an on resistance of 10 Ω maximum. CALIBRATION The AD7195 provides four calibration modes that can be programmed via the mode bits in the mode register. These modes are internal zero-scale calibration, internal full-scale calibration, system zero-scale calibration, and system full-scale calibration. A calibration can be performed at any time by setting the MD2 to MD0 bits in the mode register appropriately. A calibration should be performed when the gain is changed. After each conversion, the ADC conversion result is scaled using the ADC calibration registers before being written to the data register. The offset calibration coefficient is subtracted from the result prior to multiplication by the full-scale coefficient. To start a calibration, write the relevant value to the MD2 to MD0 bits. The DOUT/RDY pin and the RDY bit in the status register go high when the calibration is initiated. When the calibration is complete, the contents of the corresponding calibration registers are updated, the RDY bit in the status register is reset, the DOUT/ RDY pin returns low (if CS is low), and the AD7195 reverts to idle mode. During an internal zero-scale or full-scale calibration, the respective zero input and full-scale input are automatically connected internally to the ADC input pins. A system calibration, however, expects the system zero-scale and system full-scale voltages to be applied to the ADC pins before initiating the calibration mode. In this way, errors external to the ADC are removed. From an operational point of view, treat a calibration like another ADC conversion. A zero-scale calibration, if required, must always be performed before a full-scale calibration. Set the system software to monitor the RDY bit in the status register or the DOUT/RDY pin to determine the end of calibration via a polling sequence or an interrupt-driven routine. With chop disabled, both an internal zero-scale calibration and a system zero-scale calibration require a time equal to the settling time, tSETTLE, (4/fADC for the sinc4 filter and 3/fADC for the sinc3 filter). With chop enabled, an internal zero-scale calibration is not needed because the ADC itself minimizes the offset continuously. However, if an internal zero-scale calibration is performed, the settling time, tSETTLE, (2/fADC) is required to perform the calibration. Similarly, a system zero-scale calibration requires a time of tSETTLE to complete. To perform an internal full-scale calibration, a full-scale input voltage is automatically connected to the selected analog input for this calibration. For a gain of 1, the time required for an internal full-scale calibration is equal to tSETTLE. For higher gains, the internal full-scale calibration requires a time of 2 × tSETTLE. A full-scale calibration is recommended each time the gain of a channel is changed to minimize the full-scale error. A system full-scale calibration requires a time of tSETTLE. With chop disabled, the zero-scale calibration (internal or system zero-scale) should be performed before the system full-scale calibration is initiated. An internal zero-scale calibration, system zero-scale calibration and system full-scale calibration can be performed at any output data rate. An internal full-scale calibration can be performed at any output data rate for which the filter word FS[9:0] is divisible by 16, FS[9:0] being the decimal equivalent of the 10-bit word written to Bit FS9 to Bit FS0 in the mode register. Therefore, internal full-scale calibrations can be performed at output data rates such as 10 Hz or 50 Hz when chop is disabled. Using these lower output data rates results in better calibration accuracy. The offset error is, typically, 100 μV/gain. If the gain is changed, it is advisable to perform a calibration. A zero-scale calibration (an internal zero-scale calibration or system zero-scale calibration) reduces the offset error to the order of the noise. The gain error of the AD7195 is factory calibrated at a gain of 1 with a 5 V power supply at ambient temperature. Following this calibration, the gain error is 0.001%, typically, at 5 V. Table 28 shows the typical uncalibrated gain error for the different gain settings. An internal full-scale calibration reduces the gain error to 0.001%, typically, when the gain is equal to 1. For higher gains, the gain error post internal full-scale calibration is 0.0075%, typically. A system full-sale calibration reduces the gain error to the order of the noise. Table 28. Typical Precalibration Gain Error vs. Gain Gain 8 16 32 64 128 Precalibration Gain Error (%) −0.11 −0.20 −0.23 −0.29 −0.39 The AD7195 gives the user access to the on-chip calibration registers, allowing the microprocessor to read the calibration coefficients of the device and also to write its own calibration coefficients from prestored values in the EEPROM. A read of the registers can be performed at any time. However, the ADC must be placed in power-down or idle mode when writing to the registers. The values in the calibration registers are 24-bits wide. The span and offset of the part can also be manipulated using the registers. Rev. 0 | Page 33 of 44 AD7195 DIGITAL FILTER The AD7195 offers a lot of flexibility in the digital filter. The device has four filter options. The device can be operated with a sinc3 or sinc4 filter, chop can be enabled or disabled, and zero latency can be enabled. The option selected affects the output data rate, settling time, and 50 Hz/60 Hz rejection. The following sections describe each filter type, indicating the available output data rates for each filter option. The filter response along with the settling time and 50 Hz/60 Hz rejection is also discussed. When conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input. Therefore, it continues to output conversions at the programmed output data rate. However, it is at least four conversions later before the output data accurately reflect the analog input. If the step change occurs while the ADC is processing a conversion, then the ADC takes five conversions after the step change to generate a fully settled result. ANALOG INPUT FULLY SETTLED When the AD7195 is powered up, the sinc4 filter is selected by default and chop is disabled. This filter gives excellent noise performance over the complete range of output data rates. It also gives the best 50 Hz/60 Hz rejection, but it has a long settling time. 1/fADC Figure 26. Asynchronous Step Change in Analog Input The 3 dB frequency for the sinc4 filter is equal to f3dB = 0.23 × fADC ADC Table 29 gives some examples of the relationship between the values in Bits FS[9:0] and the corresponding output data rate and settling time. SINC3/SINC4 MODULATOR Table 29. Examples of Output Data Rates and the Corresponding Settling Time 08771-033 CHOP Figure 24. Sinc4 Filter (Chop Disabled) 4 Sinc Output Data Rate/Settling Time The output data rate (the rate at which conversions are available on a single channel when the ADC is continuously converting) is equal to fADC = fCLK/(1024 × FS[9:0]) The settling time for the sinc filter is equal to tSETTLE = 4/fADC When a channel change occurs, the modulator and filter are reset. The settling time is allowed to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/fADC. Sinc4 Zero Latency where: fADC is the output data rate. fCLK is the master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. CHANNEL B CH A CH A CH B CH B 1/fADC CH B 08771-038 CH A Settling Time (ms) 400 80 66.6 fADC = 1/tSETTLE = fCLK/(4 × 1024 × FS[9:0]) 4 CONVERSIONS Output Data Rate (Hz) 10 50 60 The output data rate equals The output data rate can be programmed from 4.7 Hz to 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023. CHANNEL A FS[9:0] 480 96 80 Zero latency is enabled by setting the single bit (Bit 11) in the mode register to 1. With zero latency, the complete settling time is allowed for each conversion. Therefore, the conversion time when converting on a single channel or when converting on several channels is constant. The user does not need to consider the effects of channel changes on the output data rate. where: fADC is the output data rate. fCLK is the master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. CHANNEL 08771-039 ADC OUTPUT SINC4 FILTER (CHOP DISABLED) 4 Figure 25. Sinc Channel Change Rev. 0 | Page 34 of 44 AD7195 When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. When conversions are being performed on a single channel and a step change occurs on the analog input, the ADC continues to output fully settled conversions if the step change is synchronized with the conversion process. If the step change is asynchronous, one conversion is output from the ADC, which is not completely settled (see Figure 27). Figure 29 shows the frequency response when FS[9:0] is programmed to 80 and the master clock is equal to 4.92 MHz. The output data rate is 60 Hz when zero latency is disabled and 15 Hz when zero latency is enabled. The sinc4 filter provides 60 Hz (±1 Hz) rejection of 120 dB minimum, assuming a stable master clock. 0 –10 –20 ANALOG INPUT 08771-040 ADC OUTPUT 1/fADC FILTER GAIN (dB) –30 FULLY SETTLED Figure 27. Sinc4 Zero Latency Operation –40 –50 –60 –70 –80 –90 –100 Table 30 shows examples of output data rate and the corresponding FS values. 0 Table 30. Examples of Output Data Rates and the Corresponding Settling Time (Zero Latency) Settling Time (ms) 400 80 66.6 Sinc4 50 Hz/60 Hz Rejection Figure 28 shows the frequency response of the sinc4 filter when FS[9:0] is set to 96 and the master clock is 4.92 MHz. With zero latency disabled, the output data rate is equal to 50 Hz. With zero latency enabled, the output data rate is 12.5 Hz. The sinc4 filter provides 50 Hz (±1 Hz) rejection in excess of 120 dB minimum, assuming a stable master clock. 0 –10 –20 –30 120 150 Figure 29. Sinc4 Filter Response (FS[9:0] = 80) Simultaneous 50 Hz and 60 Hz rejection is obtained when FS[9:0] is programmed to 480 and the master clock equals 4.92 MHz. The output data rate is 10 Hz when zero latency is disabled and 2.5 Hz when zero latency is enabled. The sinc4 filter provides 50 Hz (±1 Hz) and 60 Hz (±1 Hz) rejection of 120 dB minimum, assuming a stable master clock. 0 –10 –20 –30 –40 –50 –60 –70 –80 –40 –90 –50 –100 –60 –110 –70 –120 0 –80 30 60 90 120 FREQUENCY (Hz) –90 150 Figure 30. Sinc4 Filter Response (FS[9:0] = 480) –100 –110 –120 0 25 50 75 100 125 FREQUENCY (Hz) 150 08771-041 FILTER GAIN (dB) 90 08771-043 Output Data Rate (Hz) 2.5 12.5 15 60 FREQUENCY (Hz) FILTER GAIN (dB) FS[9:0] 480 96 80 30 08771-042 –110 –120 Simultaneous 50 Hz/60 Hz rejection can also be achieved using the REJ60 bit in the mode register. When FS[9:0] is set to 96 and REJ60 is set to 1, notches are placed at 50 Hz and 60 Hz. Figure 28. Sinc4 Filter Response (FS[9:0] = 96) Rev. 0 | Page 35 of 44 AD7195 The output data rate is 50 Hz when zero latency is disabled and 12.5 Hz when zero latency is enabled. Figure 31 shows the frequency response of the sinc4 filter. The filter provides 50 Hz ±1 Hz and 60 Hz ± 1 Hz rejection of 82 dB minimum, assuming a stable 4.92 MHz master clock. 0 f3dB = 0.272 × fADC Table 31 gives some examples of FS settings and the corresponding output data rates and settling times. Table 31. Examples of Output Data Rates and the Corresponding Settling Time –10 –20 FS[9:0] 480 96 80 –30 FILTER GAIN (dB) The 3 dB frequency is equal to –40 –50 –60 Output Data Rate (Hz) 10 50 60 Settling Time (ms) 300 60 50 When a channel change occurs, the modulator and filter reset. The complete settling time is allowed to generate the first conversion after the channel change (see Figure 33). Subsequent conversions on this channel are available at 1/fADC. –70 –80 –90 –100 –110 CHANNEL 0 25 50 75 100 125 08771-044 –120 150 FREQUENCY (Hz) CONVERSIONS CHANNEL B CHANNEL A CH A CH A CH A CH B CH B CH B CH B 08771-045 4 Figure 31. Sinc Filter Response (FS[9:0] = 96, REJ60 = 1) 1/fADC 3 SINC FILTER (CHOP DISABLED) Figure 33. Sinc3 Channel Change A sinc3 filter can be used instead of the sinc4 filter. The filter is selected using the SINC3 bit in the mode register. The sinc3 filter is selected when the SINC3 bit is set to 1. This filter has good noise performance when operating with output data rates up to 1 kHz. It has moderate settling time and moderate 50 Hz/60 Hz (±1 Hz) rejection. ADC When conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input. Therefore, it continues to output conversions at the programmed output data rate. However, it is at least three conversions later before the output data accurately reflects the analog input. If the step change occurs while the ADC is processing a conversion, the ADC takes four conversions after the step change to generate a fully settled result. ANALOG INPUT SINC3/SINC4 FULLY SETTLED ADC OUTPUT Figure 32. Sinc3 Filter (Chop Disabled) 1/fADC Sinc3 Output Data Rate and Settling Time Figure 34. Asynchronous Step Change in Analog Input The output data rate (the rate at which conversions are available on a single channel when the ADC is continuously converting) is equal to fADC = fCLK/(1024 × FS[9:0]) where: fADC is the output data rate. fCLK is the master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 08771-046 MODULATOR 08771-034 CHOP Sinc3 Zero Latency Zero latency is enabled by setting the single bit (Bit 11) in the mode register to 1. With zero latency, the complete settling time is allowed for each conversion. Therefore, the conversion time when converting on a single channel or when converting on several channels is constant. The user does not need to consider the effects of channel changes on the output data rate. The output data rate can be programmed from 4.7 Hz to 4800 Hz; that is, FS[9:0] can have a value from 1 to 1023. The settling time is equal to tSETTLE = 3/fADC Rev. 0 | Page 36 of 44 AD7195 Sinc3 50 Hz/60 Hz Rejection The output data rate equals Figure 36 show the frequency response of the sinc3 filter when FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The output data rate is equal to 50 Hz when zero latency is disabled and 16.7 Hz when zero latency is enabled. The sinc3 filter gives 50 Hz ± 1 Hz rejection of 95 dB minimum for a stable master clock. fADC = 1/tSETTLE = fCLK/(3 × 1024 × FS[9:0]) where: fADC is the output data rate. fCLK is the master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 0 –10 –20 –30 FILTER GAIN (dB) When the analog input is constant or a channel change occurs, valid conversions are available at a constant output data rate. When conversions are being performed on a single channel and a step change occurs on the analog input, the ADC continues to output fully settled conversions if the step change is synchronized with the conversion process. If the step change is asynchronous, one conversion is output from the ADC that is not completely settled (see Figure 35). –40 –50 –60 –70 –80 –90 –100 ANALOG INPUT –110 FULLY SETTLED ADC OUTPUT 0 25 50 75 100 125 150 FREQUENCY (Hz) Figure 36. Sinc3 Filter Response (FS[9:0] = 96) 08771-047 3 Figure 35. Sinc Zero Latency Operation Table 32 provides examples of output data rates and the corresponding FS values. Table 32. Examples of Output Data Rates and the Corresponding Settling Time (Zero Latency) Output Data Rate (Hz) 3.3 16.7 20 0 Settling Time (ms) 300 60 50 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 30 60 90 120 FREQUENCY (Hz) Figure 37. Sinc3 Filter Response (FS[9:0] = 80) Rev. 0 | Page 37 of 44 150 08771-049 FS[9:0] 480 96 80 When FS[9:0] is set to 80 and the master clock equals 4.92 MHz, 60 Hz rejection is achieved (see Figure 37). The output data rate is equal to 60 Hz when zero latency is disabled and 20 Hz when zero latency is enabled. The sinc3 filter has rejection of 95 dB minimum at 60 Hz ± 1 Hz, assuming a stable master clock. FILTER GAIN (dB) 1/fADC 08771-048 –120 AD7195 Simultaneous 50 Hz and 60 Hz rejection is obtained when FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in Figure 38. The output data rate is 10 Hz when zero latency is disabled and 3.3 Hz when zero latency is enabled. The sinc3 filter has rejection of 100 dB minimum at 50 Hz ± 1 Hz and 60 Hz ± 1 Hz. 0 –10 –20 FILTER GAIN (dB) –30 –40 CHOP ENABLED (SINC4 FILTER) With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded. The analog input pins are then inverted, and another settled conversion is obtained. Subsequent conversions are averaged to minimize the offset. This continuous swapping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. With chop enabled, the resolution increases by 0.5 bits. ADC –50 –60 –70 CHOP –80 SINC3/SINC4 MODULATOR 08771-035 –90 –100 –110 0 30 60 90 120 150 FREQUENCY (Hz) 08771-050 Figure 40. Chop Enabled –120 Figure 38. Sinc3 Filter Response (FS[9:0] = 480) Output Data Rate and Settling Time (Sinc4 Chop Enabled) For the sinc4 filter, the output data rate is equal to Simultaneous 50 Hz/60 Hz rejection is also achieved using the REJ60 bit in the mode register. When FS[9:0] is programmed to 96 and the REJ60 bit is set to 1, notches are placed at both 50 Hz and 60 Hz for a stable 4.92 MHz master clock. Figure 39 shows the frequency response of the sinc3 filter with this configuration. Assuming a stable clock, the rejection at 50 Hz/60 Hz (±1 Hz) is in excess of 67 dB minimum. fADC = fCLK/(4 × 1024 × FS[9:0]) where: fADC is the output data rate. fCLK is the master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. The value of FS[9:0] can be varied from 1 to 1023. This results in an output data rate of 1.17 Hz to 1200 Hz. The settling time is equal to 0 –10 –20 tSETTLE = 2/fADC –40 Table 33 gives some examples of FS[9:0] values and the corresponding output data rates and settling times. –50 –60 –70 Table 33. Examples of Output Data Rates and the Corresponding Settling Time –80 –90 FS[9:0] 96 80 –100 –110 –120 0 25 50 75 100 125 FREQUENCY (Hz) 150 08771-051 FILTER GAIN (dB) –30 Figure 39. Sinc3 Filter Response (FS[9:0] = 96, REJ60 = 1) Rev. 0 | Page 38 of 44 Output Data Rate (Hz) 12.5 15 Settling Time (ms) 160 133 AD7195 CH A CH A CH B CH B CH B CH B CH B 1/fADC Figure 41. Channel Change (Sinc4 Chop Enabled) –30 –40 –50 –60 –70 –80 –90 –100 When conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input; therefore, it continues to output conversions at the programmed output data rate. However, it is at least two conversions later before the output data accurately reflects the analog input. If the step change occurs while the ADC is processing a conversion, the ADC takes three conversions after the step change to generate a fully settled result. ANALOG INPUT –110 –120 0 25 50 75 100 125 08771-054 CH A –20 150 FREQUENCY (Hz) Figure 43. Sinc4 Filter Response (FS[9:0] = 96, Chop Enabled) The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown Figure 44 is achieved. The output data rate is unchanged but the 50 Hz/ 60 Hz (± 1 Hz) rejection is increased to 83 dB typically. 0 FULLY SETTLED –10 ADC OUTPUT –20 4 Figure 42. Asynchronous Step Change in Analog Input (Sinc Chop Enabled) The cutoff frequency f3dB is equal to f3dB = 0.24 × fADC FILTER GAIN (dB) –30 08771-053 1/fADC –40 –50 –60 –70 –80 –90 4 50 Hz/60 Hz Rejection (Sinc Chop Enabled) When FS[9:0] is set to 96 and chopping is enabled, the output data rate is equal to 12.5 Hz for a 4.92 MHz master clock. The filter response shown in Figure 43 is obtained. The chopping introduces notches at odd integer multiples of fADC/2. The notches due to the sinc filter in addition to the notches introduced by the chopping mean that simultaneous 50 Hz and 60 Hz rejection is achieved for an output data rate of 12.5 Hz. The rejection at 50 Hz/60 Hz ± 1 Hz is typically 63 dB, assuming a stable master clock. –100 –110 –120 0 25 50 75 100 FREQUENCY (Hz) 125 150 08771-055 CONVERSIONS CHANNEL B 08771-052 CHANNEL CHANNEL A 0 –10 FILTER GAIN (dB) When a channel change occurs, the modulator and filter reset. The complete settling time is required to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/fADC. Figure 44. Sinc4 Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1) Rev. 0 | Page 39 of 44 AD7195 With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded. The analog input pins invert and another settled conversion is obtained. Subsequent conversions are averaged to minimize the offset. This continuous swapping of the analog input pins and the averaging of subsequent conversions means that the offset drift is also minimized. With chop enabled, the resolution increases by 0.5 bits. Using the sinc3 filter with chop enabled is suitable for output data rates up to 320 Hz. If conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog input; therefore, it continues to output conversions at the programmed output data rate. However, it is at least two conversions later before the output data accurately reflects the analog input. If the step change occurs while the ADC is processing a conversion, then the ADC takes three conversions after the step change to generate a fully settled result. ANALOG INPUT FULLY SETTLED ADC OUTPUT 08771-057 CHOP ENABLED (SINC3 FILTER) ADC 1/fADC Figure 47. Asynchronous Step Change in Analog Input (Sinc3 Chop Enabled) The cutoff frequency f3dB is equal to SINC3/SINC4 f3dB = 0.24 × fADC 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) Figure 45. Chop Enabled (Sinc3 Chop Enabled) When FS[9:0] is set to 96 and chopping is enabled, the filter response shown in Figure 48 is obtained. The output data rate is equal to 16.7 Hz for a 4.92 MHz master clock. The chopping introduces notches at odd integer multiples of fADC/2. The notches due to the sinc filter in addtion to the notches introduced by the chopping means that simultaneous 50 Hz and 60 Hz rejection is achieved for an output data rate of 16.7 Hz. The rejection at 50 Hz/60 Hz ± 1 Hz is typically 53 dB, assuming a stable master clock. Output Data Rate and Settling Time (Sinc3 Chop Enabled) For the sinc3 filter, the output data rate is equal to fADC = fCLK/(3 × 1024 × FS[9:0]) where: fADC is the output data rate. fCLK is the master clock (4.92 MHz nominal). FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the mode register. 0 –10 The value of FS[9:0] can be varied from 1 to 1023. This results in an output data rate of 1.56 Hz to 1600 Hz. The settling time is equal to tSETTLE = 2/fADC Table 34. Examples of Output Data Rates and the Corresponding Settling Time (Chop Enabled, Sinc3 Filter) Output Data Rate (Hz) 16.7 20 –30 –40 –50 –60 –70 –80 –90 Settling Time (ms) 120 100 –100 –110 –120 When a channel change occurs, the modulator and filter are reset. The complete settling time is required to generate the first conversion after the channel change. Subsequent conversions on this channel occur at 1/fADC. CONVERSIONS CHANNEL A CH A CH A CH A CHANNEL B CH B CH B CH B CH B 1/fADC CH B 08771-056 CHANNEL Figure 46. Channel Change (Sinc3 Chop Enable) Rev. 0 | Page 40 of 44 0 25 50 75 100 125 150 FREQUENCY (Hz) Figure 48. Sinc3 Filter Response (FS[9:0] = 96, Chop Enabled) 08771-058 FS[9:0] 96 80 –20 FILTER GAIN (dB) MODULATOR 08771-036 CHOP AD7195 The 50 Hz/60 Hz rejection can be improved by setting the REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and REJ60 set to 1, the filter response shown in Figure 49 is achieved. The output data rate is unchanged, but the 50 Hz/60 Hz ± 1 Hz rejection improves to 73 dB typically. 0 –10 –20 SUMMARY OF FILTER OPTIONS The AD7195 has several filter options. The filter that is chosen affects the output data rate, settling time, the rms noise, the stop band attenuation, and the 50 Hz/60 Hz rejection. Table 35 shows some sample configurations and the corresponding performance in terms of throughput, settling time and 50 Hz/60 Hz rejection. FILTER GAIN (dB) –30 –40 –50 –60 –70 –80 –90 –100 0 25 50 75 100 125 FREQUENCY (Hz) 150 08771-059 –110 –120 Figure 49. Sinc3 Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1) Table 35. Filter Summary 1 Filter Sinc4, Chop Disabled 3 Sinc4, Chop Disabled Sinc3, Chop Disabled Sinc4, Chop Disabled Sinc3, Chop Disabled Sinc4, Chop Disabled Sinc4, Chop Disabled Sinc3, Chop Disabled Sinc3, Chop Disabled Sinc4, Chop Disabled Sinc3, Chop Disabled Sinc4, Chop Disabled, Zero Latency Sinc4, Chop Disabled, Zero Latency Sinc4, Chop Disabled, Zero Latency Sinc4, Chop Enabled Sinc3, Chop Enabled FS[9:0] 1 5 5 480 480 96 96 96 96 80 80 96 Output Data Rate (Hz) 4800 960 960 10 10 50 50 50 50 60 60 12.5 Settling Time (ms) 0.83 4.17 3.125 400 300 80 80 60 60 66.67 50 80 Throughput 2 (Hz) 1200 240 320 2.5 3.33 12.5 12.5 16.7 16.7 15 20 12.5 REJ60 0 0 0 0 0 0 1 0 1 0 0 0 50 Hz Rejection (dB) No 50 Hz or 60 Hz rejection No 50 Hz or 60 Hz rejection No 50 Hz or 60 Hz rejection 120 dB ( 50 Hz and 60 Hz) 100 dB (50 Hz and 60 Hz) 120 dB (50 Hz only) 82 dB ( 50 Hz and 60 Hz) 95 dB (50 Hz only) 67 dB ( 50 Hz and 60 Hz) 120 dB (60 Hz only) 95 dB (60 Hz only) 120 dB (50 Hz only) 96 12.5 80 12.5 1 82 dB ( 50 Hz and 60 Hz) 80 15 66.67 15 0 120 dB (60 Hz only) 96 96 12.5 16.7 160 120 6.25 8.33 1 1 80 dB (50 Hz and 60 Hz) 67 dB (50 Hz and 60 Hz) 1 These calculations assume a 4.92 MHz stable master clock. Throughput is the rate at which conversions are available when several channels are enabled. In zero latency mode, the output data rate and throughput are equal. 3 For output dates rates greater than 1 kHz, the sinc4 filter is recommended. 2 Rev. 0 | Page 41 of 44 AD7195 GROUNDING AND LAYOUT Because the analog inputs and reference inputs are differential, most of the voltages in the analog modulator are commonmode voltages. The high common-mode rejection of the part removes common-mode noise on these inputs. The analog and digital supplies to the AD7195 are independent and separately pinned out to minimize coupling between the analog and digital sections of the device. The digital filter provides rejection of broadband noise on the power supplies, except at integer multiples of the modulator sampling frequency. Connect an R-C filter to each analog input pin to provide rejection at the modulator sampling frequency. The digital filter also removes noise from the analog and reference inputs provided these noise sources do not saturate the analog modulator. As a result, the AD7195 is more immune to noise interference than a conventional high resolution converter. However, because the resolution of the AD7195 is so high and the noise levels from the converter so low, care must be taken with regard to grounding and layout. The printed circuit board (PCB) that houses the ADC must be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes because it gives the best shielding. Although the AD7195 has separate pins for analog and digital ground, the AGND and DGND pins are tied together internally via the substrate. Therefore, the user must not tie these two pins to separate ground planes unless the ground planes are connected together near the AD7195. In systems where AGND and DGND are connected elsewhere in the system, they should not be connected again at the AD7195 because this would result in a ground loop. In these situations, it is recommended that the ground pins of the AD7195 be tied to the AGND plane. In any layout, the user must keep in mind the flow of currents in the system, ensuring that the paths for all currents are as close as possible to the paths the currents took to reach their destinations. Avoid forcing digital currents to flow through the AGND. Avoid running digital lines under the device because this couples noise onto the die and allow the analog ground plane to run under the AD7195 to prevent noise coupling. The power supply lines to the AD7195 must use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching signals like clocks with digital ground to prevent radiating noise to other sections of the board, and never run clock signals near the analog inputs. Avoid crossover of digital and analog signals. Run traces on opposite sides of the board at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, whereas signals are placed on the solder side. Good decoupling is important when using high resolution ADCs. Decouple all analog supplies with 10 μF tantalum in parallel with 0.1 μF capacitors to AGND. To achieve the best from these decoupling components, place them as close as possible to the device, ideally right up against the device. Decouple all logic chips with 0.1 μF ceramic capacitors to DGND. In systems in which a common supply voltage is used to drive both the AVDD and DVDD of the AD7195, it is recommended that the system AVDD supply be used. For this supply, place the recommended analog supply decoupling capacitors between the AVDD pin of the AD7195 and AGND and the recommended digital supply decoupling capacitor between the DVDD pin of the AD7195 and DGND. Rev. 0 | Page 42 of 44 AD7195 APPLICATIONS INFORMATION The AD7195 provides a low-cost, high resolution analog-todigital function. Because the analog-to-digital function is provided by a Σ-Δ architecture, the part is more immune to noisy environments, making it ideal for use in sensor measurement and industrial and process control applications. ACX2 and ACX2. In this phase, the excitation voltage to the bridge is reversed while the analog input signal and the reference voltage are also reversed. The AD7195 averages the conversions from the two phases so that any offsets and thermal affects are cancelled. WEIGH SCALES AC excitation is enabled by setting Bit ACX in the configuration register to 1. When the ACX bit is set to 0, the bridge is dc excited. When the AD7195 is in power-down mode, the bridge is disconnected from the excitation voltage, which minimizes power consumption of the system. Following a reset, the ac excitation pins are undefined for a few milliseconds. Thus, pullup/pull-down resistors should be used on the pins to prevent the excitation voltage being shorted to AGND. Figure 50 shows the AD7195 being used in a weigh scale application which uses ac excitation. The load cell is arranged in a bridge network and gives a differential output voltage between its OUT+ and OUT– terminals. Assuming a 5 V excitation voltage, the full -scale output range from the transducer is 10 mV when the sensitivity is 2 mV/V. The excitation voltage for the bridge can be used to directly provide the reference for the ADC because the reference input range includes the supply voltage. For simplicity, external filters are not included in Figure 50. However, an R-C antialias filter must be included on each analog input. This is required because the on-chip digital filter does not provide any rejection around the modulator sampling frequency or multiples of this frequency. With ac-excitation, the excitation voltage to the load cell is changed on each phase. In Phase 1, the T2 and T4 transistors are turned on using ACX1 and ACX1 while the T1 and T3 transistors are turned off. The bridge is forward biased. During Phase 2, Transistor T1 and Transistor T3 are turned on using +5V T1 T2 REFIN(+) AVDD AGND IN+ AIN1 AIN2 AIN3 AIN4 OUT+ OUT– REFERENCE DETECT AVDD AINCOM IN– DVDD DGND MUX Σ-Δ ADC PGA REFIN(–) SERIAL INTERFACE AND CONTROL LOGIC DOUT/RDY DIN SCLK CS SYNC AGND T4 TEMP SENSOR BPDSW AVDD AD7195 1MΩ ACX1 ACX1 AC EXCITATION CLOCK ACX2 CLOCK CIRCUITRY ACX2 MCLK1 MCLK2 08771-032 T3 1MΩ Figure 50. Typical Application (Weigh Scale) Rev. 0 | Page 43 of 44 AD7195 OUTLINE DIMENSIONS 0.30 0.25 0.18 32 25 0.50 BSC 0.80 0.75 0.70 0.50 0.40 0.30 8 16 9 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 3.65 3.50 SQ 3.45 EXPOSED PAD 17 TOP VIEW PIN 1 INDICATOR 1 24 0.25 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD. 112408-A PIN 1 INDICATOR 5.10 5.00 SQ 4.90 Figure 51. 32-Lead Lead Frame Chip Scale Package [LFCSP-WQ] 5 mm × 5 mm Body, Very Very Thin Quad (CP-32-11) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7195BCPZ AD7195BCPZ-RL AD7195BCPZ-RL7 1 Temperature Range –40°C to +105°C –40°C to +105°C –40°C to +105°C Package Description 32-Lead LFCSP_WQ 32-Lead LFCSP_WQ 32-Lead LFCSP_WQ Z = RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08771-0-1/10(0) Rev. 0 | Page 44 of 44 Package Option CP-32-11 CP-32-11 CP-32-11