AD ADA4857-2 Ultralow distortion, low power, low noise, high speed op amp Datasheet

Ultralow Distortion, Low Power,
Low Noise, High Speed Op Amp
ADA4857-1/ADA4857-2
Data Sheet
CONNECTION DIAGRAMS
High speed
850 MHz, −3 dB bandwidth (G = +1, RL = 1 kΩ, LFCSP)
750 MHz, −3 dB bandwidth (G = +1, RL = 1 kΩ, SOIC)
2800 V/μs slew rate
Low distortion: −88 dBc at 10 MHz (G = +1, RL = 1 kΩ)
Low power: 5 mA/amplifier at 10 V
Low noise: 4.4 nV/√Hz
Wide supply voltage range: 5 V to 10 V
Power-down feature
Available in 3 mm × 3 mm 8-lead LFCSP (single), 8-lead SOIC
(single), and 4 mm × 4 mm 16-lead LFCSP (dual)
ADA4857-1
TOP VIEW
(Not to Scale)
PD 1
8 +VS
FB 2
7 OUT
–IN 3
6 NC
+IN 4
5 –VS
NOTES
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
2. THE EXPOSED PAD MAY BE CONNECTED
TO GND OR VS.
07040-001
FEATURES
Figure 1. 8-Lead LFCSP (CP)
ADA4857-1
APPLICATIONS
FB 1
8
PD
–IN 2
7
+VS
+IN 3
6
OUT
–VS 4
5
NC
NC = NO CONNECT
07040-002
TOP VIEW
(Not to Scale)
Instrumentation
IF and baseband amplifiers
Active filters
ADC drivers
DAC buffers
Figure 2. 8-Lead SOIC (R)
ADA4857-2
13 OUT1
14 +VS1
16 FB1
15 PD1
TOP VIEW
(Not to Scale)
–IN1 1
12 –VS1
+IN1 2
11 NC
10 +IN2
NC 3
9
–IN2
NOTES
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
2. THE EXPOSED PAD MAY BE CONNECTED
TO GND OR VS.
07040-003
FB2 8
PD2 7
+VS2 6
OUT2 5
–VS2 4
Figure 3. 16-Lead LFCSP (CP)
GENERAL DESCRIPTION
The ADA4857 is a unity-gain stable, high speed, voltage feedback
amplifier with low distortion, low noise, and high slew rate. With a
spurious-free dynamic range (SFDR) of −88 dBc at 10 MHz, the
ADA4857 is an ideal solution for a variety of applications, including
ultrasounds, ATE, active filters, and ADC drivers. The Analog
Devices, Inc., proprietary next-generation XFCB process and
innovative architecture enables such high performance amplifiers.
The ADA4857 has 850 MHz bandwidth, 2800 V/μs slew rate, and
settles to 0.1% in 15 ns. With a wide supply voltage range (5 V to
Rev. D
10 V), the ADA4857 is an ideal candidate for systems that require
high dynamic range, precision, and speed.
The ADA4857-1 amplifier is available in a 3 mm × 3 mm, 8-lead
LFCSP and a standard 8-lead SOIC. The ADA4857-2 is available in
a 4 mm × 4 mm, 16-lead LFCSP. The LFCSP features an exposed
paddle that provides a low thermal resistance path to the printed
circuit board (PCB). This path enables more efficient heat transfer
and increases reliability. The ADA4857 works over the extended
industrial temperature range (−40°C to +125°C).
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ADA4857-1/ADA4857-2
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Test Circuits ..................................................................................... 16
Applications ....................................................................................... 1
Applications Information .............................................................. 17
Connection Diagrams ...................................................................... 1
Power-Down Operation ............................................................ 17
General Description ......................................................................... 1
Capacitive Load Considerations .............................................. 17
Revision History ............................................................................... 2
Recommended Values for Various Gains................................ 17
Specifications..................................................................................... 3
Active Low-Pass Filter (LPF) .................................................... 18
±5 V Supply ................................................................................... 3
Noise ............................................................................................ 19
+5 V Supply ................................................................................... 4
Circuit Considerations .............................................................. 19
Absolute Maximum Ratings............................................................ 6
PCB Layout ................................................................................. 19
Thermal Resistance ...................................................................... 6
Power Supply Bypassing ............................................................ 19
Maximum Power Dissipation ..................................................... 6
Grounding ................................................................................... 19
ESD Caution .................................................................................. 6
Outline Dimensions ....................................................................... 20
Pin Configurations and Function Descriptions ........................... 7
Ordering Guide .......................................................................... 21
Typical Performance Characteristics ............................................. 9
REVISION HISTORY
1/2017—Rev. C to Rev. D
Changes to Figure 1 .......................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Figure 5 .......................................................................... 7
Added Figure 40 and Figure 43; Renumbered Sequentially ..... 14
Added Figure 44, Figure 45, Figure 46, Figure 47,
and Figure 48 ................................................................................... 15
Changes to Power-Down Operation Section .............................. 17
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
9/2013—Rev. B to Rev. C
Changes to Figure 1 and Figure 3 ................................................... 1
Change to Figure 5 ........................................................................... 7
Change to Figure 7 ........................................................................... 8
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
11/2008—Rev. 0 to Rev. A
Changes to Table 5.............................................................................7
Changes to Table 7.............................................................................8
Changes to Figure 32...................................................................... 13
Added Figure 44; Renumbered Sequentially .............................. 15
Changes to Layout .......................................................................... 15
Changes to Table 8.......................................................................... 16
Added Active Low-Pass Filter (LFP) Section ............................. 17
Added Figure 48 and Figure 49; Renumbered Sequentially ..... 17
Changes to Grounding Section .................................................... 18
Exposed Paddle Notation Added to Outline Dimensions ........ 19
Changes to Ordering Guide .......................................................... 20
5/2008—Revision 0: Initial Version
8/2011—Rev. A to Rev. B
Changes to Table 1 Conditions ....................................................... 3
Changes to Table 2 Conditions ....................................................... 4
Changes to Typical Performance Characteristics Conditions .... 9
Changes to Figure 18 ...................................................................... 10
Changes to Figure 42 ...................................................................... 15
Changes to Table 9 .......................................................................... 16
Changes to Ordering Guide .......................................................... 20
Rev. D | Page 2 of 21
Data Sheet
ADA4857-1/ADA4857-2
SPECIFICATIONS
±5 V SUPPLY
TA = 25°C, G = 2, RG = RF = 499 Ω, RS = 100 Ω for G = 1 (SOIC), RL = 1 kΩ to ground, PD = no connect, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth (LFCSP/SOIC)
Full Power Bandwidth
Bandwidth for 0.1 dB Flatness
(LFCSP/SOIC)
Slew Rate (10% to 90%)
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Test Conditions/Comments
Min
Typ
Gain (G) = 1, VOUT = 0.2 V p-p
G = 1, VOUT = 2 V p-p
G = 2, VOUT = 0.2 V p-p
G = 1, VOUT = 2 V p-p, THD < −40 dBc
G = 2, VOUT = 2 V p-p, RL = 150 Ω
650
850/750
600/550
400/350
110
75/90
MHz
MHz
MHz
MHz
MHz
G = 1, VOUT = 4 V step
G = 2, VOUT = 2 V step
2800
15
V/μs
ns
f = 1 MHz, G = 1, VOUT = 2 V p-p (HD2)
f = 1 MHz, G = 1, VOUT = 2 V p-p (HD3)
f = 10 MHz, G = 1, VOUT = 2 V p-p (HD2)
f = 10 MHz, G = 1, VOUT = 2 V p-p (HD3)
f = 50 MHz, G = 1, VOUT = 2 V p-p (HD2)
f = 50 MHz, G = 1, VOUT = 2 V p-p (HD3)
f = 100 kHz
f = 100 kHz
−108
−108
−88
−93
−65
−62
4.4
1.5
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
±2
TMIN to TMAX
TMIN to TMAX
2.3
−2
TMIN to TMAX
Input Bias Offset Current
Open-Loop Gain
PD (POWER-DOWN) PIN
PD Input Voltage
Turn-Off Time
Turn-On Time
PD Pin Leakage Current
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage
Range
Common-Mode Rejection Ratio
50
57
VOUT = −2.5 V to +2.5 V
Chip powered down
Chip powered down, TMIN to TMAX
Chip enabled
Chip enabled, TMIN to TMAX
50% off PD to <10% of final VOUT, VIN = 1 V, G = 2
50% off PD to <10% of final VOUT, VIN = 1 V, G = 2
Chip enabled
Chip powered down
Rev. D | Page 3 of 21
±4.5
±7.2
22
−3.3
−3.8
800
≥ (+VS − 2)
mV
mV
μV/°C
μA
μA
nA
dB
55
33
58
80
8
4
2
±4
MΩ
MΩ
pF
V
−86
dB
dB
≤ (+VS − 4.2)
≤ (+VS – 5.3)
−78
−70
Unit
V
V
V
V
μs
ns
μA
μA
≥ (+VS − 1.7)
Common mode
Differential mode
Common mode
VCM = ±1 V
VCM = −3.6 V to +3.7 V, TMIN to TMAX
Max
ADA4857-1/ADA4857-2
Data Sheet
Parameter
Test Conditions/Comments
OUTPUT CHARACTERISTICS
Output Overdrive Recovery Time VIN = ±2.5 V, G = 2
Output Voltage Swing
High
RL = 1 kΩ
RL = 1 kΩ, TMIN to TMAX
RL = 100 Ω
RL = 100 Ω, TMIN to TMAX
Low
RL = 1 kΩ
RL = 1 kΩ, TMIN to TMAX
RL = 100 Ω
RL = 100 Ω, TMIN to TMAX
Output Current
Short-Circuit Current
Sinking and sourcing
Capacitive Load Drive
30% overshoot, G = 2
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current (Power Down) PD ≥ VCC − 2 V
Positive Power Supply Rejection +VS = 4.5 V to 5.5 V, −VS = −5 V
Negative Power Supply Rejection +VS = 5 V, −VS = −4.5 V to −5.5 V
Min
Typ
Max
10
ns
+VS − 1
V
V
V
V
V
V
V
V
mA
mA
pF
+VS − 1.3
+VS – 1.3
+VS − 2
−VS + 1
−VS + 1.3
−VS + 1.3
−VS + 3
50
125
10
4.5
−59
−65
Unit
5
350
−62
−68
10.5
5.5
450
V
mA
μA
dB
dB
+5 V SUPPLY
TA = 25°C, G = 2, RF = RG = 499 Ω, RS = 100 Ω for G = 1 (SOIC), RL = 1 kΩ to midsupply, PD = no connect, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
–3 dB Bandwidth (LFCSP/SOIC)
Full Power Bandwidth
Bandwidth for 0.1 dB Flatness
(LFCSP/SOIC)
Slew Rate (10% to 90%)
Settling Time to 0.1%
NOISE/HARMONIC PERFORMANCE
Harmonic Distortion
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Test Conditions/Comments
Min
Typ
G = 1, VOUT = 0.2 V p-p
G = 1, VOUT = 2 V p-p
G = 2, VOUT = 0.2 V p-p
G = 1, VOUT = 2 V p-p, THD < −40 dBc
G = 2, VOUT = 2 V p-p, RL = 150 Ω
595
800/750
500/400
360/300
95
50/40
MHz
MHz
MHz
MHz
MHz
G = 1, VOUT = 2 V step
G = 2, VOUT = 2 V step
1500
15
V/μs
ns
f = 1 MHz, G = 1, VOUT = 2 V p-p (HD2)
f = 1 MHz, G = 1, VOUT = 2 V p-p (HD3)
f = 10 MHz, G = 1, VOUT = 2 V p-p (HD2)
f = 10 MHz, G = 1, VOUT = 2 V p-p (HD3)
f = 50 MHz, G = 1, VOUT = 2 V p-p (HD2)
f = 50 MHz, G = 1, VOUT = 2 V p-p (HD3)
f = 100 kHz
f = 100 kHz
−92
−90
−81
−71
−69
−55
4.4
1.5
dBc
dBc
dBc
dBc
dBc
dBc
nV/√Hz
pA/√Hz
±1
TMIN to TMAX
TMIN to TMAX
4.6
−1.7
TMIN to TMAX
Input Bias Offset Current
Open-Loop Gain
VOUT = 1.25 V to 3.75 V
Rev. D | Page 4 of 21
50
57
Max
±4.2
±6.4
23
−3.3
−4.1
800
Unit
mV
mV
μV/°C
μA
μA
nA
dB
Data Sheet
Parameter
PD (POWER-DOWN) PIN
PD Input Voltage
Turn-Off Time
Turn-On Time
PD Pin Leakage Current
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Overdrive Recovery Time
Output Voltage Swing
High
Low
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current (Power Down)
Positive Power Supply Rejection
Negative Power Supply Rejection
ADA4857-1/ADA4857-2
Test Conditions/Comments
Chip powered down
Chip powered down, TMIN to TMAX
Chip enabled
Chip enabled, TMIN to TMAX
50% off PD to <10% of final VOUT, VIN =
1 V, G = 2
50% off PD to <10% of final VOUT, VIN =
1 V, G = 2
Chip enable
Chip powered down
Min
≥ (+VS − 2)
38
V
V
V
≤ (+VS − 4.8) V
µs
30
ns
8
30
µA
µA
8
4
2
1 to 4
−84
MΩ
MΩ
pF
V
dB
dB
15
ns
+VS − 1
V
V
V
V
V
V
V
V
mA
mA
pF
≤ (+VS − 4.2)
−76
−70
G=2
RL = 1 kΩ
RL = 1 kΩ, TMIN to TMAX
RL = 100 Ω
RL = 100 Ω, TMIN to TMAX
RL = 1 kΩ
RL = 1 kΩ, TMIN to TMAX
RL = 100 Ω
RL = 100 Ω, TMIN to TMAX
Max
≥ (+VS − 1.4)
Common mode
Differential mode
Common mode
VCM = 2 V to 3 V
VCM = 1.3 V to 3.7 V, TMIN to TMAX
Typ
+VS − 1.3
+VS – 1.1
+VS – 1.7
−VS + 1
−VS + 1.3
−VS + 1.1
−VS + 1.6
50
75
10
Sinking and sourcing
30% overshoot, G = 2
4.5
PD ≥ VCC − 2 V
+VS = 4.5 V to 5.5 V, −VS = 0 V
+VS = 5 V, −VS = −0.5 V to +0.5 V
Rev. D | Page 5 of 21
−58
−65
4.5
250
−62
−68
10.5
5
350
Unit
V
mA
µA
dB
dB
ADA4857-1/ADA4857-2
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Rating
11 V
See Figure 4
−VS + 0.7 V to +VS − 0.7 V
±VS
−VS
−65°C to +125°C
−40°C to +125°C
300°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is specified
for device soldered in circuit board for surface-mount packages.
Table 4.
θJA
115
94.5
68.2
θJC
15
34.8
19
V V
PD = (VS × I S ) +  S × OUT
RL
 2
 VOUT 2
–

RL

RMS output voltages must be considered. If RL is referenced
to −VS, as in single-supply operation, the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
PD = (VS × I S ) +
(VS /4 )2
RL
In single-supply operation with RL referenced to −VS, the worst
case is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA.
In addition, more metal directly in contact with the package
leads and exposed paddle from metal traces, through holes,
ground, and power planes reduces θJA.
Figure 4 shows the maximum power dissipation in the package
vs. the ambient temperature for the SOIC and LFCSP packages
on a JEDEC standard 4-layer board. θJA values are approximations.
Unit
°C/W
°C/W
°C/W
3.0
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4857 is
limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the properties of the plastic change. Even temporarily
exceeding this temperature limit may change the stresses that
the package exerts on the die, permanently shifting the parametric
performance of the ADA4857. Exceeding a junction temperature of
175°C for an extended period can result in changes in silicon
devices, potentially causing degradation or loss of functionality.
2.5
2.0
ADA4857-2 (LFCSP)
1.5
1.0
ADA4857-1 (LFCSP)
0.5
ADA4857-1 (SOIC)
0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 100 110 120
AMBIENT TEMPERATURE (°C)
07040-004
Package Type
8-Lead SOIC
8-Lead LFCSP
16-Lead LFCSP
PD = Quiescent Power + (Total Drive Power − Load Power)
MAXIMUM POWER DISSIPATION (W)
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Exposed Paddle Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
die due to the ADA4857 drive at the output. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS).
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
Rev. D | Page 6 of 21
Data Sheet
ADA4857-1/ADA4857-2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
8 +VS
FB 1
FB 2
ADA4857-1
7 OUT
–IN 2
–IN 3
TOP VIEW
(Not to Scale)
6 NC
+IN 4
8
ADA4857-1
+VS
TOP VIEW
+IN 3 (Not to Scale) 6 OUT
–VS 4
5 NC
5 –VS
07040-005
NC = NO CONNECT
NOTES
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
2. THE EXPOSED PAD MAY BE CONNECTED
TO GND OR VS.
PD
7
07040-006
PD 1
Figure 5. 8-Lead LFCSP Pin Configuration
Figure 6. 8-Lead SOIC Pin Configuration
Table 5. 8-Lead LFCSP Pin Function Descriptions
Table 6. 8-Lead SOIC Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
EP
Pin No.
1
2
3
4
5
6
7
8
Mnemonic
PD
FB
−IN
+IN
−VS
NC
OUT
+VS
GND or VS
Description
Power Down.
Feedback.
Inverting Input.
Noninverting Input.
Negative Supply.
No Connect.
Output.
Positive Supply.
Exposed Pad. The exposed pad
may be connected to GND or VS.
Rev. D | Page 7 of 21
Mnemonic
FB
−IN
+IN
−VS
NC
OUT
+VS
PD
Description
Feedback.
Inverting Input.
Noninverting Input.
Negative Supply.
No Connect.
Output.
Positive Supply.
Power Down.
13 OUT1
–IN1 1
+IN1 2
NC 3
ADA4857-2
TOP VIEW
(Not to Scale)
12 –VS1
11 NC
10 +IN2
9
–IN2
FB2 8
PD2 7
+VS2 6
OUT2 5
–VS2 4
NOTES
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
2. THE EXPOSED PAD MAY BE CONNECTED
TO GND OR VS.
07040-007
14 +VS1
16 FB1
Data Sheet
15 PD1
ADA4857-1/ADA4857-2
Figure 7. 16-Lead LFCSP Pin Configuration
Table 7. 16-Lead LFCSP Pin Function Descriptions
Pin No.
1
2
3, 11
4
5
6
7
8
9
10
12
13
14
15
16
EP
Mnemonic
−IN1
+IN1
NC
−VS2
OUT2
+VS2
PD2
FB2
−IN2
+IN2
−VS1
OUT1
+VS1
PD1
FB1
GND or VS
Description
Inverting Input 1.
Noninverting Input 1.
No Connect.
Negative Supply 2.
Output 2.
Positive Supply 2.
Power Down 2.
Feedback 2.
Inverting Input 2.
Noninverting Input 2.
Negative Supply 1.
Output 1.
Positive Supply 1.
Power Down 1.
Feedback 1.
Exposed Pad. The exposed pad may be connected to GND or VS.
Rev. D | Page 8 of 21
Data Sheet
ADA4857-1/ADA4857-2
TYPICAL PERFORMANCE CHARACTERISTICS
3
2
2
G = +2
–2
–3
–4
G = +10
–5
–6
G = +5
–7
–8
VS = ±5V
RL = 1kΩ
VOUT = 0.2V p-p
–9
–10
1
10
100
1000
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
0
–1
±5V
–4
–5
–6
+5V
G = +1
RL = 1kΩ
VOUT = 0.2V p-p
–9
–10
1
10
100
1000
FREQUENCY (MHz)
07040-009
CLOSED-LOOP GAIN (dB)
1
–8
–4
–7
–8
9
8
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
2
1
1
0
0
CLOSED-LOOP GAIN (dB)
–40°C
–2
–3
–4
–5
+25°C
+125°C
FREQUENCY (MHz)
1000
100
1000
5pF
NO CAP LOAD
G = +2
VS = ±5V
RL = 1kΩ
VOUT = 0.2V p-p
1
10
100
1000
1V p-p
–1
–2
–3
4V p-p
–4
–5
–6
–7
G = +1
VS = ±5V
RL = 100Ω
–9
100
10
10pF
–8
–10
07040-010
–8 G = +1
VS = ±5V
–9 RL = 1kΩ
VOUT = 0.2V p-p
–10
1
10
1
Figure 12. Small Signal Frequency Response for Various Capacitive Loads (LFCSP)
3
–7
VS = ±5V
RL = 1kΩ
VOUT = 2V p-p
–9
2
–6
G = +5
–6
3
–1
G = +10
–5
FREQUENCY (MHz)
Figure 9. Small Signal Frequency Response for Various Supply Voltages (LFCSP)
CLOSED-LOOP GAIN (dB)
–3
Figure 11. Large Signal Frequency Responses for Various Gains (LFCSP)
2
–7
G = +2
–2
FREQUENCY (MHz)
3
–3
–1
–10
Figure 8. Small Signal Frequency Responses for Various Gains (LFCSP)
–2
G = +1
0
07040-012
–1
1
07040-011
G = +1
0
1
10
100
1000
FREQUENCY (MHz)
Figure 10. Small Signal Frequency Response for Various Temperatures (LFCSP)
Rev. D | Page 9 of 21
Figure 13. Large Signal Frequency Response vs. VOUT (LFCSP)
07040-013
1
NORMALIZED CLOSED-LOOP GAIN (dB)
3
07040-008
NORMALIZED CLOSED-LOOP GAIN (dB)
T = 25°C, G = +1, RF = 0 Ω, and, RG open, RS = 100 Ω for SOIC, (for G = +2, RF = RG = 499 Ω), unless otherwise noted.
3
2
RL = 1kΩ
1
RL = 100Ω
10
100
1000
Figure 14. Small Signal Frequency Response for Various Resistive Loads (LFCSP)
RL = 100Ω
–4
–5
–6
–7
G = +1
VS = ±5V
VOUT = 2V p-p
1
10
100
1000
FREQUENCY (MHz)
Figure 17. Large Signal Frequency Response for Various Resistive Loads (LFCSP)
3
G = +1
0
–1
G = +2
–2
–3
–4
G = +10
–5
–6
G = +5
–7
VS = 5V
RL = 1kΩ
VOUT = 0.2V p-p
–9
1
10
100
1000
FREQUENCY (MHz)
Figure 15. Small Signal Frequency Response for Various Gains (LFCSP)
–40
–50
G = +2
–2
–3
+VS
G = +1
–4
–5
–6
VOUT
RS
VIN
RT
RL
100Ω
–VS
–7
–8
VS = ±5V
RL = 1kΩ
VOUT = 0.2V p-p
–9
1
10
–50
G = +1
VS = ±5V
VOUT = 2V p-p
–60
DISTORTION (dBc)
–80
G = +2, HD2
G = +1, HD3
–90
1000
Figure 18. Small Signal Frequency Response for Various Gains (SOIC),
RS = 100 Ω for G = +1
–40
–70
100
FREQUENCY (MHz)
–60
–100
RL = 100Ω, HD3
–70
–80
RL = 100Ω, HD2
–90
RL = 1kΩ, HD2
–100
–110
–110
G = +2, HD3
1
10
100
FREQUENCY (MHz)
07040-016
–120
0.2
0
–1
–10
VS = ±5V
VOUT = 2V p-p
RL= 1kΩ
G = +1, HD2
G = +1
G = +5
G = +10
1
Figure 16. Harmonic Distortion vs. Frequency and Gain (LFCSP)
–120
0.2
RL = 1kΩ, HD3
1
10
100
FREQUENCY (MHz)
Figure 19. Harmonic Distortion vs. Frequency and Load (LFCSP)
Rev. D | Page 10 of 21
07040-019
–8
2
07040-018
1
NORMALIZED CLOSED-LOOP GAIN (dB)
2
07040-015
NORMALIZED CLOSED-LOOP GAIN (dB)
–3
–10
3
DISTORTION (dBc)
–2
–9
FREQUENCY (MHz)
–10
RL = 1kΩ
–8
G = +2
VS = ±5V
VOUT = 0.2V p-p
1
0
–1
07040-017
CLOSED-LOOP GAIN (dB)
9
8
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–6
–7
Data Sheet
07040-014
CLOSED-LOOP GAIN (dB)
ADA4857-1/ADA4857-2
Data Sheet
–40
ADA4857-1/ADA4857-2
0.5
G = +2
VS = ±5V
RL= 1kΩ
–50
HD3, f = 10MHz
0.3
–60
SETTLING TIME (%)
HD2, f = 10MHz
–70
–80
–90
–100
HD3, f = 1MHz
HD2, f = 1MHz
0.2
0.1
OUTPUT
0
–0.1
–0.2
–0.3
–110
INPUT
2
3
4
5
6
7
OUTPUT VOLTAGE (V p-p)
8
–0.5
TIME (5ns/DIV)
Figure 20. Harmonic Distortion vs. Output Voltage
6.3
6.3
VS = ±5V
G = +2
RL= 150Ω
6.1
VOUT = 2V p-p
6.0
5.9
VOUT = 0.2V p-p
1
10
100
FREQUENCY (MHz)
Figure 21. 0.1 dB Flatness vs. Frequency for Various Output Voltages (SOIC)
2.0
OUTPUT VOLTAGE (V)
1.5
1.0
4V p-p
VOUT = 2V p-p
5.9
VOUT = 0.2V p-p
2.0
1.5
2V p-p
–0.5
–1.0
10
100
Figure 24. 0.1 dB Flatness vs. Frequency for Various Output Voltages (LFCSP)
2.5
0
1
FREQUENCY (MHz)
VS = ±5V
RL = 1kΩ
G = +2
0.5
–1.5
1.0
4V p-p
VS = ±5V
RL = 1kΩ
G = +1
2V p-p
0.5
0
–0.5
–1.0
–1.5
07040-022
–2.0
–2.5
6.0
5.7
OUTPUT VOLTAGE (V)
2.5
6.1
5.8
07040-021
5.8
5.7
VS = ±5V
G = +2
RL= 150Ω
6.2
CLOSED-LOOP GAIN (dB)
6.2
CLOSED-LOOP GAIN (dB)
Figure 23. Short-Term Settling Time (LFCSP)
07040-024
1
07040-020
–120
07040-023
–0.4
–2.0
–2.5
TIME (10ns/DIV)
Figure 22. Large Signal Transient Response for Various Output Voltages (SOIC)
07040-025
DISTORTION (dBc)
VOUT = 2V p-p
G = +2
VS = ±5
0.4
TIME (10ns/DIV)
Figure 25. Large Signal Transient Response for Various Output Voltages (LFCSP)
Rev. D | Page 11 of 21
ADA4857-1/ADA4857-2
Data Sheet
0.25
2.0
VS = ±5V
RL = 1kΩ
G = +1
0.20
1.2
–0.05
–0.10
–0.15
CL = 10pF
–0.20
–0.25
–0.4
–0.8
RL = 100Ω
–1.6
–2.0
TIME (10ns/DIV)
TIME (10ns/DIV)
Figure 29. Large Signal Transient Response for Various Load Resistances (SOIC)
2.0
0.25
RL = 1kΩ
G = +1
0.20
0.15
1.6
1.2
OUTPUT VOLTAGE (V)
VS = ±5V
0.10
0.05
VS = ±2.5V
0
–0.05
–0.10
0
–0.4
–0.8
–1.2
–1.6
TIME (10ns/DIV)
Figure 30. Large Signal Transient Response for Various Load Resistances (LFCSP)
100
CLOSED-LOOP INPUT IMPEDANCE (kΩ)
VS = ±5V
100
10
G = +5
1
G = +2
10
100
FREQUENCY (MHz)
1000
07040-028
1
0.1
0.1
RL = 100Ω
–2.0
TIME (10ns/DIV)
Figure 27. Small Signal Transient Response for Various Supply Voltages (LFCSP)
RL = 1kΩ
0.4
–0.20
–0.25
VS = ±5V
G = +1
0.8
–0.15
07040-027
OUTPUT VOLTAGE (V)
0
–1.2
Figure 26. Small Signal Transient Response for Various Capacitive Loads (LFCSP)
CLOSED-LOOP OUTPUT IMPEDANCE (Ω)
RL = 1kΩ
07040-030
0
0.8
0.4
Figure 28. Closed-Loop Output Impedance vs. Frequency for Various Gains
Rev. D | Page 12 of 21
VS = ±5V
G = +2
10
1
0.1
0.01
1
10
100
FREQUENCY (MHz)
Figure 31. Closed-Loop Input Impedance vs. Frequency
1000
07040-031
CL = 1.5pF
0.05
07040-029
OUTPUT VOLTAGE (V)
0.10
07040-026
OUTPUT VOLTAGE (V)
0.15
1000
VS = ±5V
G = +2
1.6
Data Sheet
ADA4857-1/ADA4857-2
–60
40
–80
30
–100
20
–120
10
–140
0
–160
10
–30
–40
–50
LFCSP
–60
–70
–80
–90
–180
1000
100
FREQUENCY (MHz)
–100
0.1
1
OUTPUT VOLTAGE (V)
4
2
0
OUTPUT
RL = 100Ω
–4
OUTPUT
RL = 1kΩ
INPUT
–8
0
–4
–30
OUTPUT
RL = 1kΩ
2 × INPUT
OUTPUT
RL = 100Ω
TIME (200ns/DIV)
VS = ±5V
RL= 1kΩ
–40
–10
–50
CMRR (dB)
–20
–30
–40
–60
–70
+PSRR
–60
–80
–70
–PSRR
1
10
100
1000
FREQUENCY (MHz)
07040-034
PSRR (dB)
–2
Figure 36. Output Overdrive Recovery for Various Resistive Loads
VS = ±5V
RL= 1kΩ
–80
0.1
0
–8
TIME (40ns/DIV)
–50
2
–6
Figure 33. Input Overdrive Recovery for Various Resistive Loads
10
4
Figure 34. Power Supply Rejection Ratio (PSRR) vs. Frequency
–90
0.1
1
10
100
1000
FREQUENCY (MHz)
Figure 37. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Rev. D | Page 13 of 21
07040-037
–6
1000
VS = ±5V
G = +2
6
07040-033
OUTPUT VOLTAGE (V)
8
–2
100
Figure 35. PD Isolation vs. Frequency
VS = ±5V
G = +1
6
10
FREQUENCY (MHz)
Figure 32. Open-Loop Gain and Phase vs. Frequency
8
SOIC
07040-036
1
–20
G = +2
VS = ±5V
RL = 1kΩ
PD = 3V
07040-035
50
–10
0.1
–10
–20
–40
GAIN
0
07040-032
60
0
PD ISOLATION (dB)
PHASE
70
OPEN-LOOP GAIN (dB)
VS = ±5V
RL = 1kΩ
OPEN-LOOP PHASE (Degrees)
80
ADA4857-1/ADA4857-2
1000
10
1
10
1k
100
1M
100k
10k
FREQUENCY (Hz)
VS = ±5V
100
10
1
1
1k
100
10k
1M
100k
FREQUENCY (Hz)
Figure 41. Input Voltage Noise vs. Frequency
Figure 38. Input Current Noise vs. Frequency
3.5
50 N = 238
MEAN: 5.00
SD: 0.02
3.0
40
PD INPUT
2.5
VOLTAGE (V)
30
20
2.0
1.5
1.0
OUTPUT
0.5
10
4.90
4.95
5.05
5.00
5.10
5.15
SUPPLY CURRENT (mA)
–0.5
07040-042
0
4.85
Figure 39. Supply Current
TIME (20µs/DIV)
Figure 42. Disable/Enable Switching Speed
40
40
VS = ±5V
35
35
NUMBER OF AMPLIFIERS
30
25
20
15
10
5
VS = 5V
30
25
20
15
10
5
0
–5
–4
–3
–2
–1
0
1
2
3
4
INPUT OFFSET VOLTAGE (mV)
5
0
–5
07040-240
NUMBER OF AMPLIFIERS
07040-043
0
–4
–3
–2
–1
0
1
2
3
4
INPUT OFFSET VOLTAGE (mV)
Figure 43. Input Offset Voltage Distribution, VS = 5 V
Figure 40. Input Offset Voltage Distribution, VS = ±5 V
Rev. D | Page 14 of 21
5
07040-243
COUNT
10
07040-041
VOLTAGE NOISE (nV/√Hz)
VS = ±5V
07040-050
CURRENT NOISE (pA/√Hz)
100
Data Sheet
Data Sheet
ADA4857-1/ADA4857-2
60
70
VS = ±5V
–40°C
+125C
40
30
20
10
50
40
30
20
–5
–4
5
4
0
1
2
3
–3 –2 –1
INPUT OFFSET VOLTAGE (mV)
7
6
0
–7
07040-244
–6
Figure 44. Input Offset Voltage Distribution over Temperature, VS = ±5 V
–5
–4
0
1
2
3
4
–3 –2 –1
INPUT OFFSET VOLTAGE (mV)
5
6
7
Figure 47. Input Offset Voltage Distribution over Temperature, VS = 5 V
30
25
VS = ±5V
VS = 5V
25
20
NUMBER OF AMPLIFIERS
20
15
10
15
10
5
0
–15
–10
–5
0
5
10
15
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
07040-245
5
Figure 45. Input Offset Voltage Drift Distribution, VS = ±5 V
400
300
200
100
0
–100
–200
–300
–3
–2
–1
0
1
2
COMMON-MODE VOLTAGE (V)
3
4
07040-246
–400
–4
–10
–5
0
5
10
INPUT OFFSET VOLTAGE DRIFT (µV/°C)
Figure 48. Input Offset Voltage Drift Distribution, VS = 5 V
500
–500
0
–15
Figure 46. Common-Mode Rejection vs. Common-Mode Voltage
Rev. D | Page 15 of 21
15
07040-248
NUMBER OF AMPLIFIERS
–6
07040-247
10
0
–7
COMMON-MODE REJECTION (µV/V)
VS = 5V
–40°C
+125C
60
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
50
ADA4857-1/ADA4857-2
Data Sheet
TEST CIRCUITS
+
1kΩ
0.1µF
0.1µF
VIN
RL
49.9Ω
0.1µF
1kΩ
VOUT
RS
0.1µF
VOUT
1kΩ
53.6Ω
RL
1kΩ
+
+
10µF
10µF
–VS
–VS
Figure 49. Noninverting Load Configuration
Figure 52. Common-Mode Rejection
+VS
AC
0.1µF
07040-047
0.1µF
07040-046
VIN
+VS
+
10µF
10µF
+VS
+VS
10µF
+
49.9Ω
0.1µF
VOUT
VOUT
RL
49.9Ω
AC
07040-045
+
0.1µF
–VS
–VS
Figure 50. Positive Power Supply Rejection
10µF
07040-048
10µF
RL
Figure 53. Negative Power Supply Rejection
+VS
10µF
+VS
+
+
RF
VIN
CL
49.9Ω
RG
0.1µF
RF
0.1µF
VOUT
RL
RSNUB
VIN
49.9Ω
0.1µF
–VS
VOUT
CL
RL
10µF
+
+
10µF
0.1µF
40Ω
0.1µF
–VS
Figure 51. Typical Capacitive Load Configuration (LFCSP)
Figure 54. Typical Capacitive Load Configuration (SOIC)
Rev. D | Page 16 of 21
07040-049
0.1µF
07040-051
RG
Data Sheet
ADA4857-1/ADA4857-2
APPLICATIONS INFORMATION
POWER-DOWN OPERATION
CAPACITIVE LOAD CONSIDERATIONS
The PD pin powers down the chip, reducing the quiescent
current and the overall power consumption. To enable the
device, pull the PD pin low. Table 8 provides the PD pin voltages
that enable the correct operation at different supplies. These
voltages are applicable for ambient temperature only. Consult
Table 1 and Table 2 when designing for use at the full operating
temperature range.
When driving a capacitive load using the SOIC package, RSNUB
reduces the peaking (see Figure 54). An optimum resistor value of
40 Ω is found to maintain the peaking within 1 dB for any
capacitive load up to 40 pF.
Note that PD does not put the output in a high-Z state, which
means that the ADA4857 must not be used as a multiplexer.
RECOMMENDED VALUES FOR VARIOUS GAINS
Table 9 provides a useful reference for determining various gains
and associated performance. RF and RG are kept low to minimize
their contribution to the overall noise performance of the amplifier.
Table 8. PD Operation Table Guide
Condition
Enabled
Powered down
±5 V
≤+0.8 V
≥+3 V
Supply Voltage
±2.5 V
+5 V
≤−1.7 V
≤+0.8 V
≥+0.5 V
≥+3 V
Table 9. Various Gain and Recommended Resistor Values Associated with Conditions; VS = ±5 V, TA = 25°C, RL = 1 kΩ, RT = 49.9 Ω
Gain
+1
+2
+5
+10
RS (Ω) (CSP/SOIC)
0/100
0/0
0/0
0/0
RF (Ω)
0
499
499
499
RG (Ω)
N/A
499
124
56.2
−3 dB SS BW (MHz)
(CSP/SOIC)
850/750
360/320
90/89
43/40
Slew Rate (V/µs),
VOUT = 2 V Step
2350
1680
516
213
Rev. D | Page 17 of 21
ADA4857 Voltage
Noise (nV/√Hz), RTO
4.4
8.8
22.11
43.47
Total System
Noise (nV/√Hz), RTO
4.49
9.89
23.49
45.31
ADA4857-1/ADA4857-2
Data Sheet
Figure 55 shows the output of each stage is of the filter and the
two different filters corresponding to R = 182 Ω and R = 365 Ω.
Resistor values are kept low for minimal noise contribution,
offset voltage, and optimal frequency response. Due to the low
capacitance values used in the filter circuit, the PCB layout and
minimization of parasitics is critical. A few picofarads can detune
the corner frequency, fc of the filter. The capacitor values shown
in Figure 56 actually incorporate some stray PCB capacitance.
ACTIVE LOW-PASS FILTER (LPF)
Active filters are used in many applications such as antialiasing
filters and high frequency communication IF strips. With a
410 MHz gain bandwidth product and high slew rate, the
ADA4857-2 is an ideal candidate for active filters. Figure 55
shows the frequency response of 90 MHz and 45 MHz LPFs.
In addition to the bandwidth requirements, the slew rate must
be capable of supporting the full power bandwidth of the filter.
In this case, a 90 MHz bandwidth with a 2 V p-p output swing
requires at least 2800 V/μs.
Capacitor selection is critical for optimal filter performance.
Capacitors with low temperature coefficients, such as NPO
ceramic capacitors and silver mica, are good choices for filter
elements.
Setting the resistors equal to each other greatly simplifies the design
equations for the Sallen-Key filter. To achieve 90 MHz, the value
of R must be set to 182 Ω. However, if the value of R is doubled,
the corner frequency is cut in half to 45 MHz. This would be an
easy way to tune the filter by simply multiplying the value of R
(182 Ω) by the ratio of 90 MHz and the new corner frequency
in megahertz.
15
12
9
6
3
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36 R = 100Ω
L
–39 VS = ±5V
–42
0.1
OUT1, f = 90MHz
OUT1, f = 45MHz
OUT2, f = 90MHz
OUT2, f = 45MHz
1
10
100
FREQUENCY (MHz)
Figure 55. Low-Pass Filter Response
C1
3.9pF
+5V
C3
3.9pF
10µF
+5V
RT
49.9Ω
R
U1
R
0.1µF
R
C2
5.6pF
10µF
OUT1
U2
R
C4
5.6pF
0.1µF
RT
49.9Ω
10µF
OUT2
0.1µF
0.1µF
–5V
R2
348Ω
–5V
R1
348Ω
R4
348Ω
R3
348Ω
Figure 56. 4-Pole, Sallen-Key Low-Pass Filter (ADA4857-2)
Rev. D | Page 18 of 21
07040-075
+IN1
10µF
500
07040-074
MAGNITUDE (dB)
The circuit shown in Figure 56 is a 4-pole, Sallen-Key LPF. The
filter comprises two identical cascaded Sallen-Key LPF sections,
each with a fixed gain of G = 2. The net gain of the filter is equal
to G = 4 or 12 dB. The actual gain shown in Figure 55 is 12 dB.
This does not take into account the output voltage being divided in
half by the series matching termination resistor, RT, and the
load resistor.
Data Sheet
ADA4857-1/ADA4857-2
NOISE
CIRCUIT CONSIDERATIONS
To analyze the noise performance of an amplifier circuit, identify
the noise sources and determine if the source has a significant
contribution to the overall noise performance of the amplifier.
To simplify the noise calculations, noise spectral densities were
used rather than actual voltages to leave bandwidth out of the
expressions (noise spectral density, which is generally expressed
in nV/Hz, is equivalent to the noise in a 1 Hz bandwidth).
Careful and deliberate attention to detail when laying out the
ADA4857 board yields optimal performance. Power supply
bypassing, parasitic capacitance, and component selection all
contribute to the overall performance of the amplifier.
The noise model shown in Figure 57 has six individual noise
sources: the Johnson noise of the three resistors, the operational
amplifier voltage noise, and the current noise in each input of the
amplifier. Each noise source has its own contribution to the noise
at the output. Noise is generally referred to input (RTI), but it is
often easier to calculate the noise referred to the output (RTO)
and then divide by the noise gain to obtain the RTI noise.
VN, R2
R2
GAIN FROM
=
A TO OUTPUT
4kTR2
A
VN, R1
4kTR1
VN, R3
R1
NOISE GAIN =
R2
NG = 1 +
R1
IN–
VN
VOUT
R3
IN+
4kTR3
VN2 + 4kTR3 + 4kTR1
RTI NOISE =
R2
R1 + R2
+ IN+2R32 + IN–2 R1 × R2
R1 + R2
2
2
+ 4kTR2
R1
R1 + R2
RTO NOISE = NG × RTI NOISE
Because the ADA4857 can operate up to 850 MHz, it is essential
that RF board layout techniques be employed. All ground and
power planes under the pins of the ADA4857 must be cleared of
copper to prevent the formation of parasitic capacitance between
the input pins to ground and the output pins to ground. A single
mounting pad on the SOIC footprint can add as much as 0.2 pF
of capacitance to ground if the ground plane is not cleared from
under the mounting pads. The low distortion pinout of the
ADA4857 increases the separation distance between the inputs
and the supply pins, which improves the second harmonics. In
addition, the feedback pin reduces the distance between the output
and the inverting input of the amplifier, which helps minimize
the parasitic inductance and capacitance of the feedback path,
reducing ringing and peaking.
POWER SUPPLY BYPASSING
GAIN FROM
= – R2
B TO OUTPUT
R1
2
07040-073
B
PCB LAYOUT
Figure 57. Operational Amplifier Noise Analysis Model
All resistors have Johnson noise that is calculated by
(4kBTR)
Power supply bypassing for the ADA4857 was optimized for
frequency response and distortion performance. Figure 49 shows
the recommended values and location of the bypass capacitors. The
0.1 μF bypassing capacitors must be placed as close as possible to
the supply pins. Power supply bypassing is critical for stability,
frequency response, distortion, and PSR performance. The
capacitor between the two supplies helps improve PSR and
distortion performance. The 10 μF electrolytic capacitors must be
close to the 0.1 μF capacitors; however, it is not as critical. In some
cases, additional paralleled capacitors can help improve frequency
and transient response.
GROUNDING
where:
k is Boltzmann’s Constant (1.38 × 10–23 J/K).
B is the bandwidth in Hertz.
T is the absolute temperature in Kelvin.
R is the resistance in ohms.
A simple relationship that is easy to remember is that a 50 Ω
resistor generates a Johnson noise of 1 nV/Hz at 25°C.
In applications where noise sensitivity is critical, care must
be taken not to introduce other significant noise sources to
the amplifier. Each resistor is a noise source. Attention to the
following areas is critical to maintain low noise performance:
design, layout, and component selection. A summary of noise
performance for the amplifier and associated resistors can be
seen in Table 9.
Ground and power planes must be used where possible. Ground
and power planes reduce the resistance and inductance of the
power planes and ground returns. The returns for the input, output
terminations, bypass capacitors, and RG must all be kept as close to
the ADA4857 as possible. The output load ground and the bypass
capacitor grounds must be returned to the same point on the
ground plane to minimize parasitic trace inductance, ringing, and
overshoot and to improve distortion performance. The ADA4857
LFSCP packages feature an exposed paddle. For optimum electrical
and thermal performance, solder this paddle to the ground plane
or the power plane. For more information on high speed circuit
design, see A Practical Guide to High-Speed Printed-CircuitBoard Layout at www.analog.com.
Rev. D | Page 19 of 21
ADA4857-1/ADA4857-2
Data Sheet
OUTLINE DIMENSIONS
1.84
1.74
1.64
3.10
3.00 SQ
2.90
0.50 BSC
8
5
PIN 1 INDEX
AREA
0.50
0.40
0.30
1
4
BOTTOM VIEW
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.30
0.25
0.20
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
12-07-2010-A
TOP VIEW
SEATING
PLANE
1.55
1.45
1.35
EXPOSED
PAD
COMPLIANT TO JEDEC STANDARDS MO-229-WEED
Figure 58. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-13)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
6.20 (0.2441)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 59. 8-Lead Standard Small Outline Package [SOIC_N]
(R-8)
Dimensions shown in millimeters and (inches)
Rev. D | Page 20 of 21
012407-A
4.00 (0.1574)
3.80 (0.1497)
Data Sheet
ADA4857-1/ADA4857-2
0.35
0.30
0.25
0.65
BSC
PIN 1
INDICATOR
16
13
1
12
EXPOSED
PAD
2.25
2.10 SQ
1.95
9
TOP VIEW
0.80
0.75
0.70
0.70
0.60
0.50
4
8
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
5
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
111908-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 60. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-23)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADA4857-1YCPZ-R2
ADA4857-1YCPZ-RL
ADA4857-1YCPZ-R7
ADA4857-1YRZ
ADA4857-1YRZ-R7
ADA4857-2YCPZ-R2
ADA4857-2YCPZ-RL
ADA4857-2YCPZ-R7
ADA4857-2YCP-EBZ
1
Temperature Range
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Package Description
8-Lead LFCSP
8-Lead LFCSP
8-Lead LFCSP
8-Lead SOIC_N
8-Lead SOIC_N
16-Lead LFCSP
16-Lead LFCSP
16-Lead LFCSP
Evaluation Board
Z = RoHS Compliant Part.
©2008–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07040-0-1/17(D)
Rev. D | Page 21 of 21
Package Option
CP-8-13
CP-8-13
CP-8-13
R-8
R-8
CP-16-23
CP-16-23
CP-16-23
Ordering Quantity
250
5,000
1,500
98
2,500
250
5,000
1,500
Branding
H15
H15
H15