AKM AKD5354 Low power 20 bit adc with pga Datasheet

ASAHI KASEI
[AK5354]
AK5354
Low Power 20bit ∆Σ ADC with PGA
FEATURES
The AK5354 is a low voltage 20bit A/D converter for digital audio system. The AK5354 also includes
Analog input PGA, therefore is suitable for microphone application and etc. As digital power supply of the
AK5354 corresponds to 1.8V, the interface with microprocessor can operate at low voltage. Analog
signal input of the AK5354 is single-ended, therefore, any external filters are not required. As the
package is 16pin TSSOP, the AK5354 is a suitable for minimizing system.
FEATURES
1. Resolution : 20bits
2. Recording Functions
• 2-Stereo Inputs Selector
• Analog Input PGA
• Monaural Mixing
• Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz)
3. ADC Characteristics
• Input Level : 1.5Vpp@VA=2.5V (= 0.6 x VA)
• S/(N+D) : 84dB
• DR, S/N : 89dB
4. 3-wire Serial Control I/F
5. Master Clock : 256fs/384fs
6. Audio Data Format : MSB First, 2’s compliment
• 20bit MSB justified or I2S
8. Power Supply
• VA : 2.1 ∼ 3.3V (typ. 2.5V)
• VD : 1.8 ∼ 3.3V (typ. 2.5V)
9. Power Supply Current
• IPGA + ADC : 7mA
10. Ta = -40 ∼ 85°C
11. Package : 16pin TSSOP
LIN1
LIN2
IPGA
ADC
HPF
Audio I/F
Controller
LRCK
BCLK
SDTO
RIN1
RIN2
VD
VCOM
PDN
VA
VSS
Control Register I/F
CSN
MS0054-E-01
CCLK
CDTI
Clock Divider
MCLK
2001/01
-1-
ASAHI KASEI
[AK5354]
n Ordering Guide
-40 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK5354
AK5354VT
AKD5354
n Pin Layout
LIN1
1
16
PDN
RIN1
2
15
CSN
LIN2
3
14
CCLK
RIN2
4
13
CDTI
VCOM
5
12
LRCK
VSS
6
11
MCLK
VA
7
10
BCLK
VD
8
9
SDTO
Top View
PIN/FUNCTION
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin Name
LIN1
RIN1
LIN2
RIN2
VCOM
VSS
VA
VD
SDTO
BCLK
MCLK
LRCK
CDTI
CCLK
CSN
16
PDN
I/O
I
I
I
I
O
O
I
I
I
I
I
I
I
Function
Lch #1 Input Pin
Rch #1 Input Pin
Lch #2 Input Pin
Rch #2 Input Pin
ADC Common Voltage Output Pin
Ground Pin
Analog Power Supply Pin, +2.5V
Digital Power Supply Pin, +2.5V
Audio Serial Data Output Pin
Audio Serial Data Clock Pin
Master Clock Input Pin
Input/Output Channel Clock Pin
Control Data Input Pin
Control Clock Input Pin
Chip Select Pin
Reset & Power Down Pin
“L” : Reset & Power down
“H” : Normal operation
Note: All digital input pins should not be left floating.
MS0054-E-01
2001/01
-2-
ASAHI KASEI
[AK5354]
ABSOLUTE MAXIMUM RATINGS
(VSS=0V; Note 1)
Parameter
Power Supply
Analog
Digital
Input Current (Any Pin Except Supplies)
Analog Input Voltage (LIN2-1, RIN2-1 pins)
Digital Input Voltage
Ambient Temperature (power applied)
Storage Temperature
Symbol
VA
VD
IIN
VINA
VIND
Ta
Tstg
min
-0.3
-0.3
-0.3
-0.3
-40
-65
max
4.6
4.6
±10
VA+0.3
VD+0.3
85
150
Units
V
V
mA
V
V
°C
°C
Note: 1. All voltages with respect to ground.
WARNING: Operation at or beyond these limits may results in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=0V; Note 1)
Parameter
Power Supply
Analog (VA pin)
Digital (VD pin)
Symbol
VA
VD
min
2.1
1.8
typ
2.5
2.5
max
3.3
VA
Units
V
V
Note: 1. All voltages with respect to ground.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
MS0054-E-01
2001/01
-3-
ASAHI KASEI
[AK5354]
ANALOG CHARACTERISTICS
(Ta=25°C; VA, VD=2.5V; fs=44.1kHz; Signal Frequency=1kHz; Measurement frequency=10Hz ∼ 20kHz;
unless otherwise specified)
Parameter
min
typ
max
Resolution
20
Input PGA Characteristics (IPGA):
Input Voltage (LIN1, LIN2, RIN1, RIN2) (Note 2)
1.35
1.5
1.65
Input Impedance
6.3
9
15
+28dB ∼ -8dB
Step Width
1
0.5
0.1
-8dB ∼ -16dB
2
1
0.1
4
2
0.1
-16dB ∼ -32dB
2
-32dB ∼ -40dB
4
-40dB ∼ -52dB
ADC Analog Input Characteristics: (Note 3)
S/(N+D)
(-0.5dBFS Input)
74
84
D-Range
(EIAJ)
82
89
S/N
(EIAJ)
82
89
Interchannel Isolation
90
100
Interchannel Gain Mismatch
0.2
0.5
Power Supplies
Power Supply Current: VA+VD
Normal Operation (PDN=“H”)
IPGA+AD (PM0=1, PM1=1)
Power Down (PDN=“L”)
7
10
(Note 4)
10
100
Units
bits
Vpp
kΩ
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
mA
µA
Note: 2. Analog input voltage (full-scale voltage: IPGA = 0dB) scale with VREF. (IPGA = ADC = 0.6 x VREF)
Note: 3. ADC is input from LIN1/RIN1 or LIN2/RIN2 and it measures included in IPGA. The value of IPGA is set 0dB.
Internal HPF cancels the offset of IPGA and ADC.
Note: 4. In case of power-down mode, all digital input pins including clocks pins (MCLK, BCLK and LRCK) are held
VD or VSS. PDN pin is held VSS.
MS0054-E-01
2001/01
-4-
ASAHI KASEI
[AK5354]
FILTER CHARACTERISTICS
(Ta=25°C; VA=2.1 ∼ 3.3V, VD=1.8 ∼ 3.3; fs=44.1kHz)
Parameter
Symbol
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 5)
±0.1dB
-1.0dB
-3.0dB
Stopband
(Note 5)
SB
Passband Ripple
PR
Stopband Attenuation
SA
Group Delay
(Note 6)
GD
Group Delay Distortion
∆GD
ADC Digital Filter (HPF):
FR
Frequency Response (Note 5)
-3dB
-0.5dB
-0.1dB
min
typ
max
Units
17.4
17.0
0
kHz
kHz
kHz
kHz
dB
dB
1/fs
µs
3.4
10
22
Hz
Hz
Hz
0
20.0
21.1
27.0
±0.1
65
Note:5. The passband and stopband frequencies scale with fs (sampling frequency).
For examples, PB=0.454 x fs(@ADC: -1.0dB), PB=0.454 x fs(@DAC: -0.1dB).
Note: 6. The calculating delay time which occurred by digital filtering. This time is from the input of analog signal to
setting the 20bit data of both channels to the output register for ADC and include group delay of HPF.
DC CHARACTERISTICS
(Ta=25°C; VA=2.1 ∼ 3.3V, VD=1.8 ∼ 3.3V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=-80µA)
Low-Level Output Voltage
(Iout=80µA)
Input Leakage Current
Symbol
VIH
VIL
VOH
VOL
Iin
MS0054-E-01
min
75%VD
VD-0.4
-
Typ
-
max
25%VD
0.4
± 10
Units
V
V
V
V
µA
2001/01
-5-
ASAHI KASEI
[AK5354]
SWITCHING CHARACTERISTICS
(Ta=25°C; VA=2.1 ∼ 3.3V, VD=1.8 ∼ 3.3V; CL=20pF)
Parameter
Symbol
Control Clock Frequency
fCLK
Master Clock (MCLK) 256fs: Frequency
tCLKL
Pulse Width Low
tCLKH
Pulse Width High
fCLK
384fs: Frequency
tCLKL
Pulse Width Low
tCLKH
Pulse Width High
fs
Channel Clock (LRCK)
Frequency
Duty Cycle
Audio Interface Timing
BCLK Period
tBLK
BCLK Pulse Width Low
tBLKL
Pulse Width High
tBLKH
tBLR
BCLK “↓” to LRCK
tDLR
LRCK Edge to SDTO (MSB)
tDSS
BCLK “↓” to SDTO
Control Interface Timing
CCLK Period
tCCK
CCLK Pulse Width Low
tCCKL
Pulse Width High
tCCKH
CDATA Setup Time
tCDS
CDATA Hold Time
tCDH
CSN “H” Time
tCSW
tCSS
CSN “↓” to CCLK “↑”
tCSH
CCLK “↑” to CSN “↑”
Reset / Calibration Timing
PDN Pulse Width
tPW
PDN “↑” to SDTO
(Note 7)
tPWV
min
typ
max
2.048
28
28
3.072
23
23
8
45
11.2896
12.8
16.9344
19.2
44.1
312.5
130
130
-tBLKH+50
Units
50
55
MHz
ns
ns
MHz
ns
ns
kHz
%
tBLKL-50
80
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
80
80
50
50
150
50
50
150
4128
ns
1/fs
Note: 7. These cycles are the numbers of LRCK rising from PDN pin rising.
MS0054-E-01
2001/01
-6-
ASAHI KASEI
[AK5354]
n Timing Diagram
1/fCLK
VIH
VIL
MCLK
tCLKH
tCLKL
1/fs
VIH
VIL
LRCK
tBLK
VIH
VIL
BCLK
tBLKH
tBLKL
Figure 1. Clock Timing
VIH
VIL
LRCK
tBLR
VIH
VIL
BCLK
tDLR
tDSS
SDTO
D20 (MSB)
50%VD
Figure 2. Audio Data Input/Output Timing (Audio I/F = No.0)
VIH
VIL
CSN
tCCKL tCCKH
tCSS
VIH
VIL
CCLK
tCDS
CDTI
op0
tCDH
op1
op2
A0
VIH
VIL
Figure 3. WRITE Command Input Timing
MS0054-E-01
2001/01
-7-
ASAHI KASEI
[AK5354]
tCSW
VIH
VIL
CSN
tCSH
VIH
VIL
CCLK
CDTI
D4
D5
D6
VIH
VIL
D7
Figure 4. WRITE Data Input Timing
tPW
PDN
VIL
tPWV
SDTO
50%VD
Figure 5. Reset Timing
MS0054-E-01
2001/01
-8-
ASAHI KASEI
[AK5354]
OPERATION OVERVIEW
n System Clock
The clocks that are required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (40fs∼). The master clock
(MCLK) should be synchronized with LRCK but the phase is free of care. The frequency of MCLK can be input 256fs or
384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically.
*fs is sampling frequency.
All external clocks (MCLK, BCLK and LRCK) should always be present whenever ADC is in operation. If these clocks
are not provided, the AK5354 may draw excess current and it is not possible to operate properly because utilizes dynamic
refreshed internally. If the external clocks are not present, the AK5354 should be in the power-down mode.
n Audio Data I/F Format
Using SDTO, BCLK and LRCK pins are connected to external system. Audio data format has two kinds of mode, the data
format is MSB-first, 2’s compliment. Setting by DIF bit. The initial value is DIF = “0”.
No.
0
1
DIF bit
0
1
SDTO (ADC)
LRCK
20bit MSB justified
Lch: “H”, Rch: “L”
I2S Compatible
Lch: “L”, Rch: “H”
Table 1. Audio Data Format
BCLK
≥ 40fs
≥ 40fs
LRCK
0
1
2
12
13
14
20
21
31
0
1
2
12
13
14
20
21
31
0
1
BCLK(64fs)
SDTO(o)
19 18
8
7
6
0
19 18
8
7
6
0
19
19:MSB, 0:LSB
Lch Data
Rch Data
Figure 6. Audio Data Format (No.0)
LRCK
0
1
2
3
19
20
21
22
23
24
25
0
1
2
18
19
20
21
22
23
24
25
0
1
BCLK(64fs)
SDTO(o)
19 18
1
0
19 18
1
0
19:MSB, 0:LSB
Lch Data
Rch Data
Figure 7. Audio Data Format (No.1)
n Digital High Pass Filter
The AK5354 has a Digital High Pass Filter (HPF) to cancel DC-offset in ADC and IPGA. The cut-off frequency of the
HPF is 3.4Hz at fs=44.1kHz. It also scales with the sampling frequency (fs). And digital HPF can be selected by ON/OFF
of HPF bit.
MS0054-E-01
2001/01
-9-
ASAHI KASEI
[AK5354]
n System Reset & Offset Calibration
The AK5354 should be reset once by bringing PDN pin “L” after power-up. The control register values are initialized by
PDN “L”.
Offset calibration starts by PDN pin “L” to “H”. It takes 4128/fs to offset calibration cycle. During offset calibration, the
ADC digital data outputs of both channels are forced to a 2’s compliment “0”. Output data of settles data equivalent for
analog input signal after offset calibration. IPGA is set MUTE during offset calibration and after offset calibration.
As a normal offset calibration may not be executed, nothing write at address 01H during offset calibration.
When offset calibration is executed once, the calibration memory is held even if each block is powered down (PM0 = “0”
or PM1 = “0”) by power management bits.
Power Supply
PDN pin
PDN pin may be “L” at power-up.
ADC Internal
PD
State
4128/fs
4128/fs
PM
Normal
CAL
GD
INIT-1
Normal
GD (1)
GD
AIN
SDTO
“0”data
Control register
INIT-2
W rite to register
Inhibit-1
External clocks
(4)
(2)
(3) “0”data
Idle Noise
(1)
Normal
Inhibit-2
Normal
(5)
(5)
The clocks may be stopped.
Figure 8. Power up / Power down Timing Example
• PD:
• PM:
• CAL:
• INIT-1:
• Inhibit-1:
• Inhibit-2:
Power-down state. ADC is output “0”.
Power-down state by Power Management bit. ADC is output “0”.
During offset calibration cycle. IPGA is set MUTE state.
Initializing all control registers.
Inhibits writing to all control registers.
Enable writing to control registers except address 01H.
Note: See “Register Definitions” about the condition of each register.
(1). Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD). Output signal gradually comes to settle to input signal during a group delay.
(2). If the analog signal does not be input, digital outputs have the offset to op-amp of input and some offset error of a
internal ADC.
(3). ADC output is “0” at power down.
(4). This figure shows that MUTE of IPGA is canceled during offset calibration. If MUTE of IPGA is canceled, SDTO
outputs Idle Noise.
(5). When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK5354 should be in the power down
(PDN pin = “L” or PM1 bit = “0”) mode.
MS0054-E-01
2001/01
- 10 -
ASAHI KASEI
[AK5354]
n Timing of Control Register
The internal registers are written by the 3-wire µP interface pins: CSN, CCLK, CDTI. These data are included by Op-code
(3bit), Address (LSB-first, 5bit) and Control data (LSB-first, 8bit). A side of transmitted data is output to each bit by “↓”
of CCLK, a side of receiving data is input by “↑” of CCLK. Writing of data becomes effective by “↑” of CSN. CSN should
be held to “H” at no access.
Address except 00H ∼ 03H inhibits control of writing. And CCLK always need 16 edges of “↑” during CSN = “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
op0 op1 op2 A0 A1 A2 A3 A4 D0 D1 D2 D3 D4 D5 D6 D7
“*” “*” “1”
op0-op2: Op code (Fixed to “**1:WRITE”)
A0-A4: Register Address
D0-D7: Control data
Figure 9. Control Data Timing
n Register Map
Addr
00H
01H
02H
03H
Register Name
Input Select
Mode Control 1
Mode Control 2
Input Analog PGA Control
D7
0
0
MONO1
ZEIP
D6
0
0
MONO0
IPGA6
D5
0
0
ZTM1
IPGA5
D4
HPF
0
ZTM0
IPGA4
D3
RIN2
0
0
IPGA3
D2
RIN1
0
0
IPGA2
D1
LIN2
PM1
DIF
IPGA1
D0
LIN1
PM0
0
IPGA0
All registers are reset at PDN = “L”, then inhibits writing to all registers.
MS0054-E-01
2001/01
- 11 -
ASAHI KASEI
[AK5354]
n Register Definition
Input Select
Addr
00H
Register Name
Input Select
RESET
D7
0
0
D6
0
0
D5
0
0
HPF:
Select ON/OFF of the digital HPF. (0: ON, 1: OFF)
LIN2-1:
RIN2-1:
Select ON/OFF of Lch input. (0: OFF, 1: ON)
Select ON/OFF of Rch input. (0: OFF, 1: ON)
D4
HPF
0
D3
RIN2
0
D2
RIN1
1
D1
LIN2
0
D0
LIN1
1
D4
0
0
D3
0
0
D2
0
0
D1
PM1
1
D0
PM0
1
Mode Control 1
Addr
01H
Register Name
Mode Control 1
RESET
PM1-0:
D7
0
0
D6
0
0
D5
0
0
Power Management (0: Power down, 1: Power up)
PM0:Power control of IPGA
PM1:Power control of ADC
When PDN pin goes “L”, all circuit in the AK5354 can be powered-down in no relation to PM1-0. When PM1-0
goes all “0”, all circuit in the AK5354 can be also powered-down. However, the contents of control registers are held.
In case of PM1 = “1”, MCLK is not stopped.
MS0054-E-01
2001/01
- 12 -
ASAHI KASEI
[AK5354]
Mode Control 2
Addr
02H
Register Name
Mode Control 2
RESET
MONO1-0:
D7
MONO1
0
D6
MONO0
0
D5
ZTM1
1
D4
ZTM0
1
D3
0
0
D2
0
0
D1
DIF
0
D0
0
0
Monaural Mixing
00: Stereo (RESET)
01: (L+R)/2
10: LL
11: RR
SW1
Selector
Lch
ADC
HPF
Lch
+
x 0.5
Selector
Rch
SW2
ADC
HPF
Rch
Figure 10. Monaural mixing block
Mode
Stereo Recording
Monaural Recording
Stereo Input
Monaural Recording
Lch Input
Monaural Recording
Rch Input
SW1
Lch
SW2
Rch
MONO1
0
MONO0
0
(L+R)/2
(L+R)/2
0
1
Lch
Lch
1
0
Rch
Rch
1
1
Table 2. Monaural Mode Setting
ZTM1-0:
DIF:
Setting of Zero Crossing Timeout for IPGA
00: 256/fs
01: 512/fs
10: 1024/fs
11: 2048/fs (RESET)
Select Digital Interface Format
No.
0
1
DIF bit
0
1
SDTO(ADC)
LRCK
20bit MSB justified Lch: “H”, Rch: “L”
I2S Compatible
Lch: “L”, Rch: “H”
Table 3. Audio Data Format
BCLK
≥ 40fs
≥ 40fs
Reset
Inhibits writing at PM1 = “0”.
MS0054-E-01
2001/01
- 13 -
ASAHI KASEI
[AK5354]
Input Analog PGA Control
Addr
03H
Register Name
Input Analog PGA Control
RESET
ZEIP:
D7
ZEIP
0
D6
IPGA6
D5
IPGA5
D4
IPGA4
D3
D2
IPGA3
IPGA2
00H (MUTE)
D1
IPGA1
D0
IPGA0
Select IPGA zero crossing operation (0: Disable, 1: Enable)
Writing to IPGA value at ZEIP = “1”, IPGA value of L/R channels changes by zero crossing
detection or timeout independently.
In the timeout cycle, it is possible to set in ZTM1-0 bit.
When ZTM1-0 is “11”, timeout cycle is 2048/fs = 46.4ms (@fs=44.kHz).
When ZEIP is “0”, IPGA changes immediately. When PM1 is “0”, ZEIP is ignored and IPGA does
the operation which is the same as the case of ZEIP = “0”.
IPGA6-0: Input Analog PGA. 97 levels. 00H=MUTE.
ON/OFF of zero crossing detection can be controlled by ZEIP bit.
Inhibits writing at PM0 = “0”.
DATA
GAIN(dB)
Step
Level
60H
5FH
5EH
•
28H
27H
•
19H
18H
+28.0
+27.5
+27.0
•
+0.0
-0.5
•
-7.5
-8.0
0.5dB
73
17H
16H
•
11H
10H
-9.0
-10.0
•
-15.0
-16.0
1dB
8
0FH
0EH
•
05H
04H
-18.0
-20.0
•
-38.0
-40.0
2dB
12
03H
02H
01H
00H
-44.0
4dB
-48.0
-52.0
MUTE
Table 4. Input Gain Setting
MS0054-E-01
3
1
2001/01
- 14 -
ASAHI KASEI
[AK5354]
• About zero crossing operation
Comparator for zero crossing detection in the AK5354 has offset. Therefore, it is a possible that IPGA value is
changed by zero crossing timeout as zero crossing detection does not occur by a little offset of comparator.
For example, when Lch and Rch are in the state of IPGA = 30H, both channels are set to IPGA = 31H. And then
the only Lch completed zero crossing, Rch is waiting for zero crossing detection, zero crossing counter is reset
when IPGA is newly written 32H, zero crossing operation starts toward IPGA = 32H in state Lch = 31H, Rch =
30H. Internal IPGA value in the AK5354 has the registers of L/R channels independently, according to change
IPGA value independently, IPGA value of L/R channels may become a difference in level.
Therefore, if IPGA is written before zero crossing detection on zero crossing timeout, IPGA is keeping the same
value. When IPGA is finished by normal zero crossing timeout on IPGA value of L/R channels does not give a
difference in level, the change of IPGA should be written after zero crossing timeout cycle and over.
Internal zero crossing
operation completion flag
Lch Internal IPGA
30H
31H
32H
Zero crossing
Rch Internal IPGA
30H
30H
IPGA Register
30H
31H
WR[IPGA=31H]
Reset zero crossing timer
32H
32H
WR[IPGA=32H]
Reset zero crossing timer
Figure 11. About Zero Crossing Operation
MS0054-E-01
2001/01
- 15 -
ASAHI KASEI
[AK5354]
SYSTEM DESIGN
Figure 12 shows the system connection diagram. An evaluation board [AKD5354] is available which demonstrates
application circuit, optimum layout, power supply arrangements and measurement results.
2.1 ~ 3.3V Analog Supply
1
LIN1
PDN
16
2
RIN1
CSN
15
3
LIN2
CCLK
14
4
0.1u
2.2u
5
+
RIN2
CDTI
13
VCOM
LRCK
12
6
VSS
MCLK 11
7
VA
BCLK
10
8
VD
SDTO
9
10u
+
Micro
Controller
AK5354
Audio
Controller
0.1u
1.8 ~ 3.3V Digital Supply
+
10u
0.1u
AGND
System
Digital GND
Figure 12. System Connection Diagram Example
Notes:
- Electrolytic capacitor value of VCOM depends on low frequency noise of supply voltage.
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ASAHI KASEI
[AK5354]
1. Grounding and Power Supply Decoupling
The AK5354 requires careful attention to power supply and grounding arrangements. VA is usually supplied from analog
supply in system. VD is a power supply pin to interface with the external ICs and is supplied from digital supply in system.
VSS of the AK5354 should be connected to analog ground plane. System analog ground and digital ground should be
connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be
as near to the AK5354 as possible, with the small value ceramic capacitor being the nearest.
2. Voltage Reference
The input to VA Voltage sets the analog input range. A 0.1µF ceramic capacitor and a 10µF electrolytic capacitor is
connected to VA and VSS pins, normally. VCOM is a signal ground of this chip. An electrolytic 2.2µF in parallel with a
0.1µF ceramic capacitor attached to these pins eliminates the effects of high frequency noise. No load current may be
drawn from VCOM pin. All signals, especially clock, should be kept away from the VA, VD and VCOM pins in order to
avoid unwanted coupling into the AK5354.
3. Analog Inputs
The analog inputs are single-ended and the input resistance 9kΩ (typ). The input signal range scales with nominally 0.6 x
VA Vpp (typ) centered in the internal common voltage (typ. 0.45 x VA). Usually, the input signal cuts DC with a capacitor.
The cut-off frequency is fc=(1/2πRC). The AK5354 can accept input voltages from VSS to VA. The ADC output data
format is 2’s complement. The DC offset including ADC own DC offset removed by the internal HPF
(fc=3.4Hz@fs=44.1kHz).
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ASAHI KASEI
[AK5354]
PACKAGE
16pin TSSOP (Unit: mm)
5.0
16
1.10max
9
4.4
6.4±0.2
A
1
0.22±0.1
8
0.17±0.05
0.65
0.1±0.1
0.5±0.2
Detail A
Seating Plane
0.10
0∼10°
n Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder plate
MS0054-E-01
2001/01
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ASAHI KASEI
[AK5354]
MARKING
AKM
5354VT
XXYYY
1) Pin #1 indication
2) Date Code : XXYYY (5 digits)
XX : lot#
YYY : Date Code
3) Marketing Code : 5354VT
4) Asahi Kasei Logo
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor
concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other
official approval under the law and regulations of the country of export pertaining to customs and tariffs,
currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support,
or other hazard related device or system, and AKM assumes no responsibility relating to any such use,
except with the express written consent of the Representative Director of AKM. As used here:
a. A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
b. A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing
it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold
AKM harmless from any and all claims arising from the use of said product in the absence of such
notification.
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