Sony CXD2411AR Timing generator for color lcd panel Datasheet

CXD2411AR
Timing Generator for Color LCD Panels
For the availability of this product, please contact the sales office.
Description
The CXD2411AR is a timing signal generator for
color LCD panel drivers.
Features
• Generates the LCX005BK/BKB and
LCX009AK/AKB drive pulse.
• Supports right/left inverse display.
• Supports 16:9 wide display.
• Supports CSYNC and Separate SYNC (XHD, XVD)
input.
• Supports line inversion and field inversion.
• AC drive for LCD panel during no signal
(NTSC/PAL).
• Generates timing signal of external sample-andhold circuit.
• AFC circuit supporting static and dynamic
fluctuations.
Applications
• Color LCD viewfinder
• Single-panel and three-panel projectors
48 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C)
VSS – 0.5 to +7.0
V
• Supply voltage
VDD
• Input voltage
VI
VSS – 0.5 to VDD + 0.5 V
• Output voltage
VO VSS – 0.5 to VDD + 0.5 V
• Operating temperature
Topr
–20 to +85
°C
• Storage temperature
Tstg
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage
VDD
2.7 to 5.5
• Operating temperature
Topr
–20 to +85
V
°C
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95Z14-ST
CXD2411AR
Block Diagram and Pin Configuration
master ck
CKO 41
CKI 42
39 RPD
PLL PHASE COMPARATOR
XCLR
3
PLNT
2
SLCK
1
35 XCLP
XHD 27
XVD 45
H-SYNC
DETECTOR
H-SKEW
DETECTOR
36 HD
HALF-H
KILLER
PLL-COUNTER
6
VSS
19 VDD
TST0
7
31 VSS
TST1
8
43 VDD
TST2
9
TST3 11
TST4 12
40 VSS
V-SYNC
SEPERATOR
(NOISE SHAPE)
46 HP1
TST5 15
47 HP2
TST6 26
48 HP3
TST7 37
38 HP4
TST8 44
10
H-TIMING
PULSE
GENERATOR
RGT
22 HST1
14 HST2
24 HCK1
23 HCK2
32 SH1
33 SH2
EN 17
V-TIMING
PULSE GENERATOR
34 SH3
VD 25
VST 18
VCK1 21
30 SH4
16 CLR
PAL PULSE
ELIMINATOR
VCK2 20
13 SLFR
FIELD & LINE
CONTROLLER
FLDO 29
SBLK
5
WIDE
4
28 FRP
–2–
CXD2411AR
Pin Description
Pin
Symbol
No.
I/O
Description
Input pin for
open status
1
SLCK
I
Switches between LCX005BK (H) and LCX009 (L)
L
2
PLNT
I
Switches between PAL (H) and NTSC (L)
L
3
XCLR
I
Cleared at 0V
H
4
WIDE
I
Switches between 16:9 display (H) and 4:3 display (L)
L
5
SBLK
O
Black signal pulse output (during WIDE MODE) (positive polarity)
—
6
VSS
—
GND
7
TST0
—
Leave this open.
—
8
TST1
—
Leave this open.
—
9
TST2
—
Leave this open.
—
10
RGT
I
Switches between Normal scan (H) and Reverse scan (L)
H
11
TST3
—
Leave this open.
—
12
TST4
—
Leave this open.
—
13
SLFR
I
Switches between field inversion (H) and line inversion (L)
L
14
HST2
O
H start pulse 2 (positive polarity)
—
15
TST5
—
Leave this open.
—
16
CLR
O
CLR pulse output (positive polarity)
—
17
EN
O
EN pulse output (negative polarity)
—
18
VST
O
V start pulse (positive polarity)
—
19
VDD
—
Power supply
20
VCK2
O
V clock pulse 2
—
21
VCK1
O
V clock pulse 1
—
22
HST1
O
H start pulse 1 (positive polarity)
—
23
HCK2
O
H clock pulse 2
—
24
HCK1
O
H clock pulse 1
—
25
VD
O
VD pulse output (positive polarity)
—
26
TST6
—
Leave this open.
—
27
XHD
I
XHD (negative polarity)/Composite sync (positive polarity) input
—
28
FRP
O
AC drive timing pulse output
—
29
FLDO
O
Field identification signal output
—
30
SH4
O
Sample-and-hold pulse (positive polarity)
—
31
VSS
—
GND
32
SH1
O
Sample-and-hold pulse (positive polarity)
—
33
SH2
O
Sample-and-hold pulse (positive polarity)
—
34
SH3
O
Sample-and-hold pulse (positive polarity)
—
35
XCLP
O
Burst position clamp pulse output (negative polarity)
—
36
HD
O
HD pulse output (positive polarity)
—
37
TST7
—
Leave this open.
—
–3–
CXD2411AR
Pin
Symbol
No.
I/O
Description
Input pin for
open status
38
HP4
I
Switches for the horizontal display position
H
39
RPD
O
Phase comparator output
—
40
VSS
—
GND
41
CKO
O
Oscillation cell (output)
—
42
CKI
I
Oscillation cell (input)
—
43
VDD
—
Power supply
44
TST8
—
Leave this open.
—
45
XVD
I
XVD (negative polarity) input
L
46
HP1
I
Switches for the horizontal display position
L
47
HP2
I
Switches for the horizontal display position
L
48
HP3
I
Switches for the horizontal display position
L
(H: Pull up, L: Pull down)
Note) The CXD2411AR processes CSYNC and Separate SYNC inputs with the same pins. Therefore, care
should be given to the following points when using the CXD2411AR.
1) During CSYNC input, the XVD input pin should be set to L or left open.
2) During Separate SYNC input (XHD, XVD), the XVD width specification is from 2H to 10H.
–4–
CXD2411AR
Electrical Characteristics
1. DC characteristics
Item
(Temperature = 25°C, VSS = 0V)
Symbol
Conditions
Min.
Typ.
2.7
Max.
Unit
5.5
V
Supply voltage
VDD
Input voltage
VIH
TTL input cell (5V ±10%)
2.2
V
Input voltage
VIH
TTL input cell (3.0V ±10%)
1.8
V
Input voltage
VIL
TTL input cell
Input voltage
VIH
CMOS input cell
Input voltage
VIL
CMOS input cell
Output voltage
VOH
IOH = –4mA (HCKn, VCKn)
Output voltage
VOL
IOL = 8mA (HCKn, VCKn)
Output voltage
VOH
IOH = –3mA (CKO, CKI)
Output voltage
VOL
IOL = 3mA (CKO, CKI)
Output voltage
VOH
IOH = –2mA (other than the above)
Output voltage
VOL
IOL = 4mA (other than the above)
Input leak current
IL
Normal input pin
–10
Input leak current
IIL
With pull-up resistor
–12
Input leak current
IIH
With pull-down resistor
12
Output leak current
ILZ
RPDn, FPDn (at high impedance state)
–40
Current consumption
IDD
VDD = 5.0V
0.8
V
V
0.7VDD
0.3VDD
VDD – 0.8
V
V
0.4
VDD/2
V
V
VDD/2
VDD – 0.8
V
V
0.4
V
10
µA
–100
–240
µA
100
240
µA
40
µA
25
2. AC characteristics
mA
(VDD = 2.7 to 5.5V)
Item
Symbol
Applicable pins
Conditions
Min. Typ. Max. Unit
Clock input cycle
CKI
Cross-point time difference
HCK1, HCK2
∆t
CL = 30pF
10
ns
Cross-point time difference
VCK1, VCK2
∆t
CL = 30pF
10
ns
Output rise delay
HCKn, VCKn
tpr
CL = 30pF
30
ns
Output fall delay
HCKn, VCKn
tpf
CL = 30pF
25
ns
Output rise delay
Other than HCKn and VCKn
tpr
CL = 30pF
40
ns
Output fall delay
Other than HCKn and VCKn
tpf
CL = 30pF
22
ns
HCK1, SH1 delay time
difference
HCK1, SH1
dt1
CL = 30pF
60
85
ns
HCK1, SH1 delay time
difference
HCK1, SH1
dt2
CL = 30pF
60
95
ns
HCK2, SH1 delay time
difference
HCK2, SH1
dt1
CL = 30pF
60
85
ns
HCK2, SH1 delay time
difference
HCK2, SH1
dt2
CL = 30pF
60
95
ns
HCK1 Duty
HCK1
tH/tH + tL
CL = 30pF
46
52
%
HCK2 Duty
HCK2
tH/tH + tL
CL = 30pF
46
52
%
60
Note) n = 1, 2
–5–
ns
CXD2411AR
Timing Definition
VDD
CKI
0V
VDD
Output
0V
tpr
VDD
Output
0V
tpf
VDD
VCK1
(HCK1)
50%
50%
0V
VDD
VCK2
(HCK2)
50%
50%
0V
∆t
∆t
t
t
tH – tL = 2 (t – t1)
CKI
tH = t – t1 + t2
tL = t – t2 + t1
tH – tL = 2 (t2 – t1)
HCK1
(HCK2)
50%
t1
50%
tH
SH1
t2
tL
50%
dt1
50%
50%
dt2
–6–
CXD2411AR
LCX005BK/BKB and LCX009AK/AKB Color Coding Diagram
The delta arrangement is used for the color coding in the LCD panels with which this IC is compatible. Note
that the shaded region within the diagram is not displayed.
LCX005BK/BKB pixel arrangement
B
R
G
B
R
G
B
HSW174
R
G
B
HSW175
R
G
B
dummy2 to 5
R
G
B
R
Photo-shielding area
B
G
Vline1
Vline2
R
B
B
R
G
Vline3
G
B
B
R
G
B
R
R
G
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
R
G
G
B
R
G
B
R
G
B
R
R
G
218
dummy2
Display area
G
B
R
G
Vline217
Vline218
B
B
G
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
G
R
G
R
B
R
2
dummy3
R
dummy4
B
R
G
B
R
G
B
R
3
G
B
R
G
B
R
521
G
B
R
13
537
Basic specifications
Total horizontal dots
Horizontal display dots
:
:
537H
521H
Total vertical dots
Vertical display dots
:
:
222H
218H
Total dots
Display dots
:
:
119,214H
113,578H
–7–
G
222
G
dummy1
HSW3
2
HSW2
HSW1
CXD2411AR
LCX009AK/AKB pixel arrangement
B
R
G
B
R
G
B
R
G
B
dummy5 to 8
R
G
B
R
Photo-shielding area
dummy2
R
B
Vline1
Vline2
G
R
R
G
B
Vline3
B
R
R
G
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
R
G
G
B
R
G
B
B
R
G
B
R
R
G
B
R
G
G
B
R
G
B
R
G
B
R
R
G
Display area
B
R
R
G
B
Vline224
R
dummy3
R
B
R
G
B
Vline225
G
R
G
B
R
G
B
G
B
R
G
B
R
B
R
G
B
R
G
R
G
B
R
G
B
G
B
R
G
B
R
B
R
G
B
R
G
R
G
B
R
G
14
B
G
B
R
G
B
R
B
R
G
B
R
G
R
G
B
R
G
B
R
R
G
B
R
G
B
800
R
G
B
R
G
B
Basic specifications
Total horizontal dots
Horizontal display dots
:
:
827H
800H
Total vertical dots
Vertical display dots
:
:
228H
225H
Total dots
Display dots
:
:
188,556H
180,000H
G
R
G
R
G
B
R
B
B
R
13
827
–8–
G
B
G
B
R
R
G
228
G
HSW268
2
R
HSW267
225
B
dummy1
HSW2
1
HSW1
dummy1 to 4
CXD2411AR
Description of Mode Selection Switch (SLCK, PLNT, WIDE)
MODE
SLCK
PLNT
WIDE
H
L
L
LCX005BK/BKB, NTSC, NORMAL
H
L
H
LCX005BK/BKB, NTSC, WIDE
H
H
L
LCX005BK/BKB, PAL, NORMAL
H
H
H
LCX005BK/BKB, PAL, WIDE
L
L
L
LCX009AK/AKB, NTSC, NORMAL
L
L
H
LCX009AK/AKB, NTSC, WIDE
L
H
L
LCX009AK/AKB, PAL, NORMAL
L
H
H
LCX009AK/AKB, PAL, WIDE
∗ NORMAL (4:3 display), WIDE (16:9 display)
SLFR
SLFR is the selector switch for the AC drive timing pulse (FRP). This switch selects field inversion when H and
line inversion when L. Normally, line inversion (L) is used. The transition point is one clock cycle after the
transition point of the VCK1 and VCK2 pulses.
FRP
1H inversion
(2H cycle)
1F inversion
(2F cycle)
1H
1H
1H
1Field
1H
1Field
∗ FRP polarity is not specified.
–9–
CXD2411AR
HP1, 2, 3, 4
These are selector switches for the horizontal display position. The HST timing can be set at 2fh intervals in 16
different ways by using the four HST position bits. The picture center is set at internal preset value: HP1/2/3/4:
LLLH. However, actually, because there is a difference between the RGB signal and the drive pulse delays,
the picture center may not match the design center. In this case, adjust with these switches.
The HST timing (from SYNC termination to the rising edge of HST) for even lines is shown below.
LCX005BK/BKB (NTSC, PAL)
HST1 (NTSC/PAL)
HST2 (NTSC/PAL)
HP4
HP3
HP2
HP1
0
0
0
0
72fh (6.51/6.56µs)
74.5fh (6.74/6.79µs)
0
0
0
1
70fh
72.5fh
0
0
1
0
68fh
70.5fh
0
0
1
1
66fh
68.5fh
0
1
0
0
64fh
66.5fh
0
1
0
1
62fh
64.5fh
0
1
1
0
60fh
62.5fh
0
1
1
1
58fh
60.5fh
1
0
0
0
56fh (5.06/5.11µs)
58.5fh (5.29/5.33µs)
1
0
0
1
54fh
56.5fh
1
0
1
0
52fh
54.5fh
1
0
1
1
50fh
52.5fh
1
1
0
0
48fh
50.5fh
1
1
0
1
46fh
48.5fh
1
1
1
0
44fh
46.5fh
1
1
1
1
42fh (3.80/3.83µs)
44.5fh (4.02/4.06µs)
∗ The HST1 and 2 timing for odd lines is 1.5fh delayed and 1.5fh advanced respectively from the above
timings. (Refer to the Timing Charts for details.)
– 10 –
CXD2411AR
LCX009AK/AKB (NTSC, PAL)
HST1 (NTSC/PAL)
HST2 (NTSC/PAL)
HP4
HP3
HP2
HP1
0
0
0
0
91fh (5.51/5.55µs)
93.5fh (5.66/5.70µs)
0
0
0
1
89fh
91.5fh
0
0
1
0
87fh
89.5fh
0
0
1
1
85fh
87.5fh
0
1
0
0
83fh
85.5fh
0
1
0
1
81fh
83.5fh
0
1
1
0
79fh
81.5fh
0
1
1
1
77fh
79.5fh
1
0
0
0
75fh (4.54/4.57µs)
77.5fh (4.69/4.72µs)
1
0
0
1
73fh
75.5fh
1
0
1
0
71fh
73.5fh
1
0
1
1
69fh
71.5fh
1
1
0
0
67fh
69.5fh
1
1
0
1
65fh
67.5fh
1
1
1
0
63fh
65.5fh
1
1
1
1
61fh (3.69/3.72µs)
63.5fh (3.84/3.87µs)
∗ The HST1 and 2 timing for odd lines is 1.5fh delayed and 1.5fh advanced respectively from the above
timings. (Refer to the Timing Charts for details.)
– 11 –
CXD2411AR
Right/Left Inversion
The LCD panel is arranged in a delta pattern, where identical signal line has 1.5-dot offset at adjoining vertical
lines. For this reason, a 1.5-bit offset is attached to the horizontal start pulse (HST) between odd lines and
even lines. HCK and SH are also 1.5-bit offset in a similar manner.
When the panel is driven with left scan (Reverse scan), this offset relationship becomes inverted for even and
odd lines. Moreover, since the dot arrangement is asymmetrical, the HST position is also changed. The
CXD2411AR deals with this inversion as follows.
Right scan
Left scan
(Normal scan)
(Reverse scan)
AAAA
AAAA
AA
AA
AAA
AA
V SCANNER
H SCANNER
Display area
When using single-panel
(1) When the right/left inversed-identification pin (RGT) goes L, the relationship concerning HCK output
switches between odd and even lines. In this case, use HST1 for the horizontal direction start pulse.
When RGT is H:
Right scan mode is on. The right scan drive pulse is output by the timing generator and is supplied to
the panel.
When RGT is L:
Left scan mode is on. The left scan drive pulse is output by the timing generator and is supplied to the
panel.
When using three-panels
(1) In order to be able to simultaneously drive three panels, with a mixture of right/left inversion on and off,
output two pulses regarding HST pulse: HST1 for right scan (Normal scan) and HST2 for left scan
(Reverse scan).
In addition, left and right scan outputs are necessary for the RGT signal as well. However, since this timing
generator does not have an RGT (right/left inversed-identification) output pin for left scan, external
measures must be taken. Similarly, external measures are also taken for HCK1 and 2.
Regarding SH, the wiring of SH1 and SH4 to the driver IC.
(2) When the right/left inversed-identification pin (RGT) goes L, the relationship concerning HCK output
switches between odd and even lines for each output switches.
When RGT is H:
Right scan mode is on. The right scan (A) and left scan (B) drive pulses are output by the timing
generator and are supplied to panels 1 and 2 and panel 3, respectively.
When RGT is L:
Left scan mode is on and (A) and (B) outputs are switched. Accordingly, panels 1 and 2 are used for
left scan and panel 3 changes to right scan.
– 12 –
CXD2411AR
Application Circuit (Three-panel LCD drive)
SH1
SH2
Right scan driver
SH3
SH4
SH1 32
SH2 33
TG
SH3 34
SH4 30
SH1
SH2
Left scan driver
SH3
SH4
Signal Driver
Panel 1
TG
(Right scan)
SH1 32
SH2 33
Right scan output
SH3 34
(A)
SH4 30
Signal Driver
Panel 2
HST1 22
SH1 32
SH2 33
Left scan output
(B)
SH3
(Right scan)
Signal Driver
34
SH4 30
HST2 14
Panel 3
(Left scan)
HCK1 24
HCK2 23
(common)
RGT 10
VST 18
RGT IN
VCK1 21
VCK2 20
EN 17
(To all panels)
CLR 16
∗ The facing of the three panels is the same.
– 13 –
CXD2411AR
SH Pulse and HCK Phase Relationship
The phase relationship between the SH pulse and HCK changes according to switching between right scan
(Normal scan) and left scan (Reverse scan).
In the present timing, SH3 is the re-sampling pulse.
RGT = H (Normal scan)
RGT = L (Reverse scan)
HCK1
SH1
SH2
SH3
SH4
– 14 –
CXD2411AR
WIDE Mode
Setting the WIDE pin (Pin 4) to H, shifts the unit to WIDE mode. In this mode, the aspect ratio is converted
through pulse eliminator processing, allowing 16:9 quasi-WIDE display.
During WIDE mode, vertical pulse eliminator scanning of 1/4 for NTSC and 1/2 and 1/4 for PAL, are
performed, and the video signal is compressed to achieve a 16:9 aspect ratio. In addition, in areas outside the
display area, black is displayed by performing high-speed scanning. The timing during high-speed scanning is
a 2H cycle pulse consisting of normal drive (1H) and quadruple-speed drive (1H) and black signals are written
in 28 and 27 lines, respectively of the upper and lower side of this display area. During this time, FRP is
changed to a 4H cycle, HST to a 2H cycle, and EN and CLR are not output.
In addition, the SBLK output, which is the black signal generation timing pulse, becomes H.
(For example, black display in the panel is permitted by connecting the black signal output SBLK to the
external RGB input pin of the CXA1785R/AR.)
Refer to the attached sheets for detailed timing.
Vertical high-speed scanning
AAAA
AAA
AAAA
Black display area
218 LINES
(225 LINES)
AAA
Display area
Display area
Black display area
4 : 3 display
Vertical pulse eliminator scanning
(at normal-speed scanning)
16 : 9 display
∗ Numbers in parentheses are for the LCX009AK/AKB.
All other numbers are for the LCX005BK/BKB.
At high-speed scanning
At normal-speed scanning
VCK1
Quadruple-speed scanning
Normal-speed scanning
HST
2H cycle
FRP
4H cycle
SBLK
– 15 –
28 LINES
(28 LINES)
163 LINES
(169 LINES)
27 LINES
(28 LINES)
– 16 –
EN
CLR
VCK2
VCK1
FRP
SH4
SH3
SH2
SH1
HCK2
HCK1
HST2
HST1
XCLP
HD
(BLK)
XHD
MCK
EVEN FIELD
ODD LINE
3.0µs (33fh)
1.3µs (14fh)
2.0µs (22fh)
4.4µs (49fh)
4.7µs (52fh)
0.5µs (6fh)
18.5fh
0.5fh
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
ODD FIELD
2.1µs (23fh)
4.7µs (52fh)
LCX005BK/BKB Horizontal Direction Timing Chart
NTSC/PAL
13fh
13fh
4.5fh
HP1/2/3/4: LLLH
RGT: H (Normal scan)
CXD2411AR
– 17 –
EN
CLR
VCK2
VCK1
FRP
SH4
SH3
SH2
SH1
HCK2
HCK1
HST2
HST1
XCLP
HD
(BLK)
XHD
MCK
EVEN FIELD
EVEN LINE
3.0µs (33fh)
1.3µs (14fh)
2.0µs (22fh)
4.4µs (49fh)
4.7µs (52fh)
0.5µs (6fh)
18.0fh
2.5fh
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
ODD FIELD
2.1µs (23fh)
4.7µs (52fh)
LCX005BK/BKB Horizontal Direction Timing Chart
NTSC/PAL
13fh
13fh
3.0fh
HP1/2/3/4: LLLH
RGT: H (Normal scan)
CXD2411AR
– 18 –
EN
CLR
VCK2
VCK1
FRP
SH4
SH3
SH2
SH1
HCK2
HCK1
HST2
HST1
XCLP
HD
(BLK)
XHD
MCK
EVEN FIELD
ODD LINE
3.0µs (34fh)
1.3µs (14fh)
2.0µs (22fh)
4.4µs (49fh)
4.7µs (52fh)
0.5µs (5fh)
18.0fh
2.5fh
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
ODD FIELD
2.1µs (23fh)
4.7µs (52fh)
LCX005BK/BKB Horizontal Direction Timing Chart
NTSC/PAL
13fh
13fh
4.0fh
HP1/2/3/4: LLLH
RGT: L (Reverse scan)
CXD2411AR
– 19 –
EN
CLR
VCK2
VCK1
FRP
SH4
SH3
SH2
SH1
HCK2
HCK1
HST2
HST1
XCLP
HD
(BLK)
XHD
MCK
EVEN FIELD
3.0µs (34fh)
EVEN LINE
1.4µs (15fh)
2.0µs (22fh)
4.5µs (50fh)
4.7µs (52fh)
0.5µs (5fh)
18.5fh
0.5fh
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
ODD FIELD
2.0µs (22fh)
4.7µs (52fh)
LCX005BK/BKB Horizontal Direction Timing Chart
NTSC/PAL
13fh
13fh
5.5fh
HP1/2/3/4: LLLH
RGT: L (Reverse scan)
CXD2411AR
– 20 –
EN
CLR
VCK2
VCK1
FRP
SH4
SH3
SH2
SH1
HCK2
HCK1
HST2
HST1
XCLP
HD
(BLK)
XHD
MCK
1.3µs (22fh)
ODD LINE
3.0µs (50fh)
EVEN FIELD
2.1µs (34fh)
43.5fh
0.5µs (8fh)
2.0µs (33fh)
4.4µs (72fh)
4.7µs (78fh)
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
ODD FIELD
4.7µs (78fh)
LCX009AK/AKB Horizontal Direction Timing Chart
NTSC/PAL
0.5fh
12fh
12fh
2.5fh
HP1/2/3/4: LLLH
RGT: H (Normal scan)
CXD2411AR
– 21 –
EN
CLR
VCK2
VCK1
FRP
SH4
SH3
SH2
SH1
HCK2
HCK1
HST2
HST1
XCLP
HD
(BLK)
XHD
MCK
1.3µs (22fh)
EVEN LINE
3.0µs (50fh)
EVEN FIELD
2.1µs (34fh)
43.0fh
0.5µs (8fh)
2.0µs (33fh)
4.4µs (72fh)
4.7µs (78fh)
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
ODD FIELD
4.7µs (78fh)
LCX009AK/AKB Horizontal Direction Timing Chart
NTSC/PAL
2.5fh
12fh
12fh
4.0fh
HP1/2/3/4: LLLH
RGT: H (Normal scan)
CXD2411AR
– 22 –
EN
CLR
VCK2
VCK1
FRP
SH4
SH3
SH2
SH1
HCK2
HCK1
HST2
HST1
XCLP
HD
(BLK)
XHD
MCK
1.3µs (22fh)
ODD LINE
3.0µs (51fh)
EVEN FIELD
2.1µs (34fh)
43.0fh
0.5µs (7fh)
2.0µs (33fh)
4.4µs (72fh)
4.7µs (78fh)
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
ODD FIELD
4.7µs (78fh)
LCX009AK/AKB Horizontal Direction Timing Chart
NTSC/PAL
2.5fh
12fh
12fh
3.0fh
HP1/2/3/4: LLLH
RGT: L (Reverse scan)
CXD2411AR
– 23 –
EN
CLR
VCK2
VCK1
FRP
SH4
SH3
SH2
SH1
HCK2
HCK1
HST2
HST1
XCLP
HD
(BLK)
XHD
MCK
1.3µs (22fh)
EVEN LINE
3.0µs (51fh)
EVEN FIELD
2.1µs (34fh)
43.5fh
0.5µs (7fh)
2.0µs (33fh)
4.4µs (72fh)
4.7µs (78fh)
Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
ODD FIELD
4.7µs (78fh)
LCX009AK/AKB Horizontal Direction Timing Chart
NTSC/PAL
0.5fh
12fh
12fh
1.5fh
HP1/2/3/4: LLLH
RGT: L (Reverse scan)
CXD2411AR
– 24 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX005BK/BKB Vertical Direction Timing Chart
NTSC
CXD2411AR
– 25 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX005BK/BKB Vertical Direction Timing Chart
NTSC
CXD2411AR
– 26 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX005BK/BKB Vertical Direction Timing Chart
PAL
CXD2411AR
– 27 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX005BK/BKB Vertical Direction Timing Chart
PAL
CXD2411AR
– 28 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX009AK/AKB Vertical Direction Timing Chart
NTSC
CXD2411AR
– 29 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX009AK/AKB Vertical Direction Timing Chart
NTSC
CXD2411AR
– 30 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX009AK/AKB Vertical Direction Timing Chart
PAL
CXD2411AR
– 31 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX009AK/AKB Vertical Direction Timing Chart
PAL
CXD2411AR
– 32 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX005BK/BKB WIDE Vertical Direction Timing Chart
NTSC
CXD2411AR
– 33 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX005BK/BKB WIDE Vertical Direction Timing Chart
NTSC
CXD2411AR
– 34 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX005BK/BKB WIDE Vertical Direction Timing Chart
PAL
CXD2411AR
– 35 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX005BK/BKB WIDE Vertical Direction Timing Chart
PAL
CXD2411AR
– 36 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX009AK/AKB WIDE Vertical Direction Timing Chart
NTSC
CXD2411AR
– 37 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX009AK/AKB WIDE Vertical Direction Timing Chart
NTSC
CXD2411AR
– 38 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
ODD FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX009AK/AKB WIDE Vertical Direction Timing Chart
PAL
CXD2411AR
– 39 –
SBLK
VD
FLD
FRP
(1F inversion)
CLR
EN
HST
FRP
(1H inversion)
VCK2
VCK1
VST
(BLK)
CSYNC
XHD
XVD
EVEN FIELD
Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins.
FRP polarity is not specified for each line and field.
LCX009AK/AKB WIDE Vertical Direction Timing Chart
PAL
CXD2411AR
CXD2411AR
AC Driving for No Signal
HST1, HST2, HCK1, HCK2, FRP, VCK1, VCK2, XCLP, HD, VD, and VST are made to run free so that the
LCD panel is AC driven even when there are no horizontal and vertical sync signals from the XHD and XVD
pins.
During this time, the PLL counter is made to run free because the horizontal sync separation circuit stops. In
addition, the auxiliary V counter is used to create the reference pulse for generating VD and VST because the
vertical sync separation circuit is also stopped.
The cycle of this V counter is designed to be 269H for NTSC and 321H for PAL. However, when there is no
vertical sync signal for 301H (NTSC) or 360H (PAL), the no signal state is assumed and the free running VD
and VST pulses are generated from the next field.
The RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from causing
phase errors due to phase comparison.
AFC Circuit (702/1050fh Generation)
4.7µs
XHD
5V
RPD
2.5V
The center of SYNC
0V
A fully synchronized AFC circuit is built in. PLL error detection signal is generated at the following timing.
The phase comparison output of the entire bottom of XHD and the internal H counter becomes RPD. RPD
output is converted to DC error with the lag-lead filter, and then it changes the varicap capacitance and the
oscillating frequency is stabilized at 702, 1050fh in the LCX005BK/BKB, LCX009AK/AKB.
– 40 –
CXD2411AR
RGB decoder
AC conversion circuit (RGB driver)
Sample-and-hold circuit
(RGB driver)
Sample-and-hold circuit
(RGB driver)
RGB driver
Backlight driver circuit
Application Circuit
10k
1000p
33k
VD
N.C.
FRP
XHD
FLDO
VSS
SH4
SH1
SH3
HST1 22
40 VSS
VCK1 21
41 CKO
VCK2 20
42 CKI
VDD 19
43 VDD
VST 18
EN 17
44 N.C.
L
100k
HCK2 23
39 RPD
CLR 16
N.C. 15
45 XVD
46 FP1
VSS
TST0
TST1
TST2
3
4
5 6
7
8
9 10 11 12
2
N.C.
SBLK
1
RGT
WIDE
HST2 14
SLFR 13
XCLR
+12V
RGB decoder
47 FP2
48 FP3
SLCK
PLNT
20p
LCD panel
+5V
3300p
0.01µ
38 HP4
HCK1 24
N.C.
1k
SH2
HD
+5V
3.3µ 10k
37 N.C.
XCLP
36 35 34 33 32 31 30 29 28 27 26 25
LCD panel
16:9
LCX005BK/BKB
PAL
LCX009AK/AKB
NT
N
R
4:3
Reference examples of L value: when using LCX009AK/AKB
when using LCX005BK/BKB
4.7µH
10µH
RGB external input
(RGB driver)
+5V
Recommended varicap: 1T369 (SONY)
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 41 –
CXD2411AR
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗
7.0 ± 0.1
36
S
25
13
0.5 ± 0.2
B
A
48
(8.0)
24
37
(0.22)
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
0.18 – 0.03
+ 0.2
1.5 – 0.1
0.13 M
0.1
S
0.5 ± 0.2
(0.18)
0° to 10°
DETAIL B:SOLDER
DETAIL A
0.18 ± 0.03
0.127 ± 0.04
+ 0.08
0.18 – 0.03
(0.127)
+0.05
0.127 – 0.02
0.1 ± 0.1
DETAIL B:PALLADIUM
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
LQFP048-P-0707
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 42 –
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