Cypress CY7C1412JV18-250BZXI 36-mbit qdrâ ¢-ii sram 2-word burst architecture Datasheet

CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
36-Mbit QDR™-II SRAM 2-Word
Burst Architecture
Features
Configurations
■
Separate independent read and write data ports
❐ Supports concurrent transactions
■
267 MHz clock for high bandwidth
■
2-word burst on all accesses
CY7C1410JV18 – 4M x 8
CY7C1425JV18 – 4M x 9
CY7C1412JV18 – 2M x 18
CY7C1414JV18 – 1M x 36
■
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 534 MHz) at 267 MHz
■
Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■
Single multiplexed address input bus latches address inputs
for both read and write ports
■
Separate port selects for depth expansion
■
Synchronous internally self-timed writes
■
QDR™-II operates with 1.5 cycle read latency when Delay Lock
Loop (DLL) is enabled
■
Operates like a QDR-I device with 1 cycle read latency in DLL
off mode
■
Available in x8, x9, x18, and x36 configurations
■
Full data coherency, providing most current data
■
Core VDD = 1.8V (±0.1V); IO VDDQ = 1.4V to VDD
■
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
Variable drive HSTL output buffers
■
JTAG 1149.1 compatible test access port
■
Delay Lock Loop (DLL) for accurate data placement
Functional Description
The CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, and
CY7C1414JV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR-II architecture. QDR-II architecture consists
of two separate ports: the read port and the write port to access
the memory array. The read port has data outputs to support read
operations and the write port has data inputs to support write
operations. QDR-II architecture has separate data inputs and
data outputs to completely eliminate the need to “turn-around”
the data bus required with common IO devices. Access to each
port is accomplished through a common address bus. The read
address is latched on the rising edge of the K clock and the write
address is latched on the rising edge of the K clock. Accesses to
the QDR-II read and write ports are completely independent of
one another. To maximize data throughput, both read and write
ports are provided with DDR interfaces. Each address location
is associated with two 8-bit words (CY7C1410JV18), 9-bit words
(CY7C1425JV18), 18-bit words (CY7C1412JV18), or 36-bit
words (CY7C1414JV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turn-arounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
Cypress Semiconductor Corporation
Document #: 001-12561 Rev. *D
•
267 MHz
250 MHz
Unit
267
250
MHz
mA
x8
1330
1200
x9
1330
1200
x18
1370
1230
x36
1460
1290
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 10, 2007
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CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Logic Block Diagram (CY7C1410JV18)
K
CLK
Gen.
DOFF
21
Address
Register
Read Add. Decode
K
Write
Reg
2M x 8 Array
Address
Register
Write
Reg
2M x 8 Array
A(20:0)
21
8
Write Add. Decode
D[7:0]
A(20:0)
RPS
Control
Logic
C
Read Data Reg.
C
CQ
16
VREF
WPS
8
Control
Logic
8
NWS[1:0]
Reg.
Reg. 8
Reg.
8
CQ
8
Q[7:0]
Logic Block Diagram (CY7C1425JV18)
K
CLK
Gen.
DOFF
21
Address
Register
Read Add. Decode
K
Write
Reg
2M x 9 Array
Address
Register
Write
Reg
2M x 9 Array
A(20:0)
21
9
Write Add. Decode
D[8:0]
A(20:0)
RPS
Control
Logic
C
Read Data Reg.
C
CQ
18
VREF
WPS
9
Control
Logic
BWS[0]
Document #: 001-12561 Rev. *D
9
Reg.
Reg. 9
Reg.
9
CQ
9
Q[8:0]
Page 2 of 26
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CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Logic Block Diagram (CY7C1412JV18)
K
CLK
Gen.
DOFF
20
Address
Register
Read Add. Decode
K
Write
Reg
1M x 18 Array
Address
Register
Write
Reg
1M x 18 Array
A(19:0)
20
18
Write Add. Decode
D[17:0]
A(19:0)
RPS
Control
Logic
C
Read Data Reg.
C
CQ
36
VREF
WPS
18
Control
Logic
18
BWS[1:0]
Reg.
Reg. 18
Reg.
18
CQ
18
Q[17:0]
Logic Block Diagram (CY7C1414JV18)
K
CLK
Gen.
DOFF
19
Address
Register
Read Add. Decode
K
Write
Reg
512K x 36 Array
Address
Register
Write
Reg
512K x 36 Array
A(18:0)
19
36
Write Add. Decode
D[35:0]
A(18:0)
RPS
Control
Logic
C
Read Data Reg.
C
CQ
72
VREF
WPS
36
Control
Logic
BWS[3:0]
Document #: 001-12561 Rev. *D
36
Reg.
Reg. 36
Reg.
36
CQ
36
Q[35:0]
Page 3 of 26
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CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Pin Configuration
The pin configuration for CY7C1410JV18, CY7C1412JV18, and CY7C1414JV18 follow. [1]
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1410JV18 (4M x 8)
A
1
2
3
4
5
6
7
8
9
10
11
CQ
NC/72M
A
WPS
NWS1
K
NC/144M
RPS
A
A
CQ
B
NC
NC
NC
A
NC/288M
K
NWS0
A
NC
NC
Q3
C
NC
NC
NC
VSS
A
A
A
VSS
NC
NC
D3
D
NC
D4
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
Q2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q1
D1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D0
N
NC
D7
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
Q7
A
A
C
A
A
NC
NC
NC
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
CY7C1425JV18 (4M x 9)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/72M
A
WPS
NC
K
NC/144M
RPS
A
A
CQ
B
NC
NC
NC
A
NC/288M
K
BWS0
A
NC
NC
Q4
C
NC
NC
NC
VSS
A
A
A
VSS
NC
NC
D4
D
NC
D5
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS
VDDQ
NC
D3
Q3
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
D6
Q6
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q2
D2
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q1
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D1
N
NC
D8
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
Q8
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Note
1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document #: 001-12561 Rev. *D
Page 4 of 26
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CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Pin Configuration
The pin configuration for CY7C1410JV18, CY7C1412JV18, and CY7C1414JV18 follow. [1] (continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1412JV18 (2M x 18)
A
1
2
3
4
5
6
7
8
9
10
11
CQ
NC/144M
A
WPS
BWS1
K
NC/288M
RPS
A
NC/72M
CQ
B
NC
Q9
D9
A
NC
K
BWS0
A
NC
NC
Q8
C
NC
NC
D10
VSS
A
A
A
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
A
A
A
VSS
NC
NC
D1
P
NC
NC
Q17
A
A
C
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
CY7C1414JV18 (1M x 36)
1
2
3
4
5
6
7
8
9
10
11
WPS
BWS2
K
BWS1
RPS
A
NC/144M
CQ
D18
A
BWS3
K
BWS0
A
D17
Q17
Q8
Q28
D19
VSS
A
A
A
VSS
D16
Q7
D8
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
A
A
A
VSS
Q10
D9
D1
P
Q35
D35
Q26
A
A
C
A
A
Q9
D0
Q0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
NC/288M NC/72M
A
CQ
B
Q27
Q18
C
D27
D
E
F
Document #: 001-12561 Rev. *D
Page 5 of 26
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CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Pin Definitions
Pin Name
IO
Pin Description
D[x:0]
InputData Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
Synchronous CY7C1410JV18 - D[7:0]
CY7C1425JV18 - D[8:0]
CY7C1412JV18 - D[17:0]
CY7C1414JV18 - D[35:0]
WPS
InputWrite Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
Nibble Write Select 0, 1 − Active LOW (CY7C1410JV18 Only). Sampled on the rising edge of the K
and K clocks during Write operations. Used to select which nibble is written into the device during the
current portion of the Write operations.Nibbles not written remain unaltered. NWS0 controls D[3:0] and
NWS1 controls D[7:4].
All Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
NWS0,
NWS1
BWS0,
BWS1,
BWS2,
BWS3
InputByte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1425JV18 − BWS0 controls D[8:0]
CY7C1412JV18 − BWS0 controls D[8:0], BWS1 controls D[17:9].
CY7C1414JV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3 controls
D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
InputAddress Inputs. Sampled on the rising edge of the K (Read address) and K (Write address) clocks during
Synchronous active read and write operations. These address inputs are multiplexed for both read and write operations.
Internally, the device is organized as 4M x 8 (2 arrays each of 2M x 8) for CY7C1410JV18, 4M x 9 (2
arrays each of 2M x 9) for CY7C1425JV18, 2M x 18 (2 arrays each of 1M x 18) for CY7C1412JV18 and
1M x 36 (2 arrays each of 512K x 36) for CY7C1414JV18. Therefore, only 21 address inputs are needed
to access the entire memory array of CY7C1410JV18 and CY7C1425JV18, 20 address inputs for
CY7C1412JV18 and 19 address inputs for CY7C1414JV18. These inputs are ignored when the appropriate port is deselected.
Q[x:0]
OutputsData Output Signals. These pins drive out the requested data during a read operation. Valid data is
Synchronous driven out on the rising edge of both the C and C clocks during read operations, or K and K when in single
clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated.
CY7C1410JV18 − Q[7:0]
CY7C1425JV18 − Q[8:0]
CY7C1412JV18 − Q[17:0]
CY7C1414JV18 − Q[35:0]
RPS
InputRead Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tri-stated following the next rising edge of
the C clock. Each read access consists of a burst of two sequential transfers.
C
Input Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 9 for further details.
C
Input Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 9 for further details.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
Document #: 001-12561 Rev. *D
Page 6 of 26
[+] Feedback
CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Pin Definitions
Pin Name
(continued)
IO
Pin Description
CQ
Echo Clock
CQ is Referenced with Respect to C. This is a free - running clock and is synchronized to the Input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks is shown in the Switching Characteristics on page 22.
CQ
Echo Clock
CQ is Referenced with Respect to C. This is a free - running clock and is synchronized to the Input
clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks is shown in the Switching Characteristics on page 22.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timing
in the DLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10-Kohm or less pull up resistor. The device behaves in DDR-I
mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with QDR-I timing.
TDO
Output
TCK
Input
TCK Pin for JTAG.
TDI
Input
TDI Pin for JTAG.
TMS
Input
TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/72M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
VREF
VDD
VSS
VDDQ
InputReference
TDO for JTAG.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Power Supply Power Supply Inputs to the Core of the Device.
Ground
Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Document #: 001-12561 Rev. *D
Page 7 of 26
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CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Functional Overview
The CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, and
CY7C1414JV18 are synchronous pipelined Burst SRAMs with a
read port and a write port. The read port is dedicated to read
operations and the write port is dedicated to write operations.
Data flows into the SRAM through the write port and flows out
through the read port. These devices multiplex the address
inputs to minimize the number of address pins required. By
having separate read and write ports, the QDR-II completely
eliminates the need to “turn-around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of two 8-bit data transfers in the case of
CY7C1410JV18, two 9-bit data transfers in the case of
CY7C1425JV18, two 18-bit data transfers in the case of
CY7C1412JV18, and two 36-bit data transfers in the case of
CY7C1414JV18 in one clock cycle.
This device operates with a read latency of one and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to VSS then the device behaves in QDR-I mode with
a read latency of one clock cycle.
Accesses for both ports are initiated on the rising edge of the
positive input clock (K). All synchronous input timing is
referenced from the rising edge of the input clocks (K and K) and
all output timing is referenced to the rising edge of the output
clocks (C and C, or K and K when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the output clocks (C and C, or K and K when in
single clock mode).
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1412JV18 is described in the following sections. The same
basic descriptions apply to CY7C1410JV18, CY7C1425JV18,
and CY7C1414JV18.
Read Operations
The CY7C1412JV18 is organized internally as two arrays of 1M
x 18. Accesses are completed in a burst of two sequential 18-bit
data words. Read operations are initiated by asserting RPS
active at the rising edge of the positive input clock (K). The
address is latched on the rising edge of the K clock. The address
presented to the address inputs is stored in the read address
register. Following the next K clock rise the corresponding lowest
order 18-bit word of data is driven onto the Q[17:0] using C as the
output timing reference. On the subsequent rising edge of C, the
next 18-bit data word is driven onto the Q[17:0]. The requested
data is valid 0.45 ns from the rising edge of the output clock (C
and C or K and K when in single clock mode).
Synchronous internal circuitry automatically tri-states the outputs
following the next rising edge of the output clocks (C/C). This
allows for a seamless transition between devices without the
insertion of wait states in a depth expanded memory.
Document #: 001-12561 Rev. *D
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise, the data presented to D[17:0] is latched and stored into the
lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D[17:0] is stored into the write data register, provided
BWS[1:0] are both asserted active. The 36 bits of data are then
written into the memory array at the specified location. When
deselected, the write port ignores all inputs after completion of
pending write operations.
Byte Write Operations
Byte write operations are supported by the CY7C1412JV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each 18-bit data word. Asserting
the byte write select input during the data portion of a write
latches the data being presented and writes it into the device.
Deasserting the byte write select input during the data portion of
a write allows the data stored in the device for that byte to remain
unaltered. This feature can be used to simplify read, modify, or
write operations to a byte write operation.
Single Clock Mode
The CY7C1412JV18 can be used with a single clock that
controls both the input and output registers. In this mode, the
device recognizes only a single pair of input clocks (K and K) that
control both the input and output registers. This operation is
identical to the operation if the device had zero skew between
the K/K and C/C clocks. All timing parameters remain the same
in this mode. To use this mode of operation, the user must tie C
and C HIGH at power on. This function is a strap option and not
alterable during device operation.
Concurrent Transactions
The read and write ports on the CY7C1412JV18 operate
independently of one another. As each port latches the address
inputs on different clock edges, the user can read or write to any
location, regardless of the transaction on the other port. The user
can start reads and writes in the same clock cycle. If the ports
access the same location at the same time, the SRAM delivers
the most recent information associated with the specified
address location. This includes forwarding data from a write
cycle that was initiated on the previous K clock rise.
Depth Expansion
The CY7C1412JV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed prior to the device being deselected.
Page 8 of 26
[+] Feedback
CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR-II to simplify data capture
on high-speed systems. Two echo clocks are generated by the
QDR-II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free-running clocks and are
synchronized to the output clock (C/C) of the QDR-II. In single
clock mode, CQ is generated with respect to K and CQ is
generated with respect to K. The timing for the echo clocks is
shown in the Switching Characteristics on page 22.
DLL
These chips utilize a Delay Lock Loop (DLL) that is designed to
function between 120 MHz and the specified maximum clock
frequency. During power up, when the DOFF is tied HIGH, the
DLL is locked after 1024 cycles of stable clock. The DLL can also
be reset by slowing or stopping the input clock K and K for a
minimum of 30 ns. However, it is not necessary to reset the DLL
to lock to the desired frequency. The DLL automatically locks
1024 clock cycles after a stable clock is presented. The DLL may
be disabled by applying ground to the DOFF pin. When the DLL
is turned off, the device behaves in QDR-I mode (with one cycle
latency and a longer access time). For information refer to the
application note DLL Considerations in QDRII/DDRII.
Application Example
Figure 1 shows two QDR-II used in an application.
Figure 1. Application Example
SRAM #1
Vt
R
D
A
R
P
S
#
W
P
S
#
B
W
S
#
ZQ
CQ/CQ#
Q
C C# K K#
DATA IN
DATA OUT
Address
RPS#
BUS
WPS#
MASTER
BWS#
(CPU CLKIN/CLKIN#
or
Source K
ASIC)
Source K#
R = 250ohms
SRAM #2
R
P
S
#
D
A
R
W
P
S
#
B
W
S
#
ZQ R = 250ohms
CQ/CQ#
Q
C C# K K#
Vt
Vt
Delayed K
Delayed K#
R
Document #: 001-12561 Rev. *D
R = 50ohms Vt = Vddq/2
Page 9 of 26
[+] Feedback
CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Truth Table
The truth table for CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, and CY7C1414JV18 follows. [2, 3, 4, 5, 6, 7]
Operation
K
RPS WPS
DQ
DQ
Write Cycle:
Load address on the rising edge of K;
input write data on K and K rising edges.
L-H
X
L
D(A + 0) at K(t) ↑
Read Cycle:
Load address on the rising edge of K;
wait one and a half cycle; read data on C and C rising edges.
L-H
L
X
Q(A + 0) at C(t + 1) ↑ Q(A + 1) at C(t + 2) ↑
NOP: No Operation
L-H
H
H
D=X
Q = High-Z
D=X
Q = High-Z
Stopped
X
X
Previous State
Previous State
Standby: Clock Stopped
D(A + 1) at K(t) ↑
Write Cycle Descriptions
The write cycle description table for CY7C1410JV18 and CY7C1412JV18 follows. [2, 8]
BWS0/ BWS1/
K
K
L
L–H
–
L
L
–
L
H
L–H
L
H
–
H
L
L–H
H
L
–
H
H
L–H
H
H
–
NWS0
NWS1
L
Comments
During the data portion of a write sequence:
CY7C1410JV18 − both nibbles (D[7:0]) are written into the device.
CY7C1412JV18 − both bytes (D[17:0]) are written into the device.
L-H During the data portion of a write sequence:
CY7C1410JV18 − both nibbles (D[7:0]) are written into the device.
CY7C1412JV18 − both bytes (D[17:0]) are written into the device.
–
During the data portion of a write sequence:
CY7C1410JV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1412JV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L–H During the data portion of a write sequence:
CY7C1410JV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C1412JV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
–
During the data portion of a write sequence:
CY7C1410JV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1412JV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L–H During the data portion of a write sequence:
CY7C1410JV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C1412JV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
3. Device powers up deselected with the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst.
5. “t” represents the cycle at which a Read/Write operation is started. t + 1, and t + 2 are the first, and second clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1,BWS0, BWS1,BWS2 and BWS3 can be altered on
different portions of a write cycle, as long as the setup and hold requirements are achieved.
Document #: 001-12561 Rev. *D
Page 10 of 26
[+] Feedback
CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Write Cycle Descriptions
The write cycle description table for CY7C1425JV18 follows. [2, 8]
BWS0
K
K
Comments
L
L–H
–
During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L
–
L–H
During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H
L–H
–
No data is written into the device during this portion of a write operation.
H
–
L–H
No data is written into the device during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C1414JV18 follows. [2, 8]
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L–H
–
During the Data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L
H
H
H
L–H
L
H
H
H
–
H
L
H
H
L–H
H
L
H
H
–
H
H
L
H
L–H
H
H
L
H
–
H
H
H
L
L–H
H
H
H
L
–
H
H
H
H
L–H
H
H
H
H
–
Document #: 001-12561 Rev. *D
L–H During the Data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
–
During the Data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L–H During the Data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
–
During the Data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
L–H During the Data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
–
During the Data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L–H During the Data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
–
During the Data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L–H During the Data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Page 11 of 26
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CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8V IO logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively
be connected to VDD through a pull up resistor. TDO must be left
unconnected. Upon power up, the device comes up in a reset
state, which does not interfere with the operation of the device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see the TAP Controller State
Diagram on page 14. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 15. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The Boundary Scan Order on page 18 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Test Data-Out (TDO)
Identification (ID) Register
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 17).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 17.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document #: 001-12561 Rev. *D
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 17. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Page 12 of 26
[+] Feedback
CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
IDCODE
BYPASS
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is given a
Test-Logic-Reset state.
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is given during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tri-state,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is pre-set LOW to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
Document #: 001-12561 Rev. *D
Page 13 of 26
[+] Feedback
CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [9]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
SELECT
DR-SCAN
1
1
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-DR
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-IR
UPDATE-DR
1
0
0
1
0
Note
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 001-12561 Rev. *D
Page 14 of 26
[+] Feedback
CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
TAP Controller Block Diagram
0
Bypass Register
2
Selection
Circuitry
TDI
1
0
Selection
Circuitry
Instruction Register
31
30
29
.
.
2
1
0
1
0
TDO
Identification Register
108
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics
Over the Operating Range [10, 11, 12]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH = −100 μA
1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 μA
0.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input and Output Load Current
0.65VDD VDD + 0.3
GND ≤ VI ≤ VDD
V
–0.3
0.35VDD
V
–5
5
μA
Notes
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table.
11. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2).
12. All Voltage referenced to Ground.
Document #: 001-12561 Rev. *D
Page 15 of 26
[+] Feedback
CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
TAP AC Switching Characteristics
Over the Operating Range [13, 14]
Parameter
Description
Min
Max
Unit
20
MHz
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
20
ns
tTL
TCK Clock LOW
20
ns
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
50
ns
Setup Times
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
0
ns
ns
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions. [14]
Figure 2. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
1.8V
50Ω
0.9V
TDO
0V
Z0 = 50Ω
(a)
CL = 20 pF
tTH
GND
tTL
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Notes
13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document #: 001-12561 Rev. *D
Page 16 of 26
[+] Feedback
CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Identification Register Definitions
Instruction Field
Value
CY7C1410JV18
CY7C1425JV18
CY7C1412JV18
CY7C1414JV18
001
001
001
001
Revision Number
(31:29)
Description
Version number.
Cypress Device ID 11010011010000111 11010011010001111 11010011010010111 11010011010100111 Defines the type of
(28:12)
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
00000110100
00000110100
00000110100
1
1
1
1
ID Register
Presence (0)
Allows unique
identification of
SRAM vendor.
Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
109
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document #: 001-12561 Rev. *D
Page 17 of 26
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CY7C1412JV18, CY7C1414JV18
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
28
10G
56
6A
84
1J
1
6P
29
9G
57
5B
85
2J
2
6N
30
11F
58
5A
86
3K
3
7P
31
11G
59
4A
87
3J
4
7N
32
9F
60
5C
88
2K
5
7R
33
10F
61
4B
89
1K
6
8R
34
11E
62
3A
90
2L
7
8P
35
10E
63
2A
91
3L
8
9R
36
10D
64
1A
92
1M
9
11P
37
9E
65
2B
93
1L
10
10P
38
10C
66
3B
94
3N
3M
11
10N
39
11D
67
1C
95
12
9P
40
9C
68
1B
96
1N
13
10M
41
9D
69
3D
97
2M
14
11N
42
11B
70
3C
98
3P
15
9M
43
11C
71
1D
99
2N
16
9N
44
9B
72
2C
100
2P
17
11L
45
10B
73
3E
101
1P
18
11M
46
11A
74
2D
102
3R
19
9L
47
10A
75
2E
103
4R
20
10L
48
9A
76
1E
104
4P
21
11K
49
8B
77
2F
105
5P
22
10K
50
7C
78
3F
106
5N
23
9J
51
6C
79
1G
107
5R
24
9K
52
8A
80
1F
108
Internal
25
10J
53
7A
81
3G
26
11J
54
7B
82
2G
27
11H
55
6B
83
1H
Document #: 001-12561 Rev. *D
Page 18 of 26
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CY7C1412JV18, CY7C1414JV18
Power Up Sequence in QDR-II SRAM
QDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations. During
Power Up, when the DOFF is tied HIGH, the DLL gets locked
after 1024 cycles of stable clock.
Power Up Sequence
■
Apply power with DOFF tied HIGH (All other inputs can be
HIGH or LOW)
❐ Apply VDD before VDDQ
❐ Apply VDDQ before VREF or at the same time as VREF
■
Provide stable power and clock (K, K) for 1024 cycles to lock
the DLL.
DLL Constraints
■
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
■
The DLL functions at frequencies down to 120 MHz.
■
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid DLL locking provide 1024 cycles
stable clock to relock to the desired clock frequency.
~
~
Power Up Waveforms
K
K
~
~
Unstable Clock
> 1024 Stable clock
Start Normal
Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
Document #: 001-12561 Rev. *D
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns )
Fix High (or tied to VDDQ)
Page 19 of 26
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CY7C1412JV18, CY7C1414JV18
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V
Latch-up Current ................................................... > 200 mA
Operating Range
Ambient Temperature with Power Applied.... –10°C to +85°C
Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V
Range
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
Commercial
DC Applied to Outputs in High-Z ........ –0.5V to VDDQ + 0.3V
Industrial
DC Input Voltage
[11]
Ambient
Temperature (TA)
VDD [15]
VDDQ [15]
0°C to +70°C
1.8 ± 0.1V
1.4V to
VDD
–40°C to +85°C
.............................. –0.5V to VDD + 0.3V
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range [12]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDQ
IO Supply Voltage
1.4
1.5
VDD
V
VOH
Output HIGH Voltage
Note 16
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
Output LOW Voltage
Note 17
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH Voltage
IOH = −0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
0.2
V
VIH
Input HIGH Voltage
VREF + 0.1
VDDQ + 0.3
V
VIL
Input LOW Voltage
–0.3
VREF – 0.1
V
IX
Input Leakage Current
GND ≤ VI ≤ VDDQ
−5
5
μA
IOZ
Output Leakage Current
GND ≤ VI ≤ VDDQ, Output Disabled
−5
5
μA
VREF
Input Reference Voltage
IDD
VDD Operating Supply
[18]
Typical Value = 0.75V
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
0.68
267MHz
250MHz
ISB1
Automatic Power down
Current
Max VDD,
Both Ports Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC,
Inputs Static
267MHz
250MHz
0.95
V
(x8)
0.75
1330
mA
(x9)
1330
(x18)
1370
(x36)
1460
(x8)
1200
(x9)
1200
(x18)
1230
(x36)
1290
(x8)
375
(x9)
375
(x18)
380
(x36)
385
(x8)
345
(x9)
345
(x18)
350
(x36)
350
mA
mA
mA
Notes
15. Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
16. Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
17. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.
18. VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.
Document #: 001-12561 Rev. *D
Page 20 of 26
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CY7C1412JV18, CY7C1414JV18
AC Electrical Characteristics
Over the Operating Range [11]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIH
Input HIGH Voltage
VREF + 0.2
–
–
V
VIL
Input LOW Voltage
–
–
VREF – 0.2
V
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
Max
Unit
5
pF
Clock Input Capacitance
4
pF
Output Capacitance
5
pF
165 FBGA
Package
Unit
17.2
°C/W
3.2
°C/W
CIN
Input Capacitance
CCLK
CO
Test Conditions
TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
AC Test Loads and Waveforms
VREF = 0.75V
VREF
0.75V
VREF
OUTPUT
Z0 = 50Ω
Device
Under
Test
RL = 50Ω
VREF = 0.75V
ZQ
R = 50Ω
ALL INPUT PULSES
1.25V
0.75V
OUTPUT
Device
Under
Test ZQ
RQ =
250Ω
(a)
0.75V
INCLUDING
JIG AND
SCOPE
5 pF
[19]
0.25V
Slew Rate = 2 V/ns
RQ =
250Ω
(b)
Note
19. Unless otherwise noted, test conditions are based on signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input
pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
Document #: 001-12561 Rev. *D
Page 21 of 26
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CY7C1412JV18, CY7C1414JV18
Switching Characteristics
Over the Operating Range [19, 20]
Cypress Consortium
Parameter Parameter
267 MHz
Description
Min Max Min Max
VDD(Typical) to the first access [21]
tPOWER
250 MHz
1
1
Unit
ms
tCYC
tKHKH
K Clock and C Clock Cycle Time
3.75
8.4
4.0
8.4
ns
tKH
tKHKL
Input Clock (K/K and C/C) HIGH
1.5
–
1.6
–
ns
tKL
tKLKH
Input Clock (K/K and C/C) LOW
1.5
–
1.6
–
ns
tKHKH
tKHKH
K Clock Rise to K Clock Rise and C to C Rise (rising edge to rising edge) 1.68
–
1.8
–
ns
tKHCH
tKHCH
K/K Clock Rise to C/C Clock Rise (rising edge to rising edge)
0
1.68
0
1.8
ns
Setup Times
tSA
tAVKH
Address Setup to K Clock Rise
0.3
–
0.35
–
ns
tSC
tIVKH
Control Setup to K Clock Rise (RPS, WPS)
0.3
–
0.35
–
ns
tSCDDR
tIVKH
DDR Control Setup to Clock (K/K) Rise (BWS0, BWS1, BWS3, BWS4)
0.3
–
0.35
–
ns
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.3
–
0.35
–
ns
Hold Times
tHA
tKHAX
Address Hold after K Clock Rise
0.3
–
0.35
–
ns
tHC
tKHIX
Control Hold after K Clock Rise (RPS, WPS)
0.3
–
0.35
–
ns
tHCDDR
tKHIX
DDR Control Hold after Clock (K/K) Rise (BWS0, BWS1, BWS3,BWS4)
0.3
–
0.35
–
ns
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
0.3
–
0.35
–
ns
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
ns
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
ns
–
0.27
–
0.30
ns
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in Single Clock Mode) to Data Valid
tDOH
tCHQX
Data Output Hold after Output C/C Clock Rise (Active to Active)
tCCQO
tCHCQV
C/C Clock Rise to Echo Clock Valid
tCQOH
tCHCQX
Echo Clock Hold after C/C Clock Rise
tCQD
tCQHQV
Echo Clock High to Data Valid
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
–0.27
–
–0.30
–
ns
tCQH
tCQHCQL
Output Clock (CQ/CQ) HIGH [22]
1.43
–
1.55
–
ns
1.43
–
1.55
–
ns
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
ns
–
0.20
–
0.20
ns
tCQHCQH
tCHZ
tCLZ
tCQHCQH
tCHQZ
tCHQX1
CQ Clock Rise to CQ Clock Rise (rising edge to rising edge)
Clock (C/C) Rise to High-Z (Active to High-Z)
Clock (C/C) Rise to Low-Z
[23, 24]
[23, 24]
[22]
DLL Timing
tKC Var
tKC Var
Clock Phase Jitter
tKC lock
tKC lock
DLL Lock Time (K, C)
1024
–
1024
–
Cycles
tKC Reset
tKC Reset
K Static to DLL Reset
30
–
30
–
ns
Notes
20. When a part with a maximum frequency above 250 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
21. This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD minimum initially before a read or write operation can be initiated.
22. These parameters are extrapolated from the input timing parameters (tKHKH - 250 ps, where 250 ps is the internal jitter. An input jitter of 200 ps (tKC Var) is already
included in the tKHKH). These parameters are only guaranteed by design and are not tested in production.
23. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms on page 21. Transition is measured ± 100 mV from steady
state voltage.
24. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document #: 001-12561 Rev. *D
Page 22 of 26
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CY7C1412JV18, CY7C1414JV18
Switching Waveforms
Figure 3. Read/Write/Deselect Sequence [25, 26, 27]
READ
WRITE
READ
WRITE
READ
WRITE
NOP
WRITE
NOP
1
2
3
4
5
6
7
8
9
10
K
tKH
tKL
tKHKH
tCYC
K
RPS
tSC
t HC
WPS
A
D
A1
A2
tSA tHA
tSA tHA
D11
D30
A0
D10
A3
A4
A5
D31
D50
D51
tSD
Q00
t CLZ
C
tKL
tKH
tKHCH
D60
D61
tSD tHD
tHD
Q
tKHCH
A6
Q01
tDOH
tCO
Q20
Q21
Q41
Q40
tCQDOH
t CHZ
tCQD
t CYC
tKHKH
C
tCQOH
tCCQO
CQ
tCQOH
tCCQO
tCQH
tCQHCQH
CQ
DON’T CARE
UNDEFINED
Notes
25. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.
26. Outputs are disabled (High-Z) one clock cycle after a NOP.
27. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document #: 001-12561 Rev. *D
Page 23 of 26
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CY7C1412JV18, CY7C1414JV18
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or
visit www.cypress.com for actual products offered.
Speed
(MHz)
267
Ordering Code
CY7C1410JV18-267BZC
Package
Diagram
Package Type
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Operating
Range
Commercial
CY7C1425JV18-267BZC
CY7C1412JV18-267BZC
CY7C1414JV18-267BZC
CY7C1410JV18-267BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1425JV18-267BZXC
CY7C1412JV18-267BZXC
CY7C1414JV18-267BZXC
CY7C1410JV18-267BZI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
CY7C1425JV18-267BZI
CY7C1412JV18-267BZI
CY7C1414JV18-267BZI
CY7C1410JV18-267BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1425JV18-267BZXI
CY7C1412JV18-267BZXI
CY7C1414JV18-267BZXI
250
CY7C1410JV18-250BZC
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Commercial
CY7C1425JV18-250BZC
CY7C1412JV18-250BZC
CY7C1414JV18-250BZC
CY7C1410JV18-250BZXC
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1425JV18-250BZXC
CY7C1412JV18-250BZXC
CY7C1414JV18-250BZXC
CY7C1410JV18-250BZI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)
Industrial
CY7C1425JV18-250BZI
CY7C1412JV18-250BZI
CY7C1414JV18-250BZI
CY7C1410JV18-250BZXI
51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free
CY7C1425JV18-250BZXI
CY7C1412JV18-250BZXI
CY7C1414JV18-250BZXI
Document #: 001-12561 Rev. *D
Page 24 of 26
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CY7C1410JV18, CY7C1425JV18
CY7C1412JV18, CY7C1414JV18
Package Diagram
Figure 4. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195
BOTTOM VIEW
TOP VIEW
Ø0.25 M C A B
+0.14
(165X)
-0.06
Ø0.50
1
PIN 1 CORNER
Ø0.05 M C
PIN 1 CORNER
2
3
4
5
6
7
8
9
10
11
11
10
9
8
7
6
5
4
3
2
1
A
B
B
C
C
1.00
A
D
D
F
F
G
G
H
J
14.00
E
17.00±0.10
E
H
J
K
L
L
7.00
K
M
M
N
N
P
P
R
R
A
1.00
5.00
10.00
B
15.00±0.10
0.15 C
0.35±0.06
0.53±0.05
0.25 C
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.65g
JEDEC REFERENCE : MO-216 / DESIGN 4.6C
PACKAGE CODE : BB0AD
SEATING PLANE
Document #: 001-12561 Rev. *D
1.40 MAX.
0.36
C
51-85195-*A
Page 25 of 26
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CY7C1412JV18, CY7C1414JV18
Document History Page
Document Title: CY7C1410JV18/CY7C1425JV18/CY7C1412JV18/CY7C1414JV18, 36-Mbit QDR™-II SRAM 2-Word
Burst Architecture
Document Number: 001-12561
REV.
ECN NO.
ISSUE
DATE
ORIG. OF
CHANGE
**
808457
See ECN
VKN
New Data Sheet
*A
1061960 See ECN
VKN
Removed 300MHz speed bin
*B
1397384 See ECN
VKN
Added 267MHz speed bin
*C
1462587 See ECN VKN/AESA Converted from preliminary to final
Removed 200MHz speed bin
Updated IDD/ISB specs
Changed DLL minimum operating frequency from 80MHz to 120MHz
Changed tCYC max spec to 8.4ns for all speed bins
*D
2189567 See ECN VKN/AESA Minor Change-Moved to the external web
DESCRIPTION OF CHANGE
© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-12561 Rev. *D
Revised March 10, 2007
Page 26 of 26
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
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