ASIX AX88790L 10/100base 3-in-1 pcmcia fast ethernet controller Datasheet

AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
10/100BASE 3-in-1 PCMCIA Fast Ethernet Controller
Document No.: AX790-15 / V1.5 / Jan. 24 ’02
Features
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Highly integrated with embedded 10/100Mbps
MAC, PHY and Transceiver
Compliant
with
IEEE
802.3/802.3u
100BASE-TX/FX specification
Single chip PCMCIA bus 10/100Mbps Fast
Ethernet MAC Controller
Embedded 8K * 16 bit SRAM
NE2000 register level compatible instruction
Compliant with 16 bit PC Card Standard February 1995
Support both 10Mbps and 100Mbps data rate
Support both full-duplex or half-duplex operation
Provides FAX/MODEM interface for COMBO AP
Provides an extra MII port for supporting other
media. For example, Home-LAN application
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Support 128/256 bytes EEPROM (used for saving
CIS)
Support automatic loading of Ethernet ID, CIS and
Adapter Configuration from EEPROM on
power-on initialization
External and internal loop-back capability
Support 3 General Purpose Input pins
Low Power Consumption, typical under 100mA
128-pin LQFP low profile package
0.25 Micron low power CMOS process. 25MHz
Operation, Pure 3.3V operation with 5V I/O
tolerance.
*IEEE is a registered trademark of the Institute of Electrical and Electronic
Engineers, Inc.
*All other trademarks and registered trademark are the property of their
respective holders.
Product description
The AX88790 Fast Ethernet Controller is a high performance and highly integrated PCMCIA bus Ethernet Controller
with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88790 contains a 16 bit PCMCIA
interfaces to host CPU and compliant with PC Card Standard – February 1995. The AX88790 implements both 10Mbps
and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88790 also provides an extra
IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using MII interface,
Home LAN PHY type media can be supported. The AX88790 is built in interface to connect FAX/MODEM chipset with
parallel bus interface.
Typical System Block Diagram
RJ11
RJ45
RJ11
DAA
MAGNETIC
MAGNETIC
MODEM
Home LAN PHY
/TxRx
AX88790 with 10/100 PHY/TxRx
EEPROM
PCMCIA I/F
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
Frist Released Date : Jun/19/2000
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
CONTENTS
1.0 INTRODUCTION .............................................................................................................................................. 5
1.1 GENERAL DESCRIPTION:..................................................................................................................................... 5
1.2 AX88790 BLOCK DIAGRAM: .............................................................................................................................. 5
1.3 AX88790 PIN CONNECTION DIAGRAM ............................................................................................................... 6
2.0 SIGNAL DESCRIPTION ................................................................................................................................... 7
2.1 PCMCIA BUS INTERFACE SIGNALS GROUP ......................................................................................................... 7
2.2 EEPROM SIGNALS GROUP ................................................................................................................................ 8
2.3 MII INTERFACE SIGNALS GROUP.......................................................................................................................... 8
2.4 10/100MBPS TWISTED-PAIR INTERFACE PINS GROUP ........................................................................................... 9
2.5 BUILT-IN PHY LED INDICATOR PINS GROUP ....................................................................................................... 9
2.6 MODEM INTERFACE PINS GROUP.......................................................................................................................... 9
2.7 GENERAL PURPOSE I/O PINS GROUP .................................................................................................................. 10
2.8 MISCELLANEOUS PINS GROUP............................................................................................................................ 11
2.9 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE ................................................................ 12
3.0 MEMORY AND I/O MAPPING...................................................................................................................... 13
3.1 EEPROM MEMORY MAPPING.......................................................................................................................... 13
3.2 ATTRIBUTE MEMORY MAPPING ........................................................................................................................ 13
3.3 I/O MAPPING ................................................................................................................................................... 14
3.4 SRAM MEMORY MAPPING .............................................................................................................................. 14
4.0 REGISTERS OPERATION ............................................................................................................................. 15
4.1 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF LAN........................................................................... 15
4.1.1 Configuration Option Register of LAN (LCOR) Offset 3C0H (Read/Write) ............................................... 16
4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write) ......................................... 17
4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write) ...................................... 17
4.2 PCMCIA FUNCTION CONFIGURATION REGISTER SET OF MODEM .................................................................... 18
4.2.1 Configuration Option Register of MODEM (MCOR) Offset 3E0H (Read/Write)...................................... 18
4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H (Read/Write) ................................. 19
4.2.3 I/O Base Register 0/1 of MODEM (MIOBASE0/1) Offset 3EAH/3ECH (Read/Write) .............................. 19
4.3 MAC CORE REGISTERS.................................................................................................................................... 20
4.3.1 Command Register (CR) Offset 00H (Read/Write) ................................................................................... 22
4.3.2 Interrupt Status Register (ISR) Offset 07H (Read/Write).......................................................................... 22
4.3.3 Interrupt mask register (IMR) Offset 0FH (Write).................................................................................... 23
4.3.4 Data Configuration Register (DCR) Offset 0EH (Write) .......................................................................... 23
4.3.5 Transmit Configuration Register (TCR) Offset 0DH (Write) .................................................................... 23
4.3.6 Transmit Status Register (TSR) Offset 04H (Read)................................................................................... 24
4.3.7 Receive Configuration (RCR) Offset 0CH (Write).................................................................................... 24
4.3.8 Receive Status Register (RSR) Offset 0CH (Read) ................................................................................... 24
4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write)....................................................................................... 24
4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write) ................................................................. 25
4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write) ................................................................. 25
4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)................................................. 25
4.3.13 Test Register (TR) Offset 15H (Write).................................................................................................... 25
4.3.14 Test Register (TR) Offset 15H (Read) .................................................................................................... 25
4.3.15 General Purpose Input Register (GPI) Offset 17H (Read)...................................................................... 26
4.3.16 GPO and Control (GPOC) Offset 17H (Write)....................................................................................... 26
4.4 THE EMBEDDED PHY REGISTERS ..................................................................................................................... 27
4.4.1 MR0 -- Control Register Bit Descriptions................................................................................................. 28
4.4.2 MR1 -- Status Register Bit Descriptions ................................................................................................... 29
4.4.3 MR2, MR3 -- Identification Registers (1 and 2) Bit Descriptions.............................................................. 30
4.4.4 MR4 – Autonegotiation Advertisement Registers Bit Descriptions............................................................ 30
4.4.5 MR5 – Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions................................. 30
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.4.6 MR5 –Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions .......................... 31
4.4.7 MR6 – Autonegotiation Expansion Register Bit Descriptions ................................................................... 31
4.4.8 MR7 –Next Page Transmit Register Bit Descriptions ............................................................................... 32
4.4.9 MR16 – PCS Control Register Bit Descriptions........................................................................................ 32
4.4.10 MR17 –Autonegotiation Register A Bit Descriptions .............................................................................. 33
4.4.11 MR18 –Autonegotiation Register B Bit Descriptions .............................................................................. 33
4.4.12 MR20 –User Defined Register Bit Descriptions...................................................................................... 33
4.4.13 MR21 –RXER Counter Register Bit Descriptions ................................................................................... 34
4.4.14 MR28 –Device-Specific Register 1 (Status Register) Bit Descriptions..................................................... 34
4.4.15 MR29 –Device-Specific Register 2 (100Mbps Control) Bit Descriptions................................................. 35
4.4.16 MR30 –Device-Specific Register 3 (10Mbps Control) Bit Descriptions................................................... 36
4.4.17 MR31 –Device-Specific Register 4 (Quick Status) Bit Descriptions ........................................................ 37
5.0 DEVICE ACCESS FUNCTIONS.................................................................................................................... 38
5.1 PCMCIA INTERFACE ACCESS FUNCTIONS.......................................................................................................... 38
5.1.1 Attribute Memory access function functions. ............................................................................................ 38
5.1.1 I/O access function functions.................................................................................................................... 38
5.2 MII STATION MANAGEMENT FUNCTIONS. ......................................................................................................... 39
6.0 ELECTRICAL SPECIFICATION AND TIMINGS....................................................................................... 40
6.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 40
6.2 GENERAL OPERATION CONDITIONS................................................................................................................... 40
6.3 DC CHARACTERISTICS ..................................................................................................................................... 40
6.4 A.C. TIMING CHARACTERISTICS ....................................................................................................................... 41
6.4.1 XTAL / CLOCK........................................................................................................................................ 41
6.4.2 Reset Timing ............................................................................................................................................ 41
6.4.3 Attribute Memory Read Timing ................................................................................................................ 43
6.4.4 Attribute Memory Write Timing................................................................................................................ 44
6.4.5 I/O Read Timing....................................................................................................................................... 45
6.4.6 I/O Write Timing ...................................................................................................................................... 46
6.4.7 MII Timing............................................................................................................................................... 47
7.0 PACKAGE INFORMATION........................................................................................................................... 48
APPENDIX A: APPLICATION NOTE 1 ............................................................................................................. 49
A.1 USING CRYSTAL 25MHZ ................................................................................................................................. 49
A.2 USING OSCILLATOR 25MHZ ............................................................................................................................ 49
APPENDIX B: POWER CONSUMPTION REFERENCE DATA...................................................................... 50
ERRATA OF AX88790 .......................................................................................................................................... 51
DEMONSTRATION CIRCUIT (A) : AX88790 + HOMEPNA 1M8 PHY.......................................................... 52
DEMONSTRATION CIRCUIT (B) : AX88790 ONLY ....................................................................................... 57
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
FIGURES
FIG - 1 AX88790 BLOCK DIAGRAM ............................................................................................................................. 5
FIG - 2 AX88790 PIN CONNECTION DIAGRAM .............................................................................................................. 6
TABLES
TAB - 1 PCMCIA BUS INTERFACE SIGNALS GROUP ........................................................................................................ 7
TAB - 2 EEPROM BUS INTERFACE SIGNALS GROUP ....................................................................................................... 8
TAB - 3 MII INTERFACE SIGNALS GROUP ....................................................................................................................... 8
TAB - 4 10/100MBPS TWISTED-PAIR INTERFACE PINS GROUP......................................................................................... 9
TAB - 5 BUILT-IN PHY LED INDICATOR PINS GROUP .................................................................................................... 9
TAB - 6 MODEM INTERFACE SIGNALS GROUP ............................................................................................................... 10
TAB – 7 GENERAL PURPOSES I/O PINS GROUP ............................................................................................................. 10
TAB – 8 MISCELLANEOUS PINS GROUP ........................................................................................................................ 11
TAB - 9 POWER ON CONFIGURATION SETUP TABLE ..................................................................................................... 12
TAB – 10 EEPROM MEMORY MAPPING .................................................................................................................... 13
TAB – 11 ATTRIBUTE MEMORY MAPPING................................................................................................................... 13
TAB – 12 I/O ADDRESS MAPPING............................................................................................................................... 14
TAB – 13 LOCAL MEMORY MAPPING.......................................................................................................................... 14
TAB – 14 PCMCIA FUNCTION CONFIGURATION REGISTER MAPPING OF LAN ............................................................. 15
TAB – 15 PCMCIA FUNCTION CONFIGURATION REGISTER MAPPING OF MODEM ...................................................... 18
TAB - 16 PAGE 0 OF MAC CORE REGISTERS MAPPING ................................................................................................ 20
TAB - 17 PAGE 1 OF MAC CORE REGISTERS MAPPING ................................................................................................ 21
TAB – 18 THE EMBEDDED PHY REGISTERS ................................................................................................................ 27
TAB - 19 MII MANAGEMENT FRAME FORMAT ............................................................................................................ 39
TAB - 20 MII MANAGEMENT FRAMES- FIELD DESCRIPTION......................................................................................... 39
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
1.0 Introduction
1.1 General Description:
The AX88790 provides industrial standard NE2000 registers level compatible instruction set. Various drivers are easy
acquired, maintenance and usage with no pain and tears
The AX88790 Fast Ethernet Controller is a high performance and highly integrated PCMCIA bus Ethernet Controller
with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88790 contains a 16 bit PCMCIA
interfaces to host CPU and compliant with PC Card Standard – February 1995. The AX88790 implements both 10Mbps
and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88790 also provides an extra
IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using MII interface,
Home LAN PHY type media can be supported. The AX88790 is also built in interface to connect FAX/MODEM chipset
with parallel bus interface.
The main difference between AX88790 and AX88190 are: 1) Embedded packet buffer memory 2) Built-in 10/100Mbps
PHY/Transceiver 3) Replace memory I/F with PHY/Transceiver I/F. 4) Fix OE# signal synchronous problem 5) Fix
interrupt status can’t always clean up problem of AX88190. 6) Add 3 general-purpose input pins.
AX88790 use 128-pin LQFP low profile package, 25MHz operation, and single 3.3V operation with 5V I/O tolerance.
The ultra low power consumption is an outstanding feature and enlarges the application field. It is suitable for some
power consumption sensitive product like Compact Flash Adapter Card, PDA (Personal Digital Assistant) and Palm size
computer …etc.
1.2 AX88790 Block Diagram:
SMDC
SMDIO
MODEM
I/F
EECS
EECK
EEDI
EEDO
8K* 16 SRAM
and Memory Arbiter
SEEPROM
LOADER I/F
STA
MAC
Core
&
PHY
Remote
DMA
FIFOs
NE2000/GPI
Registers
TPI, TPO
MII I/F
GPI
PCMCIA Interface
Ctl BUS
SA[9:0]
SD[15:0]
Fig - 1 AX88790 Block Diagram
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
1.3 AX88790 Pin Connection Diagram
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
RX_DV
COL
CRS
RX_CLK
RXD[3]
RXD[2]
RXD[1]
RXD[0]
VSS
VSSM
ZVREG
VDDO
VSSO
VSSO
TPOP
TPON
VSSO
VSSA
REXT10
REXT100
VDDA
VSSPD
XTALOUT
LCLK/XTALIN
VDDPD
VSSM
VDDM
VSSA
REXTBS
VDDA
VSSA
TPIN
TPIP
VDDA
VSSA
MDC
MDIO
TEST1
The AX88790 is housed in the 128-pin plastic light quad flat pack. See Fig - 2 AX88790 Pin
Connection Diagram.
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
AX88790
VSS
VSS
I_ACT
I_SPEED
I_LINK
FAST_MODE#
EEPROM_SIZE
VDD
VDDA
VSSA
VSS
VDD
VSS
EECS
EECK
EEDI
EEDO
TEST2
IDDQ
BIST
CLKO25M
VSS
SD[0]
SD[1]
VDD
SD[2]
INPACK#
WAIT#
RESET
SA[0]
SA[1]
SA[2]
SA[3]
SA[4]
SA[5]
SA[6]
SA[7]
SA[8]
VDD
VSS
SA[9]
IREQ#
WE#
IOWR#
IORD#
OE#
CE2#
CE1#
SD[15]
SD[14]
SD[13]
SD[12]
VDD
VSS
SD[11]
SD[10]
SD[9]
SD[8]
SD[7]
VSS
SD[6]
SD[5]
SD[4]
SD[3]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
GPI[0]/LINK
VDD
VSS
GPI[1]/DPX
TX_CLK
TX_EN
TXD[0]
TXD[1]
TXD[2]
TXD[3]
GPI[2]/SPD
VDD
VSS
MDCS#
MINT
MAUDIO
MRIN#
MPWDN
MRESET#
MRDY
IOIS16#
STSCHG#
SPKR#
VDD
VSS
REG#
Fig - 2 AX88790 Pin Connection Diagram
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
2.0 Signal Description
The following terms describe the AX88790 pin-out:
All pin names with the “#” suffix are asserted low.
The following abbreviations are used in following Tables.
I
O
I/O
OD
Input
Output
Input/Output
Open Drain
PU
PD
P
Pull Up
Pull Down
Power Pin
2.1 PCMCIA Bus Interface Signals Group
SIGNAL
SA[9:0]
TYPE
I/PD
IREQ#
O
PIN NO.
15,
12 – 4
23 – 26,
29 – 33,
35 – 39,
41 – 42
16
SD[15:0]
I/O/PD
WAIT#
O
2
REG#
I/PU
128
IORD#
I/PU
19
IOWR#
I/PU
18
OE#
I/PU
20
WE#
I/PU
17
IOIS16#
O
123
INPACK#
O
1
I/PU
22, 21
O
O
124
125
CE1#-CE2#
STSCHG#
SPKR#
DESCRIPTION
System Address: Signals SA[9:0] are address bus input lines which
enable direct address of up to 2K memory and I/O spaces on card.
System Data Bus: Signals SD[15:0] constitute the bi-directional data
bus.
Interrupt Request: IREQ# is asserted to indicate the host system that
the PC Card device requires host software service.
Wait: This signal is set low to insert wait states during Remote DMA
transfer.
Attribute Memory and I/O Space Select: When the REG# signal is
asserted, access is limited to Attribute Memory and to the I/O space.
I/O Read: The host asserts IORD# to read data from AX88790 I/O
space.
I/O Write: The host asserts IOWR# to write data into AX88790 I/O
space.
Output Enable : The OE# line is used to gate Memory Read data from
memory on PC Card
Write Enable: The WE# signal is used for strobing Memory Write
data into the memory on PC Card.
I/O is 16 Bit Port: The IOIS16# is asserted when the address at the
socket corresponds to an I/O address to which the card responds, and
the I/O port addressed is capable of 16-bit access.
Input Port Acknowledge: The signal is asserted when the AX88790 is
selected and can respond to and I/O read cycle at the address on the
address bus.
Card Enable : The CE1# enables even numbered address bytes and
CE2# enables odd numbered address bytes
Battery Voltage Detect 1 / Status Change
Battery Voltage Detect 2 / Audio speaker out
Tab - 1 PCMCIA bus interface signals group
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
2.2 EEPROM Signals Group
SIGNAL
EECS
EECK
EEDI
EEDO
TYPE
O
O/PD
O
I/PU
PIN NO.
51
50
49
48
DESCRIPTION
EEPROM Chip Select: EEPROM chip select signal.
EEPROM Clock: Signal connected to EEPROM clock pin.
EEPROM Data In: Signal connected to EEPROM data input pin.
EEPROM Data Out: Signal connected to EEPROM data output pin.
Tab - 2 EEPROM bus interface signals group
2.3 MII interface signals group
SIGNAL
RXD[3:0]
TYPE
I/PU
CRS
I/PD
RX_DV
I/PD
RX_ER
(Omit)
RX_CLK
I/PU
COL
TX_EN
I/PD
O
TXD[3:0]
O
TX_CLK
I/PU
MDC
O/PU
MDIO
I/O/PU
PIN NO.
98 – 95
DESCRIPTION
Receive Data: RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
100
Carrier Sense: Asynchronous signal CRS is asserted by the PHY when
either transmit or receive medium is non-idle.
102
Receive Data Valid: RX_DV is driven by the PHY synchronously with
respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
No Support Receive Error: RX_ER is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
99
Receive Clock: RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV, RXD[3:0] and
RX_ER signals from the PHY to the MII port.
101
Collision: this signal is driven by PHY when collision is detected.
108
Transmit Enable: TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
112 – 109 Transmit Data: TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
107
Transmit Clock: TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
67
Station Management Data Clock: The timing reference for MDIO. All
data transfers on MDIO are synchronized to the rising edge of this
clock. MDC is a 2.5MHz frequency clock output.
66
Station Management Data Input / Output: Serial data input/output
transfers from/to the PHYs. The transfer protocol conforms to the
IEEE 802.3u MII specification.
Tab - 3 MII interface signals group
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
2.4 10/100Mbps Twisted-Pair Interface pins group
SIGNAL
TPIP
TYPE
I
PIN NO.
70
TPIN
I
71
TPOP
O
88
TPON
O
87
REXT10
I
84
REXT100
I
83
REXTBS
I
74
DESCRIPTION
Received Data. Positive differential received 125M baud MLT3 or
10M baud Manchester data from magnetic.
Fiber-Optic Data Input. Positive differential received 125M baud
pseudo-ECL data from fiber transceiver.
Received Data. Negative differential received 125M baud MLT3 or
10M baud Manchester data from magnetic.
Fiber-Optic Data Input. Negative differential received 125M baud
pseudo-ECL data from fiber transceiver.
Transmit Data. Positive differential transmit 125M baud MLT3 or
10M baud Manchester data to magnetic.
Fiber-Optic Data Output. Positive differential transmit 125M baud
pseudo-ECL compatible data to fiber transceiver.
Transmit Data. Negative differential transmit 125M baud MLT3 or
10M baud Manchester data to magnetic.
Fiber-Optic Data Output. Negative differential transmit 125M baud
pseudo-ECL compatible data to fiber transceiver.
Current Setting 10Mbits/s. An external resistor 20.1k ohm is placed
from this signal to ground to set the 10Mbits/s TP driver transmit
output level.
Current Setting 100Mbits/s. An external resistor 2.49k ohm is placed
from this signal to ground to set the 100Mbits/s TP driver transmit
output level.
External Bias Resistor. Band Gap Reference for the Receive Channel.
Connect this signal to a 24.9k ohm +/- 1 percent resistor to ground.
The parasitic load capacitance should be less than 15 pF.
Tab - 4 10/100Mbps Twisted-Pair Interface pins group
2.5 Built-in PHY LED indicator pins group
SIGNAL
I_ACT
TYPE
O
PIN NO.
62
I_SPEED
O
61
I_LINK
Or
I_LK/ACT
O
60
or
I_FULL/COL
DESCRIPTION
Active Status: When I_OP is logic 1. If there is activity, transmit or
receive, on the line occurred, the output will be driven low for 0.67 sec
and then driven high at least 0.67 sec.
Full-Duplex/Collision Status. When I_OP is logic 0. If this signal is
low, it indicates full-duplex link established, and if it is high, then the
link is in half-duplex mode. When in half-duplex and collision
occurrence, the output will be driven low for 0.67 sec and driven high
at least 0.67 sec.
Speed Status: If this signal is low, it indicates 100Mbps, and if it is
high, then the speed is 10Mbps.
Link Status: When I_OP is logic 1. If this signal is low, it indicates
link, and if it is high, then the link is fail.
Link Status/Active: When I_OP is logic 0. If this signal is low, it
indicates link, and if it is high, then the link is fail. When in link status
and line activity occurrence, the output will be driven low for 0.67 sec
and driven high at least 0.67 sec.
Tab - 5 Built-in PHY LED indicator pins group
2.6 Modem interface pins group
9
ASIX ELECTRONICS CORPORATION
AX88790 L
Signal Name
3-in-1 PCMCIA Fast Ethernet Controller
Type
Pin No.
Description
MRDY
I/PU
122
MRESET#
MDCS#
MPWDN
O
O/PU
O/PU
121
116
120
MINT
I/PD
117
MRIN#
I/PU
119
MAUDIO
I/PU
118
Modem Ready: MRDY low indicates that modem is initializing the
modem after reset signal asserted or the modem is at SLEEP/STOP
mode.
Modem Reset: This signal asserts low to reset the modem chipset.
Modem Chip Select: This signal connected to modem chip select pin.
Modem Power Down: Rockwell modem chipset, this signal asserts
low to let modem chipset into power down mode. AT&T modem
chipset, this signal asserts high to let modem chipset into power down
mode.
Modem Interrupt: This signal driven by modem chipset to active
interrupt.
Ring Input: This signal is driven by DAA’s ring detect circuit. When
a telephone-ringing signal is being received.
Modem Audio: This signal is passed to PCMCIA interface via SPKR.
Tab - 6 Modem interface signals group
2.7 General Purpose I/O pins group
Signal Name
GPI[2]/SPD
GPI[1]/DPX
GPI[0]/LINK
Type
Pin No.
I/PU
I/PU
I/PU
113
106
103
Description
Read register offset 17h bit 6 value reflects this input value.
Read register offset 17h bit 5 value reflects this input value.
Read register offset 17h bit 4 value reflects this input value.
Tab – 7 General Purposes I/O pins group
10
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
2.8 Miscellaneous pins group
SIGNAL
LCLK/XTALIN
TYPE
I
XTALOUT
O
CLKO25M
RESET
O
I/PU
TEST[2:1]
I/PD
IDDQ
BIST
I
I/PD
FAST_MODE#
I/PU
EEPROM_SIZE
I/PU
ZVREG
O
VDD
P
VSS
P
VDDA
P
VSSA
P
VDDM
P
VSSM
P
VDDPD
P
VSSPD
P
VDDO
VSSO
P
P
PIN NO.
79
DESCRIPTION
CMOS Local Clock: Typical a 25Mhz clock, +/- 100 PPM, 40%-60%
duty cycle. The signal not supports 5 Volts tolerance ( See application
note also )
Crystal Oscillator Input: Typical a 25Mhz crystal, +/- 25 PPM can be
connected across XTALIN and XTALOUT.
80
Crystal Oscillator Output: Typical a 25Mhz crystal, +/- 25 PPM can be
connected across XTALIN and XTALOUT. If a single-ended external
clock (LCLK) is connected to XTALIN, the crystal output pin should
be left floating.
44
Clock Output: This clock is source from LCLK/XTALIN.
3
Reset
Reset is active high then place AX88790 into reset mode immediately.
During falling edge the AX88790 loads the power on setting data.
And, after the falling edge the AX88790 loads the EEPROM data.
47, 65
Test Pins : Active high
These pins are just for test mode setting purpose only. Must be pull
down or keep no connection when normal operation.
46
For test only. Must be pulled down at normal operation.
45
For test only. Must be pulled down or keep no connection when normal
operation.
59
FAST_MODE : Active LOW
The pin is just for test mode only. Must be pulled high or keep no
connection when normal operation.
58
EEPROM SIZE = 0: 93C46 type 128 byte EEPROM is used.
EEPROM SIZE = 1: 93C56 type 256 byte EEPROM is used.
92
This sets the common mode voltage for 10Base-T and 100Base-TX
modes. It should be connected to the center tap of the transmit side of
the transformer
13, 27, 40, Power Supply: +3.3V DC.
53, 57, 104,
114, 126
14, 28, 34, Power Supply: +0V DC or Ground.
43, 52, 54,
63, 64, 94,
105,115,
127
56, 69,
Power Supply for Analog Circuit: +3.3V DC.
73, 82
55, 68,
Power Supply for Analog Circuit: +0V DC or Ground.
72, 75, 85,
76
Powers the analog block around the transmit/receive area. This should
be connected to VDDA: +3.3V DC.
77, 93
Powers the analog block around the transmit/receive area. This should
be connected to VSSA: +0V DC or Ground Power.
78
The Phase Detector (or PLL) power. This should be isolated with other
power: +3.3V DC.
81
The Phase Detector (or PLL) power. This should be isolated with other
power: +0V DC or Ground.
91
Power Supply for Transceiver Output Driver: +3.3V DC.
86, 89, 90 Power Supply for Transceiver Output Driver: +0V DC or Ground.
Tab – 8 Miscellaneous pins group
11
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
2.9 Power on configuration setup signals cross reference table
Signal Name
Share with
MPD_SET
MPWDN
PPD_SET
EECK
I_OP
MDCS#
Description
MPD_SET = 0: MPWDN pin active high.
MPD_SET = 1: MPWDN pin active low. (default)
PPD_SET = 0: Internal PHY in normal mode. (default)
PPD_SET = 1: Internal PHY in power down mode.
LED Indicator Option: Selection of LED display mode.
I_OP = 0: I_LK/ACT, I_SPEED and I_FULL/COL LED display mode.
I_OP = 1: I_LINK, I_SPEED and I_ACT LED display mode. (default)
Tab - 9 Power on Configuration Setup Table
12
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
3.0 Memory and I/O Mapping
There are four memories or I/O mapping used in AX88790.
1.
2.
3.
4.
EEPROM Memory Mapping
Attribute Memory Mapping
I/O Mapping
Local Memory Mapping
3.1 EEPROM Memory Mapping
EEPROM OFFSET
00H
01H
02H
03H
04H
05H
06H – 10H
10H – FFH
HIGH BYTE
RESERVED
CFH
NODE-ID1
NODE ID 3
NODE ID 5
CHECKSUM
RESERVED
CIS
LOW BYTE
WORD COUNT
CFL
NODE ID 0
NODE ID 2
NODE ID 4
RESERVED
RESERVED
CIS
Tab – 10 EEPROM Memory Mapping
Note: bit 3 register of LCOR in AX88190 is replaced by bit 0 of CFL in AX88790
Bit 0 of CFL: Enable Power Down mode
This bit is set to 1; the LAN will go into power down mode. At power down mode AX88790 will disable MAC
transmitting and receiving operation. But the host interface will not be affected.
3.2 Attribute Memory Mapping
ATTRIBUTE MEMORY
OFFSET
0000H
03BFH
03C0H
03C2H
03C4H
03C6H
03CAH
03CCH
03CEH
03DFH
03E0H
03E2H
03E4H
03E6H
03EAH
03ECH
03EEH
03FFH
CONTENTS
CIS
LCOR
LCCSR
LIOBASE0
LIOBASE1
RESERVED
MCOR
MCCSR
MIOBASE0
MIOBASE1
RESERVED
Tab – 11 Attribute Memory Mapping
13
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
3.3 I/O Mapping
SYSTEM I/O OFFSET
0000H
001FH
FUNCTION
MAC CORE REGISTER
Tab – 12 I/O Address Mapping
3.4 SRAM Memory Mapping
OFFSET
0000H
03BFH
03C0H
03C2H
03C4H
03C6H
03CAH
03CCH
03CEH
03DFH
03E0H
03E2H
03E4H
03E6H
03EAH
03ECH
03EEH
03FFH
0400H
0401H
0402H
0403H
0404H
0405H
0406H
07FFH
4000H
7FFFH
FUNCTION
CIS *1
LCOR *1
LCCSR *1
LIOBASE0 *1
LIOBASE1 *1
RESERVED
MCOR *1
MCCSR *1
MIOBASE0 *1
MIOBASE1 *1
RESERVED
NODE ID 0
NODE ID 1
NODE ID 2
NODE ID 3
NODE ID 4
NODE ID 5
RESERVED
8K X 16
SRAM BUFFER
Tab – 13 Local Memory Mapping
14
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.0 Registers Operation
There are four register sets in AX88790:
The PCMCIA function configuration registers of LAN.
The PCMCIA function configuration registers of MODEM.
The MAC core register.
The embedded PHY registers.
4.1 PCMCIA Function Configuration Register Set of LAN
REGISTER
LCOR
LCSR
LIOBASE0
LIOBASE1
NAME
CONFIGURATION OPTION REGISTER
CONFIGURATION AND STATUS REGISTER
I/O BASED REGISTER 0
I/O BASED REGISTER 1
OFFSET
3C0H
3C2H
3CAH
3CCH
Tab – 14 PCMCIA Function Configuration Register Mapping of LAN
15
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.1.1 Configuration Option Register of LAN (LCOR) Offset 3C0H (Read/Write)
FIELD
7
6
5:0
R/W/C
DESCRIPTION
R/W Software Reset
Assert this bit will reset the LAN function of AX88790. Return a 0 to this bit will leave the
LAN function of AX88790 in a post-reset state as same as that following hardware reset.
The value of this bit is 0 at power-on.
R/W
Level IRQ
This bit should be set to 1; the AX88790 always generates Level Mode Interrupt.
R/W
Function Configuration Index
These six bits are used to indicate entry of the card configuration table locate in the CIS.
The default value is 0
.
On multifunction PC Card,
Bit 5, Bit 4, Bit 3 : MODEM I/O base registers
Bit 5
Bit 4
Bit 3
LAN I/O base
MODEM I/O base
0
0
0
300H
Decided by MIOBASE registers
0
0
1
320H
2f8H
0
1
0
340H
3e8H
0
1
1
360H
2e8H
1
0
0
380H
Decided by MIOBASE registers
1
0
1
200H
2f8H
1
1
0
220H
3e8H
1
1
1
240H
2e8H
Bit 2 : Enable IREQ# Routing
If bit 0 of LCOR is set to 0, this bit is ignored.
If bit 0 of LCOR is set to 1 and this bit is set to 1, the LAN will generate interrupt request
via IREQ# signal. If this bit is set to 0, the LAN will not generate interrupt request via
IREQ# line.
Bit 1 : Enable Base and Limit Registers
If bit 0 of LCOR is set to 0, this bit is ignored.
If bit 0 of LCOR is set to 1 and this bit is set to 1,only I/O addresses that are qualified by
the Base and Limit registers are passed to LAN function. If this bit is set to 0,all I/O
addresses are passed to LAN function.
Bit 0 : Enable Function
If this bit is set to 0, the LAN function is disabled.
If this bit is set to 1, the LAN function is enabled.
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.1.2 Configuration and Status Register of LAN (LCSR) Offset 3C2H (Read/Write)
FIELD
7:3
2
1
0
R/W/C
DESCRIPTION
Reserved
R/W PPwrDwn : PHY power down setting
While this bit set to 1, AX88790 will force embedded PHY into power down mode. As for
PPWDN is active high or active low. Please refer section 2.9 Power on configuration setup
signal cross-reference table.
Note: The master control of Power Down mode is place on Bit 0 of CFL. If user want to
enable power down mode, must set the relative bit of EEPROM that map to bit 0 of CFL
register to logic 1. When this bit is set to 1, the LAN will go into power down mode. At
power down mode AX88790 will disable MAC transmitting and receiving operation. But
the host interface will not be affected.
R
Intr: Interrupt Request
The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it
is not request interrupt service.
R
IntrAck: Interrupt Acknowledge
This bit will be 0. The Intr will reflect the status of interrupt requesting.
4.1.3 I/O Base Register 0/1 of LAN (LIOBASE0/1) Offset 3CAH/3CCH (Read/Write)
The I/O Base registers (LIOBASE0 and LIOBASE1) determine the base address of the I/O range used to access the
LAN specific registers (MAC Core Registers).
I/O Base Register 0
FIELD
7:0
R/W/C
R/W Base I/O address bit 7 – 0.
DESCRIPTION
I/O Base Register 1
FIELD
7:0
R/W/C
R/W Base I/O address bit 15 – 8.
DESCRIPTION
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.2 PCMCIA Function Configuration Register Set of MODEM
REGISTER
MCOR
MCSR
MIOBASE0
MIOBASE1
NAME
CONFIGURATION OPTION REGISTER
CONFIGURATION AND STATUS REGISTER
I/O BASED REGISTER 0
I/O BASED REGISTER 1
OFFSET
3E0H
3E2H
3EAH
3ECH
Tab – 15 PCMCIA Function Configuration Register Mapping of MODEM
4.2.1 Configuration Option Register of MODEM (MCOR) Offset 3E0H (Read/Write)
FIELD
7
6
5:0
R/W/C
DESCRIPTION
R/W Software Reset
Assert this bit will reset the MODEM function of AX88790. Return a 0 to this bit will
leave the MODEM function of AX88790 in a post-reset state as same as that following
hardware reset. The value of this bit is 0 at power-on.
R/W
Level IRQ
This bit should be set to 1; the AX88790 always generates Level Mode Interrupt.
R/W
Function Configuration Index
These six bits are used to indicate entry of the card configuration table locate in the CIS.
The default value is 0
.
On multifunction PC Card,
Bit 5, Bit4 : Reserved
Bit 3 : MINT route to STSCHG#
If bit 0 of MCOR is set to 0, this bit is ignored.
If both bit 0 and bit 2 of MCOR are set to 1 and this bit is set to 1, the MODEM will route
interrupt request to STSCHG# signal. If this bit is set to 0, the MODEM will generate
interrupt request via IREQ# line.
Bit 2 : MINT route to IREQ# (Enable IREQ# Routing)
If bit 0 of MCOR is set to 0, this bit is ignored.
If bit 0 of MCOR is set to 1 and this bit is set to 1, the MODEM will generate interrupt
request via IREQ# signal. If this bit is set to 0, the MODEM will not generate interrupt
request via IREQ# line.
Bit 1 : Enable Base and Limit Registers
If bit 0 of MCOR is set to 0, this bit is ignored.
If bit 0 of MCOR is set to 1 and this bit is set to 1,only I/O addresses that are qualified
by the Base and Limit registers are passed to MODEM function. If this bit is set to 0,all
I/O addresses are passed to LAN function.
Bit 0 : Enable Function
If this bit is set to 0, the MODEM function is disabled.
If this bit is set to 1, the MODEM function is enabled.
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.2.2 Configuration and Status Register of MODEM (MCSR) Offset 3E2H (Read/Write)
FIELD
7:3
2
1
0
R/W/C
DESCRIPTION
Reserved
R/W MPwrDwn : Modem power down setting
While this bit set to 1, MPWDN pin (pin 116) will be active to force modem chip into power
down mode. As for MPWDN is active high or active low. Please refer section 2.7 Power on
configuration setup signal cross-reference table.
R
Intr: Interrupt Request
The LAN function will set this bit to 1 when it need interrupt service and set it to 0 when it
is not request interrupt service.
R
IntrAck: Interrupt Acknowledge
This bit will be 0. The Intr will reflect the status of interrupt requesting.
4.2.3 I/O Base Register 0/1 of MODEM (MIOBASE0/1) Offset 3EAH/3ECH (Read/Write)
The I/O Base registers (MIOBASE0 and MIOBASE1) determine the base address of the I/O range used to access the
MODEM specific registers.
I/O Base Register 0
FIELD
7:0
R/W/C
R/W Base I/O address bit 7 – 0.
DESCRIPTION
I/O Base Register 1
FIELD
7:0
R/W/C
R/W Base I/O address bit 15 – 8.
DESCRIPTION
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.3 MAC Core Registers
All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS (Page Select) in
the Command Register.
PAGE 0 (PS1=0,PS0=0)
OFFSET
00H
0AH
READ
Command Register
( CR )
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Status Register
( TSR )
Number of Collisions Register
( NCR )
Current Page Register
( CPR )
Interrupt Status Register
( ISR )
Current Remote DMA Address 0
( CRDA0 )
Current Remote DMA Address 1
( CRDA1 )
Reserved
0BH
Reserved
0CH
Receive Status Register
( RSR )
Frame Alignment Errors
( CNTR0 )
CRC Errors
( CNTR1 )
Missed Packet Errors
( CNTR2 )
Data Port
01H
02H
03H
04H
05H
06H
07H
08H
09H
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H - 1EH
1FH
WRITE
Command Register
( CR )
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Page Start Address
( TPSR )
Transmit Byte Count Register 0
( TBCR0 )
Transmit Byte Count Register 1
( TBCR1 )
Interrupt Status Register
( ISR )
Remote Start Address Register 0
( RSAR0 )
Remote Start Address Register 1
( RSAR1 )
Remote Byte Count 0
( RBCR0 )
Remote Byte Count 1
( RBCR1 0
Receive Configuration Register
( RCR )
Transmit Configuration Register ( TCR )
Data Configuration Register
( DCR )
Interrupt Mask Register
( IMR )
Data Port
IFGS1
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
GPI
Reserved
Reset
IFGS1
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
GPOC
Reserved
Reserved
Tab - 16 Page 0 of MAC Core Registers Mapping
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
PAGE 1 (PS1=0,PS0=1)
OFFSET
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H - 1EH
1FH
READ
Command Register
( CR )
Physical Address Register 0
( PARA0 )
Physical Address Register 1
( PARA1 )
Physical Address Register 2
( PARA2 )
Physical Address Register 3
( PARA3 )
Physical Address Register 4
( PARA4 )
Physical Address Register 5
( PARA5 )
Current Page Register
( CPR )
Multicast Address Register 0
( MAR0 )
Multicast Address Register 1
( MAR1 )
Multicast Address Register 2
( MAR2 )
Multicast Address Register 3
( MAR3 )
Multicast Address Register 4
( MAR4 )
Multicast Address Register 5
( MAR5 )
Multicast Address Register 6
( MAR6 )
Multicast Address Register 7
( MAR7 )
Data Port
WRITE
Command Register
( CR )
Physical Address Register 0
( PAR0 )
Physical Address Register 1
( PAR1 )
Physical Address Register 2
( PAR2 )
Physical Address Register 3
( PAR3 )
Physical Address Register 4
( PAR4 )
Physical Address Register 5
( PAR5 )
Current Page Register
( CPR )
Multicast Address Register 0
( MAR0 )
Multicast Address Register 1
( MAR1 )
Multicast Address Register 2
( MAR2 )
Multicast Address Register 3
( MAR3 )
Multicast Address Register 4
( MAR4 )
Multicast Address Register 5
( MAR5 )
Multicast Address Register 6
( MAR6 )
Multicast Address Register 7
( MAR7 )
Data Port
Inter-frame Gap Segment 1
IFGS1
Inter-frame Gap Segment 2
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
GPI
Reserved
Reset
Inter-frame Gap Segment 1
IFGS1
Inter-frame Gap Segment 2
IFGS2
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
GPOC
Reserved
Reserved
Tab - 17 Page 1 of MAC Core Registers Mapping
21
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.3.1 Command Register (CR) Offset 00H (Read/Write)
FIELD
7:6
5:3
2
1
0
NAME
DESCRIPTION
PS1,PS0 PS1,PS0 : Page Select
The two bits selects which register page is to be accessed.
PS1
PS0
0
0
page 0
0
1
page 1
RD2,RD1 RD2,RD1,RD0 : Remote DMA Command
,RD0 These three encoded bits control operation of the Remote DMA channel. RD2 could be set
to abort any Remote DMA command in process. RD2 is reset by AX88790 when a Remote
DMA has been completed. The Remote Byte Count should be cleared when a Remote DMA
has been aborted. The Remote Start Address is not restored to the starting address if the
Remote DMA is aborted.
RD2 RD1 RD0
0
0
0
Not allowed
0
0
1
Remote Read
0
1
0
Remote Write
0
1
1
Not allowed
1
X
X
Abort / Complete Remote DMA
TXP TXP : Transmit Packet
This bit could be set to initiate transmission of a packet
START START :
This bit is used to active AX88790 operation.
STOP STOP : Stop AX88790
This bit is used to stop the AX88790 operation.
4.3.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)
FIELD
7
6
5
4
3
2
1
0
NAME
DESCRIPTION
RST Reset Status :
Set when AX88790 enters reset state and cleared when a start command is issued to the
CR. Writing to this bit is no effect.
RDC Remote DMA Complete
Set when remote DMA operation has been completed
CNT Counter Overflow
Set when MSB of one or more of the Tally Counters has been set.
OVW Over Write: Set when receive buffer ring storage resources have been exhausted.
TXE Transmit Error
Set when packet transmitted with one or more of the following errors
n Excessive collisions
n FIFO Under-run
RXE Receive Error
Indicates that a packet was received with one or more of the following errors
CRC error
Frame Alignment Error
FIFO Overrun
Missed Packet
PTX Packet Transmitted
Indicates packet transmitted with no error
PRX Packet Received
Indicates packet received with no error.
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.3.3 Interrupt mask register (IMR) Offset 0FH (Write)
FIELD
7
6
5
4
3
2
1
0
NAME
RDCE
CNTE
OVWE
TXEE
RXEE
PTXE
PRXE
DESCRIPTION
Reserved
DMA Complete Interrupt Enable. Default “low” disabled.
Counter Overflow Interrupt Enable. Default “low” disabled.
Overwrite Interrupt Enable. Default “low” disabled.
Transmit Error Interrupt Enable. Default “low” disabled.
Receive Error Interrupt Enable. Default “low” disabled.
Packet Transmitted Interrupt Enable. Default “low” disabled.
Packet Received Interrupt Enable. Default “low” disabled.
4.3.4 Data Configuration Register (DCR) Offset 0EH (Write)
FIELD
7
6:2
1
0
NAME
DESCRIPTION
RDCR Remote DMA always completed
Reserved
BOS Byte Order Select
0: MS byte placed on AD15:AD8 and LS byte on AD7-AD0 (80X86).
1: MS byte placed on AD7::AD0 and LS byte on AD15:AD0(68K)
WTS Word Transfer Select
0 : Selects byte-wide DMA transfers.
1 : Selects word-wide DMA transfers.
4.3.5 Transmit Configuration Register (TCR) Offset 0DH (Write)
FIELD
7
6
5
4:3
2:1
0
NAME
DESCRIPTION
FDU Full Duplex :
This bit indicates the current media mode is Full Duplex or not.
0 : Half duplex
1 : Full duplex
PD
Pad Disable
0 : Pad will be added when packet length less than 60.
1 : Pad will not be added when packet length less than 60.
RLO Retry of late collision
0 : Don’t retransmit packet when late collision happens.
1 : Retransmit packet when late collision happens.
Reserved
LB1,LB0 Encoded Loop-back Control
These encoded configuration bits set the type of loop-back that is to be performed.
LB1 LB0
Mode 0
0
0
Normal operation
Mode 1
0
1
Internal NIC loop-back
Mode 2
1
0
PHYcevisor loop-back
CRC Inhibit CRC
0 : CRC appended by transmitter.
1 : CRC inhibited by transmitter.
23
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.3.6 Transmit Status Register (TSR) Offset 04H (Read)
FIELD
7
6:4
3
2
1
0
NAME
DESCRIPTION
OWC Out of window collision
Reserved
ABT Transmit Aborted
Indicates the AX88790 aborted transmission because of excessive collision.
COL Transmit Collided
Indicates that the transmission collided at least once with another station on the network.
Reserved
PTX Packet Transmitted
Indicates transmission without error.
4.3.7 Receive Configuration (RCR) Offset 0CH (Write)
FIELD
7
6
5
4
3
2
1
0
NAME
DESCRIPTION
INT_RG Interrupt Regeneration
0 : Enable interrupt regeneration function in multifunction application. (default) But must
set CIS relative Enable function first, than the function will be open.
1: Disable
Reserved
MON Monitor Mode
0 : Normal Operation
1 : Monitor Mode, the input packet will be checked on NODE ADDRESS and CRC but not
buffered into memory.
PRO PRO : Promiscuous Mode
Enable the receiver to accept all packets with a physical address.
AM
AM : Accept Multicast
Enable the receiver to accept packets with a multicast address. That multicast address must
pass the hashing array.
AB
AB : Accept Broadcast
Enable the receiver to accept broadcast packet.
AR
AR : Accept Runt
Enable the receiver to accept runt packet.
SEP
SEP : Save Error Packet
Enable the receiver to accept and save packets with error.
4.3.8 Receive Status Register (RSR) Offset 0CH (Read)
FIELD
7
6
5
4
3
2
1
0
NAME
DIS
PHY
MPA
FO
FAE
CR
PRX
DESCRIPTION
Reserved
Receiver Disabled
Multicast Address Received.
Missed Packet
FIFO Overrun
Frame alignment error.
CRC error.
Packet Received Intact
4.3.9 Inter-frame gap (IFG) Offset 16H (Read/Write)
FIELD
7
6:0
NAME
DESCRIPTION
Reserved
IFG
Inter-frame Gap. Default value 15H.
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.3.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)
FIELD
7
6:0
NAME
DESCRIPTION
Reserved
IFG
Inter-frame Gap Segment 1. Default value 0cH.
4.3.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)
FIELD
7
6:0
NAME
DESCRIPTION
Reserved
IFG
Inter-frame Gap Segment 2. Default value 12H.
4.3.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)
FIELD
7
6
5
4
3
2
1
0
NAME
DESCRIPTION
EECLK EECLK:
EEPROM Clock
EEO EEO : (Read only)
EEPROM Data Out value. That reflects Pin-48 EEDO value.
EEI
EEI
EEPROM Data In. That output to Pin-49 EEDI as EEPROM data input value.
EECS EECS
EEPROM Chip Select
MDO MDO
MII Data Out
MDI MDI: (Read only)
MII Data In. That reflects Pin-66 MDIO value.
MDIR MII STA MDIO signal Direction
MII Read Control Bit, assert this bit let MDIO signal as the input signal. Deassert this bit
let MDIO as output signal.
MDC MDC
MII Clock
4.3.13 Test Register (TR) Offset 15H (Write)
FIELD
7:5
4
3
2:0
NAME
TF16T
TPE
IFG
DESCRIPTION
Reserved
Test for Collision
Test pin Enable
Select Test Pins Output
4.3.14 Test Register (TR) Offset 15H (Read)
FIELD
7:4
3
2
1
0
NAME
RST_TX
B
RST_10B
RST_B
AUTOD
DESCRIPTION
Reserved
100BASE-TX in Reset: This signal indicates that 100BASE-TX logic of internal PHY is in
reset.
10BASE-T in Reset: This signal indicates that 10BASE-T logic of internal PHY is in reset.
Reset Busy: This signal indicates that internal PHY is in reset.
Autonegotiation Done: This signal goes high whenever internal PHY autonegotiation has
completed. It will go low if autonegotiation has to restart.
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AX88790 L
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4.3.15 General Purpose Input Register (GPI) Offset 17H (Read)
FIELD
7
6
5
4
3
2
1
0
NAME
GPI2
GPI1
GPI0
I_SPD
I_DPX
I_LINK
DESCRIPTION
Reserved
This register reflects GPI[2] input value. May connect to external PHY speed status.
This register reflects GPI[1] input value. May connect to external PHY duplex status.
This register reflects GPI[0] input value. May connect to external PHY link status.
Reserved
This register reflects internal PHY speed status value. Logic one means 100Mbps
This register reflects internal PHY duplex status value. Logic one means full duplex.
This register reflects internal PHY link status value. Logic one means link ok.
4.3.16 GPO and Control (GPOC) Offset 17H (Write)
FIELD
7:6
5
4
3:0
NAME
DESCRIPTION
Reserved
MPSET Media Set by Program: The signal is valid only when MPSEL is set to high.
When MPSET is logic 0, internal PHY is selected.
When MPSET is logic 1, external MII PHY is selected.
MPSEL Media Priority Select :
MPSEL I_LINK
GPI0
Media Selected
0
1
0
Internal PHY
0
1
1
Internal PHY
0
0
0
External MII PHY
0
0
1
Internal PHY
1
X
X
Depend on MPSET bit
Reserved
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ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.4 The Embedded PHY Registers
The MII management 16-bit register set implemented is as follows. And the following sub-section will describes each
field of the registers. The format for the “FIELD” descriptions is as follows: the first number is the register number, the
second number is the bit position in the register and the name of the instantiated pad is in capital letters. The format for
the “TYPE” descriptions is as follows: R = read, W = write, LH = latch high, NA = not applicable.
ADDRESS
0
1
2
3
4
5
6
7
8 - 15
16
17
18
19
20
21
22 - 24
25 - 27
28
29
30
31
NAME
MR0
MR1
MR2
MR3
MR4
MR5
MR6
MR7
MR8 -15
MR16
MR17
MR18
MR19
MR20
MR21
MR22 -24
MR25 -27
MR28
MR29
MR30
MR31
DESCRIPTION
Control
Status
PHY Identifier 1
PHY Identifier 2
Autonegotiation Advertisement
Autonegotiation Link Partner Ability
Autonegotiation Expansion
Next Page Transmit
(Reserved)
PCS Control Register
Autonegotiation (read register A)
Autonegotiation (read register B)
Analog Test Register
User-defined Register
RXER Counter
Analog Test Registers
Analog Test (tuner) Registers
Device Specific 1
Device Specific 2
Device Specific 3
Quick Status Register
DEFAULT(Hex Code)
3000h
7849h
0180h
BB10h
01E1h
0000
0000
0000
0000
0000
0000
0000
2080
0000
-
Tab – 18 The Embedded PHY Registers
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4.4.1 MR0 -- Control Register Bit Descriptions
FIELD
0.15 (SW_RESET)
TYPE
R/W
0.14 (LOOPBACK)
R/W
0.13(SPEED100)
R/W
0.12 (NWAY_ENA)
R/W
0.11 (PWRDN)
R/W
0.10 (ISOLATE)
R/W
0.9 (REDONWAY)
R/W
0.8 (FULL_DUP)
R/W
0.7 (COLTST)
R/W
0.6:0 (RESERVED)
NA
DESCRIPTION
Reset. Setting this bit to a 1 will reset the PHY. All registers will be set to
their default state. This bit is self-clearing. The default is 0.
Loopback. When this bit is set to 1, no data transmission will take place on
the media. Any receive data will be ignored. The loopback signal path will
contain all circuitry up to, but not including, the PMD. The default value is
a 0.
Speed Selection. The value of this bit reflects the current speed of operation
(1 =100 Mbits/s; 0 =10 Mbits/s). This bit will only affect operating speed
when the autonegotiation enable bit (register 0, bit 12) is disabled (0). This
bit is ignored when autonegotiation is enabled (register 0, bit 12). This bit is
ANDed with the SPEED_PIN signal.
Autonegotiation Enable. The autonegotiation process will be enabled by
set-ting this bit to a 1. The default state is a 1.
Powerdown. The PHY may be placed in a low-power state by setting this bit
to a 1, both the 10Mbits/s transceiver and the 100Mbits/s transceiver will be
powered down. While in the powerdown state, the PHY will respond to
management transactions. The default state is a 0.
Isolate. When this bit is set to a 1, the MII outputs will be brought to the
high-impedance state. The default state is a 0.
Restart Autonegotiation. Normally, the autonegotiation process is started
at powerup. Setting this bit to a 1 may restart the process. The default state is
a 0. The NWAYDONE bit (register 1, bit 5) is reset when this bit goes to a
1. This bit is self-cleared when autonegotiation restarts.
Duplex Mode. This bit reflects the mode of operation (1 = full duplex; 0 =
half duplex). This bit is ignored when the autonegotiation enable bit
(register 0, bit 12) is enabled. The default state is a 0. This bit is ORed with
the F_DUP pin.
Collision Test. When this bit is set to a 1, the PHY will assert the MCOL
signal in response to MTX_EN.
Reserved. All bits will read 0.
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4.4.2 MR1 -- Status Register Bit Descriptions
FIELD
1.15 (T4ABLE)
TYPE
R
1.14 (TXFULDUP)
R
1.13 (TXHAFDUP)
R
1.12 (ENFULDUP)
R
1.11 (ENHAFDUP)
R
1.10:7 (RESERVED)
1.6 (NO_PA_OK)
R
R
1.5 (NWAYDONE)
R
1.4 (REM_FLT)
R
1.3 (NWAYABLE)
R
1.2 (LSTAT_OK)
R
1.1 (JABBER)
R
1.0 (EXT_ABLE)
R
DESCRIPTION
100Base-T4 Ability. This bit will always be a 0.
0: Not able.
1: Able.
100Base-TX Full-Duplex Ability. This bit will always be a 1.
0: Not able.
1: Able.
100Base-TX Half-Duplex Ability. This bit will always be a 1.
0: Not able.
1: Able.
10Base-T Full-Duplex Ability. This bit will always be a 1.
0: Not able.
1: Able.
10Base-T Half-Duplex Ability. This bit will always be a 1.
0: Not able.
1: Able.
Reserved. All bits will read as a 0.
Suppress Preamble. When this bit is set to a 1, it indicates that the PHY
accepts management frames with the preamble suppressed.
Autonegotiation Complete. When this bit is a 1, it indicates the
autonegotiation process has been completed. The contents of registers MR4,
MR5, MR6, and MR7 are now valid. The default value is a 0. This bit is reset
when autonegotiation is started.
Remote Fault. When this bit is a 1, it indicates a remote fault has been
detected. This bit will remain set until cleared by reading the register. The
default is a 0.
Autonegotiation Ability. When this bit is a 1, it indicates the ability to
perform autonegotiation. The value of this bit is always a 1.
Link Status. When this bit is a 1, it indicates a valid link has been
established. This bit has a latching function: a link failure will cause the bit
to clear and stay cleared until it has been read via the management interface.
Jabber Detect. This bit will be a 1 whenever a jabber condition is detected.
It will remain set until it is read, and the jabber condition no longer exists.
Extended Capability. This bit indicates that the PHY supports the
extended register set (MR2 and beyond). It will always read a 1.
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4.4.3 MR2, MR3 -- Identification Registers (1 and 2) Bit Descriptions
FIELD
2.15:0 (OUI[3:18])
TYPE
R
3.15:10 (OUI[19:24])
R
3.9:4 (MODEL[5:0])
R
3.3:0 (VERSION[3:0])
R
DESCRIPTION
Organizationally Unique Identifier. The third through the twenty-fourth
bit of the OUI assigned to the PHY manufacturer by the IEEE are to be
placed in bits. 2.15:0 and 3.15:10. This value is programmable.
Organizationally Unique Identifier. The remaining 6 bits of the OUI. The
value for bits 24:19 is programmable.
Model Number. 6-bit model number of the device. The model number is
programmable.
Revision Number. The value of the present revision number. The version
number is programmable.
4.4.4 MR4 – Autonegotiation Advertisement Registers Bit Descriptions
FIELD
4.15 (NEXT_PAGE)
TYPE
R/W
4.14 (ACK)
4.13 (REM_FAULT)
R/W
R/W
4.12:10 (PAUSE)
R/W
4.9 (100BASET4)
4.8 (100BASET_FD)
R/W
R/W
4.7 (100BASETX)
R/W
4.6 (10BASET_FD)
R/W
4.5 (10BASET)
R/W
4.4:0 (SELECT)
R/W
DESCRIPTION
Next Page. Setting this bit to a 1 activates the next page function. This will
allow the exchange of additional data. Data is carried by optional next pages
of information.
Acknowledge. This bit is the acknowledge bit from the link code word.
Remote Fault. When set to 1, the PHY indicates to the link partner a remote
fault condition.
Pause. When set to a 1, it indicates that the PHY wishes to exchange flow
control information with its link partner.
100Base-T4. This bit should always be set to 0.
100Base-TX Full Duplex. If written to 1, autonegotiation will advertise
that the PHY is capable of 100Base-TX full-duplex operation.
100Base-TX. If written to 1, autonegotiation will advertise that the PHY is
capable of 100Base-TX operation.
10Base-T Full Duplex. If written to 1, autonegotiation will advertise that
the PHY is capable of 10Base-T full-duplex operation.
10Base-T. If written to 1, autonegotiation will advertise that the PHY is
capable of 10Base-T operation.
Selector Field. Reset with the value 00001 for IEEE 802.3.
4.4.5 MR5 – Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions
FIELD
5.15
(LP_NEXT_PAGE)
5.14 (LP_ACK)
5.13
(LP_REM_FAULT)
5.12:5
(LP_TECH_ABILITY)
5.4:0 (LP_SELECT)
TYPE
R
R
R
R
R
DESCRIPTION
Link Partner Next Page. When this bit is set to 1, it indicates that the link
partner wishes to engage in next page exchange.
Link Partner Acknowledge. When this bit is set to 1, it indicates that the
link partner has successfully received at least three consecutive and
consistent FLP bursts.
Remote Fault. When this bit is set to 1, it indicates that the link partner has
a fault.
Technology Ability Field. This field contains the technology ability of the
link partner. These bits are similar to the bits defined for the MR4 register
(see Table 16).
Selector Field. This field contains the type of message sent by the link
partner. For IEEE 802.3 compliant link partners, this field should read
00001.
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ASIX ELECTRONICS CORPORATION
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3-in-1 PCMCIA Fast Ethernet Controller
4.4.6 MR5 –Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit
Descriptions
FIELD
5.15
(LP_NEXT_PAGE)
5.14 (LP_ACK)
TYPE
R
5.13
(LP__MES_PAGE)
5.12 (LP_ACK2)
R
5.11 (LP_TOGGLE)
R
5.10:0 (MCF)
R
R
R
DESCRIPTION
Next Page. When this bit is set to logic 0, it indicates that this is the last
page to be transmitted. Logic 1 indicates that additional pages will follow.
Acknowledge. When this bit is set to a logic 1, it indicates that the link
partner has successfully received its partner’s link code word.
Message Page. This bit is used by the NEXT _PAGE function to
differentiate a message page (logic 1) from an unformatted page (logic 0).
Acknowledge 2. This bit is used by the NEXT_PAGE function to indicate
that a device has the ability to comply with the message (logic 1) or not
(logic 0).
Toggle. This bit is used by the arbitration function to ensure
synchroniza-tion with the link partner during next page exchange. Logic 0
indicates that the previous value of the transmitted link code word was logic
1. Logic 1 indicates that the previous value of the transmitted link code word
was logic 0.
Message/Unformatted Code Field. With these 11 bits, there are 2048
possible messages. Message code field definitions are described in annex
28C of the IEEE 802.3u standard.
4.4.7 MR6 – Autonegotiation Expansion Register Bit Descriptions
FIELD
6.15:5 (RESERVED)
6.4
(PAR_DET_FAULT)
6.3
(LP_NEXT_PAGE_AB
LE)
6.2
(NEXT_PAGE_ABLE)
6.1 (PAGE_REC)
6.0
(LP_NWAY_ABLE)
TYPE
R
R/LH
R
R
R/LH
R
DESCRIPTION
Reserved.
Parallel Detection Fault. When this bit is set to 1, it indicates that a fault
has been detected in the parallel detection function. This fault is due to more
than one technology detecting concurrent link conditions. This bit can only
be cleared by reading this register.
Link Partner Next Page Able. When this bit is set to 1, it indicates that the
link partner supports the next page function.
Next Page Able. This bit is set to 1, indicating that this device supports the
NEXT_PAGE function.
Page Received. When this bit is set to 1, it indicates that a NEXT_PAGE
has been received.
Link Partner Autonegotiation Capable. When this bit is set to 1, it
indicates that the link partner is autonegotiation capable.
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4.4.8 MR7 –Next Page Transmit Register Bit Descriptions
FIELD
7.15 (NEXT_PAGE)
TYPE
R/W
7.14 (ACK)
7.13 (MESSAGE)
R
R/W
7.12 (ACK2)
R/W
7.11 (TOGGLE)
7.10:0 (MCF)
R
R/W
DESCRIPTION
Next Page. This bit indicates whether or not this is the last next page to be
transmitted. When this bit is 0, it indicates that this is the last page. When
this bit is 1, it indicates there is an additional next page.
Acknowledge. This bit is the acknowledge bit from the link code word.
Message Page. This bit is used to differentiate a message page from an
unformatted page. When this bit is 0, it indicates an unformatted page.
When this bit is 1, it indicates a formatted page.
Acknowledge 2. This bit is used by the next page function to indicate that a
device has the ability to comply with the message. It is set as follows:
When this bit is 0, it indicates the device cannot comply with the message.
When this bit is 1, it indicates the device will comply with the message.
Toggle. This bit is used by the arbitration function to ensure
synchronization with the link partner during next page exchange. This bit
will always take the opposite value of the toggle bit in the previously
exchanged link code word: If the bit is a logic 0, the previous value of the
transmitted link code word was a logic 1.
If the bit is a 1, the previous value of the transmitted link code word was a 0.
The initial value of the toggle bit in the first next page transmitted is the
inverse of the value of bit 11 in the base link code word, and may assume a
value of 1 or 0.
Message/Unformatted Code Field. With these 11 bits, there are 2048
possible messages. Message code field definitions are described in annex
28C of the IEEE 802.3u standard.
4.4.9 MR16 – PCS Control Register Bit Descriptions
FIELD
16.15 (LOCKED)
16.14-12 (UNUSED)
16.11-4 (TESTBITS)
TYPE
R
R
R/W
16.3 (LOOPBACK)
R/W
16.2 (SCAN)
16.1
(FORCE
LOOPBACK)
16.0 (SPEEDUP
COUNTERS)
R/W
R/W
R/W
DESCRIPTION
Locked. Locked pin from descrambler block.
Unused. Will always be read back as 0.
Generic Test Bits. These bits have no effect on the PCS block. They are for
external use only. A 0 should be written to these bits.
Loopback Configure. When this bit is high, the entire loopback is
performed in the PCS macro. When this bit is low, only the collision pin is
disabled in loopback.
Scan Test Mode.
Force Loopback. Force a loopback without forcing idle on the transmit side
or disabling the collision pin.
Speedup Counters. Reduce link monitor counter to 10 us from 620 us.
(Same as FASTTEST = 1.)
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4.4.10 MR17 –Autonegotiation Register A Bit Descriptions
FIELD
17.15-13
17.12
17.11
17.10
17.9
17.8
17.7
17.6
17.5
17.4
17.3
17.2
17.1
17.0
TYPE
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DESCRIPTION
Reserved. Always 0.
Next Page Wait.
Wait Link_Fail_Inhibit_Wait_Timer (Link Status Check).
Wait Autoneg_Wait_Timer (Link Status Check).
Wait Break_Link_Timer (Transmit Disable).
Parallel Detection Fault.
Autonegotiation Enable.
FLP Link Good Check.
Complete Acknowledge.
Acknowledge Detect.
FLP Link Good.
Link Status Check.
Ability Detect.
Transmit Disable.
4.4.11 MR18 –Autonegotiation Register B Bit Descriptions
18.15
FIELD
TYPE
R
18.14
18.13
18.12
18.11
18.10
18.9
18.8
18.7
18.6
18.5
18.4
18.3
18.2
18.1
18.0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DESCRIPTION
Receiving FLPs. Any of FLP Capture, Clock, Data_0, or Data_1 (FLP
Rcv).
FLP Pass (FLP Rcv).
Link Pulse Count (FLP Rcv).
Link Pulse Detect (FLP Rcv).
Test Pass (NLP Rcv).
Test Fail Count (NLP Rcv).
Test Fail Extend (NLP Rcv).
Wait Max Timer Ack (NLP Rcv).
Detect Freeze (NLP Rcv).
Test Fail (NLP Rcv).
Transmit Count Ack (FLP Xmit).
Transmit Data Bit (FLP Xmit).
Transmit Clock Bit (FLP Xmit).
Transmit ability (FLP Xmit).
Transmit Remaining Acknowledge (FLP Xmit).
Idle (FLP Xmit).
4.4.12 MR20 –User Defined Register Bit Descriptions
FIELD
20.[15:0]
TYPE
R/W
DESCRIPTION
The data written into this user-defined register appears on the
REG20_OUT[15:0] bus.
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4.4.13 MR21 –RXER Counter Register Bit Descriptions
FIELD
21.0
TYPE
W
21.15:0
R
21.7:0
R
21.11:8
R
21.15:12
R
DESCRIPTION
This bit, when 0 puts this register in 16-bit counter mode. When 1, it puts
this register in 8-bit counter mode. This bit is reset to a 0 and cannot be read.
When in 16-bit counter mode, these maintain a count of RXERs. It is reset
on a read operation.
When in 8-bit counter mode, these maintain a count of RXERs. It is reset on
a read operation
When in 8-bit mode, these contain a count of false carrier events (802.3
section 27.3.1.5.1). It is reset on a read operaton.
When in 8-bit mode, these contain a count of disconnect events (Link
Unstable 6, 802.3 section 27.3.1.5.1). It is reset on a read operation.
4.4.14 MR28 –Device-Specific Register 1 (Status Register) Bit Descriptions
FIELD
28.15:9 (UNUSED)
28.8 (BAD_FRM)
TYPE
R
R/LH
28.7 (CODE)
R/LH
28.6 (APS)
R
28.5 (DISCON)
R/LH
28.4 (UNLOCKED)
R/LH
28.3 (RXERR_ST)
R/LH
28.2 (FRC_JAM)
R/LH
28.1 (LNK100UP)
R
28.0 (LNK10UP)
R
DESCRIPTION
Unused. Read as 0.
Bad Frame. If this bit is a 1, it indicates a packet has been received without
an SFD. This bit is only valid in 10Mbits/s mode.
This bit is latching high and will only clear after it has been read or the
device has been reset.
Code Violation. When this bit is a 1, it indicates a Manchester code
violation has occurred. The error code will be output on the MRXD lines.
Refer to Table 1 for a detailed description of the MRXD pin error codes.
This bit is only valid in 10Mbits/s mode.
This bit is latching high and will only clear after it has been read or the
device has been reset.
Autopolarity Status. When register 30, bit 3 is set and this bit is a 1, it
indicates the PHY has detected and corrected a polarity reversal on the
twisted pair.
If the APF_EN bit (register 30, bit 3) is set, the reversal will be corrected
inside the PHY. This bit is not valid in 100Mbits/s operation.
Disconnect. If this bit is a 1, it indicates a disconnect. This bit will latch
high until read. This bit is only valid in 100Mbits/s mode.
Unlocked. Indicates that the TX scrambler lost lock. This bit will latch high
until read. This bit is only valid in 100Mbits/s mode.
RX Error Status. Indicates a false carrier. This bit will latch high until
read. This bit is only valid in 100Mbits/s mode.
Force Jam. This bit will latch high until read. This bit is only valid in
100Mbits/s mode.
Link Up 100. This bit, when set to a 1, indicates a 100Mbits/s transceiver is
up and operational.
Link Up 10. This bit, when set to a 1, indicates a 10Mbits/s transceiver is up
and operational.
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4.4.15 MR29 –Device-Specific Register 2 (100Mbps Control) Bit Descriptions
FIELD
29.15 (LOCALRST)
TYPE
R/W
29.14 (RST1)
29.13 (RST2)
29.12 (100_OFF)
R/W
R/W
R/W
29.11 (LED_BLINK)
R/W
29.10 (CRS_SEL)
R/W
29.9 (LINK_ERR)
R/W
29.8 (PKT_ERR)
R/W
29.7 (PULSE_STR)
R/W
29.6 (EDB)
R/W
29.5 (SAB)
R/W
29.4 (SDB)
R/W
29.3 (CARIN_EN)
R/W
29.2 (JAM_COL)
R/W
29.1 (FEF-EN)
R/W
29.0 (FX)
R/W
DESCRIPTION
Management Reset. This is the local management reset bit. Writing logic 1
to this bit will cause the lower 16 registers and registers 28 and 29 to be reset
to their default values. This bit is self-clearing.
Generic Reset 1. This register is used for manufacture test only.
Generic Reset 2. This register is used for manufacture test only.
100Mbits/s Transmitter Off. When this bit is set to 0, it forces TPI low and
TPIN- high. This bit defaults to 1.
LED Blinking. This register, when 1, enables LED blinking. This is ORed
with LED_BLINK_EN. Default is 0.
Carrier Sense Select. MCRS will be asserted on receive only when this bit
is set to a 1. If this bit is set to logic 0, MCRS will by asserted on receive or
transmit. This bit is ORed with the CRS_SEL pin.
Link Error Indication. When this bit is a 1, a link error code will be
reported on MRXD[3:0] of the PHY when MRX_ER is asserted on the MII.
The specific error codes are listed in the MRXD pin description. If it is 0, it
will disable this function.
Packet Error Indication Enable. When this bit is a 1, a packet error code,
which indicates that the scrambler is not locked, will be reported on
MRXD[3:0] of the PHY when MRX_ER is asserted on the MII. When this
bit is 0, it will disable this function.
Pulse Stretching. When this bit is set to 1, the CS, XS, and RS output
signals will be stretched between approximately 42 ms- 84 ms. If this bit is
0, it will disable this feature. Default state is 0.
Encoder/Decoder Bypass. When this bit is set to 1, the 4B/5B-encoder and
5B/4B-decoder function will be disabled. This bit is ORed with the EDBT
pin.
Symbol Aligner Bypass. When this bit is set to 1, the aligner function will
be disabled.
Scrambler/Descrambler Bypass. When this bit is set to 1, the scrambling/
descrambling functions will be disabled. This bit is ORed with the SDBT
pin.
Carrier Integrity Enable. When this bit is set to a 1, carrier integrity is
enabled. This bit is ORed with the CARIN_EN pin.
Jam Enable. When this bit is a 1, it enables JAM associated with carrier
integrity to be ORed with MCOLMCRS.
Far-End Fault Enable. This bit is used to enable the far-end fault detection
and transmission capability. This capability may only be used if
autonegotiation is disabled. This capability is to be used only with media,
which does not support autonegotiation. Setting this bit to 1 enables far-end
fault detection and logic 0 will disable the function. Default state is 0.
Fiber-Optic Mode. When this bit is a 1, the PHY is in fiber-optic mode.
This bit is ORed with FX_MODE.
35
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.4.16 MR30 –Device-Specific Register 3 (10Mbps Control) Bit Descriptions
FIELD
30.15 (Test10TX)
TYPE
R/W
30.14 (RxPLLEn)
R/W
30.13 (JAB_DIS)
R/W
30.12:7 (UNUSED)
30.6 (LITF_ENH)
R/W
R/W
30.5 (HBT_EN)
R/W
30.4 (ELL_EN)
R/W
30.3 (APF_EN)
R/W
30.2 (RESERVED)
30.1 (SERIAL _SEL)
R/W
R/W
30.0 (ENA_NO_LP)
R/W
DESCRIPTION
When high and 10Base-T is powered up, a continuous 10 MHz signal
(1111) will be transmitted. This is only meant for testing. Default 0.
When high, all 10Base-T logic will be powered up when the link is up.
Otherwise, portions of the logic will be powered down when no data is being
received to conserve power. Default is 0.
Jabber Disable. When this bit is 1, disables the jabber function of the
10Base-T receive. Default is 0.
Unused. Read as 0.
Enhanced Link Integrity Test Function. When high, function is enabled.
This is ORed with the LITF_ENH input. Default is 0.
Heartbeat Enable. When this bit is a 1, the heartbeat function will be
enabled. Valid in 10Mbits/s mode only.
Extended Line Length Enable. When this bit is a 1, the receive squelch
levels are reduced from a nominal 435 mV to 350 mV, allowing reception of
signals with a lower amplitude. Valid in 10Mbits/s mode only.
Autopolarity Function Disable. When this bit is a 0 and the PHY is in
10Mbits/s mode, the autopolarity function will determine if the TP link is
wired with a polarity reversal.
If there is a polarity reversal, the PHY will assert the APS bit (register 28, bit
6) and correct the polarity reversal. If this bit is a 1 and the device is in
10Mbits/s mode, the reversal will not be corrected.
Reserved.
Serial Select. When this bit is set to a 1, 10Mbits/s serial mode will be
Selected. When the PHY is in 100Mbits/s mode, this bit will be ignored.
No Link Pulse Mode. Setting this bit to a 1 will allow 10Mbits/s operation
with link pulses disabled. If the PHY is configured for 100Mbits/s operation,
setting this bit will not affect operation.
36
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
4.4.17 MR31 –Device-Specific Register 4 (Quick Status) Bit Descriptions
FIELD
31.15 (ERROR)
TYPE
R
31.14
(RXERR_ST)/(LINK_ST
AT_CHANGE)
R
31.13 (REM_FLT)
R
31.12
(UNLOCKED)/(JABBE
R)
R
31.11 (LSTAT_OK)
R
31.10 (PAUSE)
R
31.9 (SPEED100)
R
31.8 (FULL_DUP)
R
31.7 (INT_CONF)
R/W
31.6 (INT_MASK)
R/W
31.5:3
(LOW_AUTO__STATE)
R
31.2:0
(HI_AUTO_STATE)
R
DESCRIPTION
Receiver Error. When this bit is a 1, it indicates that a receive error has been
detected. This bit is valid in 100Mbits/s only. This bit will remain set until
cleared by reading the register. Default is a 0.
False Carrier. When bit [31.7] is set to 0 and this bit is a 1, it indicates that the
carrier detect state machine has found a false carrier. This bit is valid in
100Mbits/s only. This bit will remain set until cleared by reading the register.
Default is 0.
Link Status Change. When bit [31.7] is set to a 1, this bit is redefined to become
the LINK_STAT_CHANGE bit and goes high whenever there is a change in link
status (bit [31.11] changes state)
Remote Fault. When this bit is a 1, it indicates a remote fault has been detected.
This bit will remain set until cleared by reading the register. Default is a 0.
Unlocked/Jabber. If this bit is set when operating in 100Mbits/s mode, it
indicates that the TX descrambler has lost lock. If this bit is set when operating
in 10Mbits/s mode, it indicates a jabber condition has been detected. This bit will
remain set until cleared by reading the register.
Link Status. When this bit is a 1, it indicates a valid link has been established.
This bit has a latching low function: a link failure will cause the bit to clear and
stay cleared until it has been read via the management interface.
Link Partner Pause. When this bit is set to a 1, it indicates that the
LU3X54FTL wishes to exchange flow control information.
Link Speed. When this bit is set to a 1, it indicates that the link has negotiated to
100Mbits/s. When this bit is a 0, it indicates that the link is operating at
10Mbits/s.
Duplex Mode. When this bit is set to a 1, it indicates that the link has negotiated
to full-duplex mode. When this bit is a 0, it indicates that the link has negotiated
to half-duplex mode.
Interrupt Configuration. When this bit is set to a 0, it defines bit [31.14] to be
the RXERR_ST bit and the interrupt pin (MASK_STAT_INT) goes high
whenever any of bits [31.15:12] go high, or bit [31.11] goes low. When this bit is
set high, it redefines bit [31.14] to become the LINK_STAT_CHANGE bit, and
the interrupt pin (MASK_STAT_INT) goes high only when the link status
changes (bit [31.14] goes high). This bit defaults to 0.
Interrupt Mask. When set high, no interrupt is generated by this channel under
any condition. When set low, interrupts are generated according to bit [31.7].
Lowest Autonegotiation State. These 3 bits report the state of the lowest
autonegotiation state reached since the last register read, in the priority order
defined below:
000: Autonegotiation enable.
001: Transmit disable or ability detect.
010: Link status check.
011: Acknowledge detect.
100: Complete acknowledge.
101: FLP link good check.
110: Next page wait.
111: FLP link good.
Highest Autonegotiation State. These 3 bits report the state of the highest
autonegotiation state reached since the last register read, as defined above for bit
[31.5:3].
37
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
5.0 Device Access Functions
5.1 PCMCIA interface access functions.
5.1.1 Attribute Memory access function functions.
Attribute Memory Read function
Function Mode
REG#
Standby Mode
X
Byte Access (8 bits)
L
L
Word Access (16 bits)
L
Odd Byte Only Access
L
CE2#
H
H
H
L
L
CE1#
H
L
L
L
H
SA0
X
L
H
X
X
OE#
X
L
L
L
L
WE#
X
H
H
H
H
SD[15:8]
High-Z
High-Z
High-Z
Not Valid
Not Valid
SD[7:0]
High-Z
Even-Byte
Not Valid
Even-Byte
High-Z
Attribute Memory Write function
Function Mode
REG#
Standby Mode
X
Byte Access (8 bits)
L
L
Word Access (16 bits)
L
Odd Byte Only Access
L
CE2#
H
H
H
L
L
CE1#
H
L
L
L
H
SA0
X
L
H
X
X
OE#
X
H
H
H
H
WE#
X
L
L
L
L
SD[15:8]
X
X
X
X
X
SD[7:0]
X
Even-Byte
X
Even-Byte
X
OE#
X
L
L
L
L
L
WE#
X
H
H
H
H
H
SD[15:8]
High-Z
High-Z
High-Z
Odd-Byte
High-Z
Odd-Byte
SD[7:0]
High-Z
Even-Byte
Odd-Byte
Even-Byte
High-Z
High-Z
SD[15:8]
X
X
X
Odd-Byte
X
Odd-Byte
SD[7:0]
X
Even-Byte
Odd-Byte
Even-Byte
X
X
5.1.1 I/O access function functions.
I/O Read function
Function Mode
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
I/O Inhibit
Odd Byte Only Access
I/O Write function
Function Mode
Standby Mode
Byte Access (8 bits)
Word Access (16 bits)
I/O Inhibit
Odd Byte Only Access
REG#
X
L
L
L
H
L
CE2#
H
H
H
L
X
L
CE1#
H
L
L
L
X
H
SA0
X
L
H
L
X
X
REG#
X
L
L
L
H
L
CE2#
H
H
H
L
X
L
CE1#
H
L
L
L
X
H
SA0
X
L
H
L
X
X
38
IORD# IOWR#
X
X
H
L
H
L
H
L
H
L
H
L
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
5.2 MII Station Management functions.
Basic Operation
The primary function of station management is to transfer control and status information about the PHY to a
management entity. This function is accomplished by the MDC clock input from MAC entity, which has a
maximum frequency of 12.5 MHz (for internal PHY only, as to external PHY please refer to the relevant
specification), along with the MDIO signal.
The Internal PHY address is fixed to 10h and the equivalent circuit is shown as below:
From Register
Offset 14h
MDC
(Internal PHY)
MDIO-OUT MDIO-IN
MDC
MDO
Pin66
MDIO
0
Y (MUX)
1
S
MDI
MDIR
Pin67
MDC
If (PHY_ID==10h) then S=1 else S=0
A specific set of registers and their contents (described in Tab-19) defines the nature of the information
transferred across the MDIO interface. Frames transmitted on the MII management interface will have the
frame structure shown in Tab-18. The order of bit transmission is from left to right. Note that reading and
writing the management register must be completed without interruption.
Read/Write
(R/W)
R
W
Pre
ST
OP
PHYAD
REGAD
TA
DATA
IDLE
1. . .1
1. . .1
01
01
10
01
AAAAA
AAAAA
RRRRR
RRRRR
Z0
10
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
Z
Z
Tab - 19 MII Management Frame Format
Field
Pre
ST
OP
PHYADD
REGAD
TA
DATA
IDLE
Descriptions
Preamble. The PHY will accept frames with no preamble. This is indicated by a 1 in register 1, bit 6.
Start of Frame. The start of frame is indicated by a 01 pattern.
Operation Code. The operation code for a read transaction is 10. The operation code for a write
transaction is a 01.
PHY Address. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address
bit transmitted and received is the MSB of the address. A station management entity that is
attached to multiple PHY entities must have prior knowledge of the appropriate PHY address for
each entity.
Register Address. The register address is 5 bits, allowing for 32 unique registers within each PHY. The
first register address bit transmitted and received is the MSB of the address.
Turnaround. The turnaround time is a 2-bit time spacing between the register address field, and
the data field of a frame, to avoid drive contention on MDIO during a read transaction. During a
write to the PHY, these bits are driven to 10 by the station. During a read, the MDIO is not
driven during the first bit time and is driven to a 0 by the PHY during the second bit time.
Data. The data field is 16 bits. The first bit transmitted and received will be bit 15 of the register
being addressed.
Idle Condition. The IDLE condition on MDIO is a high-impedance state. All three state drivers will be
disabled and the PHY’s pull-up resistor will pull the MDIO line to logic 1.
Tab - 20 MII Management Frames- field Description
39
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
6.0 Electrical Specification and Timings
6.1 Absolute Maximum Ratings
Description
SYM
Min
Max
Units
Operating Temperature
Ta
0
+85
°C
Storage Temperature
Ts
-55
+150
°C
Supply Voltage
Vdd
-0.3
+4.6
V
Input Voltage
Vin
-0.3
5.5*
V
Output Voltage
Vout
-0.3
Vdd+0.5
V
Lead Temperature (soldering 10 seconds maximum)
Tl
-55
+220
°C
Note: Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure
to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.
Note: * All digital input signals can sustain 5 Volts input voltage except pin-79 LCLK/XTALIN
6.2 General Operation Conditions
Description
Operating Temperature
Supply Voltage
SYM
Min
Ta
0
Vdd
+3.14
Tpy
25
+3.30
Max
+75
+3.46
Units
°C
V
Max
Units
V
V
V
V
uA
uA
Max
Units
mA
6.3 DC Characteristics
(Vdd=3.3V, Vss=0V, Ta=0°C to 75°C)
Description
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
Input Leakage Current
Output Leakage Current
SYM
Vil
Vih
Vol
Voh
Iil
Iol
Min
1.9
Vdd-0.4
-1
-1
Tpy
0.8
0.4
+1
+1
Description
SYM
Min
Tpy
Power Consumption (3.3V)
SPt3v
87
Note: Please reference “Appendix B: Power Consumption Reference Data”
40
120
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
6.4 A.C. Timing Characteristics
6.4.1 XTAL / CLOCK
Thigh
LCLK/XTALIN
Tr
Tf
Tlow
Tcyc
CLKO
Tod
Description
Symbol
Tcyc
Thigh
Tlow
Tr/Tf
Tod
Min
CYCLE TIME
CLK HIGH TIME
CLK LOW TIME
CLK SLEW RATE
LCLK/XTALIN TO CLKO OUT DELAY
16
16
1
Typ.
40
20
20
10
Max
24
24
4
Units
ns
ns
ns
ns
Typ.
-
Max
-
Units
LClk
6.4.2 Reset Timing
LCLK
RESET
Symbol
Trst
Description
Min
100
Reset pulse width
Note: Some chips may need long power down for successful PHY auto negotiation
Root of cause:
The PHY inside of AX88790 has a special request due to the semiconductor’s process. Namely,
it needs a very long power down for successful Auto Negotiation for some chips. We made a test
in lab and found it would be no problem if the PHY's initial time kept for 2 sec for all chips. If the
power down is less then this number, some of the PHY's Auto Negotiation will not be complete
and there will be potential to cause the link fail. If the auto negotiation time is not long enough,
uncertain numbers of chip may not work properly.
Countermeasure:
Following actions on chip initialization will fix the problem of long auto negotiation.
1. Set the PHY register MR0 with 0x800h (1000,0000,0000) -- bit 11 of MR0 to '1'
(Power down Mode).
2. Wait for 2.5 sec
41
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
3. Set the PHY register MR0 with 0x1200h(0001,0010,0000,0000) -- bit 12,9 of MR0 to
'1' (auto negotiation enable and restart auto negotiation)
42
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
6.4.3 Attribute Memory Read Timing
TcR
Ta(A)
Th(A)
A[9:0], REG#
Ta(CE)
Tsu(CE)
Tv(A)
CE#
Tsu(A)
Ta(OE)
Th(CE)
OE#
Tv(WT-OE)
Tw(WT)
Tdis(CE)
WAIT#
Ten(OE)
Tv(WT)
Tdis(OE)
D[15:0]
Symbol
TcR
Ta(A)
Ta(CE)
Ta(OE)
Tdis(OE)
Ten(OE)
Tv(A)
Tsu(A)
Th(A)
Tsu(CE)
Th(CE)
Tv(WT-OE)
Tw(WT)
Tv(WT)
DATA Valid
Description
Min
300
0.5
0
30
20
0
20
100
READ CYCLE TIME
ADDRESS ACCESS TIME
CARD ENABLE ACCESS TIME
OUTPUT ENABLE ACCESS TIME
OUTPUT DISABLE TIME FROM OE#
OUTPUT ENABLE TIME FROM OE#
DATA VALID FROM ADDRESS CHANGE
ADDRESS SETUP TIME
ADDRESS HOLD TIME
CARD ENABLE SETUP TIME
CARD ENABLE HOLD TIME
WAIT# VALID FROM OE#
WAIT# PULSE WIDTH
DATA SETUP FOR WAIT# RELEASED
43
Typ.
-
Max
120
100
100
100
10
200
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
6.4.4 Attribute Memory Write Timing
TcW
A[9:0], REG#
Tsu(CE-WEH)
CE#
Tsu(CE)
Tsu(A-WEH)
Th(CE)
OE#
Tsu(A)
Tw(WE)
Trec(WE)
WE#
Tv(WT-WE)
Tw(WT)
Tv(WT)
Th(OE-WE)
WAIT#
Tsu(OE-WE)
Tsu(D-WEH)
D[15:0](Din)
Th(D)
DATA Input Establish
Tdis(WE)
Tdis(OE)
Ten(OE)
Ten(WE)
D[15:0](Dout)
Symbol
TcW
Tw(WE)
Tsu(A)
Tsu(A-WEH)
Tsu(CE-WEH)
Tsu(D-WEH)
Th(D)
Trec(WE)
Tdis(WE)
Tdis(OE)
Ten(WE)
Ten(OE)
Tsu(OE-WE)
Th(OE-WE)
Tsu(CE)
Th(CE)
Tv(WT-WE)
Tw(WT)
Tv(WT)
Description
WRITE CYCLE TIME
WRITE PULSE WIDTH
ADDRESS SETUP TIME
ADDRESS SETUP TIME FOR WE#
CARD ENABLE SETUP TIME FOR WE#
DATA SETUP TIME FOR WE#
DATA HOLD TIME
WRITE RECOVER TIME
OUTPUT DISABLE TIME FROM WE#
OUTPUT DISABLE TIME FROM OE#
OUTPUT ENABLE TIME FROM WE#
OUTPUT ENABLE TIME FROM OE#
OUTPUT ENABLE SETUP TIME FROM OE#
OUTPUT ENABLE HOLD TIME FROM OE#
CARD ENABLE SETUP TIME
CARD ENABLE HOLD TIME
WAIT# VALID FROM WE#
WAIT# PULSE WIDTH
WE# HIGH FROM WAIT# RELEASED
44
Min
250
150
30
180
180
80
30
30
5
5
10
10
0
20
0
Typ.
-
Max
5
5
15
200
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
6.4.5 I/O Read Timing
A[9:0]
TsuREG
ThA
ThREG
TsuCE
ThCE
REG#
CE#
Tw
IORD#
TsuA
TdrINPACK
INPACK#
TdfINPACK
TdrIOIS16
IOIS16#
TdfIOIS16
Td
Tdr(WT)
WAIT#
TdfWT
Tw(WT)
D[15:0]
Symbol
Td
Th
Tw
TsuA
ThA
TsuCE
ThCE
TsuREG
ThREG
TdfINPACK
TdrINPACK
TdfIOIS16
TdrIOIS16
TdfWT
Tdr(WT)
Tw(WT)
Th
DATA Valid
Description
Min
0.5
165
70
20
5
20
5
0
0
-
DATA DELAY AFTER IORD#
DATA HOLD FOLLOWING IORD#
IORD# WIDTH TIME
ADDRESS SETUP BEFORE IORD#
ADDRESS HOLD BEFORE IORD#
CE# SETUP BEFORE IORD#
CE# HOLD BEFORE IORD#
REG# SETUP BEFORE IORD#
REG# HOLD BEFORE IORD#
INPACK# DELAY FALLING FROM IORD#
INPACK# DELAY RISING FROM IORD#
IOIS16# DELAY FALLING FROM ADDRESS*
IOIS16# DELAY RISING FROM ADDRESS*
WAIT# DELAY FALLING FROM IORD#
DATA DELAY FROM WAIT# RISING
WAIT# WIDTH TIME
Typ.
-
Max
50
10
10
10
0
5
0
100
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
* Note : The address includes REG# and CE1# signal
45
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
6.4.6 I/O Write Timing
A[9:0]
TsuREG
ThA
ThREG
TsuCE
ThCE
REG#
CE#
Tw
IOWR#
TsuA
TdrIOIS16
IOIS16#
TdfIOIS16
TdrIOWR
WAIT#
TdfWT
Tw(WT)
Th
Tsu
D[15:0]
Symbol
Tsu
Th
Tw
TsuA
ThA
TsuCE
ThCE
TsuREG
ThREG
TdfIOIS16
TdrIOIS16
TdfWT
Tw(WT)
TdrIOWR
DATA
Description
Min
60
30
165
70
20
5
20
5
0
0
DATA SETUP BEFORE IOWR#
DATA HOLD FOLLOWING IOWR#
IOWR# WIDTH TIME
ADDRESS SETUP BEFORE IOWR#
ADDRESS HOLD BEFORE IOWR#
CE# SETUP BEFORE IOWR#
CE# HOLD BEFORE IOWR#
REG# SETUP BEFORE IOWR#
REG# HOLD BEFORE IOWR#
IOIS16# DELAY FALLING FROM ADDRESS*
IOIS16# DELAY RISING FROM ADDRESS*
WAIT# DELAY FALLING FROM IOWR#
WAIT# WIDTH TIME
IOWR# HIGH FROM WAIT# HIGH
Typ.
-
Max
10
0
**
**
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
*Note : The address includes REG# and CE1# signal
** Note : There is no wait state while I/O Write operation
46
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
6.4.7 MII Timing
Ttclk
Ttch
Ttcl
TXCLK
Ttv
Tth
TXD<3:0>
TXEN
Trclk
Trch
Trcl
RXCLK
Trs
Trh
RXD<3:0>
RXDV
Trs1
RXER
Symbol
Ttclk
Ttclk
Ttch
Ttch
Trch
Trch
Ttv
Tth
Trclk
Trclk
Trch
Trch
Trcl
Trcl
Trs
Trh
Trs1
Description
Min
14
140
14
140
5
14
140
14
140
6
10
10
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
Clock to data valid
Data output hold time
Cycle time(100Mbps)
Cycle time(10Mbps)
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
data setup time
data hold time
RXER data setup time
47
Typ.
40
400
40
400
-
Max
26
260
26
260
20
26
260
26
260
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
7.0 Package Information
He
A
A2
A1
L
L1
D
Hd
E
pin 1
e
b
θ
SYMBOL
MILIMETER
MIN.
NOM
MAX
A1
0.05
0.1
0.15
A2
1.35
1.40
1.45
A
1.6
b
0.17
0.22
0.27
D
13.90
14.00
14.10
E
19.90
20.00
20.10
e
0.5
Hd
15.60
16.00
16.40
He
21.00
22.00
23.00
L
0.45
0.60
0.75
L1
θ
1.00
0°
7°
48
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
Appendix A: Application Note 1
A.1 Using Crystal 25MHz
AX88790
CLKO25M
25MHz
XTALIN
XTALOUT
25MHz
Crystal
33pf
33pf
Note: The capacitors (33pf) may be various depend on the specification of crystal. While designing,
please refer to the suggest circuit provided by crystal supplier.
A.2 Using Oscillator 25MHz
AX88790
CLKO25M
XTALIN
3.3V Power OSC
25MHz
XTALOUT
NC
25MHz
49
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
Appendix B: Power Consumption Reference Data
The following reference data of power consumption are measured base on prime application, that is AX88790 +
EEPROM + 74LV04, at 3.3V/25 °C room temperature.
Note: 74LV04 is used for LEDs buffer or driver. Designer may omit the part and drive LED directly by AX88790.
Item
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Test Conditions
Power save mode ( Power Down register bit set to “1” asserted)
Idel without Link
Idel with 10M Link
Idel with 100M Link
Full traffic with 10Mbps at half-duplex mode
Full traffic with 10Mbps at full-duplex mode
Full traffic with 100Mbps at half-duplex mode
Full traffic with 100Mbps at full-duplex mode
Power save mode ( Power Down register bit set to “1” asserted) no LED drive
Idel without Link, no LED drive
Idel with 10M Link, no LED drive
Idel with 100M Link, no LED drive
Full traffic with 10Mbps at half-duplex mode, no LED drive
Full traffic with 10Mbps at full-duplex mode, no LED drive
Full traffic with 100Mbps at half-duplex mode, no LED drive
Full traffic with 100Mbps at full-duplex mode, no LED drive
50
Typical Value Units
3
mA
16
mA
22
mA
80
mA
37 – 69
mA
31 – 57
mA
83
mA
87
mA
0
mA
12
mA
15
mA
74
mA
40 – 68
mA
35 – 60
mA
76
mA
76
mA
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
Errata of AX88790
1. MII Station Management functions have some differences from previous target
specification.
Description: The target specification is using station management can access both
internal PHY registers and external PHY registers when the PHY address is matched
as describe in section 5.2. Anyway, this version can only access the current selected
PHY’s registers. How do you know which is the selected media or PHY? Please refer
to section 4.3.16 GPO and Control (GPOC) register.
Solution: The defect will not affect single media application that is using embedded
PHY. When using MII interface connects to external media (for example HomePNA)
to come out with combo solution. Care must be taken, be sure which media is the
current selected when you access PHY registers.
51
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
IREQ#
IOIS16#
WAIT#
INPACK#
SPKR#
STSCHG#
CE1#
OE#
WE#
CE2#
IORD#
IOWR#
RESET
REG#
Demonstration Circuit (A) : AX88790 + HomePNA 1M8 PHY
AX88790 10BASE-T/100BASE-TX & 1M HomePNA Application
with NS83851 PHYceiver.(reference only)
IREQ#
IOIS16#
WAIT#
INPACK#
SPKR#
STSCHG#
CE1#
OE#
WE#
CE2#
IORD#
IOWR#
RESET
REG#
SD[0..15]
SA[0..9]
3.3V
GND
3.3V
GND
U4
GND
SD3
SD4
SD5
SD6
SD7
CE1#
OE#
SA9
SA8
WE#
IREQ#
VDD
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
SD0
SD1
SD2
IOIS16#
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GND
CD1#
D11
D12
D13
D14
D15
CE2#
VS1#
IORD#
IOWR#
A17
A18
A19
A20
A21
VCC
VPP2
A22
A23
A24
A25
VS2#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
D8
D9
D10
CD2#
GND
GND
D3
D4
D5
D6
D7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
IREQ#
VCC
VPP1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
IOIS16#
GND
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GND
GND
SD11
SD12
SD13
SD14
SD15
CE2#
R33
IORD#
IOWR#
1k
*1
R33 : 3.3V card tpye be used.
VDD
VDD
C33
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
SD8
SD9
SD10
GND
GND
0.01u
GND
PCMCIA
PCMCIA 168 pin
U6
VDD
3
+ C14
C47
0.01u
IN
TAB/OUT
OUT
ADJ/GND
4
2
1
3.3V
+ C11
C42
0.01u
LT1117A
GND
4.7uF/16V
ASIX ELECTRONICS CORPORATION
Title
PCMCIA INTERFACE
4.7uF/16V
Size
A4
Date:
52
Document Number
Rev
1.1
790NS2A.SCH
Monday, July 10, 2000
Sheet
1
of
5
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
RESET#
SA[0..9]
SD[0..15]
U3
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
CE1#
OE#
WE#
IREQ#
IOIS16#
CE2#
IORD#
IOWR#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
CE1#
OE#
WE#
CE2#
IORD#
IOWR#
RESET
REG#
CE1#
OE#
WE#
CE2#
IORD#
IOWR#
RESET
REG#
IREQ#
IOIS16#
WAIT#
INPACK#
SPKR#
STSCHG#
IREQ#
IOIS16#
WAIT#
INPACK#
SPKR#
STSCHG#
3.3V
GND
3.3V
GND
VCC
3.3V
GND
+
C20
C4
0.01u
4
5
6
7
8
9
10
11
12
15
42
41
39
38
37
36
35
33
32
31
30
29
26
25
24
23
22
20
17
16
123
21
19
18
3
2
1
128
125
124
4.7uF/16V
3.3V
C32
C41
C23
C40
0.01u
0.01u
0.01u
0.01u
14
28
34
43
52
54
63
64
94
105
115
127
GND
56
69
73
82
76
L1
3.3V
0.01u
GND
RXD0
RXD1
RXD2
RXD3
RX_CLK
CRS
COL
RX_DV
TX_CLK
TX_EN
TXD0
TXD1
TXD2
TXD3
MDIO
MDC
GPI0/LINK
GPI1/DPX
GPI2/SPD
CLKO25M
LCLK/XTALIN
XTALOUT
PPD_SET
F.B.
1206
+
C3
C19
0.01u
C22
0.01u
C30
55
68
72
75
85
77
93
0.01u
4.7uF/16V
EECS
EECK
EEDI
EEDO
ZVREG
TPOP
TPON
TPIP
TPIN
LNK_LED
ACT_LED
13
27
40
53
57
104
114
126
C18
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
CE1#
OE#
WE#
IREQ#
IOIS16#
CE2#
IORD#
IOWR#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDA
VDDA
VDDA
VDDA
VDDM
LNK/ACT_LED
SPDDELED
FULL/COL_LED
REXTBS
REXT100
REXT10
BIST
IDDQ
TEST2
FAST_MODE#
TEST1
EEPROM_SIZE
LED_OP
MPD_SET
MDCS#
MINT
MAUDIO
MRIN#
MPWDN
MRESET#
MRDY
RXD0
RXD1
RXD2
RXD3
RXCK
CRS
COL
RXDV
TXCK
TXEN
TXD0
TXD1
TXD2
TXD3
MDIO
MDC
TXEN
TXD0
TXD1
TXD2
TXD3
XIN
XOUT
92
88
87
ZVREG
TPOP
TPON
70
71
TPIP
TPIN
10K
R25
20
ZVREG
TPOP
TPON
R20
10K
45
46
47
59
65
58
116
117
118
119
120
121
122
PCLK
TPIP
TPIN
ZVREG
TPOP
TPON
*2
60
61
62
74
83
84
PCLK
TPIP
TPIN
44
EECS
EESK
EEDI
EEDO
MDC
MDIO
PCLK
R34
51
50
49
48
TXEN
TXD0
TXD1
TXD2
TXD3
MDC
MDIO
103
106
113
79
80
RXER
RXDV
COL
CRS
RXCLK
RXD0
RXD1
RXD2
RXD3
TXCLK
U1A
1
74LV04
2
R17
330
U1C
5
74LV04
6
R13
330
U1E
11
74LV04
10
R16
330
R30
R31
R32
24.9K
2.49K
20.1K
R22
10K
SPDLED
Y1
10K
R37
10K
C49
0.1u
FULLED
25MHZ CRYSTAL
XIN
R19
3.3V
LNKLED
U1B
3
74LV04
4
U1D
9
74LV04
8
U1F
13
74LV04
12
XOUT
3.3V
C27
33p
C29
33p
*3
RESET#
L4
VDDO
VSSO
VSSO
VSSO
3.3V
91
90
89
86
C31
C37
0.01u
0.01u
F.B.
1206
+ C9
4.7uF/16V
C10
0.01u
U2
EECS
EESK
EEDI
EEDO
1
2
3
4
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
3.3V
GND
C21
0.1u
93C56
L2
VDDPD
VSSA
VSSA
VSSA
VSSA
VSSA
VSSM
VSSM
95
96
97
98
99
100
101
102
107
108
109
110
111
112
66
67
RESET#
RXER
RXDV
COL
CRS
RXCK
RXD0
RXD1
RXD2
RXD3
TXCK
VSSPD
3.3V
78
81
C28
C7
0.01u
0.01u
+ C6
F.B.
1206
4.7uF/16V
C5
0.01u
AX88790
*2
*3
Pin
Pin
Pin
Pin
Pin
Pin
50 PPD_SET = 0
50 PPD_SET = 1
58 EEPROM SIZE
58 EEPROM SIZE
116 I_OP = 0 :
116 I_OP = 1 :
: Internal PHY in normal mode.(default)
: Internal PHY in power down mode.(match up CIS)
= 0 : 93C46 type 256 byte EEPROM is used.
= 1 : 93C56 type 512 byte EEPROM is used. (default)
LNK/ACT & FULL/COL LED Display be used.
LNK & ACT LED Display be used.
ASIX ELECTRONICS CORPORATION
Title
AX88790
Size
A3
Date:
53
Document Number
Rev
1.1
790NS2A1.SCH
Monday, July 10, 2000
Sheet
2
of
5
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
TIP
RING
HACTLED
HCOLLED
HSPDLED
TIP
RING
HACTLED
HCOLLED
HSPDLED
RESET#
RESET#
RXER
RXDV
COL
CRS
RXCK
RXD0
RXD1
RXD2
RXD3
TXCK
RXER
RXDV
COL
CRS
RXCLK
RXD0
RXD1
RXD2
RXD3
TXCLK
R7
TXCK
TXEN
TXD0
TXD1
TXD2
TXD3
TXEN
TXD0
TXD1
TXD2
TXD3
R8
20
R5
U5
36
35
34
33
32
31
RXD3
RXD2
RXD1
RXD0
RXDV
23
24
25
26
27
28
COL
CRS
37
38
MDIO
MDC
21
22
RXCK
MDC
MDIO
MDC
MDIO
20
TXD3
TXD2
TXD1
TXD0
TXEN
2K
3.3V
PCLK
PCLK
PCLK
3.3V
GND
3.3V
GND
3.3V
3.3V
C15
+
C48
0.1u
C46
0.1u
C44
0.1u
C39
45
46
19
29
39
0.1u
TXD3
TXD2
TXD1
TXD0/TXD
TX_EN
TX_CLK
RXD3/PHYAD0
RXD2/CMDDIS#
RXD1/HI_POWER_EN#
RXD0/RXD/LOW_SPEED_EN#
RX_DV/GPSI_SEL#
RX_CLK
ACTLED
R43
330
HACTLED
COLLED
R41
330
HCOLLED
SPDLED
R39
330
HSPDLED
Set PHY address to 00001.
TIP
COL/MDIO_INT_EN#
CRS/PIN_INTRP_EN#
RING
MDIO
MDC
RBIAS
7
8
RXD3
R6
4.7K
ACTLED
R44
4.7K
COLLED
R42
4.7K
SPDLED
R40
4.7K
PWRLED
R4
4.7K
3.3V
TIP
RING
4
X1
X2
GND
R45
9.31K
1%
IO_VDD1
IO_VDD2
CORE_VDD
GND
3.3VA1
4.7uF/16V
3.3VA2
48
5
11
ANA_VDD1
ANA_VDD2
ANA_VDD3
L3
LED_SPEED/PHYAD3
LED_POWER/PHYAD4
3.3V
C34
F.B.
1206
0.1u
C35
C38
0.1u
0.1u
20
30
GND
40
41
L5
3.3V
C36
0.1u
GND
F.B.
1206
C43
C45
0.1u
0.1u
LED_COL/PHYAD2
LED_ACT/PHYAD1
47
3
6
10
1
2
9
RESET#
17
18
COLLED
ACTLED
16
15
SPDLED
PWRLED
44
RESET#
IO_GND1
IO_GND2
CORE_GND
CORE_SUB(0V)
ANA_GND1
ANA_GND2
ANA_GND3
ANA_GND4
SUB_GND1
SUB_GND2
SUB_GND3
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
12
13
14
42
43
DP83851C
ASIX ELECTRONICS CORPORATION
Title
DP83851B
Size
A4
Date:
54
Document Number
Rev
1.1
790NS2A2.SCH
Monday, July 10, 2000
Sheet
3
of
5
ASIX ELECTRONICS CORPORATION
AX88790 L
ZVREG
TPOP
TPON
TPIP
TPIN
LNKLED
SPDLED
FULLED
TIP
RING
HSPDLED
HCOLLED
HACTLED
3.3V
GND
3-in-1 PCMCIA Fast Ethernet Controller
ZVREG
TPOP
TPON
3.3V
TPIP
TPIN
C8
0.1u
LNKLED
SPDLED
FULLED
R3
49.9
R2
49.9
T2
TIP
RING
TIP
4
RING
6
HSPDLED
HCOLLED
HACTLED
1
2
3.3V
GND
C13
P0800SA
D0-214AA
TUT+
TIP+
TUT-
RING-
Z+
C+
Z-
C-
11
LTIP
9
LRING
14
C12
0.01u/2KV
13
LHR002
*4 1CT : 1CT
J5
R12
0
RXRX+
HACTLED
ZVREG
*5 RECEIVE 1CT : 1CT
TRANSMIT 1CT : 1CT
C2
+
C17
0.1u
R14
49.9
HCOLLED
FULLED
LNKLED
HSPDLED
R15
49.9
T1
SPDLED
LTIP
LRING
GND
TXTX+
10uF/16V
6
7
8
TPOP
TPON
TPIP
TPIN
1
2
3
R28
49.9
R29
49.9
C26
0.1u
C25
0.001u
CT
TD+
TD-
CT
TX+
TX-
RD+
RDCT
RX+
RXCT
11
10
9
16
15
14
TX+
TXRX+
RX-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PCMCIA15
16ST0009P
R11
75
C24
0.01u
C16
R10
75
R26
75
R27
75
C1
0.01u/2KV
0.01u
CHASSIS
R9
1M
ASIX ELECTRONICS CORPORATION
Title
16ST009P & LHR002
Size
A4
Date:
55
Document Number
790NS2A3.SCH
Monday, July 10, 2000
Rev
1.1
Sheet
4
of
5
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
J1
D1
1
2
3
4
5
6
7
8
HACTLED
HCOLLED
HSPDLED
GND
R45
R78
LTIP
LRING
HCOLLED
BLINK : Collision
J4
LTIP
LRING
1
2
3
4
5
6
NC
A1
TIP
RING
A2
NC
LED
Link
Activity
LED
RJ11-S
CON8
ON
:
BLINK :
D3
HACTLED
D4
HSPDLED
ON :
1M
OFF : 0.7M
LED
J3
1
2
3
4
5
6
7
8
FULLED
LNKLED
SPDLED
GND
RXRX+
TXTX+
D2
CON8
J2
TX+
TXRX+
RXR45
R78
FULLED
1
2
3
6
Full DPX
Activity
D5
LNKLED
ON : Link OK
OFF : Link fail
LED
4
5
7
8
ON
:
BLINK :
LED
D6
SPDLED
ON : 100M
OFF : 10M
LED
RJ45N
ASIX ELECTRONICS CORPORATION
Title
RJ45 / RJ11 CONNECT & LED
Size
A4
Date:
56
Document Number
Rev
1.1
790NS2A4.SCH
Monday, July 10, 2000
Sheet
5
of
5
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
Demonstration Circuit (B) : AX88790 Only
IREQ#
IOIS16#
WAIT#
INPACK#
SPKR#
STSCHG#
CE1#
OE#
WE#
CE2#
IORD#
IOWR#
RESET
REG#
AX88790 10BASE-T/100BASE-TX Application. (reference only)
IREQ#
IOIS16#
WAIT#
INPACK#
SPKR#
STSCHG#
CE1#
OE#
WE#
CE2#
IORD#
IOWR#
RESET
REG#
SD[0..15]
SA[0..9]
3.3V
GND
3.3V
GND
U4
GND
SD3
SD4
SD5
SD6
SD7
CE1#
OE#
SA9
SA8
WE#
IREQ#
VDD
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
SD0
SD1
SD2
IOIS16#
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GND
D3
D4
D5
D6
D7
CE1#
A10
OE#
A11
A9
A8
A13
A14
WE#
IREQ#
VCC
VPP1
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
IOIS16#
GND
GND
CD1#
D11
D12
D13
D14
D15
CE2#
VS1#
IORD#
IOWR#
A17
A18
A19
A20
A21
VCC
VPP2
A22
A23
A24
A25
VS2#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
D8
D9
D10
CD2#
GND
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GND
GND
SD11
SD12
SD13
SD14
SD15
CE2#
R33
IORD#
IOWR#
1k
*1
R33 : 3.3V card tpye be used.
VDD
VDD
C33
0.01u
GND
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
SD8
SD9
SD10
GND
GND
PCMCIA
PCMCIA 168 pin
U6
VDD
3
+ C14
C47
0.01u
IN
TAB/OUT
OUT
ADJ/GND
4
2
1
3.3V
+ C11
C42
0.01u
LT1117A
GND
4.7uF/16V
ASIX ELECTRONICS CORPORATION
Title
PCMCIA INTERFACE
4.7uF/16V
Size
A4
Date:
57
Document Number
Rev
1.1
790TX1A.SCH
Monday , July 10, 2000
Sheet
1
of
4
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
SA[0..9]
SD[0..15]
U3
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
CE1#
OE#
WE#
IREQ#
IOIS16#
CE2#
IORD#
IOWR#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
CE1#
OE#
WE#
CE2#
IORD#
IOWR#
RESET
REG#
CE1#
OE#
WE#
CE2#
IORD#
IOWR#
RESET
REG#
IREQ#
IOIS16#
WAIT#
INPACK#
SPKR#
STSCHG#
IREQ#
IOIS16#
WAIT#
INPACK#
SPKR#
STSCHG#
3.3V
GND
3.3V
GND
4
5
6
7
8
9
10
11
12
15
42
41
39
38
37
36
35
33
32
31
30
29
26
25
24
23
22
20
17
16
123
21
19
18
3
2
1
128
125
124
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
CE1#
OE#
WE#
IREQ#
IOIS16#
CE2#
IORD#
IOWR#
RESET
WAIT#
INPACK#
REG#
SPKR#
STSCHG#
RXD0
RXD1
RXD2
RXD3
RX_CLK
CRS
COL
RX_DV
TX_CLK
TX_EN
TXD0
TXD1
TXD2
TXD3
MDIO
MDC
GPI0/LINK
GPI1/DPX
GPI2/SPD
CLKO25M
LCLK/XTALIN
XTALOUT
PPD_SET
ZVREG
TPOP
TPON
TPIP
TPIN
LNK_LED
ACT_LED
13
27
40
53
57
104
114
126
3.3V
C32
C41
C23
C40
0.01u
0.01u
0.01u
0.01u
14
28
34
43
52
54
63
64
94
105
115
127
GND
56
69
73
82
76
L1
3.3V
C18 F.B.
0.01u
+
C3
C19
0.01u
C22
0.01u
C30
55
68
72
75
85
77
93
0.01u
GND
10uF/16V
1206
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDA
VDDA
VDDA
VDDA
VDDM
EECS
EECK
EEDI
EEDO
LNK/ACT_LED
SPDDELED
FULL/COL_LED
REXTBS
REXT100
REXT10
BIST
IDDQ
TEST2
FAST_MODE#
TEST1
EEPROM_SIZE
LED_OP
MDCS#
MINT
MAUDIO
MRIN#
MPD_SET
MPWDN
MRESET#
MRDY
TPIP
TPIN
103
106
113
44
79
80
XIN
XOUT
51
50
49
48
EECS
EESK
EEDI
EEDO
92
88
87
ZVREG
TPOP
TPON
70
71
TPIP
TPIN
ZVREG
TPOP
TPON
R20
10K
3.3V
*2
U1B
3
TPIP
TPIN
U1C
5
60
61
62
U1A
1
74
83
84
45
46
47
59
65
58
R30
R31
R32
24.9K
2.49K
20.1K
R22
10K
74LV04
4
74LV04
6
74LV04
2
R40
330
R17
330
R39
330
R13
330
R38
330
R16
330
3.3V
Y1
10K
R37
10K
LNKLED
C48
0.1u
SPDLED
FULLED
*3
25MHZ CRYSTAL
XIN
R19
ZVREG
TPOP
TPON
XOUT
R1
2M
3.3V
116
117
118
119
120
121
122
C27
20p
C29
20p
*4
U1D
9
74LV04
8
U1E
11
74LV04
10
U1F
13
74LV04
12
RESET#
L4
VDDO
VSSO
VSSO
VSSO
3.3V
91
90
89
86
C31
C37
0.01u
0.01u
F.B.
1206
+ C9
4.7uF/16V
C10
0.01u
L2
VDDPD
VSSA
VSSA
VSSA
VSSA
VSSA
VSSM
VSSM
95
96
97
98
99
100
101
102
107
108
109
110
111
112
66
67
VSSPD
U2
3.3V
78
81
C28
C7
0.01u
0.01u
+ C6
F.B.
1206
4.7uF/16V
EECS
EESK
EEDI
EEDO
C5
1
2
3
4
0.01u
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
3.3V
GND
C21
0.1u
93C56
AX88790
*2
*3
*4
Pin
Pin
LED
LED
Pin
Pin
Pin
Pin
50 PPD_SET = 0 : Internal PHY in normal mode.(default)
50 PPD_SET = 1 : Internal PHY in power down mode.(match up CIS)
Low Activity : R40,R39,R38 be used.
High Activity : R17,R13,R16,U1 be used.
58 EEPROM SIZE = 0 : 93C46 type 256 byte EEPROM is used.
58 EEPROM SIZE = 1 : 93C56 type 512 byte EEPROM is used. (default)
116 I_OP = 0 : LNK/ACT & FULL/COL LED Display be used.
116 I_OP = 1 : LNK & ACT LED Display be used.
ASIX ELECTRONICS CORPORATION
Title
AX88790
Size
A3
Date:
58
Document Number
Rev
1.2
790TX1A1.SCH
Thursday, August 31, 2000
Sheet
2
of
4
ASIX ELECTRONICS CORPORATION
AX88790 L
ZVREG
TPOP
TPON
TPIP
TPIN
LNKLED
SPDLED
FULLED
3.3V
GND
3-in-1 PCMCIA Fast Ethernet Controller
ZVREG
TPOP
TPON
TPIP
TPIN
LNKLED
SPDLED
FULLED
*5
R41 : LED Low Activity be used.
R41
0
3.3V_Out
GND
J5
ZVREG
RXRX+
*6 RECEIVE 1CT : 1CT
TRANSMIT 1CT : 1CT
3.3V_Out
FULLED
LNKLED
C2
+
C17
0.1u
R14
49.9
R15
49.9
T1
SPDLED
10uF/16V
6
7
8
TPOP
TPON
TPIP
TPIN
1
2
3
R28
49.9
R29
49.9
C26
0.1u
C25
0.001u
CT
TX+
TX-
CT
TD+
TDRD+
RDCT
RX+
RXCT
11
10
9
16
15
14
TX+
TX-
GND
TXTX+
RX+
RX-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PCMCIA15
16ST0009P
R11
75
C24
0.01u
C16
0.01u
C50
0.01u
R10
75
R42
75
R43
75
C1
0.01u/2KV
CHASSIS
ASIX ELECTRONICS CORPORATION
Title
16ST009P
Size
A4
Date:
59
Document Number
790TX1A2.SCH
Monday, July 10, 2000
Rev
1.1
Sheet
3
of
4
ASIX ELECTRONICS CORPORATION
AX88790 L
3-in-1 PCMCIA Fast Ethernet Controller
J1
1
2
3
4
5
6
7
8
GND
R45
R78
CON8
D2
J3
1
2
3
4
5
6
7
8
CON8
FULLED
LNKLED
SPDLED
GND
RXRX+
TXTX+
RX+
RXR45
R78
ON
:
BLINK :
FULLED
J2
TX+
TX-
1
2
Full DPX
Activity
LED
D5
3
6
LNKLED
ON : Link OK
OFF : Link fail
LED
4
5
D6
SPDLED
7
8
ON : 100M
OFF : 10M
LED
RJ45N
ASIX ELECTRONICS CORPORATION
Title
RJ45 CONNECT & LED
Size
A4
Date:
60
Document Number
Rev
1.1
790TX1A3.SCH
Monday, July 10, 2000
Sheet
4
of
4
ASIX ELECTRONICS CORPORATION