ATMEL AT91R40008 At91 arm thumb microcontroller Datasheet

Features
• Incorporates the ARM7TDMI® ARM® Thumb® Processor Core
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– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Little-endian
– EmbeddedICE™ (In-circuit Emulation)
8-, 16- and 32-bit Read and Write Support
256K Bytes of On-chip SRAM
– 32-bit Data Bus
– Single-clock Cycle Access
Fully-programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to Eight Chip Selects
– Software Programmable 8/16-bit External Data Bus
Eight-level Priority, Individually Maskable, Vectored Interrupt Controller
– Four External Interrupts, Including a High-priority, Low-latency Interrupt Request
32 Programmable I/O Lines
Three-channel 16-bit Timer/Counter
– Three External Clock Inputs
– Two Multi-purpose I/O Pins per Channel
Two USARTs
– Two Dedicated Peripheral Data Controller (PDC) Channels per USART
Programmable Watchdog Timer
Advanced Power-saving Features
– CPU and Peripheral Can be Deactivated Individually
Fully Static Operation
– 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85°C
2.7V to 3.6V I/O Operating Range
1.65V to 1.95V Core Operating Range
Available in 100-lead TQFP Package
-40° C to +85° C Temperature Range
AT91
ARM® Thumb®
Microcontrollers
AT91R40008
Electrical
Characteristics
1. Description
The AT91R40008 microcontroller is a member of the Atmel AT91 16-/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a
high-performance, 32-bit RISC architecture with a high-density, 16-bit instruction set
and very low power consumption. Furthermore, it features 256K bytes of on-chip
SRAM and a large number of internally banked registers, resulting in very fast exception handling, and making the device ideal for real-time control applications.
The AT91R40008 microcontroller features a direct connection to off-chip memory,
including Flash, through the fully-programmable External Bus Interface (EBI). An
8-level priority vectored interrupt controller, in conjunction with the Peripheral Data
Controller, significantly improves the real-time performance of the device.
The device is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with a large, on-chip, high-speed SRAM and a
wide range of peripheral functions on a monolithic chip, the AT91R40008 is a powerful
microcontroller that offers a flexible and high-performance solution to many computeintensive embedded control applications.
1795E–ATARM–12-Dec-05
2. Absolute Maximum Ratings*
Operating Temperature (Industrial) .. -40° C to + 85° C
Storage Temperature...................... -60° C to + 150° C
Voltage on Any Input Pin with Respect to Ground
..................................................-0.3V to max of VDDIO
.......................................................... + 0.3V and 3.6V
*NOTICE:
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or other conditions
beyond those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Maximum Operating Voltage (VDDIO) ....................3.6V
Maximum Operating Voltage (VDDCORE) .............1.95V
2
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1795E–ATARM–12-Dec-05
AT91R40008
3. DC Characteristics
The following characteristics are applicable to the Operating Temperature range: TA = -40° C to +85° C, unless otherwise
specified and are certified for a Junction Temperature up to 100° C.
Table 3-1.
DC Characteristics
Symbol
Parameter
VDDIO
DC Supply I/Os
VDDCORE
Max
Units
2.7
3.6
V
DC Supply Core
1.65
1.95
V
VIL
Input Low Voltage
-0.3
0.8
V
VIH
Input High Voltage
2.0
VDDIO + 0
.3
V
Pin Group 1(2): IOL = 16 mA(1)
0.4
V
Pin Group 2(3): IOL = 8 mA(1)
0.4
V
0.4
V
0.2
V
VOL
Output Low Voltage
Conditions
Min
(4)
Typ
(1)
Pin Group 3 : IOL = 2 mA
(1)
All Output Pins: IOL = 0 mA
(2)
Pin Group 1 : IOH = 16 mA
VOH
Output High Voltage
(1)
VDDIO - 0.4
Pin Group 2(3): IOH = 8 mA(1)
(4)
VDDIO - 0.4
(1)
Pin Group 3 : IOH = 2 mA
VDDIO - 0.4
(1)
All Output Pins: IOH = 0 mA
ILEAK
Input Leakage Current
IPULL
Input Pull-up Current
IOUT
Output Current
VDDIO - 0.2
10
µA
VDDIO = 3.6V, VIN = 0V
280
µA
Pin Group 1(2)
16
mA
(3)
8
mA
(4)
2
mA
5.3
pF
TA = 25° C
120
µA
TA = 85° C
2.3
mA
Pin Group 2 :
Pin Group 3 :
CIN
ISC
Notes:
V
Input Capacitance
TQFP100 Package
Static Current
VDDIO= 3.6V, VDDCORE = 1.95V,
MCKI = 0Hz
All Inputs Driven
TMS, TCK, TDI, NRST = 1
1. IOL = Output Current at low level. IOH= Output Current at high level.
2. Pin Group 1 = NUB/NWR1, NWE/NWR0, NOE/NRD1
3. Pin Group 2 = D0-D15, A0/NLB, A1-A19, P28/A20/CS7, P29/A21/CS6, P30/A22/CS5, P31/A23/CS4,
NCS0, NCS1, P26/NCS2, P27/NCS3
4. Pin Group 3 = All Others
3
1795E–ATARM–12-Dec-05
4. Power Consumption
The values in the following tables are values measured in the typical operating conditions (i.e.,
VDDIO = 3.3V, VDDCORE = 1.8V, TA = 25° C) on the AT91EB40A Evaluation Board and are given
as demonstrative values.
Table 4-1.
Mode
Power Consumption
Conditions
Consumption
Reset
Unit
0.02
Normal
Fetch in ARM mode from internal SRAM
All peripheral clocks activated
0.83
Fetch in ARM mode from internal SRAM
All peripheral clocks deactivated
0.73
Fetch in ARM mode from external SRAM(1)
All peripheral clocks deactivated
0.20
Fetch in Thumb mode from external SRAM(1)
All peripheral clocks deactivated
0.24
All peripheral clocks activated
0.16
All peripheral clocks deactivated
0.06
mW/MHz
Idle
Note:
1. With two Wait States.
Table 4-2.
Power Consumption per Peripheral
Peripheral
Consumption
PIO Controller
15.3
Timer/Counter Channel
15.0
Timer/Counter Block (3 Channels)
36.3
USART
27.8
Unit
µW/MHz
4.1
4.1.1
Thermal and Reliability Considerations
Thermal Data
In Table 4-3, the device lifetime is estimated with the MIL-217 standard in the “moderately
controlled” environmental model (this model is described as corresponding to an installation in
a permanent rack with adequate cooling air), depending on the device Junction Temperature.
(For details see the section ”Junction Temperature” on page 5.)
Note that the user must be extremely cautious with this MTBF calculation: as the MIL-217
model is pessimistic with respect to observed values due to the way the data/models are
obtained (test under severe conditions). The life test results that have been measured are
always better than the predicted ones.
4
AT91R40008
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AT91R40008
Table 4-3.
MTBF Versus Junction Temperature
Junction Temperature (TJ) (°C)
Estimated Lifetime (MTBF) (Year)
100
10
125
5
150
3
175
2
Table 4-4 summarizes the thermal resistance data related to the package of interest.
Table 4-4.
4.1.2
Thermal Resistance Data
Symbol
Parameter
θJA
Junction-to-ambient thermal resistance
θJC
Junction-to-case thermal resistance
Condition
Package
Typ
Still Air
TQFP100
40
TQFP100
6.4
Unit
°C/W
Reliability Data
The number of gates and the device die size are provided for the user to calculate reliability
data with another standard and/or in another environmental model.
Table 4-5.
Reliability Data
Parameter
Data
Unit
Number of Logic Gates
280
K gates
12,897
K gates
21.2
mm2
Number of Memory Gates
Device Die Size
4.2
Junction Temperature
The average chip-junction temperature TJ in °C can be obtained from the following:
1.
T J = T A + ( P D × θ JA )
2.
T J = T A + ( P D × ( θ HEATSINK + θ JC ) )
Where:
• θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 4-4 on
page 5.
• θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in
Table 4-4 on page 5.
• θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet.
• PD = device power consumption (W) estimated from data provided in the section ”Power
Consumption” on page 4.
• TA = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and thereby
decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the
second equation should be used to compute the resulting average chip-junction temperature
TJ in °C
5
1795E–ATARM–12-Dec-05
5. Conditions
5.1
Timing Results
The delays are given as typical values in the following conditions:
• VDDIO = 3.0V
• VDDCORE = 1.8V
• Ambient Temperature = 25° C
• Load Capacitance = 0 pF
• The output level change detection is 0.5 x VDDIO
• The input level is 0.8V for a low-level detection and is 2.0V for a high level detection.
The minimum and maximum values given in the AC characteristic tables of this datasheet take
into account the process variation and the design.
In order to obtain the timing for other conditions, the following equation should be used:
t = δT° × ⎛ ( δVDDCORE × t DATASHEET ) + ⎛ δVDDIO ×
⎝
⎝
∑( CSIGNAL × δCSIGNAL )⎞⎠ ⎞⎠
Where:
• δT° is the derating factor in temperature given in Figure 5-1.
• δVDDCORE is the derating factor for the Core Power Supply given in Figure 5-2 on page 7.
• tDATASHEET is the minimum or maximum timing value given in this datasheet for a load
capacitance of 0 pF.
• δVDDIO is the derating factor for the I/O Power Supply given in Figure 5-3 on page 8.
• CSIGNAL is the capacitance load on the considered output pin.(1)
• δCSIGNAL is the load derating factor depending on the capacitance load on the related output
pins given in Min and Max values in this datasheet.
The input delays are given as typical values.
Note:
6
The user must take into account the package capacitance load contribution (CIN) described in
Table 3-1 on page 3.
AT91R40008
1795E–ATARM–12-Dec-05
AT91R40008
5.2
Temperature
Derating Factor
Figure 5-1.
Derating Curve for Different Operating Temperatures
1.2
Derating Factor
1.1
1
Derating Factor for
Typ Case is 1
0.9
0.8
-60
-40
-20
0
20
40
60
80
100
120
140
160
Operating Temperature °C
5.3
Core Voltage
Derating Factor
Figure 5-2.
Core Voltage Derating Factor
Derating Factor
3
Derating Factor
for Typ Case is 1
2.5
2
1.5
1
0.5
1
1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95
Core Supply Voltage (V)
7
1795E–ATARM–12-Dec-05
5.4
IO Voltage
Derating Factor
Figure 5-3.
Derating Factor for Different VDDIO Power Supply Levels
1.6
Derating Factor for
Typ Case is 1
Derating Factor
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VDDIO Voltage Level
8
AT91R40008
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AT91R40008
6. Clock Waveforms
Table 6-1.
Master Clock Waveform Parameters
Symbol
Parameter
Conditions
Min
Max
Units
1/(tCP)
Oscillator Frequency
82.1
MHz
tCP
Oscillator Period
12.2
ns
tCH
High Half-period
5.0
ns
tCL
Low Half-period
5.5
ns
Table 1. Clock Propagation Times
Symbol
Parameter
tCDLH
Rising Edge Propagation Time
tCDHL
Falling Edge Propagation Time
Conditions
Min
Max
Units
CMCKO = 0 pF
4.4
6.6
ns
0.199
0.295
ns/pF
4.5
6.7
ns
0.153
0.228
ns/pF
CMCKO derating
CMCKO = 0 pF
CMCKO derating
Figure 6-1.
Clock Waveform
tCH
MCKI
2.0V
2.0V
0.8V
0.8V
0.8V
tCL
tCP
tCDLH
Table 6-2.
0.5 VDDIO
0.5 VDDIO
MCKO
tCDHL
NRST to MCKO
Symbol
Parameter
tD
NRST Rising Edge to MCKO Valid Time
Min
Max
Units
3(tCP/2)
7(tCP/2)
ns
9
1795E–ATARM–12-Dec-05
Figure 6-2.
MCKO Relative to NRST
NRST
tD
MCKO
10
AT91R40008
1795E–ATARM–12-Dec-05
AT91R40008
7. AC Characteristics
7.1
EBI Signals Relative to MCKI
The following tables show timings relative to operating condition limits defined in the section ”Timing Results” on page 6.
See Figure 7-1 on page 14.
Table 7-1.
General-purpose EBI Signals
Symbol
Parameter
EBI1
MCKI Falling to NUB Valid
EBI2
MCKI Falling to NLB/A0 Valid
EBI3
MCKI Falling to A1 - A23 Valid
EBI4
MCKI Falling to Chip Select
Change
EBI5
NWAIT Setup before MCKI Rising
1.7
ns
EBI6
NWAIT Hold after MCKI Rising
1.7
ns
Table 7-2.
Conditions
Min
Max
Units
CNUB = 0 pF
4.4
8.9
ns
0.030
0.043
ns/pF
3.7
6.7
ns
0.045
0.069
ns/pF
3.4
7.8
ns
0.045
0.076
ns/pF
3.7
8.6
ns
0.045
0.078
ns/pF
CNUB derating
CNLB = 0 pF
CNLB derating
CADD = 0 pF
CADD derating
CNCS = 0 pF
CNCS derating
EBI Write Signals
Symbol
Parameter
EBI7
MCKI Rising to NWR Active (No Wait States)
EBI8
MCKI Rising to NWR Active (Wait States)
EBI9
MCKI Falling to NWR Inactive (No Wait States)
EBI10
MCKI Rising to NWR Inactive (Wait States)
EBI11
MCKI Rising to D0 - D15 Out Valid
EBI12
NWR High to NUB Change
EBI13
NWR High to NLB/A0 Change
EBI14
NWR High to A1 - A23 Change
Conditions
Min
Max
Units
CNWR = 0 pF
3.9
6.3
ns
0.029
0.043
ns/pF
4.4
7.0
ns
0.029
0.043
ns/pF
3.8
6.3
ns
0.029
0.044
ns/pF
4.2
6.7
ns
0.029
0.044
ns/pF
4.2
7.5
ns
0.045
0.080
ns/pF
3.1
7.0
ns
0.030
0.043
ns/pF
3.1
5.4
ns
0.043
0.073
ns/pF
2.9
7.0
ns
0.043
0.076
ns/pF
CNWR derating
CNWR = 0 pF
CNWR derating
CNWR = 0 pF
CNWR derating
CNWR = 0 pF
CNWR derating
CDATA = 0 pF
CDATA derating
CNUB = 0 pF
CNUB derating
CNLB = 0 pF
CNLB derating
CADD = 0 pF
CADD derating
11
1795E–ATARM–12-Dec-05
Table 7-2.
EBI Write Signals (Continued)
Symbol
Parameter
EBI15
NWR High to Chip Select Inactive
Conditions
Min
Max
Units
CNCS = 0 pF
2.9
6.8
ns
0.052
0.067
ns/pF
CNCS derating
C = 0 pF
Data Out Valid before NWR High (No Wait States)(1)
EBI16
tCH - 1.8
ns
CDATA derating
-0.080
ns/pF
CNWR derating
0.044
C = 0 pF
EBI17
Data Out Valid before NWR High (Wait States)
(1)
EBI18
Data Out Valid after NWR High
EBI19
NWR Minimum Pulse Width (No Wait States)(1)
EBI20
NWR Minimum Pulse Width (Wait States)(1)
Notes:
ns/pF
(2)
n x tCP - 1.3
ns
CDATA derating
-0.080
ns/pF
CNWR derating
0.044
ns/pF
2.2
ns
tCH - 0.6
ns
0
ns/pF
n x tCP - 0.9(2)
ns
0
ns/pF
CNWR = 0 pF
CNWR derating
CNWR = 0 pF
CNWR derating
1. The derating factor should not be applied to tCH or tCP.
2. n = number of standard wait states inserted.
Table 7-3.
EBI Read Signals
Symbol
Parameter
EBI21
MCKI Falling to NRD Active(1)
EBI22
MCKI Rising to NRD Active(2)
EBI23
MCKI Falling to NRD Inactive(1)
EBI24
MCKI Falling to NRD Inactive (2)
EBI25
D0 - D15 In Setup before MCKI Falling Edge(5)
Min
Max
Units
CNRD = 0 pF
4.5
7.9
ns
0.029
0.043
ns/pF
3.8
7.3
ns
0.029
0.043
ns/pF
4.1
6.5
ns
0.030
0.044
ns/pF
3.9
5.8
ns
0.030
0.044
ns/pF
CNRD derating
CNRD = 0 pF
CNRD derating
CNRD = 0 pF
CNRD derating
CNRD = 0 pF
CNRD derating
EBI26
D0 - D15 In Hold after MCKI Falling Edge
EBI27
NRD High to NUB Change
EBI28
NRD High to NLB/A0 Change
EBI29
NRD High to A1 - A23 Change
EBI30
NRD High to Chip Select Inactive
12
Conditions
(6)
CNUB = 0 pF
CNUB derating
CNLB = 0 pF
CNLB derating
CADD = 0 pF
CADD derating
CNCS = 0 pF
CNCS derating
1.5
ns
1.2
ns
3.2
7.1
ns
0.030
0.043
ns/pF
3.2
4.6
ns
0.043
0.073
ns/pF
2.8
6.1
ns
0.043
0.076
ns/pF
2.9
6.2
ns
0.052
0.067
ns/pF
AT91R40008
1795E–ATARM–12-Dec-05
AT91R40008
Table 7-3.
EBI Read Signals
Symbol
Parameter
EBI31
Data Setup before NRD High(6)
EBI32
Data Hold after NRD High(6)
EBI33
NRD Minimum Pulse Width(1) (3)
Min
CNRD = 0 pF
8.0
ns
0.044
ns/pF
-3.1
ns
-0.030
ns/pF
(n +1) tCP - 1.9(4)
ns
CNRD derating
CNRD = 0 pF
CNRD derating
CNRD = 0 pF
CNRD derating
NRD Minimum Pulse Width(2) (3)
EBI34
Notes:
Conditions
CNRD = 0 pF
CNRD derating
Max
0.001
n x tCP + (tCH - 1.5)
Units
ns/pF
(4)
ns
0.001
ns/pF
1. Early Read Protocol.
2. Standard Read Protocol.
3. The derating factor should not be applied to tCH or tCP.
4. n = number of standard wait states inserted.
5. Only one of these two timings, EB25 or EBI31, needs to be met.
6. Only one of these two timings, EB26 or EBI32, needs to be met.
Table 7-4.
EBI Read and Write Control Signals. Capacitance Limitation
Symbol
Parameter
TCPLNRD(1)
Master Clock Low Due to NRD Capacitance
TCPLNWR(2)
Master CLock Low Due to NWR Capacitance
Notes:
Conditions
Min
CNRD = 0 pF
7.3
ns
CNRD derating
0.044
ns/pF
CNWR = 0 pF
7.6
ns
0.044
ns/pF
CNWR derating
Max
Units
1. If this condition is not met, the action depends on the read protocol intended for use.
• Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle.
• Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state.
2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be
programmed.
13
1795E–ATARM–12-Dec-05
Figure 7-1.
EBI Signals Relative to MCKI
MCKI
EBI4
EBI4
NCS
CS
EBI3
A1 - A23
EBI5
EBI6
NWAIT
EBI1/EBI2
NUB/NLB/A0
EBI21
NRD(1)
EBI27-30
EBI23
EBI33
EBI22
NRD(2)
EBI24
EBI34
EBI31
EBI32
EBI25
EBI26
D0 - D15 Read
EBI9
EBI7
EBI12-15
EBI19
NWR (No Wait States)
EBI8
EBI10
EBI20
NWR (Wait States)
EBI11
EBI17
EBI16
EBI18
EBI18
D0 - D15 to Write
No Wait
Notes:
14
Wait
1. Early Read Protocol.
2. Standard Read Protocol.
AT91R40008
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AT91R40008
7.2
7.2.1
Peripheral Signals
USART Signals
The inputs have to meet the minimum pulse width and period constraints shown in Table 7-5
and Table 7-6, and represented in Figure 7-2.
Table 7-5.
USART Input Minimum Pulse Width
Symbol
Parameter
US1
SCK/RXD Minimum Pulse Width
Table 7-6.
Units
5(tCP/2)
ns
Min Input Period
Units
9(tCP/2)
ns
USART Minimum Input Period
Symbol
Parameter
US2
SCK Minimum Input Period
Figure 7-2.
Min Pulse Width
USART Signals
US1
RXD
US2
US1
SCK
7.2.2
Timer/Counter Signals
Due to internal synchronization of input signals, there is a delay between an input event and a
corresponding output event. This delay is 3(tCP) in Waveform Event Detection mode and 4(tCP)
in Waveform Total-count Detection mode. The inputs have to meet the minimum pulse width
and minimum input period shown in Table 7-7 and Table 7-8, and as represented in Figure 73.
Table 7-7.
Timer Input Minimum Pulse Width
Symbol
Parameter
TC1
TCLK/TIOA/TIOB Minimum Pulse Width
Min Pulse Width
Units
3(tCP/2)
ns
15
1795E–ATARM–12-Dec-05
Table 7-8.
Timer Input Minimum Period
Symbol
Parameter
TC2
TCLK/TIOA/TIOB Minimum Input Period
Figure 7-3.
Min Input Period
Units
5(tCP/2)
ns
Timer Input
TC2
3(tCP/2)
3(tCP/2)
MCKI
TC1
TIOA/
TIOB/
TCLK
7.2.3
Reset Signals
A minimum pulse width is necessary, as shown in Table 7-9 and as represented in Figure 7-4.
Table 7-9.
Reset Minimum Pulse Width
Symbol
Parameter
RST1
NRST Minimum Pulse Width
Figure 7-4.
Min Pulse-width
Units
10(tCP)
ns
Reset Signal
RST1
NRST
Only the NRST rising edge is synchronized with MCKI. The falling edge is asynchronous.
7.2.4
16
Advanced Interrupt Controller Signals
Inputs have to meet the minimum pulse width and minimum input period shown in Table 7-10
and Table 7-11 and represented in Figure 7-5.
AT91R40008
1795E–ATARM–12-Dec-05
AT91R40008
Table 7-10.
AIC Input Minimum Pulse Width
Symbol
Parameter
AIC1
FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse
Width
Table 7-11.
Units
3(tCP/2)
ns
Min Input Period
Units
5(tCP/2)
ns
AIC Input Minimum Period
Symbol
Parameter
AIC2
AIC Minimum Input Period
Figure 7-5.
Min Pulse Width
AIC Signals
AIC2
MCKI
AIC1
FIQ/IRQ0/
IRQ1/IRQ2/
IRQ3 Input
7.2.5
Parallel I/O Signals
The inputs have to meet the minimum pulse width shown in Table 7-12 and represented in
Figure 7-6.
Table 7-12.
PIO Input Minimum Pulse Width
Symbol
Parameter
PIO1
PIO Input Minimum Pulse Width
Figure 7-6.
Min Pulse Width
Units
3(tCP/2)
ns
PIO Signal
PIO1
PIO
Inputs
17
1795E–ATARM–12-Dec-05
7.2.6
ICE Interface Signals
Table 7-13.
ICE Interface Timing Specifications
Symbol
Parameter
Conditions
Min
ICE0
NTRST Minimum Pulse
Width
10.9
ns
ICE1
NTRST High Recovery to
TCK High
0.9
ns
ICE2
NTRST High Removal
from TCK High
-0.3
ns
ICE3
TCK Low Half-period
23.5
ns
ICE4
TCK High Half-period
22.7
ns
ICE5
TCK Period
46.1
ns
ICE6
TDI, TMS Setup before
TCK High
0.4
ns
ICE7
TDI, TMS Hold after TCK
High
0.4
ns
3.3
ns
ICE8
TDO Hold Time
0.001
ns/pF
ICE9
TCK Low to TDO Valid
CTDO = 0 pF
CTDO derating
Figure 7-7.
Max
Units
CTDO = 0 pF
7.4
ns
CTDO derating
0.28
ns/pF
ICE Interface Signal
ICE0
NTRST
ICE1
ICE2
ICE5
TCK
ICE4
ICE3
TMS/TDI
ICE6
ICE7
TDO
ICE8
ICE9
18
AT91R40008
1795E–ATARM–12-Dec-05
AT91R40008
Revision History
Version
page
Comments
1795A
10-Dec-01 First Issue
1795B
7-Aug-2002
page 2
Absolute Maximum Ratings: changed
page 2
Table 1. DC Characteristics: changed
page 3
Table 2. Power Consumption: changed
page 3
Table 3. Power Consumption per Peripheral: changed
page 9
Table 7. Master Waveclock Parameters: changed
1795C
24-Mar-2004
page 1
Features: Change to “Fully Static Operation” values.
page 9
Figure 4. Clock Waveform: tR and tF removed, tCL measurement changed.
page 13
Table 12. Footnote 5 changed and footnote 6 added to clarify selection needs.
1795D
22-Oct-04
page 6
Change to Timing Results (CSR 04-320)
page 9
Change to Table 7 and Figure 4 (CSR 04-320)
1795E
12-Dec-05
all
Reformatted in Atmel template version 5.2. Numbering properties are changed as a result.
page 9
Table 6-1, “Master Clock Waveform Parameters,” note deleted. (CSR 05-446)
19
1795E–ATARM–12-Dec-05
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