AD ADL5330 10 mhz to 3 ghz vga with 60 db gain control range Datasheet

10 MHz to 3 GHz VGA with
60 dB Gain Control Range
ADL5330
GAIN
ENBL
VPS2
VPS2
VPS2
VPS1
COM1
INHI
RFIN
INPUT
GM
STAGE
INLO
COM1
APPLICATIONS
VPS1
Transmit and receive power control at RF and IF
VREF
VPS2
VPS2
GAIN
CONTROL
COM2
CONTINUOUSLY
VARIABLE
ATTENUATOR
Voltage-controlled amplifier/attenuator
Operating frequency 10 MHz to 3 GHz
Optimized for controlling output power
High linearity: OIP3 31 dBm @ 900 MHz
Output noise floor: −150 dBm/Hz @ 900 MHz
50 Ω input and output impedances
Single-ended or differential operation
Wide gain-control range: −34 dB to +22 dB @ 900 MHz
Linear-in-dB gain control function, 20 mV/dB
Single-supply 4.75 V to 5.25 V
FUNCTIONAL BLOCK DIAGRAM
O/P OPHI
(TZ)
STAGE
OPLO
RFOUT
BALUN
COM2
BIAS
AND
VREF
VPS2
IPBS
OPBS COM1 COM2 COM2
05134-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
The ADL5330 is a high performance, voltage-controlled
variable gain amplifier/attenuator for use in applications with
frequencies up to 3 GHz. The balanced structure of the signal
path minimizes distortion while it also reduces the risk of
spurious feed-forward at low gains and high frequencies caused
by parasitic coupling. While operation between a balanced
source and load is recommended, a single-sided input is
internally converted to differential form.
The input impedance is 50 Ω from INHI to INLO. The outputs
are usually coupled into a 50 Ω grounded load via a 1:1 balun. A
single supply of 4.75 V to 5.25 V is required.
The 50 Ω input system converts the applied voltage to a pair of
differential currents with high linearity and good common
rejection even when driven by a single-sided source. The signal
currents are then applied to a proprietary voltage-controlled
attenuator providing precise definition of the overall gain under
the control of the linear-in-dB interface. The GAIN pin accepts
a voltage from 0 V at minimum gain to 1.4 V at full gain with a
20 mV/dB scaling factor.
The output of the high accuracy wideband attenuator is applied
to a differential transimpedance output stage. The output stage
sets the 50 Ω differential output impedances and drives
Pin OPHI and Pin OPLO. The ADL5330 has a power-down
function. It can be powered down by a Logic LO input on the
ENBL pin. The current consumption in power-down mode is
250 μA.
The ADL5330 is fabricated on an ADI proprietary high
performance, complementary bipolar IC process. The ADL5330
is available in a 24-lead (4 mm × 4 mm), Pb-free LFCSP_VQ
package and is specified for operation from ambient
temperatures of −40°C to +85°C. An evaluation board is also
available.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
ADL5330
TABLE OF CONTENTS
Specifications..................................................................................... 3
Gain Control Input .................................................................... 15
Absolute Maximum Ratings............................................................ 5
Automatic Gain Control............................................................ 15
ESD Caution.................................................................................. 5
Interfacing to an IQ Modulator................................................ 17
Pin Configuration and Function Descriptions............................. 6
WCDMA Transmit Application............................................... 18
Typical Performance Characteristics ............................................. 7
CDMA2000 Transmit Application........................................... 19
Theory of Operation ...................................................................... 12
Soldering Information ............................................................... 19
Applications..................................................................................... 13
Evaluation Board ........................................................................ 20
Basic Connections ...................................................................... 13
Outline Dimensions ....................................................................... 24
RF Input/Output Interface ........................................................ 14
Ordering Guide .......................................................................... 24
REVISION HISTORY
6/05—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Changes to Table 3............................................................................ 6
Changes to Figure 27...................................................................... 11
Changes to Figure 35...................................................................... 14
Changes to the Gain Control Input Section................................ 15
Changes to Figure 42...................................................................... 17
4/05—Revision 0: Initial Version
Rev. A | Page 2 of 24
ADL5330
SPECIFICATIONS
VS = 5 V; TA = 25°C; M/A-COM ETC1-1-13 1:1 balun at input and output for single-ended 50 Ω match.
Table 1.
Parameter
GENERAL
Usable Frequency Range
Nominal Input Impedance
Nominal Output Impedance
100 MHz
Gain Control Span
Maximum Gain
Minimum Gain
Gain Flatness vs. Frequency
Gain Control Slope
Gain Control Intercept
Input Compression Point
Input Compression Point
Output Third-Order Intercept (OIP3)
Output Noise Floor 1
Noise Figure
Input Return Loss 2
Output Return Loss2
450 MHz
Gain Control Span
Maximum Gain
Minimum Gain
Gain Flatness vs. Frequency
Gain Control Slope
Gain Control Intercept
Input Compression Point
Input Compression Point
Output Third-Order Intercept (OIP3)
Output Noise Floor1
Noise Figure
Input Return Loss2
Output Return Loss2
900 MHz
Gain Control Span
Maximum Gain
Minimum Gain
Gain Flatness vs. Frequency
Gain Control Slope
Gain Control Intercept
Input Compression Point
Input Compression Point
Output Third-Order Intercept (OIP3)
Output Noise Floor1
Noise Figure
Input Return Loss2
Output Return Loss2
Conditions
Min
Typ
0.01
Max
Unit
3
Via 1:1 single-sided-to-differential balun
Via 1:1 differential-to-single-sided balun
50
50
GHz
Ω
Ω
±3 dB gain law conformance
VGAIN = 1.4 V
VGAIN = 0.1 V
±30 MHz around center frequency,
VGAIN = 1.0 V (differential output)
58
23
−35
0.09
dB
dB
dB
dB
20.7
0.88
1.8
−0.3
38
−140
7.8
−12.8
−15.5
mV/dB
V
dBm
dBm
dBm
dBm/Hz
dB
dB
dB
57
22
−35
0.08
dB
dB
dB
dB
20.4
0.89
3.3
1.2
36
−146
8.0
−19
−13.4
mV/dB
V
dBm
dBm
dBm
dBm/Hz
dB
dB
dB
53
21
−32
0.14
dB
dB
dB
dB
19.7
0.92
2.7
1.3
31.5
−144
9.0
−18
−18
mV/dB
V
dBm
dBm
dBm
dBm/Hz
dB
dB
dB
Gain = 0 dB, gain = slope (VGAIN − intercept)
VGAIN = 1.2 V
VGAIN = 1.4 V
VGAIN = 1.4 V
20 MHz carrier offset, VGAIN = 1.4 V
VGAIN = 1.4 V
1 V < VGAIN < 1.4 V
±3 dB gain law conformance
VGAIN = 1.4 V
VGAIN = 0.1 V
±30 MHz around center frequency,
VGAIN = 1.0 V, (differential output)
Gain = 0 dB, gain = slope (VGAIN − intercept)
VGAIN = 1.2 V
VGAIN = 1.4 V
VGAIN = 1.4 V
20 MHz carrier offset, VGAIN = 1.4 V
VGAIN = 1.4 V
1 V < VGAIN < 1.4 V
±3 dB gain law conformance
VGAIN = 1.4 V
VGAIN = 0.2 V
±30 MHz around center frequency,
VGAIN = 1.0 V (differential output)
Gain = 0 dB, gain = slope (VGAIN − intercept)
VGAIN = 1.2 V
VGAIN = 1.4 V
VGAIN = 1.4 V
20 MHz carrier offset, VGAIN = 1.4 V
VGAIN = 1.4 V
1 V < VGAIN < 1.4 V
Rev. A | Page 3 of 24
ADL5330
Parameter
2200 MHz
Gain Control Span
Maximum Gain
Minimum Gain
Gain Flatness vs. Frequency
Gain Control Slope
Gain Control Intercept
Input Compression Point
Input Compression Point
Output Third-Order Intercept (OIP3)
Output Noise Floor1
Noise Figure
Input Return Loss2
Output Return Loss2
2700 MHz
Gain Control Span
Maximum Gain
Minimum Gain
Gain Flatness vs. Frequency
Gain Control Slope
Gain Control Intercept
Input Compression Point
Input Compression Point
Output Third-Order Intercept (OIP3)
Output Noise Floor1
Noise Figure
Input Return Loss2
Output Return Loss2
GAIN CONTROL INPUT
Gain Control Voltage Range 3
Incremental Input Resistance
Response Time
POWER SUPPLIES
Voltage
Current, Nominal Active
Current, Disabled
1
2
3
Conditions
Min
±3 dB gain law conformance
VGAIN = 1.4 V
VGAIN = 0.6 V
±30 MHz around center frequency,
VGAIN = 1.0 V (differential output)
Gain = 0 dB, gain = slope (VGAIN − intercept)
VGAIN = 1.2 V
VGAIN = 1.4 V
VGAIN = 1.4 V
20 MHz carrier offset, VGAIN = 1.4 V
VGAIN = 1.4 V
1 V < VGAIN < 1.4 V
±3 dB gain law conformance
VGAIN = 1.4 V
VGAIN = 0.7 V
±30 MHz around center frequency,
VGAIN = 1.0 V (differential output)
Gain = 0 dB, gain = slope (VGAIN − intercept)
VGAIN = 1.2 V
VGAIN = 1.4 V
VGAIN = 1.4 V
20 MHz carrier offset, VGAIN = 1.4 V
VGAIN = 1.4 V
1 V < VGAIN < 1.4 V
Typ
Max
Unit
46
16
−30
0.23
dB
dB
dB
dB
16.7
1.06
0.9
−2.0
21.2
−147
12.5
−11.7
−9.5
mV/dB
V
dBm
dBm
dBm
dBm/Hz
dB
dB
dB
42
10
−32
0.3
dB
dB
dB
dB
16
1.15
1.2
−0.9
17
−152
14.7
−9.7
−5
mV/dB
V
dBm
dBm
dBm
dBm/Hz
dB
dB
dB
GAIN pin
0
GAIN pin to COM1 pin
Full scale: to within 1 dB of final gain
3 dB gain step, POUT to within 1 dB of final gain
Pin VPS1, Pin VPS2, Pin COM1, Pin COM2, Pin ENBL
4.75
VGN = 0 V
VGN = 1.4 V
ENBL = LO
Noise floor varies slightly with output power level. See Figure 9 through Figure 13.
See Figure 27 and Figure 29 for differential input and output impedances.
Minimum gain voltage varies with frequency. See Figure 3 through Figure 7.
Rev. A | Page 4 of 24
1.4
V
MΩ
ns
ns
5.25
V
mA
mA
μA
1
380
20
5
100
215
250
ADL5330
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage VPS1, VPS2
RF Input Power at Maximum Gain
OPHI, OPLO
ENBL
GAIN
Internal Power Dissipation
θJA (with Pad Soldered to Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 60 sec)
Rating
5.5 V
5 dBm at 50 Ω
5.5 V
VPS1, VPS2
2.5 V
1.1 W
60°C/W
150°C
−40°C to +85°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 24
ADL5330
24 GAIN
23 ENBL
22 VPS2
21 VPS2
20 VPS2
19 VPS2
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
ADL5330
TOP VIEW
(Not to Scale)
18 VPS2
17 COM2
16 OPHI
15 OPLO
14 COM2
13 VPS2
05134-002
1
2
3
4
5
6
VREF 7
IPBS 8
OPBS 9
COM1 10
GNLO 11
COM2 12
VPS1
COM1
INHI
INLO
COM1
VPS1
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 6, 13, 18 to 22
2, 5, 10
3, 4
7
8
9
11
12, 14, 17
15
16
23
24
Mnemonic
VPS1, VPS2
COM1
INHI, INLO
VREF
IPBS
OPBS
GNLO
COM2
OPLO
OPHI
ENBL
GAIN
Descriptions
Positive Supply. Nominally equal to 5 V.
Common for Input Stage.
Differential Inputs, AC-Coupled.
Voltage Reference. Output at 1.5 V; normally ac-coupled to ground.
Input Bias. Normally ac-coupled to ground.
Output Bias. AC-Coupled to ground.
Gain Control Common. Connect to ground.
Common for Output Stage.
Low Side of Differential Output. Bias to VP with RF chokes.
High Side of Differential Output. Bias to VP with RF chokes.
Device Enable. Apply logic high for normal operation.
Gain Control Voltage Input. Nominal range 0 V to 1.4 V.
Rev. A | Page 6 of 24
ADL5330
TYPICAL PERFORMANCE CHARACTERISTICS
20
3
–40°C ERROR
1
–10
0
+25°C ERROR
–1
–20
+85°C GAIN
–2
–30
+85°C ERROR
+25°C GAIN
–40°C GAIN
6
+85°C ERROR
0
–3
3
–10
0
–20
–3
–30
–6
–9
–40
+85°C GAIN
0
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
–4
1.4
05134-003
+25°C GAIN
–50
–50
0
Figure 3. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 100 MHz
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
4
20
3
10
–40°C GAIN
–40°C GAIN
20
GAIN (dB)
1
–40°C ERROR
0
+85°C GAIN
+25°C ERROR
–1
–20
+85°C ERROR
–2
–30
0
GAIN (dB)
2
GAIN LAW CONFORMANCE (dB)
10
–20
0
–3
–6
–40
+85°C ERROR
–9
–50
0.6
0.8
VGAIN (V)
1.0
1.2
–4
1.4
–60
05134-004
0.4
3
+85°C GAIN
–50
0.2
–10
+25°C ERROR
+25°C GAIN
0
6
+25°C GAIN
–30
–3
–40
12
9
–40°C ERROR
–10
–12
1.4
Figure 6. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 2200 MHz
30
0
9
0
Figure 4. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 450 MHz
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
–12
1.4
05134-007
–40
+25°C ERROR
GAIN LAW CONFORMANCE (dB)
0
–40°C GAIN
10
GAIN (dB)
2
12
–40°C ERROR
20
GAIN LAW CONFORMANCE (dB)
10
GAIN (dB)
30
GAIN LAW CONFORMANCE (dB)
4
05134-006
30
Figure 7. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 2700 MHz
30
4
180
3
160
10
2
–40°C ERROR
1
0
–10
–20
–1
+25°C ERROR
–2
–30
+85°C GAIN
–40
+85°C ERROR
–3
–50
0
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
–4
1.4
120
100
VGAIN = 1.0V
80
60
40
20
05134-005
GAIN (dB)
0
140
0
10
100
1,000
FREQUENCY (kHz)
Figure 8. Frequency Response of Gain Control Input,
Carrier Frequency = 900 MHz
Figure 5. Gain and Gain Law Conformance vs. VGAIN
over Temperature at 900 MHz
Rev. A | Page 7 of 24
10,000
05134-008
+25°C GAIN
GAIN CONTROL SLOPE (dB/V)
20
GAIN LAW CONFORMANCE (dB)
–40°C GAIN
ADL5330
40
30
–115
–115
OIP3
20
–125
10
–130
0
–135
–140
–10
OUTPUT P1dB
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
–130
–10
–135
–20
–40
–150
–155
1.4
–50
0
Figure 9. Input Compression Point, Output Compression Point,
OIP3, and Noise Floor vs. VGAIN at 100 MHz
40
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
–155
1.4
1.2
Figure 12. Input Compression Point, Output Compression Point,
OIP3, and Noise Floor vs. VGAIN at 2200 MHz
–115
30
–120
20
–120
OIP3
30
–140
OUTPUT P1dB
–150
–30
0.2
0
–145
–145
0
–125
INPUT P1dB
–30
–20
–40
POWER (dBm)
INPUT P1dB
10
–120
NOISE FLOOR (dBm/Hz)
20
05134-012
–120
NOISE FLOOR (dBm/Hz)
30
05134-009
POWER (dBm)
OIP3
OIP3
–125
0
–135
–140
–10
OUTPUT P1dB
10
–130
0
–135
–10
–20
–145
–30
–150
–155
–20
–145
–30
–150
–40
–155
1.4
–50
–40
0
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
0
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
–160
1.4
1.2
Figure 13. Input Compression Point, Output Compression Point,
OIP3, and Noise Floor vs. VGAIN at 2700 MHz
Figure 10. Input Compression Point, Output Compression Point,
OIP3, and Noise Floor vs. VGAIN at 450 MHz
40
–140
OUTPUT P1dB
T
–115
T
30
–120
OIP3
–130
0
–135
–10
–140
OUTPUT P1dB
–20
–145
–30
–150
–40
0
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
–155
1.4
2
1
CH1 200mV CH2 100mV Ω
M100ns
A CH4
T
382.000ns
2.70V
Figure 14. Step Response of Gain Control Input
Figure 11. Input Compression Point, Output Compression Point,
OIP3, and Noise Floor vs. VGAIN at 900 MHz
Rev. A | Page 8 of 24
05134-014
10
NOISE FLOOR (dBm/Hz)
–125
INPUT P1dB
05134-011
POWER (dBm)
20
05134-013
–130
POWER (dBm)
INPUT P1dB
10
NOISE FLOOR (dBm/Hz)
–125
05134-010
POWER (dBm)
20
NOISE FLOOR (dBm/Hz)
INPUT P1dB
ADL5330
30
40
30
20
20
10
10
OIP3 (+85°C)
OIP3, OP1dB (dBm)
OIP3, OP1dB (dBm)
OIP3 (–40°C)
OP1dB (–40°C)
0 OIP3 (+25°C)
–10
–20
OP1dB (+85°C)
OIP3 (–40°C)
0
–10
OIP3 (+85°C)
OP1dB (+85°C)
OIP3 (+25°C)
–20
–30
–30
–40
OP1dB (–40°C)
OP1dB (+25°C)
0
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
1.4
05134-015
–50
OP1dB (+25°C)
–50
0
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
1.4
05134-018
–40
Figure 18. OP1dB and OIP3 vs. Gain over Temperature at 2200 MHz
Figure 15. OP1dB and OIP3 vs. Gain over Temperature at 100 MHz
20
40
OIP3 (+85°C)
30
10
0
10
OIP3, OP1dB (dBm)
OIP3 (–40°C)
OIP3 (+25°C)
0
–10
OP1dB (+25°C)
–20
OIP3 (+85°C)
–10
OIP3 (+25°C)
OP1dB (+25°C)
–20
OP1dB (–40°C)
OIP3 (–40°C)
–30
OP1dB (+85°C)
–40
–30
OP1dB (+85°C)
OP1dB (–40°C)
0
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
1.4
–50
05134-016
–40
0
Figure 16. OP1dB and OIP3 vs. Gain over Temperature at 450 MHz
40
OP1dB (+25°C)
30
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
1.4
05134-019
OIP3, OP1dB (dBm)
20
Figure 19. OP1dB and OIP3 vs. Gain over Temperature at 2700 MHz
250
OIP3 (–40°C)
OIP3 (+85°C)
200
TEMP = +85°C
ISUPPLY (mA)
10
OIP3 (+25°C)
0
–10
OP1dB (+85°C)
150
TEMP = +25°C
TEMP = –40°C
100
–20
50
–30
0
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
1.4
0
0
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
Figure 20. Supply Current vs. VGAIN and Temperature
Figure 17. OP1dB and OIP3 vs. Gain over Temperature at 900 MHz
Rev. A | Page 9 of 24
1.4
05134-020
OP1dB (–40°C)
–40
05134-017
OIP3, OP1dB (dBm)
20
ADL5330
30
70
60
25
PERCENTAGE (%)
40
30
20
20
15
10
5
10
0
18 18.5 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24
05134-021
0
18.5 19 19.5 20 20.5 21 21.5 22 22.5 23 23.5 24 24.5
OP1dB (dBm)
OIP3 (dBm)
Figure 21. OP1dB Distribution at 900 MHz at Maximum Gain, VGAIN = 1.4 V
05134-024
PERCENTAGE (%)
50
Figure 24. OIP3 Distribution at 2200 MHz at Maximum Gain; VGAIN = 1.4 V
30
30
VGAIN = 1.4V
20
VGAIN = 1.2V
10
VGAIN = 1.0V
0
VGAIN = 0.8V
–10
VGAIN = 0.6V
–20
VGAIN = 0.4V
–30
VGAIN = 0.2V
20
GAIN (dB)
PERCENTAGE (%)
25
15
10
5
–50
10
Figure 22. OP1dB Distribution at 2200 MHz at Maximum Gain, VGAIN = 1.4 V
100
1,000
FREQUENCY (MHz)
10,000
05134-025
10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16
OP1dB (dBm)
05134-022
0
9.5
10,000
05134-026
–40
Figure 25. Gain vs. Frequency (Differential)
30
30
VGAIN = 1.4V
20
VGAIN = 1.2V
25
GAIN (dB)
PERCENTAGE (%)
10
20
15
VGAIN = 1.0V
0
VGAIN = 0.8V
–10
VGAIN = 0.6V
–20
VGAIN = 0.4V
–30
VGAIN = 0.2V
10
5
28.5
29
29.5
30
30.5
31
31.5
32
32.5
OIP3 (dBm)
33
33.5
34
34.5
35
33.5
05134-023
0
28
–40
Figure 23. OIP3 Distribution at 900 MHz at Maximum Gain, VGAIN = 1.4 V
Rev. A | Page 10 of 24
–50
10
100
1,000
FREQUENCY (MHz)
Figure 26. Gain vs. Frequency (Using ETC1-1-13 Baluns)
ADL5330
90
90
60
120
60
120
150
150
30
30
450MHz
VGAIN = 0.2V
450MHz
3GHz
VGAIN = 0.2V
VGAIN = 1.2V
180
180
0
0
3GHz
VGAIN = 1.2V
1.9GHz
1.9GHz
210
330
240
300
270
270
Figure 29. Output Impedance (Differential)
0
–5
–5
–10
–10
–15
–15
S11 (dB)
0
–20
–20
–25
–25
–30
–30
600
1100
1600
2100
FREQUENCY (MHz)
2600
05134-029
S11 (dB)
Figure 27. Input Impedance (Differential)
–35
100
300
05134-027
240
05134-028
330
Figure 28. Input Return Loss with ETC1-1-13 Baluns
–35
100
600
1100
1600
2100
FREQUENCY (MHz)
2600
Figure 30. Output Return Loss with ETC1-1-13 Baluns
Rev. A | Page 11 of 24
05134-030
210
ADL5330
THEORY OF OPERATION
The ADL5330 is a high performance, voltage-controlled
variable gain amplifier/attenuator for use in applications with
frequencies up to 3 GHz. This device is intended to serve as an
output variable gain amplifier (OVGA) for applications where a
reasonably constant input level is available and the output level
adjusts over a wide range. One aspect of an OVGA is the output
metrics, IP3 and P1dB, decrease with decreasing gain.
The signal path is fully differential throughout the device in
order to provide the usual benefits of differential signaling,
including reduced radiation, reduced parasitic feedthrough, and
reduced susceptibility to common-mode interference with other
circuits. Figure 31 provides a simplified schematic of the
ADL5330.
TRANSIMPEDANCE
AMPLIFIER
INHI
INLO
OPHI
OPLO
GAIN
CONTROL
05134-031
Gm STAGE
Figure 31. Simplified Schematic
A controlled input impedance of 50 Ω is achieved through a
combination of passive and active (feedback-derived)
termination techniques in an input Gm stage. The input
compression point of the Gm stage is 1 dBm to 3 dBm,
depending on the input frequency.
Note that the inputs of the Gm stage are internally biased to a
dc level, and dc blocking capacitors are generally needed on the
inputs to avoid upsetting operation of the device.
Linear-in-dB gain control is accomplished by the application of
a voltage in the range of 0 Vdc to 1.4 Vdc to the gain control pin,
with maximum gain occurring at the highest voltage.
The output of the ladder attenuator is passed into a fixed-gain
transimpedance amplifier (TZA) to provide gain and buffer the
ladder terminating impedance from load variations. The TZA
uses feedback to improve linearity and to provide controlled
50 Ω differential output impedance. The quiescent current of
the output amplifier is adaptive; it is slaved to the gain control
voltage to conserve power at times when the gain (and hence,
output power) are low.
The outputs of the ADL5330 require external dc bias to the
positive supply voltage. This bias is typically supplied through
external inductors. The outputs are best taken differentially to
avoid any common-mode noise that is present, but, if necessary,
can be taken single-ended from either output.
If only a single output is used, it is still necessary to provide
bias to the unused output pin, and it is advisable to arrange a
reasonably equivalent ac load on the unused output. Differential
output can be taken via a 1:1 balun into a 50 Ω environment. In
virtually all cases, it is necessary to use dc blocking in the
output signal path.
At high gain settings, the noise floor is set by the input stage, in
which case the noise figure (NF) of the device is essentially
independent of the gain setting. Below a certain gain setting,
however, the input stage noise that reaches the output of the
attenuator falls below the input-equivalent noise of the output
stage. In such a case, the output noise is dominated by the
output stage itself; therefore, the overall NF of the device gets
worse on a dB-per-dB basis, because the gain is reduced below
the critical value. Figure 9 through Figure 13 provide details of
this behavior.
The currents from the Gm stage are then injected into a
balanced ladder attenuator at a deliberately diffused location
along the ladder, wherein the location of the centroid of the
injection region is dependent on the applied gain control
voltage. The steering of the current injection into the ladder is
accomplished by proprietary means to achieve linear-in-dB gain
control and low distortion.
Rev. A | Page 12 of 24
ADL5330
APPLICATIONS
Since the differential outputs are biased to the positive supply,
ac-coupling capacitors, preferably 100 pF, are needed between
the ADL5330 outputs and the next stage in the system.
Similarly, the INHI and INLO input pins are at bias voltages of
about 3.3 V above ground.
BASIC CONNECTIONS
Figure 32 shows the basic connections for operating the
ADL5330. There are two positive supplies, VPS1 and VPS2,
which must be connected to the same potential. Both COM1
and COM2 (common pins) should be connected to a low
impedance ground plane.
The nominal input and output impedance looking into each
individual RF input/output pin is 25 Ω. Consequently, the
differential impedance is 50 Ω.
A power supply voltage between 4.75 V and 5.25 V should be
applied to VPS1 and VPS2. Decoupling capacitors with 100 pF
and 0.1 μF power supplies should be connected close to each
power supply pin. The VPS2 pins (Pin 18 through Pin 22) can
share a pair of decoupling capacitors because of their proximity
to each other.
To enable the ADL5330, the ENBL pin must be pulled high.
Taking ENBL low puts the ADL5330 in sleep mode, reducing
current consumption to 250 μA at ambient. The voltage on
ENBL must be greater than 1.7 V to enable the device. When
enabled, the device draws 100 mA at low gain to 215 mA at
maximum gain.
The outputs of the ADL5330, OPHI and OPLO, are open
collectors that need to be pulled up to the positive supply with
120 nH RF chokes. The ac-coupling capacitors and the RF
chokes are the principle limitations for operation at low
frequencies. For example, to operate down to 1 MHz, 0.1 μF accoupling capacitors and 1.5 μH RF chokes should be used. Note
that in some circumstances, the use of substantially larger
inductor values results in oscillations.
VPOS
VPOS
C1
0.1μF
C3
0.1μF
C2
100pF
C4
100pF
VPS2
VPS2
L1
120nH
VPS1
VPS2
COM1
COM2
INHI
L2
120nH
C5
100pF
OPHI
ADL5330
RF INPUT
C10
1nF
COM2
VPS2
GNLO
VPS1
COM1
C11
100pF
COM2
OPBS
C12
0.1μF
COM1
IPBS
VPOS
OPLO
VREF
C14
100pF
RF OUTPUT
INLO
C6
100pF
C7
100pF
C8
0.1μF
C9
1nF
VPOS
Figure 32. Basic Connections
Rev. A | Page 13 of 24
05334-032
C13
100pF
VPS2
C16
100pF
VPS2
C12
0.1μF
GAIN
VPOS
ENBL
GAIN
ADL5330
band baluns can be used for applications requiring lower
insertion loss over smaller bandwidths.
RF INPUT/OUTPUT INTERFACE
The ADL5330 is primarily designed for differential signals;
however, there are several configurations that can be
implemented to interface the ADL5330 to single-ended
applications. Figure 33 to Figure 35 show three options for
differential-to-single-ended interfaces. All three configurations
use ac-coupling capacitors at the input/output and RF chokes at
the output.
The device can be driven single-ended with similar
performance, as shown in Figure 34. The single-ended input
interface can be implemented by driving one of the input
terminals and terminating the unused input to ground. To
achieve the optimal performance, the output must remain
balanced. In the case of Figure 34, a transformer balun is used at
the output.
+5V
As an alternative to transformer baluns, lumped-element baluns
comprised of passive L and C components can be designed at
specific frequencies. Figure 35 illustrates differential balance at
the input and output of the ADL5330 using discrete lumpedelement baluns. The lumped-element baluns present 180° of
phase difference while also providing impedance
transformation from source to load, and vice versa. Table 4 lists
recommended passive values for various center frequencies
with single-ended impedances of 50 Ω. Agilent’s free
AppCADTM program allows for simple calculation of passive
components for lumped-element baluns.
120nH
120nH
ADL5330
RF VGA
100pF
100pF
INHI
OPHI
INLO
OPLO
RFOUT
100pF
100pF
ETC1-1-13
05134-033
ETC1-1-13
Figure 33. Differential Operation with Balun Transformers
+5V
The lumped-element baluns offer ±0.5 dB flatness across
50 MHz for 900 MHz and 2200 MHz. At 2.7 GHz, the
frequency band is limited by stray capacitances that dominate
the passive components in the lumped-element balun at these
high frequencies. Thus, PCB parasitics must be considered
during lumped-element balun design and board layout.
120nH
120nH
RFIN
ADL5330
RF VGA
100pF
INHI
OPHI
INLO
OPLO
RFOUT
100pF
100pF
ETC1-1-13
Table 4. Recommended Passive Values for Lumped-Element
Balun, 50 Ω Impedance Match
05134-041
100pF
Center
Frequency
100 MHz
900 MHz
2.2 GHz
2.7 GHz
Figure 34. Single-Ended Drive with Balanced Output
Figure 33 illustrates differential balance at the input and output
using a transformer balun. Input and output baluns are recommended for optimal performance. Much of the characterization
for the ADL5330 was completed using 1:1 baluns at the input
and output for single-ended 50 Ω match. Operation using
M/A-COM ETC1-1-13 transmission line transformer baluns
is recommended for a broadband interface; however, narrow-
Ci
27 pF
3.3 pF
1.5 pF
1.5 pF
Input
Li
82 nH
9 nH
3.3 nH
2.4 nH
Cip
1 pF
16 nH
Co
33 pF
3.9 pF
1.5 pF
1.3 pF
+5V
120nH
120nH
Li
100pF
Ci
Ci
RFIN
Cip
OPHI
ADL5330
RF VGA
INLO
Ci
Li
Ci
Lo
100pF
INHI
Co
Co
RFOUT
Cop
OPLO
100pF
100pF
Co
Figure 35. Differential Operation with Discrete LC Baluns
Rev. A | Page 14 of 24
Lo
Co
05134-035
RFIN
Output
Lo
72 nH
8.7 nH
3.6 nH
2.7 nH
Cop
3.3 pF
0.5 pF
27 nH
33 nH
ADL5330
GAIN CONTROL INPUT
When the VGA is enabled, the voltage applied to the GAIN pin
sets the gain. The input impedance of the GAIN pin is 1 MΩ.
The gain control voltage range is between 0 V and +1.4 V, which
corresponds to a typical gain range between −38 dB and
+22 dB. The useful lower limit of the gain control voltage
increases at high frequencies to about 0.5 V and 0.6 V for
2.2 GHz and 2.7 GHz, respectively. The supply current to the
ADL5330 can vary from approximately 100 mA at low gain
control voltages to 215 mA at 1.4 V.
The detector’s error amplifier uses CFLT, a ground-referenced
capacitor pin, to integrate the error signal (in the form of a
current). A capacitor must be connected to CFLT to set the loop
bandwidth and to ensure loop stability.
+5V
+5V
VPOS
COMM
RFIN
OPHI
INHI
ADL5330
OPLO
INLO
GAIN
The 1 dB input compression point remains constant at 3 dBm
through the majority of the gain control range, as shown in
Figure 9 through Figure 13. The output compression point
increases dB for dB with increasing gain setting. The noise floor
is constant up to 1 V where it begins to rise.
ATTENUATOR
VOUT
LOG AMP OR
TRUPWR
DETECTOR
DAC
The bandwidth on the gain control pin is approximately 3 MHz.
Figure 14 shows the response time of a pulse on the GAIN pin.
VSET
RFIN
05134-036
CLPF
AUTOMATIC GAIN CONTROL
Although the ADL5330 provides accurate gain control, precise
regulation of output power can be achieved with an automatic
gain control (AGC) loop. Figure 36 shows the ADL5330 in an
AGC loop. The addition of the log amp (AD8318/AD8315) or a
TruPwr™ detector (AD8362) allows the AGC to have improved
temperature stability over a wide output power control range.
To operate the ADL5330 in an AGC loop, a sample of the
output RF must be fed back to the detector (typically using a
directional coupler and additional attenuation). A setpoint
voltage is applied to the VSET input of the detector while
VOUT is connected to the GAIN pin of the ADL5330. Based on
the detector’s defined linear-in-dB relationship between VOUT
and the RF input signal, the detector adjusts the voltage on the
GAIN pin (the detector’s VOUT pin is an error amplifier
output) until the level at the RF input corresponds to the
applied setpoint voltage. The GAIN setting settles to a value
that results in the correct balance between the input signal level
at the detector and the setpoint voltage.
DIRECTIONAL
COUPLER
Figure 36. ADL5330 in AGC Loop
The basic connections for operating the ADL5330 in an AGC
loop with the AD8318 are shown in Figure 37. The AD8318 is a
1 MHz to 8 GHz precision demodulating logarithmic amplifier.
It offers a large detection range of 60 dB with ±0.5 dB temperature stability. This configuration is similar to Figure 36.
The gain of the ADL5330 is controlled by the output pin of the
AD8318. This voltage, VOUT, has a range of 0 V to near VPOS.
To avoid overdrive recovery issues, the AD8318 output voltage
can be scaled down using a resistive divider to interface with the
0 V to 1.4 V gain control range of ADL5330.
A coupler/attenuation of 23 dB is used to match the desired
maximum output power from the VGA to the top end of the
linear operating range of the AD8318 (at approximately −5 dBm
at 900 MHz).
Rev. A | Page 15 of 24
ADL5330
+5V
+5V
RF INPUT
SIGNAL
RF OUTPUT
SIGNAL
120nH
VPOS
120nH
COMM
100pF
100pF
INHI
OPHI
ADL5330
INLO
100pF
DIRECTIONAL
COUPLER
OPLO
100pF
GAIN
412Ω
+5V
ATTENUATOR
1kΩ
SETPOINT
VOLTAGE
VOUT
VPOS
VSET
DAC
1nF
INHI
AD8318
LOG AMP
CLPF
220pF
1nF
INLO
05134-037
COMM
Figure 37. ADL5330 Operating in an Automatic Gain Control Loop in Combination with the AD8318
Figure 38 shows the transfer function of the output power vs.
the VSET voltage over temperature for a 900 MHz sine wave
with an input power of −1.5 dBm. Note that the power control
of the AD8318 has a negative sense. Decreasing VSET, which
corresponds to demanding a higher signal from the ADL5330,
tends to increase GAIN.
30
4
20
3
10
2
0
1
–10
0
–20
–1
–30
–2
–40
–3
T
AM MODULATED INPUT
T
1
AD8318 OUTPUT
ERROR (dB)
OUTPUT POWER (dBm)
The AGC loop is capable of controlling signals just under the
full 60 dB gain control range of the ADL5330. The performance
over temperature is most accurate over the highest power range,
where it is generally most critical. Across the top 40 dB range of
output power, the linear conformance error is well within
±0.5 dB over temperature.
In order for the AGC loop to remain in equilibrium, the
AD8318 must track the envelope of the ADL5330 output signal
and provide the necessary voltage levels to the ADL5330’s gain
control input. Figure 39 shows an oscilloscope screenshot of the
AGC loop depicted in Figure 37. A 100 MHz sine wave with
50% AM modulation is applied to the ADL5330. The output
signal from the ADL5330 is a constant envelope sine wave with
amplitude corresponding to a setpoint voltage at the AD8318 of
1.5 V. Also shown is the gain control response of the AD8318 to
the changing input envelope.
3
0.6
0.8
1.0
1.2
1.4
1.6
SETPOINT VOLTAGE (V)
1.8
2.0
–4
2.2
05134-038
–50
0.4
M2.00ms
A CH4
T
0.00000s
1.80V
05134-039
ADL5330 OUTPUT
CH1 250mV Ω
CH3 250mV Ω
Figure 39. Oscilloscope Screenshot Showing an AM Modulated Input Signal
Figure 38. ADL5330 Output Power vs. AD8318 Setpoint Voltage,
PIN = −1.5 dBm
The broadband noise added by the logarithmic amplifier is
negligible.
Rev. A | Page 16 of 24
ADL5330
Figure 40 shows the response of the AGC RF output to a pulse
on VSET. As VSET decreases to 1 V, the AGC loop responds
with an RF burst. Response time and the amount of signal
integration are controlled by the capacitance at the AD8318 CFLT
pin—a function analogous to the feedback capacitor around an
integrating amplifier. An increase in the capacitance results in
slower response time.
The output of the AD8349 is designed to drive 50 Ω loads and
easily interfaces with the ADL5330. The input to the ADL5330
can be driven single-ended, as shown in Figure 42. Similar configurations are possible with the AD8345 (250 MHz to 1 GHz)
and AD8346 (800 MHz to 2.5 GHz) quadrature modulators.
Figure 41 shows how output power, EVM, ACPR, and noise
vary with the gain control voltage. VGAIN is varied from 0 V to
1.4 V. Figure 41 shows that the modulation generated by the
AD8349 is a 1 GHz 64 QAM waveform with a 1 MHz symbol
rate. The ACPR values are measured in 1 MHz bandwidths at
1.1 MHz and 2.2 MHz carrier offsets. Noise floor is measured at
a 20 MHz carrier offset.
T
T
AD8318 WITH PULSED VSET
1
M10.0μs
A CH1
T
20.2000μs
05134-040
CH1 2.00V CH2 50.0mVΩ
2.60V
Figure 40. Oscilloscope Screenshot Showing the
Response Time of the AGC Loop
More information on the use of AD8318 in an AGC application
can be found in the AD8318 data sheet.
0
4.0
OUTPUT POWER
–20
3.5
–40
3.0
ACPR 1.1MHz OFFSET
–60
2.5
–80
2.0
ACPR 2.2MHz OFFSET
–100
1.5
EVM
–120
1.0
NOISE FLOOR
–140
0.5
–160
0
INTERFACING TO AN IQ MODULATOR
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
0
1.4
1.2
Figure 41. AD8349 and ADL5330 Output Power, ACPR, EVM, and Noise vs.
VGAIN for a 1 GHz 64 QAM Waveform with 1 MHz Symbol Rate
The basic connections for interfacing the AD8349 with the
ADL5330 are shown in Figure 42. The AD8349 is an RF
quadrature modulator with an output frequency range of
700 MHz to 2.7 GHz. It offers excellent phase accuracy and
amplitude balance, enabling high performance direct RF
modulation for communication systems.
The output of the AD8349 driving the ADL5330 should be
limited to the range that provides the optimal EVM and ACPR
performance. The power range is found by sweeping the output
power of the AD8349 to find the best compromise between
EVM and ACPR of the system. In Figure 41, the AD8349 output
power is set to −15 dBm.
+5V
120nH
+5V
+5V
120nH
VPOS
IBBP
DAC
IBBN
DIFFERENTIAL I/Q
BASEBAND INPUTS
COMM
AD8349
IQ MOD
VPOS
VOUT
COMM
ADL5330
RF VGA
100pF
INHI
INLO
QBBP
DAC
100pF
OPHI
RF OUTPUT
OPLO
100pF
QBBN
100pF
ETC1-1-13
100pF
LO
200Ω
05134-034
GAIN CONTROL
100pF
EVM (%)
ADL5330 OUTPUT
2
4.5
05134-042
OUTPUT POWER (dBm)
ACPR (dBm) (1MHz BANDWIDTH)
NOISE (dBm/Hz) (20MHz CARRIER OFFSET)
20
200Ω
ETC1-1-13
Figure 42. AD8349 Quadrature Modulator and ADL5330 Interface
Rev. A | Page 17 of 24
–20
–50
Figure 43 shows a plot of the output spectrum of the ADL5330
transmitting a single-carrier WCDMA signal (Test Model 1-64
at 2140 MHz). The carrier power output is approximately
−9.6 dBm. The gain control voltage is equal to 1.4 V giving a
gain of approximately 14.4 dB. At this power level, an adjacent
channel power ratio of −65.61 dBc is achieved. The alternate
channel power ratio of −71.37 dBc is dominated by the noise
floor of the ADL5330.
–30
–55
RF ATT 0dB
UNIT
–29.78 dBm
2.13996994 GHz
CH PWR
–9.56 dBm
ACP Up
–66.30 dB
ACP Low
–65.61 dB
ALT1 Up
–71.37 dB
ALT1 Low
–72.79 dB
–30
–40
–50
–70
–80
–100
–110
C0
CU1
CU1
–80
–80
NOISE –50MHz OFFSET
–85
–90
–35
–30
–25 –20 –15 –10
–5
OUTPUT POWER (dBm)
0
5
–90
10
10
–20
0
–30
CU2
SPAN 24.6848MHz
05134-043
2.46848MHz/
OUTPUT POWER
–10
CU2
–120
CENTER 2.14GHz
–75
C0
CL1
CL1
–70
Figure 45 shows how output power, ACPR, and noise vary with
the gain control voltage. VGAIN is varied from 0 V to 1.4 V and
input power is held constant at −19 dBm.
EXT
CL2
ACPR +10MHZ
OFFSET
Figure 44. ACPR and Noise vs. Output Power; Single-Carrier
WCDMA Input (Test Model 1-64 at 2140 MHz), VGAIN = 1.4 V (Fixed)
1RM
1 AVG
CL2
–70
–60
–100
–40
A
–60
–90
–65
dBm
1 [T1]
0.4 dB OFFSET
–50
05134-044
RBW 30kHz
VBW 300kHz
SWT 100ms
Figure 43. Single-Carrier WCDMA Spectrum at 2140 MHz;
VGAIN = 1.4 V, PIN = −23 dBm
Figure 44 shows how ACPR and noise vary with different input
power levels (gain control voltage is held at 1.4 V). At high
power levels, both adjacent and alternate channel power ratios
sharply increase. As output power drops, adjacent and alternate
channel power ratios both reach minima before the measurement becomes dominated by the noise floor of the ADL5330. At
this point, adjacent and alternate channel power ratios become
approximately equal.
OUTPUT POWER (dBm)
–20
–29.78dBm
2.13996994GHz
–60
ACPR +5MHZ OFFSET
–40
–20
–50
ACPR 5MHz
–30
–60
–70
–40
ACPR 10MHz
–50
–60
–70
0.4
–80
NOISE –50MHz OFFSET
0.5
0.6
0.7
0.8
0.9
VGAIN (V)
1.0
1.1
–90
1.2
1.3
–100
1.4
ACPR (dBc)
NOISE @ 50MHz OFFSET (1MHz BW)
REF LVL
–20dBm
–40
05134-045
MARKER 1 [T1]
ADJACENT/ALTERNATE CHANNEL
POWER RATIO (dBc)
WCDMA TRANSMIT APPLICATION
NOISE – dBm @ 50MHz CARRIER
OFFSET (1MHz BW)
ADL5330
Figure 45. Output Power, ACPR, and Noise vs. VGAIN;
Single-Carrier WCDMA (Test Model 1-64 at 2140 MHz) Input at −19 dBm
As the output power drops, the noise floor, measured in dBm/
Hz at 50 MHz carrier offset, initially falls and then levels off.
Rev. A | Page 18 of 24
ADL5330
CDMA2000 TRANSMIT APPLICATION
To test the compliance to the CDMA2000 base station standard,
an 880 MHz, three-carrier CDMA2000 test model signal
(forward pilot, sync, paging, and six traffic, as per 3GPP2
C.S0010-B, Table 6.5.2.1) was applied to the ADL5330. A cavitytuned filter with a 4.6 MHz pass band was used to reduce noise
from the signal source being applied to the device.
Figure 46 shows the spectrum of the output signal under
nominal conditions. Total POUT of the three-carrier signal is
equal to 0.46 dBm and VGAIN = 1.4 V. Adjacent and alternate
channel power ratio is measured in a 30 kHz bandwidth at
750 kHz and 1.98 MHz carrier offset, respectively.
1 [T1]
1
–20
CH PWR
ACP Up
ACP Low
ALT1 Up
ALT1 Low
ALT2 Up
ALT2 Low
–30
–40
1 AVG
–50
RF ATT 10dB
MIXER –10dBm
UNIT
dBm
–18.55dBm
880MHz
0.46dBm
–65.13dB
–64.40dB
–89.05dB
–83.68dB
–80.72dB
–81.24dB
A
1RM
EXT
–60
–70
CL3
–80
CL3
C0
C0
CL2
CL2
–90
CL1
CL1
CU1
CU1 CU2
CU2
–100
CU3
SPAN 15MHz
–0
–40
–10
–50
–20
–60
–30
ACPR 750kHz OFFSET
–70
–40
–80
–50
–60
–90
ACPR 1.98MHz OFFSET
–70
–100
NOISE 4MHz OFFSET
–80
–110
–20
–15
–10
–5
0
5
TOTAL OUTPUT POWER (dBm)
OUTPUT POWER
10
–90
15
–50
–20
–60
ACPR 750kHz OFFSET
–30
–70
ACPR 1.98MHz OFFSET
–40
–80
–50
–90
NOISE 4MHz OFFSET
0.2
0.4
0.6
0.8
VGAIN (V)
1.0
1.2
–100
1.4
Figure 48. Total Output Power and ACPR vs. VGAIN, 880 MHz Three-Carrier
CDMA2000 Test Model at −23 dBm Total Input Power; ACPR Measured in
30 kHz Bandwidth at 750 kHz and 1.98 MHz Carrier Offset
Above VGAIN = 0.4 V, the ACPR is still in compliance with the
standard. As the gain control input drops below 1.0 V, the noise
floor drops below −90 dBm.
SOLDERING INFORMATION
On the underside of the chip scale package, there is an exposed
compressed paddle. This paddle is internally connected to the
chip’s ground. Solder the paddle to the low impedance ground
plane on the printed circuit board to ensure specified electrical
performance and to provide thermal relief. It is also
recommended that the ground planes on all layers under the
paddle be stitched together with vias to reduce thermal
impedance.
05134-047
–30
NOISE – dBm @ 4MHz CARRIER OFFSET
(1MHz RBW)
ACPR – dBc (30kHz RBW)
In testing, by holding the gain control voltage steady at 1.4 V,
input power was swept. Figure 47 shows ACPR and noise floor
vs. total output power. Noise floor is measured at 1 MHz
bandwidth at 4 MHz carrier offset.
–25
–40
0
Figure 46. 880 MHz Output Spectrum, Three-Carrier CDMA2000 Test Model
at −23 dBm Total Input Power, VGAIN = 1.4 V, ACPR Measured at 750 kHz and
1.98 MHz Carrier Offset, Input Signal Filtered Using a Cavity Tuned Filter
(Pass Band = 4.6 MHz)
–120
–30
0
–10
05134-046
1.5MHz/
–30
–60
CU3
–110
CENTER 880MHz
10
05134-048
0.4 dB OFFSET
RBW 30kHz
VBW 300kHz
SWT 200ms
ACPR (dBc)
NOISE – 4MHz CARRIER OFFSET – (1MHz RBW)
–10
–18.55dBm
880.00000000MHz
With a fixed input power of −23 dBm, the output power was
again swept by exercising the gain control input. VGAIN was
swept from 0 V to 1.4 V. The resulting total output power,
ACPR, and noise floor are shown in Figure 48.
TOTAL OUTPUT POWER (dBm)
MARKER 1 [T1]
REF LVL
–10dBm
The results show that up to a total output power of +8 dBm,
ACPR remains in compliance with the standard (<−45 dBc @
750 kHz and <−60 dBc @ 1.98 MHz). At low output power
levels, ACPR at 1.98 MHz carrier offset degrades as the noise
floor of the ADL5330 becomes the dominant contributor to
measured ACPR. Measured noise at 4 MHz carrier offset begins
to increase sharply above 0 dBm output power. This increase is
not due to noise but results from increased carrier-induced
distortion. As output power drops below 0 dBm total, the noise
floor drops towards −85 dBm.
Figure 47. ACPR vs. Total Output Power, 880 MHz Three-Carrier CDMA2000
Test Model; VGAIN = 1.4 V (Fixed), ACPR Measured in 30 kHz Bandwidth at
750 kHz and 1.98 MHz Carrier Offset
Rev. A | Page 19 of 24
ADL5330
EVALUATION BOARD
Figure 49 shows the schematic of the ADL5330 evaluation
board. The silkscreen and layout of the component and circuit
sides are shown in Figure 50 through Figure 53. The board is
powered by a single-supply in the 4.75 V to 5.25 V range. The
power supply is decoupled by 100 pF and 0.1 μF capacitors at
each power supply pin. Additional decoupling, in the form of a
series resistor or inductor at the supply pins, can also be added.
Table 5 details the various configuration options of the
evaluation board.
The output pins of the ADL5330 require supply biasing with
120 nH RF chokes. Both the input and output pins have 50 Ω
differential impedances and must be ac-coupled. These pins are
converted to single-ended with a pair of baluns (M/A-COM
part number ETC1-1-13).
Instead of using balun transformers, lumped-element baluns
comprising passive L and C components can be designed.
Alternate input and output RF paths with component pads are
available on the circuit side of the board. Components M1
through M9 are used for the input interface, and M10 through
M18 are used for the output interface. DC blocking capacitors
of 100 pF must be installed in C15 and C16 for the input and
C17 and C18 for the output. The C5, C6, C11, and C12
capacitors must be removed. An alternate set of SMA
connectors, INPUT2 and OUT2, are used for this
configuration.
The ADL5330 can be driven single-ended; use the RF input
path on the circuit side of the board. A set of 100 pF dc blocking
capacitors must be installed in C15 and C16. C5 and C6 must
be removed. Use the INPUT2 SMA to drive one of the
differential input pins. The unused pin should be terminated to
ground, as shown in Figure 34.
The ADL5330 is enabled by applying a logic high voltage to the
ENBL pin by placing a jumper across the SW1 header in the
O position. Remove the jumper for disable. This pulls the ENBL
pin to ground through the 10 kΩ resistor.
Rev. A | Page 20 of 24
Figure 49. Evaluation Board Schematic
Rev. A | Page 21 of 24
05134-049
INPUT2
INPUT
M2
OPEN
M8
OPEN
M9
OPEN
M5
OPEN
M4
OPEN
M7
OPEN
M3
OPEN
M1
OPEN
T1
C16
OPEN
M6
OPEN
C15
OPEN
C6
100pF
C5
100pF
IPBS
VREF
R7
0Ω
R8
0Ω
C3
0.1μF
VPOS
C8
0.1μF
VPOS
GAIN
R14
OPEN
C4
100pF
R4
0Ω
C7
100pF
R5
0Ω
R3
0Ω
R10
1nF
R15
OPEN
VPS1
COM1
INLO
INHI
COM1
VPS1
R13
10kΩ
R2
0Ω
ADL5330
ENBL
IPBS
R1
0Ω
GAIN
VREF
SW1
VPS2
OPBS
R11
1nF
VPOS
VPS2
GNLO
SMA
VPS2
COM1
VPS2
C1
100pF
C2
0.1μF
VPS2
COM2
OPLO
OPHI
COM2
VPS2
COM2
VPOS
VPOS
R9
0Ω
R6
0Ω
C18
OPEN
M10
OPEN
C17
OPEN
C12
100pF
C11
100pF
C13
100pF
C14
0.1μF
IPBS
C9
0.1μF
C10
100pF
L2
120nH
L1
120nH
R12
0Ω
VPOS
M16
OPEN
M18
OPEN
M13
OPEN
M14
OPEN
M17
OPEN
M12
OPEN
M11
OPEN
M15
OPEN
T2
OUT2
OUT
ADL5330
ADL5330
Table 5. Evaluation Board Configuration Options
Components
C1 to C4, C7 to C10, C13,
C14, R2, R4, R5, R6, R12
Function
Power Supply Decoupling. The nominal supply decoupling consists of
100 pF and 0.1 μF capacitors at each power supply pin (the VPS2 pins, Pin 18
to Pin 22, share a pair of decoupling capacitors because of their proximity). A
series inductor or small resistor can be placed between the capacitors for
additional decoupling.
T1, C5, C6
Input Interface. The 1:1 balun transformer T1 converts a 50 Ω single-ended
input to the 50 Ω differential input. C5 and C6 are dc blocks.
Output Interface. The 1:1 balun transformer T2 converts the 50 Ω differential
output to 50 Ω single-ended output. C11 and C2 are dc blocks. L3 and
L4 provide dc biases for the output.
Enable Interface. The ADL5330 is enabled by applying a logic high voltage
to the ENBL pin by placing a jumper across SW1 to the O position. Remove
the jumper for disable. To exercise the enable function by applying an
external high or low voltage, use the pin labeled O on the SW1 header.
Alternate Input/Output Interface. The circuit side of the evaluation board
offers an alternate RF input and output interface. A lumped-element balun
can be built using L and C components instead of using the balun
transformer (see the Applications section). The components, M1 through
M9, are used for the input, and M10 through M18 are used for the output.
To use the alternate RF paths, disconnect the dc blocking capacitors
(Capacitor C5 and Capacitor C6 for the input and Capacitor C11 and
Capacitor C12 for the output). Place 100 pF dc blocking capacitors on
C15, C16, C17, and C18. Use the alternate set of SMA connectors,
INPUT2 and OUT2.
T2, C11, C12, L1, L2
SW1, R1, R13
C15 to C18, M1 to M18
Rev. A | Page 22 of 24
Default Conditions
C1, C4, C7, C10, C13 = 100 pF
(size 0603)
C2, C3, C8, C9, C14 = 0.1 μF
(size 0603)
R2, R4, R5, R6, R12 = 0 Ω
(size 0402)
T1 = ETC1-1-13 (M/A-COM)
C5, C6 = 100 pF (size 0603)
T2 = ETC1-1-13 (M/A-COM)
C11, C12 = 100 pF (size 0603)
L1, L2 = 120 nH (size 0805)
SW1 = installed
R1 = 0 Ω (size 0402)
R13 = 10 kΩ (size 0402)
M1 to M18 = not installed
(size 0603)
C15 to C18 = not installed
(size 0603)
05134-051
05134-053
ADL5330
Figure 50. Component Side Silkscreen
05134-050
05134-052
Figure 52. Component Side Layout
Figure 53. Circuit Side Layout
Figure 51. Circuit Side Silkscreen
Rev. A | Page 23 of 24
ADL5330
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
PIN 1
INDICATOR
0.60 MAX
TOP
VIEW
0.50
BSC
3.75
BSC SQ
0.50
0.40
0.30
1.00
0.85
0.80
12° MAX
PIN 1
INDICATOR
19
18
24 1
*2.45
2.30 SQ
2.15
EXPOSED
PAD
(BOTTOMVIEW)
13
12
7
0.80 MAX
0.65 TYP
6
0.23 MIN
2.50 REF
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
*COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 54. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADL5330ACPZ-WP 1, 2
ADL5330ACPZ-REEL71
ADL5330ACPZ-R21
ADL5330-EVAL
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
24-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
24-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
Z = Pb-free part.
WP = waffle pack.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05134–0–6/05(A)
Rev. A | Page 24 of 24
Package
Option
CP-24-2
CP-24-2
CP-24-2
Ordering
Quantity
64
1,500
250
1