FAN103 Primary-Side-Regulation PWM Controller (PWM-PSR) Features Description Low Standby Power Under 30mW Green-Mode Function: Linearly-Decreasing PWM Frequency This third-generation Primary-Side-Regulation (PSR) and highly integrated PWM controller provides several features to enhance the performance of low-power flyback converters. The proprietary topology, TURECURRENT™, of FAN103 enables precise CC regulation and simplified circuit for battery charger applications. A low-cost, smaller and lighter charger results as compared to a conventional design or a linear transformer. Fixed PWM Frequency at 50kHz with Frequency Hopping to Solve EMI Problem Cable Compensation in CV Mode Available in the 8-Lead SOP Package High Voltage Startup Fewest External Component Counts Constant-Voltage (CV) and Constant-Current (CC) Control without Secondary-Feedback Circuitry Peak-Current-Mode Control in CV Mode Cycle-by-Cycle Current Limiting VDD Over-Voltage Protection with Auto Restart VDD Under-Voltage Lockout (UVLO) To minimize standby power consumption, the proprietary green-mode function provides off-time modulation to linearly decrease PWM frequency under light-load conditions. This green mode assists the power supply in meeting the power conservation requirement. By using the FAN103, a charger can be implemented with few external components and minimized cost. A typical output CV/CC characteristic envelope is shown in Figure 1. Gate Output Maximum Voltage Clamped at 15V Maximum Minimum Before Cable Compensation After Cable Compensation VO Fixed Over-Temperature Protection with Auto Restart Applications Battery chargers for cellular phones, cordless phones, PDA, digital cameras, power tools, etc. Replaces linear transformer and RCC SMPS IO Figure 1. Typical Output V-I Characteristic Ordering Information Part Number Operating Temperature Range Eco Status Package Packing Method FAN103MY -40°C to +105°C Green 8-Lead, Small Outline Package (SOP-8) Tape & Reel For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 www.fairchildsemi.com FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) March 2010 Rsn L1 T1 Rsn2 D1 Csn DF D4 Dsn RF CO1 Rsn1 AC Input C1 D2 Csn2 C2 CVDD DFa R1 CVS D3 3 VDD 7 N.C 8 HV VS 5 RGATE R2 MOSFET GATE 2 CS 1 6 GND Rcs COMR 4 RSENSE CCR Figure 2. Typical Application Internal Block Diagram CO2 Rd DC Output FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Application Diagram Figure 3. Functional Block Diagram © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 www.fairchildsemi.com 2 FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Marking Information F: Fairchild Logo Z: Plant Code X: 1-Digit Year Code Y: 1-Digit Week Code TT: 2-Digit Die Run Code T: Package Type (M=SOP) P: Y=Green Package M: Manufacture Flow Code Figure 4. Top Mark Pin Configuration Figure 5. Pin Configuration Pin Definitions Pin # Name Description 1 CS 2 GATE 3 VDD Power Supply. IC operating current and MOSFET driving current are supplied using this pin. This pin is connected to an external VDD capacitor of typically 10µF. The threshold voltages for startup and turn-off are 16V and 5V, respectively. The operating current is lower than 5mA. 4 COMR Cable Compensation. This pin connects a capacitance between the COMR and GND pins for compensation voltage drop due to output cable loss in CV mode. 5 VS 6 GND 7 NC No Connect 8 HV High Voltage. This pin connects to bulk capacitor for high-voltage startup. Current Sense. This pin connects a current sense resistor, to detect the MOSFET current for peak-current-mode control in CV mode, and provides the output-current regulation in CC mode. PWM Signal Output. This pin uses the internal totem-pole output driver to drive the power MOSFET. It is internally clamped below 15V. Voltage Sense. This pin detects the output voltage information and discharge time based on voltage of auxiliary winding. Ground © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VHV Parameter Min. HV Pin Input Voltage (1)(2) Max. Unit 500 V VVDD DC Supply Voltage 30 V VVS VS Pin Input Voltage -0.3 7.0 V VCS CS Pin Input Voltage -0.3 7.0 V VCOMV Voltage Error Amplifier Output Voltage -0.3 7.0 V VCOMI Current Error Amplifier Output Voltage -0.3 7.0 V Power Dissipation (TA<50°C) 660 mW θJA Thermal Resistance (Junction-to-Air) 150 °C/W θJC Thermal Resistance (Junction-to-Case) 39 °C/W +150 °C PD TJ TSTG TL ESD Operating Junction Temperature -40 Storage Temperature Range -55 Lead Temperature (Wave Soldering or IR, 10 Seconds) Electrostatic Discharge Capability +150 °C +260 °C Human Body Model (Except HV Pin), JEDEC-JESD22_A114 4.50 Charged Device Model (Except HV Pin), JEDEC-ESD22_C101 1.25 kV Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin. FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Absolute Maximum Ratings Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 Min. Max. Unit -40 +105 °C www.fairchildsemi.com 4 Unless otherwise specified, VDD=15V and TA=25°C. Symbol Parameter Conditions Min. Typ. Max. Units 25 V VDD Section VOP Continuously Operating Voltage VDD-ON Turn-On Threshold Voltage 15 16 17 V VDD-OFF Turn-Off Threshold Voltage 4.5 5.0 5.5 V Operating Current 3.2 5.0 mA IDD-GREEN Green-Mode Operating Supply Current 0.95 1.20 mA VDD-OVP VDD Over-Voltage Protection Level IDD-OP VDD-OVPHYST tD-VDDOVP 28 V Hysteresis Voltage for VDD OVP 1.5 2.0 2.5 V VDD Over-Voltage-Protection Debounce Time 90 200 350 µs 50 V HV Startup Current Source Section VHV-MIN Minimum Startup Voltage on HV Pin IHV Supply Current Drawn from Pin HV VDC=100V 1.2 3.0 mA Leakage Current after Startup HV=500V, VDD=VDDOFF +1V 0.5 3.0 µA 47 50 53 ±1.5 ±2.0 ±2.5 IHV-LC Oscillator Section Center Frequency fOSC Frequency tFHR Frequency Hopping Period fOSC-N-MIN Frequency Hopping Range Minimum Frequency at No-Load fOSC-CM-MIN Minimum Frequency at CCM fDV Frequency Variation vs. VDD Deviation VDD=10~25V fDT Frequency Variation vs. Temperature Deviation TA=-40°C to +105°C kHz 3 ms 370 Hz 13 kHz 1 2 % 15 % 2.525 V FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Electrical Characteristics Voltage-Error-Amplifier Section VVR Reference Voltage 2.475 2.500 VN Green-Mode Starting Voltage on EA_V fOSC=-2kHz 2.5 V VG Green-Mode Ending Voltage on EA_V fOSC=1kHz 0.5 V RVS=20kΩ 1.4 V 10 µA Voltage-Sense Section VBIAS-COMV Adaptive Bias Voltage Dominated by VCOMV Itc IC Bias Current Current-Sense Section tPD tMIN-N Propagation Delay to GATE Output 90 Minimum On Time at No-Load VCOMR=1V 200 ns 950 ns VTH Threshold Voltage for Current Limit 0.8 V VTL Threshold Voltage on VS Pin Smaller than 0.5V 0.25 V Continued on the following page… © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 www.fairchildsemi.com 5 Unless otherwise specified, VDD=15V and TA=25°C. Symbol Parameter Conditions Min. Typ. Max. Units 2.475 2.500 2.525 V Current-Error-Amplifier Section VIR Reference Voltage Cable Compensation Section VCOMR COMR Pin for Cable Compensation 0.85 V Gate Section DCYMAX VOL VOH Maximum Duty Cycle 70 Output Voltage Low VDD=20V, Gate Sinks 10mA 75 80 % 1.5 V Output Voltage High VDD=8V, Gate Sources 1mA tr Rising Time CL=1nF 200 250 ns tf Falling Time CL=1nF 60 100 ns Output Clamp Voltage VDD=25V 15 18 V VCLAMP 5 V Over-Temperature-Protection Section TOTP Threshold Temperature for OTP (3) +140 °C Note: 3. When the over-temperature protection is activated, the power system enters latch mode and output is disabled. © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Electrical Characteristics (Continued) www.fairchildsemi.com 6 5.5 16.6 5.3 VDD_OFF (V) VDD_ON (V) 17 16.2 15.8 15.4 5.1 4.9 4.7 15 4.5 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 Temperature (ºC) Figure 6. Turn-On Threshold Voltage (VDD-ON) vs. Temperature Figure 7. 75 85 100 125 Turn-Off Threshold Voltage (VDD-OFF) vs. Temperature 54 f osc (KHz) 4.2 IDD_OP (mA) 50 56 5 3.4 2.6 1.8 52 50 48 46 44 1 -40 -30 -15 0 25 50 75 85 100 -40 125 -30 -15 Figure 8. 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Operating Current (IDD-OP) vs. Temperature Figure 9. 2.525 1.2 2.515 1.12 IDD_Green (mA) VVR (V) 25 Temperature (ºC) FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Typical Performance Characteristics 2.505 2.495 Center Frequency (fOSC) vs. Temperature 1.04 0.96 0.88 2.485 0.8 2.475 -40 -30 -15 0 25 50 75 85 100 -40 125 Figure 10. Reference Voltage (VVR) vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 11. Green-Mode Operating Supply Current (IDD-GREEN) vs. Temperature www.fairchildsemi.com 7 16 450 15 f osc_CM_MIN (KHz) f osc_Green (Hz) 420 390 360 330 14 13 12 11 300 -40 -30 -15 0 25 50 75 85 100 10 125 -40 -30 -15 Temperature (ºC) 25 75 85 100 125 Figure 13. Minimum Frequency at CCM (fOSC-CM-MIN) vs. Temperature 1100 2.5 1050 2 1000 tMIN_N (ns) 3 1.5 1 950 900 850 0.5 800 0 -40 -30 -15 0 25 50 75 85 100 -40 125 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 14. Supply Current Drawn from Pin HV (IHV) vs. Temperature Figure 15. Minimum On Time at No Load (tMIN-N) vs. Temperature 2.7 0.65 2.62 0.56 2.54 0.47 Vg (V) Vn (V) 50 Temperature (ºC) Figure 12. Minimum Frequency at No Load (fOSC-N-MIN) vs. Temperature IHV (mA) 0 FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Typical Performance Characteristics 2.46 2.38 0.38 0.29 2.3 0.2 -40 -30 -15 0 25 50 75 85 100 125 -40 Temperature (ºC) -15 0 25 50 75 85 100 125 Temperature (ºC) Figure 16. Green Mode Starting Voltage on EA_V (VN) vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 -30 Figure 17. Green Mode Ending Voltage on EA_V (VG) vs. Temperature www.fairchildsemi.com 8 12 Itc (µA) 11.2 10.4 9.6 8.8 8 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Figure 18. IC Bias Current (Itc) vs. Temperature 1.6 VBIAS_COMV (V) 1.5 1.4 1.3 1.2 1.1 FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Typical Performance Characteristics 1 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Figure 19. Output Clamp Voltage (VCLAMP) vs. Temperature 18 VCLAMP (V) 17.2 16.4 15.6 14.8 14 -40 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Figure 20. Variation Test Voltage on COMR Pin for Cable Compensation (VCOMR) vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 www.fairchildsemi.com 9 Figure 21 shows the basic circuit diagram of a primaryside regulated flyback converter with typical waveforms shown in Figure 22. Generally, discontinuous conduction mode (DCM) operation is preferred for primary-side regulation since it allows better output regulation. The operation principles of DCM flyback converter are as follows: constant current regulation mode, VCOMI determines the duty cycle while VCOMV is saturated to HIGH. Io D + V DL During the MOSFET on time (tON), input voltage (VDL) is applied across the primary-side inductor (Lm). Then, MOSFET current (Ids) increases linearly from zero to the peak value (Ipk). During this time, the energy is drawn from the input and stored in the inductor. Lm VO L O A D I ds EA_I CS Io Estimator RCS Ref V COMV Vs t DIS Detector PWM Control VDD Vo Estimator EA_V NA RS1 Ref RS2 Primary-Side Regulation Controller When the diode current reaches zero, the transformer auxiliary winding voltage (Vw) begins to oscillate by the resonance between the primary-side inductor (Lm) and the effective capacitor loaded across MOSFET. + - Gate V COMI + VF - - VAC When the MOSFET is turned off, the energy stored in the inductor forces the rectifier diode (D) to be turned on. While the diode is conducting, the output voltage (Vo), together with diode forward voltage drop (VF), are 2 applied across the secondary-side inductor (Lm×Ns / 2 Np ) and the diode current (ID) decreases linearly from the peak value (Ipk×Np/Ns) to zero. At the end of inductor current discharge time (tDIS), all the energy stored in the inductor has been delivered to the output. + Vw - Figure 21. Simplified PSR Flyback Converter Circuit During the inductor current discharge time, the sum of output voltage and diode forward-voltage drop is reflected to the auxiliary winding side as (Vo+VF) × Na/Ns. Since the diode forward-voltage drop decreases as current decreases, the auxiliary winding voltage reflects the output voltage best at the end of diode conduction time, where the diode current diminishes to zero. Thus, by sampling the winding voltage at the end of the diode conduction time, the output voltage information can be obtained. The internal error amplifier for output voltage regulation (EA_V) compares the sampled voltage with internal precise reference to generate error voltage (VCOMV), which determines the duty cycle of the MOSFET in CV mode. I pk I pk ⋅ NP NS I D.avg = I o Meanwhile, the output current can be estimated using the peak drain current and inductor current discharge time since output current is same as average of the diode current in steady state. VF ⋅ The output current estimator picks up the peak value of the drain current with a peak detection circuit and calculates the output current using the inductor discharge time (tDIS) and switching period (ts). This output information is compared with internal precise reference to generate error voltage (VCOMI), which determines the duty cycle of the MOSFET in CC mode. With Fairchild’s innovative technique TRUECURRENT™, constant current (CC) output can be precisely controlled. NA NS VO ⋅ NA NS Figure 22. Key Waveforms of DCM Flyback Converter Among the two error voltages, VCOMV and VCOMI, the small one determines the duty cycle. Therefore, during constant voltage regulation mode, VCOMV determines the duty cycle while VCOMI is saturated to HIGH. During © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 ID Np:Ns FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Functional Description www.fairchildsemi.com 10 When it comes to cellular phone charger applications, the battery is located at the end of cable, which causes, typically, several percentage of voltage drop on the actual battery voltage. FAN103 has a built-in cable voltage drop compensation, which provides a constant output voltage at the end of the cable over the entire load range in CV mode. As load increases, the voltage drop across the cable is compensated by increasing the reference voltage of voltage regulation error amplifier. Operating Current The operating current in FAN103 is as small as 3.2mA. The small operating current results in higher efficiency and reduces the VDD hold-up capacitance requirement. Once FAN103 enters deep-green mode, the operating current is reduced to 0.95mA, assisting the power supply in meeting power conservation requirements. Green-Mode Operation The FAN103 uses voltage regulation error amplifier output (VCOMV) as an indicator of the output load and modulates the PWM frequency, as shown in Figure 23. The switching frequency decreases as load decreases. In heavy load conditions, the switching frequency is fixed at 50kHz. Once VCOMV decreases below 2.5V, the PWM frequency linearly decreases from 50kHz. When FAN103 enters into deep-green mode, the PWM frequency is reduced to a minimum frequency of 370Hz, gaining power saving to help meet international power conservation requirements. Figure 24. Frequency Hopping High-Voltage Startup Figure 25 shows the HV-startup circuit for FAN103 applications. The HV pin is connected to the line input or bulk capacitor through a resistor, RSTART (100kΩ is recommended). During startup, the internal startup circuit in FAN103 is enabled. Meanwhile, line input supplies the current, ISTARTUP, to charge the hold-up capacitor, CDD, through RSTART. When the VDD voltage reaches VDD-ON, the internal startup circuit is disabled, blocking ISTARTUP from flowing into the HV pin. Once the IC turns on, CDD is the only energy source to supply the IC consumption current before the PWM starts to switch. Thus, CDD must be large enough to prevent VDD from dropping to VDD-OFF before the power can be delivered from the auxiliary winding. FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Cable Voltage Drop Compensation Figure 23. Switching Frequency in Green Mode Frequency Hopping EMI reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. FAN103 has an internal frequency hopping circuit that changes the switching frequency between 47kHz and 53kHz with a period, as shown in Figure 24. Figure 25. HV Startup Circuit © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 www.fairchildsemi.com 11 Over-Temperature Protection (OTP) The turn-on and turn-off thresholds are fixed internally at 16V and 5V, respectively. During startup, the hold-up capacitor must be charged to 16V through the startup resistor to enable the FAN103. The hold-up capacitor continues to supply VDD until power can be delivered from the auxiliary winding of the main transformer. VDD is not allowed to drop below 5V during this startup process. This UVLO hysteresis window ensures that hold-up capacitor properly supplies VDD during startup. The built-in temperature-sensing circuit shuts down PWM output if the junction temperature exceeds 140°C. Pulse-by-pulse Current Limit When the sensing voltage across the current sense resistor exceeds the internal threshold of 0.8V, the MOSFET is turned off for the remainder of switching cycle. In normal operation, the pulse-by-pulse current limit is not triggered since the peak current is limited by the control loop. Protections Leading-Edge Blanking (LEB) The FAN103 has several self-protection functions, such as Over-Voltage Protection (OVP), Over-Temperature Protection (OTP), and Pulse-by-Pulse Current limit. All the protections are implemented as auto-restart mode. Once an abnormal condition occurs, switching is terminated and the MOSFET remains off, causing VDD to drop. When VDD drops to the VDD turn-off voltage of 5V, the internal startup circuit is enabled again, then the supply current drawn from HV pin charges the hold-up capacitor. When VDD reaches the turn-on voltage of 16V, FAN103 resumes normal operation. In this manner, the auto-restart alternately enables and disables the switching of the MOSFET until the abnormal condition is eliminated (see Figure 26). Each time the power MOSFET switches on, a turn-on spike occurs at the sense resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. Conventional RC filtering can be omitted. During this blanking period, the currentlimit comparator is disabled and cannot switch off the gate driver. Gate Output The FAN103 output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 15V Zener diode to protect power MOSFET transistors against undesired over-voltage gate signals. Built-in Slope Compensation FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Under-Voltage Lockout (UVLO) The sensed voltage across the current sense resistor is used for current mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillations due to peak-current mode control. The FAN103 has a synchronized, positive-slope ramp built-in at each switching cycle. Noise Immunity Noise from the current sense or the control signal can cause significant pulse-width jitter, particularly in continuous-conduction mode. While slope compensation helps alleviate these problems, further precautions should still be taken. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the FAN103, and increasing the power MOS gate resistance is advised. Figure 26. Auto Restart Operation VDD Over-Voltage Protection (OVP) VDD over-voltage protection prevents damage from overvoltage conditions. If the VDD voltage exceeds 28V at open-loop feedback condition, OVP is triggered and the PWM switching is disabled. The OVP has a de-bounce time (typically 200µs) to prevent false triggering due to switching noises. © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 www.fairchildsemi.com 12 Application Fairchild Devices Input Voltage Range Output Output DC Cable Cell Phone Charger FAN103 90~265VAC 5V/1A (5W) AWG26, 1.8 Meter Features High efficiency (>68.17% at Full Load) Meeting EPS 2.0 Regulation with Enough Margin Low standby (Pin <30mW at No Load Condition) Tight output regulation (CV: ±5%, CC: ±5%) 6 74.00% 5 72.00% 4 70.00% 3 68.00% 66.00% 2 64.00% 1 62.00% 0.250 90Vac 115Vac 230Vac 264Vac 0 0.500 0.750 1.000 0 200 400 600 Figure 27. Measured Efficiency and Output Regulation 800 1000 1200 1400 FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Typical Application Circuit (Primary-Side-Regulated Flyback Charger) Figure 28. Schematic of Typical Application Circuit © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 www.fairchildsemi.com 13 FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Typical Application Circuit (Continued) Transformer Specification Core: EE16 Bobbin: EE16 Figure 29. Bobbin Winding Diagram Notes: 4. When W4R’s winding is reversed winding, it must wind one layer. 5. When W2 is winding, put 1 layer tape after wind first layer. TERMINAL NO W1 W2 S F 4 5 3 W3 1 W4R 7 1 Ts 2UEW 0.23*2 15 2 40 1 40 0 37 2 COPPER SHIELD 1.2 3 TEX-E 0.6*1 9 3 2UEW 0.17*1 9 INSULATION WIRE CORE ROUNDING TAPE Ts BARRIER Primary Seconds 3 Pin Specification Remark Primary-Side Inductance 1－3 1.75mH ± 5% 100kHz, 1V Primary-Side Effective Leakage 1－3 80μH ± 5% Short one of the secondary windings © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 www.fairchildsemi.com 14 5.00 4.80 A 0.65 3.81 5 8 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION 0.25 0.10 SEE DETAIL A 1.75 MAX R0.10 0.10 0.51 0.33 0.50 x 45° 0.25 C OPTION A - BEVEL EDGE GAGE PLANE R0.10 8° 0° 0.90 0.406 0.25 0.19 C FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) Physical Dimensions OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 30. 8-Lead, Small Outline Package (SOP-8) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 www.fairchildsemi.com 15 FAN103 — Primary-Side-Regulation PWM Controller (PWM-PSR) © 2010 Fairchild Semiconductor Corporation FAN103 • Rev. 1.0.3 www.fairchildsemi.com 16