Cypress CY7C408A-25VC 64 x 8 cascadable fifo 64 x 9 cascadable fifo Datasheet

1CY 7C40 9A
CY7C408A
CY7C409A
64 x 8 Cascadable FIFO
64 x 9 Cascadable FIFO
Features
•
•
•
•
•
•
•
•
•
•
•
64 x 8 and 64 x 9 first-in first-out (FIFO) buffer memory
35-MHz shift in and shift out rates
Almost Full/Almost Empty and Half Full flags
Dual-port RAM architecture
Fast (50-ns) bubble-through
Independent asynchronous inputs and outputs
Output enable (CY7C408A)
Expandable in word width and FIFO depth
5V ± 10% supply
TTL complete
Capable of withstanding greater than 2001V electrostatic discharge voltage
• 300-mil, 28-pin DIP
Functional Description
The CY7C408A and CY7C409A are 64-word deep by 8- or
9-bit wide first-in first-out (FIFO) buffer memories. In addition
to the industry-standard handshaking signals, almost full/almost empty (AFE) and half-full (HF) flags are provided.
AFE is HIGH when the FIFO is almost full or almost empty,
otherwise AFE is LOW. HF is HIGH when the FIFO is half full,
otherwise HF is LOW.
The CY7C408A has an output enable (OE) function.
The memory accepts 8- or 9-bit parallel words as its inputs (DI0
– DI8) under the control of the shift in (SI) input when the input
ready (IR) control signal is HIGH. The data is output, in the
same order as it was stored on the DO0 – DO8 output pins
under the control of the shift out (SO) input when the output
ready (OR) control signal is HIGH. If the FIFO is full (IR LOW),
pulses at the SI input are ignored; if the FIFO is empty (OR
LOW), pulses at the SO input are ignored.
The IR and OR signals are also used to connect the FIFOs in
parallel to make a wider word or in series to make a deeper
buffer, or both.
Parallel expansion for wider words is implemented by logically
ANDing the IR an OR outputs (respectively) of the individual
FIFOs together (Figure 5). The AND operation insures that all
of the FIFOs are either ready to accept more data (IR HIGH)
or ready to output data (OR HIGH) and thus compensate for
variations in propagation delay times between devices.
Serial expansion (cascading) for deeper buffer memories is
accomplished by connecting data outputs of the FIFO closet
to the data source (upstream device) to the data inputs of the
following (downstream) FIFO (Figure 4). In addition, to insure
proper operation, the SO signal of the upstream FIFO must be
connected to the OR output of the upstream FIFO. In this serial
expansion configuration, the IR and OR signals are used to
pass data through the FIFOs.
Reading and writing operations are completely asynchronous,
allowing the FIFO to be used as a buffer between two digital
machines of widely differing operating frequencies. The high
shift in and shift out rates of these FIFOs, and their throughput
rate due to the fast bubblethrough time, which is due to their
dual-port RAM architecture, make them ideal for high-speed
communications and controllers.
Pin Configurations
Logic Block Diagram
SI
IR
INPUT
CONTROL
LOGIC
DI 0
.
.
.
DI 7
(7C409A)DI 8
DATA IN
MR
MASTER
RESET
WRITE POINTER
ALMOST FULL/
ALMOST EMPTY
WRITEMULTIPLEXER
HALF FULL
AFE
HF
IR
SI
AFE
HF
DI 0
DI 1
GND
DO 0
.
.
.
DO 7
MEMORY
ARRAY
DI 2
DI 3
DO 8 (7C409A)
DI 4
DI 5
DI 6
OE (7C408A)
DI 7
OR
(7C408A) NC
(7C409A) DI8
SO
DATAOUT
READ MULTIPLEXER
OUTPUT
CONTROL
LOGIC
READ POINTER
1
28
2
27
3
26
4
25
5
24
6
23
7C408A
7 7C409A 22
21
8
9
20
10
19
11
18
12
17
13
16
15
14
VCC
MR
SO
OR
DO0
DO1
GND
DO2
DO3
DO4
DO5
DO6
DO7
OE (7C408A)
DO8 (7C409A)
C408A–3
C408A–1
Flag Definitions
HF
AFE
Words Stored
L
H
0-8
L
L
9 - 31
H
L
32 - 55
H
H
56 - 64
Cypress Semiconductor Corporation
•
3901 North First Street
DI 0
DI 1
GND
DI 2
DI 3
DI 4
DI 5
4 3 2 1 28 27 26
25
5
24
6
23
7
7C408A
22
8
7C409A
21
9
20
10
19
11
12 13 14 15 1617 18
OR
DO 0
DO 1
GND
DO 2
DO 3
DO 4
C408A–2
•
San Jose
•
CA 95134 •
408-943-2600
July 1986 – Revised July 1994
CY7C408A
CY7C409A
Selection Guide
7C408A-15
7C409A-15
Maximum Shift Rate (MHz)
Maximum Operating
Current (mA)[1]
7C408A-25
7C409A-25
7C408A-35
7C409A-35
15
25
35
Commercial
115
125
135
Military
140
150
N/A
Power Dissipation.......................................................... 1.0W
Maximum Ratings
Output Current, into Outputs (Low) ............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Supply Voltage to Ground Potential .................−0.5V to +7.0V
Range
DC Voltage Applied to Outputs
in High Z State (7C408A)...................................−0.5V to +7.0V
Commercial
Military[2]
DC Input Voltage .................................................−3.0V to +7.0V
Ambient
Temperature
VCC
0°C to +70°C
5V ±10%
−55°C to +125°C
5V ±10%
Electrical Characteristics Over the Operating Range (Unless Otherwise Noted) [3]
Parameter
Description
Test Conditions
Min.
Max.
Unit
0.4
V
VOH
Output HIGH Voltage
VCC = Min., IOH = –4.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 8.0 mA
VIH
Input HIGH Voltage
2.2
VCC
V
VIL
Input LOW Voltage
−3.0
0.8
V
IIX
Input Leakage Current
GND < VI < VCC
−10
+10
µA
IOS
Output Short Circuit Current[4]
VCC = Max., VOUT = GND
−90
mA
ICCQ
Quiescent Power Supply Current
VCC = Max., IOUT = 0 mA
VIN < VIL, VIN > VIH
Commercial
100
mA
Military
125
V
ICC = ICCQ + 1 mA/MHz × (fSI + fSO)/2
Power Supply Current
ICC
2.4
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
Max.
Unit
5
pF
7
pF
TA = 25°C, f = 1 MHz,
VCC = 4.5V
Notes:
1.
2.
3.
4.
5.
ICC = ICCQ + 1 mA/MHz × (fSI + fSO )/2
TA is the “instant on” case temperature.
See the last page of this specification for Group A subgroup testing information.
For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
R1 482Ω
R1 482Ω
5V
5V
OUTPUT
OUTPUT
30 pF
CL
INCLUDING
JIG AND
SCOPE
R2
256Ω
90%
R2
256Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
3.0V
≤ 5 ns
THÉVENIN EQUIVALENT
167Ω
OUTPUT
1.73V
90%
10%
≤ 5 ns
(b)
C408A–4
Equivalent to:
GND
10%
C408A–6
2
C408A–5
CY7C408A
CY7C409A
Switching Characteristics Over the Operating Range[3, 6]
Parameter
Description
Test
Conditions
7C408A-15
7C409A-15
Min.
Max.
7C408A-25
7C409A-25
Min.
15
Max.
7C408A-35
7C409A-35
Min.
25
Max.
Unit
35
MHz
fO
Operating Frequency
Note 7
tPHSI
SI HIGH Time
Note 7
23
11
9
ns
tPLSI
SI LOW Time
Note 7
25
24
17
ns
tSSI
Data Set-Up to SI
Note 8
0
0
0
ns
tHSI
Data Hold from SI
Note 8
30
tDLIR
Delay, SI HIGH to IR LOW
tDHIR
Delay, SI LOW to IR HIGH
tPHSO
SO HIGH Time
Note 7
23
tPLSO
SO LOW Time
Note 7
25
tDLOR
Delay, SO HIGH to OR LOW
tDHOR
Delay, SO LOW to OR HIGH
tSOR
Data Set-Up to OR HIGH
tHSO
Data Hold from SO LOW
0
tBT
Fall-through, Bubble-back Time
10
tSIR
Data Set-Up to IR
Note 9
5
5
5
ns
tHIR
Data Hold from IR
Note 9
30
20
20
ns
tPIR
Input Ready Pulse HIGH
Note 10
6
6
6
ns
tPOR
Output Ready Pulse HIGH
Note 11
6
6
6
ns
tDLZOE
OE LOW to LOW Z (7C408A)
Note 12
35
30
25
ns
tDHZOE
OE HIGH to HIGH Z (7C408A)
Note 7
35
30
25
ns
tDHHF
SI LOW to HF HIGH
65
55
45
ns
tDLHF
SO LOW to HF LOW
65
55
45
ns
tDLAFE
SO or SI LOW to AFE LOW
65
55
45
ns
tDHAFE
SO or SI LOW to AFE HIGH
65
55
45
ns
tPMR
MR Pulse Width
55
45
35
ns
tDSI
MR HIGH to SI HIGH
25
10
10
ns
tDOR
MR LOW to OR LOW
55
45
35
ns
tDIR
MR LOW to IR HIGH
55
45
35
ns
tLZMR
MR LOW to Output LOW
55
45
35
ns
tAFE
MR LOW to AFE HIGH
55
45
35
ns
tHF
MR LOW to HF LOW
55
45
35
ns
tOD
SO LOW to Next Data Out Valid
28
20
16
ns
20
35
40
23
11
23
0
10
16
ns
ns
ns
15
ns
16
ns
0
0
65
ns
17
21
40
0
ns
15
9
24
35
Note 13
12
21
ns
0
60
10
ns
50
ns
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V and output loading of the specified I OL/IOH and 30-pF load
capacitance, as in parts (a) and (b) of AC Test Loads and Waveforms.
7. 1/f O > (tPHSI + tPLSI ), 1/fO > (tPHSO + tPLSO).
8. tSSI and tHSI apply when memory is not full.
9. tSIR and tHIR apply when memory is full, SI is high and minimum bubble-through (tBT) conditions exist.
10. At any given operating condition tPIR > (t PHSO required).
11. At any given operating condition tPOR > (tPHSI required).
12. tDHZOE and tDLZOE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. tDHZOE transition is measured ±500 mV from steady-state
voltage. tDLZOE transition is measured ±100 mV from steady-state voltage. These parameters are guaranteed and not 100% tested.
13. All data outputs will be at LOW level after reset goes HIGH until data is entered into the FIFO.
3
CY7C408A
CY7C409A
Switching Waveforms
Data In Timing Diagram
I/fO
I/fO
SHIFT IN
NOTE 14
tPHSI
tPLSI
tDHIR
INPUT READY
tHSI
tDLIR
DATA IN
tSSI
tDLAFE
AFE
HF
(LOW)
C408A–7
Data Out Timing Diagram
I/fO
I/fO
SHIFT OUT
NOTE 15
tPHSO
tPLSO
tDHOR
OUTPUT READY
tDLOR
tHSO
tSOR
DATA OUT
tOD
HF
(LOW)
tDHAFE
AFE
C408A–8
Notes:
14. FIFO contains 8 words.
15. FIFO contains 9 words.
4
CY7C408A
CY7C409A
Switching Waveforms (continued)
Data In Timing Diagram
I/fO
I/fO
SHIFT IN
NOTE 16
tPHSI
tPLSI
tDHIR
INPUT READY
tHSI
tDLIR
DATA IN
tSSI
AFE
(LOW)
tDHHF
HF
C408A–9
Data Out Timing Diagram
I/fO
I/fO
SHIFT OUT
NOTE 17
tPHSO
tPLSO
tDHOR
OUTPUT READY
tDLOR
tHSO
tSOR
DATA OUT
tOD
HF
tDLHF
AFE
(LOW)
C408A–10
Output Enable (CY7C408A only)
OUTPUT ENABLE
tDHZOE
DATA OUT
tDLZOE
NOTE 12
C408A–11
Notes:
16. FIFO contains 31 words.
17. FIFO contains 32 words.
5
CY7C408A
CY7C409A
Switching Waveforms (continued)
Data In Timing Diagram
I/fO
I/fO
SHIFT IN
NOTE 18
tPHSI
tPLSI
tDHIR
INPUT READY
tDLIR
tHSI
DATA IN
tSSI
HF
(HIGH)
tDHAFE
AFE
C408A–12
Data Out TimingDiagram
I/fO
I/fO
SHIFT OUT
NOTE 19
tPHSO
tPLSO
tDHOR
OUTPUT READY
tDLOR
tHSO
tSOR
DATA OUT
tOD
AFE
tDLAFE
HF
(HIGH)
C408A–13
Bubble-Back, Data Out To Data In Diagram
SHIFT OUT NOTE 20
SHIFT IN
tBT
INPUT READY
tPIR
DATA IN
tSIR
Notes:
18. FIFO contains 55 words.
19. FIFO contains 56 words.
20. FIFO contains 64 words.
6
tHIR
C408A–14
CY7C408A
CY7C409A
Switching Waveforms (continued)
Fall-Through, Data In to Data Out Diagram
SHIFT IN
NOTE 21
SHIFT OUT
tPOR
tBT
OUTPUT READY
tSOR
DATA OUT
C408A–15
Master Reset Timing Diagram
tPMR
MASTER RESET
tDIR
INPUT READY
tDOR
OUTPUT READY
tDSI
SHIFT IN
tLZMR
DATA OUT
HF
tHF
AFE
tAFE
C408A–16
Notes:
21. FIFO is empty.
7
CY7C408A
CY7C409A
Architecture of the CY7C408A and CY7C409A
tion, which is signified by the OR signal being LOW at the
same time that the IR signal is HIGH. In this condition, the data
outputs (DO0 – DO8) will be LOW. The AFE flag will be HIGH
and the HF flag will be LOW.
The CY7C408A and CY7C409A FIFOs consist of an array of
64 words of 8 or 9 bits each (which are implemented using a
dual-port RAM cell), a write pointer, a read pointer, and the
control logic necessary to generate the handshaking (SI/IR,
SO/OR) signals as well as the almost full/almost empty (AFE)
and half full (HF) flags. The handshaking signals operate in a
manner identical to those of the industry standard
CY7C401/402/403/404 FIFOs.
Shifting Data Into the FIFO
The availability of an empty location is indicated by the HIGH
state of the input ready (IR) signal. When IR is HIGH a LOW
to HIGH transition on the shift in (SI) pin will clock the data on
the DI0 - DI8 inputs into the FIFO. Data propagates through the
device at the falling edge of SI.
Dual-Port RAM
The IR output will then go LOW, indicating that the data has
been sampled. The HIGH-to-LOW transition of the SI signal
initiates the LOW-to-HIGH transition of the IR signal if the FIFO
is not full. If the FIFO is full, IR will remain LOW.
The dual-port RAM architecture refers to the basic memory
cell used in the RAM. The cell itself enables the read and write
operations to be independent of each other, which is necessary to achieve truly asynchronous operation of the inputs and
outputs. A second benefit is that the time required to increment
the read and write pointers is much less than the time that
would be required for data to propagate through the memory,
which it would have to do if the memory were implemented
using the conventional register array architecture.
Shifting Data Out of the FIFO
The availability of data at the outputs of the FIFO is indicated
by the HIGH state of the output ready (OR) signal. After the
FIFO is reset all data outputs (DO0 – DO8) will be in the LOW
state. As long as the FIFO remains empty, the OR signal will
be LOW and all SO pulses applied to it will be ignored. After
data is shifted into the FIFO, the OR signal will go HIGH. The
external control logic (designed by the user) should use the
HIGH state of the OR signal to generate a SO pulse. The data
outputs of the FIFO should be sampled with edge-sensitive
type D flip-flops (or equivalent), using the SO signal as the
clock input to the flip-flop.
Fall-Through and Bubble-Back
The time required for data to propagate from the input to the
output of an initially empty FIFO is defined as the fall-through
time.
The time required for an empty location to propagate from the
output to the input of an initially full FIFO is defined as the
bubble-back time.
AFE and HF Flags
The maximum rate at which data can be passed through the
FIFO (called the throughput) is limited by the fall-through time
when it is empty (or near empty) and by the bubble-back time
when it is full (or near full).
Two flags, almost full/almost empty (AFE) and half full (HF),
describe how many words are stored in the FIFO. AFE is HIGH
when there are 8 or fewer or 56 or more words stored in the
FIFO. Otherwise the AFE flag is LOW. HF is HIGH when there
are 32 or more words stored in the FIFO, otherwise the HF flag
is LOW. Flag transitions occur relative to the falling edges of
SI and SO (Figures 1 and 2).
The conventional definitions of fall-through and bubble-back
do not apply to the CY7C408A and CY7C409A FIFOs because the data is not physically propagated through the memory. The read and write pointers are incremented instead of
moving the data. However, the parameter is specified because
it does represent the worst-case propagation delay for the control signals. That is, the time required to increment the write
pointer and propagate a signal from the SI input to the OR
output of an empty FIFO or the time required to increment the
read pointer and propagate a signal from the SO input to the
IR output of a full FIFO.
Due to the asynchronous nature of the SI and SO signals, it is
possible to encounter specific timing relationships which may
cause short pulses on the AFE and HF flags. These pulses are
entirely due to the dynamic relationship of the SI and SO signals. The flags, however, will always settle to their correct state
after the appropriate delay (tDHAFE, tDLAFE, tDHHF, or tDLHF).
Therefore, use of level-sensitive rather than edge-sensitive
flag detection devices is recommended to avoid false flag encoding.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a master reset
(MR) signal. This causes the device to enter the empty condiEMPTY
1
2
8
9
10
31
32
33
55
56
57
FULL
64
SHIFT IN
HF
AFE
C408A–17
Figure 1. Shifting Words In.
8
CY7C408A
CY7C409A
Possible Minimum Pulse Width Violation at the Boundary
Conditions
3). Two things should be noted when this configuration is implemented.
If the handshaking signals IR and OR are not properly used to
generate the SI and SO signals, it is possible to violate the
minimum (effective) SI and SO positive pulse widths at the full
and empty boundaries.
Secondly, the frequency at the cascade interface is less than
the 35 MHz rate at which the external clocks may operate.
Therefore, the first device has its data shifted in faster than it
is shifted out, and eventually this device becomes momentarily
full. When this occurs, the maximum sustainable external
clock frequency changes from 35 MHz to the cascade interface frequency.[28]
Cascading the 7C408/9A-35 Above 25 MHz
First, the capacity of N cascaded FIFOs is decreased from N
× 64 to (N × 63) + 1.
When data packets[29] are transmitted, this phenomenon does
not occur unless more than three FIFOs are depth cascaded.
For example, if two FIFOs are cascaded, a packet of 127 (=2
× 63 + 1) words may be shifted in at up to 35 MHz and then
the entire packet may be shifted out at up to 35 MHz.
If cascaded FIFOs are to be operated with an external clock
rate greater than 25 MHz, the interface IR signal must be inverted before being fed back to the interface SO pin (Figure
FULL
64
63
56
55
54
32
31
30
9
8
EMPTY
1
7
SHIFT OUT
HF
AFE
C408A–18
Figure 2. Shifting Words Out.
A
IR
IRX
SI
SIX
C
B
IR
SO
IR
SO
IR
SO
SOX
SI
OR
SI
OR
SI
OR
ORX
DIN
DINX
DOUTX
1
2
N
UPSTREAM
DOWNSTREAM
C408A–19
Figure 3. Cascaded Configuration Above 25 MHz.
128 x 9 Configuration
HF/AFE
HF/AFE
SHIFT IN
INPUT READY
DATA IN
SI
IR
OR
SO
DO0
DI0
DO0
DO1
DI1
DO1
DI2
DO2
DI2
DO2
DI3
DI4
DO3
DO4
DI3
DI4
DO3
DO4
DI5
DO5
DI5
DO5
DI6
DI7
DI8
DO6
DI6
DI7
DI8
DO6
SI
IR
OR
SO
DI0
DI1
MR
DO7
DO8
MR
OUTPUT READY
SHIFT OUT
DATA OUT
DO7
DO8
C408A–20
MR
Figure 4. Cascaded Configuration at or below 25 MHz [22,23,24,25,26].
9
CY7C408A
CY7C409A
192 x 27 Configuration
HF/AFE
HF/AFE
IR
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
MR
SO
OR
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
IR
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
MR
SO
OR
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
IR
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
MR
SO
OR
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
COMPOSITE
INPUT READY
IR
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
SHIFT IN
IR
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
MR
MR
SO
OR
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
IR
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
SO
OR
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
IR
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
MR
MR
SO
OR
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
IR
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
SO
OR
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
IR
SI
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
MR
MR
SO
OR
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
SHIFT OUT
COMPOSITE
OUTPUT READY
SO
OR
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
MR
C408A–21
Figure 5. Depth and Width Expansion[23,24,25,26,27].
Notes:
22. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the
devices.
23. When the memory is empty the last word read will remain on the outputs until the master reset is strobed or a new data word falls through to the output.
24. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until
the new data has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.
25. If SO is held HIGH while the memory is empty and a word is written into the input, that word will fall through the memory to the output. OR will go HIGH for
one internal cycle (at least tPOR) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will
line up behind the first word and will not appear on the outputs until SO has been brought LOW.
26. When the master reset is brought LOW, the outputs are cleared to LOW, IR goes HIGH, and OR goes LOW.
27. FIFOs are expandable in depth and width. However, in forming wider words, two external gates are required to generate composite input ready and output
ready flags. This need is due to the variation of delays of the FIFOs
28. Because the data throughput in the cascade interface is dependent on the inverter delay, it is recommended that the fastest available inverter be used.
29. Transmission of data packets assumes that up to the maximum cumulative capacity of the FIFOs is shifted in without simultaneous shift out clock occurring.
The complement of this holds when data is shifted out as a packet.
10
CY7C408A
CY7C409A
The exact complement of this occurs if the FIFOs initially contain data and a high shift out frequency is to be maintained,
i.e., a 35 MHz fSOx can be sustained when reading data packets from devices cascaded two or three deep.[31] If data is
shifted in simultaneously, Figure 6 applies with fSIx and fSOx
interchanged.
If data is to be shifted out simultaneously with the data being
shifted in, the concept of “virtual capacity” is introduced. Virtual
capacity is simply how large a packet of data can be shifted in
at a fixed frequency, e.g., 35 MHz, simultaneously with data
being shifted out at any given frequency. Figure 6 is a graph
of packet size[30] vs. shift out frequency (f SOx) for two different
values of shift in frequency (fSIx) when two FIFOs are
cascaded.
400
350
fSIx =30MHz
300
250
200
150
fSIx =35MHz
100
50
0
0
4
8 12 16 20 24 28 32 36
OUTPUT RATE(fSOx) OF BOTTOM FIFO (MHz)
C408A–22
Figure 6. Virtual Capacity vs. Output Rate for Two FIFOs Cascaded Using an Inverter.
Notes:
30. These are typical packet sizes using an inverter whose delay is 4 ns.
31. Only devices with the same speed grade are specified to cascade together.
11
CY7C408A
CY7C409A
Typical DC and AC Characteristics
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
1.4
1.0
1.2
60
50
40
0.8
1.0
0.6
4.5
5.0
20
0.8
VIN =5.0V
TA =25°C
0.4
4.0
30
5.5
6.0
VCC =5.5V
VIN =5.0V
0.0
-55
25
0
0.0
125
1.0
AMBIENT TEMPERATURE (°C)
SUPPLYVOLTAGE(V)
1.3
1.6
1.2
1.4
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
NORMALIZED FREQUENCY
vs. AMBIENT TEMPERATURE
NORMALIZED FREQUENCY
vs. SUPPLY VOLTAGE
140
120
100
1.1
1.2
80
1.0
60
1.0
0.9
40
0.8
0.8
0.7
4.0
VCC =5.0V
TA =25°C
10
4.5
5.0
5.5
6.0
VCC =5.0V
TA =25°C
20
0.6
-55
25
0
0.0
125
1.0
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
TYPICAL FREQUENCY CHANGE
vs. OUTPUT LOADING
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
NORMALIZED I CC
vs. FREQUENCY
1.6
1.1
1.5
1.0
1.4
0.9
1.3
0.8
1.2
0.7
1.1
1.0
0.0
0
200
400
600
0
800 1000
5
10
15
20
25
30
35
C408A–23
FREQUENCY (MHz)
CAPACITANCE (pF)
12
CY7C408A
CY7C409A
Ordering Information
Frequency
(MHz)
15
25
35
Frequency
(MHz)
15
25
35
Ordering Code
CY7C408A-15PC
Package
Name
Package Type
P21
28-Lead (300-Mil) Molded DIP
CY7C408A-15VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C408A-15DMB
D22
28-Lead (300-Mil) CerDIP
CY7C408A-15LMB
L64
28-Square Leadless Chip Carrier
CY7C408A-25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C408A-25VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C408A-25DMB
D22
28-Lead (300-Mil) CerDIP
CY7C408A-25LMB
L64
28-Square Leadless Chip Carrier
CY7C408A-35PC
P21
28-Lead (300-Mil) Molded DIP
CY7C408A-35VC
V21
28-Lead (300-Mil) Molded SOJ
Ordering Code
CY7C409A-15PC
Package
Name
Package Type
P21
28-Lead (300-Mil) Molded DIP
CY7C409A-15VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C409A-15DMB
D22
28-Lead (300-Mil) CerDIP
CY7C409A-15LMB
L64
28-Square Leadless Chip Carrier
CY7C409A-25PC
P21
28-Lead (300-Mil) Molded DIP
CY7C409A-25VC
V21
28-Lead (300-Mil) Molded SOJ
CY7C409A-25DMB
D22
28-Lead (300-Mil) CerDIP
CY7C409A-25LMB
L64
28-Square Leadless Chip Carrier
CY7C409A-35PC
P21
28-Lead (300-Mil) Molded DIP
CY7C409A-35VC
V21
28-Lead (300-Mil) Molded SOJ
13
Operating
Range
Commercial
Military
Commercial
Military
Commercial
Operating
Range
Commercial
Military
Commercial
Military
Commercial
CY7C408A
CY7C409A
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Parameters
Switching Characteristics
Subgroups
Parameters
Subgroups
VOH
1, 2, 3
fO
7, 8, 9, 10, 11
VOL
1, 2, 3
tPHSI
7, 8, 9, 10, 11
VIH
1, 2, 3
tPLSI
7, 8, 9, 10, 11
VIL Max.
1, 2, 3
tSSI
7, 8, 9, 10, 11
IIX
1, 2, 3
tHSI
7, 8, 9, 10, 11
IOZ
1, 2, 3
tDLIR
7, 8, 9, 10, 11
IOS
1, 2, 3
tDHIR
7, 8, 9, 10, 11
ICCQ
1, 2, 3
tPHSO
7, 8, 9, 10, 11
tPLSO
7, 8, 9, 10, 11
tDLOR
7, 8, 9, 10, 11
tDHOR
7, 8, 9, 10, 11
tSOR
7, 8, 9, 10, 11
tHSO
7, 8, 9, 10, 11
tBT
7, 8, 9, 10, 11
tSIR
7, 8, 9, 10, 11
tHIR
7, 8, 9, 10, 11
tPIR
7, 8, 9, 10, 11
tPOR
7, 8, 9, 10, 11
tSIIR
7, 8, 9, 10, 11
tSOOR
7, 8, 9, 10, 11
tDLZOE
7, 8, 9, 10, 11
tDHZOE
7, 8, 9, 10, 11
tDHHF
7, 8, 9, 10, 11
tDLHF
7, 8, 9, 10, 11
tDLAFE
7, 8, 9, 10, 11
tDHAFE
7, 8, 9, 10, 11
tB
7, 8, 9, 10, 11
tOD
7, 8, 9, 10, 11
tPMR
7, 8, 9, 10, 11
tDSI
7, 8, 9, 10, 11
tDOR
7, 8, 9, 10, 11
tDIR
7, 8, 9, 10, 11
tLZMR
7, 8, 9, 10, 11
tAFE
7, 8, 9, 10, 11
tHF
7, 8, 9, 10, 11
Document #: 38-00059-G
14
CY7C408A
CY7C409A
Package Diagrams
28-Lead (300-Mil) CerDIP D22
MIL-STD-1835
28-Square Leadless Chip Carrier L64
D-15 Config.A
MIL-STD-1835 C-4
28-Lead (300-Mil) Molded DIP P21
15
CY7C408A
CY7C409A
Package Diagrams (continued)
28-Lead (300-Mil) Molded SOJ V21
© Cypress Semiconductor Corporation, 1994. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.