AD AD8366 Dual-digital variable gain amplifier Datasheet

DC to 600 MHz,
Dual-Digital Variable Gain Amplifiers
AD8366
Data Sheet
SENB
OPMA
OPPA
VPSOA
VCMA
CCMA
DECA
VPSIA
BIT0/CS
IPPA
BIT1/SDAT
IPMA
BIT2/SCLK
BIT3
ENBL
DIGITAL GAIN
CONTROL LOGIC
ICOM
OCOM
IPMB
BIT4
IPPB
BIT 5
DENB
OPMB
OPPB
VPSOB
VCMB
CCMB
OFSB
07584-001
DENA
VPSIB
DECB
Matched pair of differential, digitally controlled VGAs
Gain range: 4.5 dB to 20.25 dB
0.25 dB gain step size
Operating frequency
DC to 150 MHz (2 V p-p)
3 dB bandwidth: 600 MHz
Noise figure (NF)
11.4 dB at 10 MHz at maximum gain
18 dB at 10 MHz at minimum gain
OIP3: 45 dBm at 10 MHz
HD2/HD3
Better than −90 dBc for 2 V p-p output at 10 MHz at
maximum gain
Differential input and output
Adjustable output common-mode
Optional dc output offset correction
Serial/parallel mode gain control
Power-down feature
Single 5 V supply operation
OFSA
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Figure 1.
APPLICATIONS
Baseband I/Q receivers
Diversity receivers
Wideband ADC drivers
GENERAL DESCRIPTION
The AD8366 is a matched pair of fully differential, low noise and
low distortion, digitally programmable variable gain amplifiers
(VGAs). The gain of each amplifier can be programmed separately
or simultaneously over a range of 4.5 dB to 20.25 dB in steps of
0.25 dB. The amplifier offers flat frequency performance from dc
to 70 MHz, independent of gain code.
The AD8366 offers excellent spurious-free dynamic range, suitable
for driving high resolution analog-to-digital converters (ADCs).
The NF at maximum gain is 11.4 dB at 10 MHz and increases
~2 dB for every 4 dB decrease in gain. Over the entire gain range,
the HD3/HD2 are better than −90 dBc for 2 V p-p at the output at
10 MHz into 200 Ω. The two-tone intermodulation distortion of
−90 dBc into 200 Ω translates to an OIP3 of 45 dBm (38 dBVrms).
The differential input impedance of 200 Ω provides a well-defined
termination. The differential output has a low impedance of ~25 Ω.
Rev. B
The output common-mode voltage defaults to VPOS/2 but can
be programmed via the VCMA and VCMB pins over a range
of voltages. The input common-mode voltage also defaults
to VPOS/2 but can be driven down to 1.5 V. A built-in, dc offset
compensation loop can be used to eliminate dc offsets from prior
stages in the signal chain. This loop can also be disabled if dccoupled operation is desired.
The digital interface allows for parallel or serial mode gain
programming. The AD8366 operates from a 4.75 V to 5.25 V
supply and consumes typically 180 mA. When disabled, the
part consumes roughly 3 mA. The AD8366 is fabricated using
Analog Devices, Inc., advanced silicon-germanium bipolar
process, and it is available in a 32-lead exposed paddle LFCSP
package. Performance is specified over the −40°C to +85°C
temperature range.
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AD8366
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Output Differential Offset Correction .................................... 15
Applications ....................................................................................... 1
Output Common-Mode Control ............................................. 15
Functional Block Diagram .............................................................. 1
Gain Control Interface............................................................... 16
General Description ......................................................................... 1
Applications Information .............................................................. 17
Revision History ............................................................................... 2
Basic Connections ...................................................................... 17
Specifications..................................................................................... 3
Direct Conversion Receiver Design ......................................... 18
Parallel and Serial Interface timing ............................................ 5
Quadrature Errors and Image Rejection ................................. 18
Absolute Maximum Ratings............................................................ 6
Low Frequency IMD3 Performance ........................................ 19
ESD Caution .................................................................................. 6
Baseband Interface ..................................................................... 21
Pin Configuration and Function Descriptions ............................. 7
Characterization Setups ................................................................. 22
Typical Performance Characteristics ............................................. 8
Evaluation Board ............................................................................ 25
Circuit Description ......................................................................... 15
Outline Dimensions ....................................................................... 28
Inputs ........................................................................................... 15
Ordering Guide .......................................................................... 28
Outputs ........................................................................................ 15
REVISION HISTORY
8/2017—Rev. A to Rev. B
Change to Figure 4 ........................................................................... 7
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28
3/2011—Rev. 0 to Rev. A
Changes to Table 2, Internal Power Dissipation Value ................ 6
10/2010—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
AD8366
SPECIFICATIONS
VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Bandwidth
Slew Rate
INPUT STAGE
Linear Input Swing
Differential Input Impedance
Minimum Input Common-Mode Voltage
Maximum Input Common-Mode Voltage
Test Conditions/Comments
3 dB; all gain codes
1 dB; all gain codes
Maximum gain
Minimum gain
IPPA, IPMA, IPPB, IPMB
At minimum gain AV = 4.5 dB, 1 dB gain compression
Input pins left floating
GAIN
Minimum Voltage Gain
Maximum Voltage Gain
Gain Step Size
Gain Step Accuracy
Gain Flatness
Gain Mismatch
Group Delay Flatness
Mismatch
Gain Step Response
Common-Mode Rejection Ratio
OUTPUT STAGE
Linear Output Swing
Differential Output Impedance
Output DC Offset
Minimum Output Common-Mode Voltage
Maximum Output Common-Mode Voltage
Common-Mode Setpoint Input Impedance
NOISE/DISTORTION
3 MHz
Noise Figure
Second Harmonic
Third Harmonic
OIP3 1
OIP21
Output 1 dB Compression Point1
All gain codes
All gain codes
Maximum gain, DC to 70 MHz
Channel A/Channel B at minimum/maximum gain code
All gain codes, 20% fractional bandwidth, fC < 100 MHz
Channel A and Channel B at same gain code
Maximum gain to minimum gain
Minimum gain to maximum gain
OPPA, OPMA, OPPB, OPMB, VCMA, VCMB
1 dB gain compression
Inputs shorted, offset loop disabled at
minimum/maximum gain
Inputs shorted, offset loop enabled (across all gain codes)
HD3, HD2 > −90 dBc, 2 V p-p output
HD3, HD2 > −90 dBc, 2 V p-p output
VCMA and VCMB left floating
Maximum gain
Minimum gain
2 V p-p output, maximum gain
2 V p-p output, minimum gain
2 V p-p output, maximum gain
2 V p-p output, minimum gain
2 V p-p composite, maximum gain
2 V p-p composite, minimum gain
2 V p-p composite, maximum gain
2 V p-p composite, minimum gain
Maximum gain
Minimum gain
Rev. B | Page 3 of 28
Min
Typ
Max
Unit
600
200
1100
1500
MHz
MHz
V/µs
V/µs
3.6
217
1.5
VPOS/2 + 0.075
VPOS/2
V p-p
Ω
V
V
V
4.5
20.25
0.25
±0.25
0.1
0.1
<0.5
2
30
60
−66.2
dB
dB
dB
dB
dB
dB
ns
ps
ns
ns
dB
6
28
−10/−30
V p-p
Ω
mV
10
1.6
3
VPOS/2
4
mV
V
V
V
kΩ
11.3
18.2
−82
−82
−87
−90
34
35
76
76
6.7
6.9
dB
dB
dBc
dBc
dBc
dBc
dBVrms
dBVrms
dBVrms
dBVrms
dBVrms
dBVrms
AD8366
Parameter
10 MHz
Noise Figure
Second Harmonic
Third Harmonic
OIP31
OIP21
Output 1 dB Compression Point1
50 MHz
Noise Figure
Second Harmonic
Third Harmonic
OIP31
OIP21
Output 1 dB Compression Point1
DIGITAL LOGIC
Input High Voltage, VINH
Input Low Voltage, VINL
Input Capacitance, CIN
Input Resistance, RIN
SPI INTERFACE TIMING
fSCLK
t1
t2
t3
t4
t5
t6
PARALLEL PORT TIMING
t7
t8
t9
t10
POWER AND ENABLE
Supply Voltage Range
Total Supply Current
Disable Current
Disable Threshold
Enable Response Time
Disable Response Time
1
Data Sheet
Test Conditions/Comments
Min
Typ
Max
Unit
Maximum gain
Minimum gain
2 V p-p output, maximum gain
2 V p-p output, minimum gain
2 V p-p output, maximum gain
2 V p-p output, minimum gain
2 V p-p composite, maximum gain
2 V p-p composite, minimum gain
2 V p-p composite, maximum gain
2 V p-p composite, minimum gain
Maximum gain
Minimum gain
11.4
18
−97
−96
−97
−90
38
36
72
76
7
6.7
dB
dB
dBc
dBc
dBc
dBc
dBVrms
dBVrms
dBVrms
dBVrms
dBVrms
dBVrms
Maximum gain
Minimum gain
2 V p-p output, maximum gain
2 V p-p output, minimum gain
2 V p-p output, maximum gain
2 V p-p output, minimum gain
2 V p-p composite, maximum gain
2 V p-p composite, minimum gain
2 V p-p composite, maximum gain
2 V p-p composite, minimum gain
Maximum gain
Minimum gain
SENB, DENA, DENB, BIT0, BIT1, BIT2, BIT3, BIT4, BIT5
11.8
18.2
−82
−84
−80
−71
32
26
71
78
6.7
6.7
dB
dB
dBc
dBc
dBc
dBc
dBVrms
dBVrms
dBVrms
dBVrms
dBVrms
dBVrms
2.2
1.2
1
50
V
V
pF
kΩ
44.4
7.5
7.5
15
7.5
7.5
15
MHz
ns
ns
ns
ns
ns
ns
7.5
15
7.5
7.5
ns
ns
ns
ns
SENB = high
Serial clock frequency (maximum)
CS rising edge to first SCLK rising edge (minimum)
SCLK high pulse width (minimum)
SCLK low pulse width (minimum)
SCLK falling edge to CS low (minimum)
SDAT setup time (minimum)
SDAT hold time (minimum)
SENB = low
DENA/DENB high pulse width (minimum)
DENA/DENB low pulse width (minimum)
BITx setup time (minimum)
BITx hold time (minimum)
VPSIA, VPSIB, VPSOA, VPSOB, ICOM, OCOM, ENBL
4.75
ENBL = 5 V
ENBL = 0 V
Delay following high-to-low transition until device
meets full specifications
Delay following low-to-high transition until device
produces full attenuation
To convert to dBm for a 200 Ω load impedance, add 7 dB to the dBVrms value.
Rev. B | Page 4 of 28
180
3.2
1.65
150
5.25
V
mA
mA
V
ns
3
µs
Data Sheet
AD8366
PARALLEL AND SERIAL INTERFACE TIMING
CS
t3
t2
t1
t4
SCLK
SDAT
X
t6
B-LSB
B-MSB
A-LSB
A-MSB
ALWAYS HIGH
SENB
X
07584-003
t5
Figure 2. SPI Port Timing Diagram
DENA
DENB
SENB
GAIN A
GAIN A, GAIN B
GAIN B
t10
t9
t7
t8
ALWAYS LOW
Figure 3. Parallel Port Timing Diagram
Rev. B | Page 5 of 28
07584-004
BIT[5:0]
AD8366
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltages, VPSIx and VPSOx
ENBL, SENB, DENA, DENB, BIT0, BIT1, BIT2,
BIT3, BIT4, BIT5
IPPA, IPMA, IPPB, IPMB
OPPA, OPMA, OPPB, OPMB
OFSA, OFSB
DECA, DECB, VCMA, VCMB, CCMA, CCMB
Internal Power Dissipation
θJA (With Pad Soldered to Board)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 60 sec)
Rating
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
1.4 W
45.4°C/W
150°C
−40°C to +85°C
−65°C to +150°C
300°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. B | Page 6 of 28
Data Sheet
AD8366
32
31
30
29
28
27
26
25
DECA
OFSA
CCMA
VCMA
VPSOA
OPPA
OPMA
SENB
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
AD8366
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
BIT0/CS
BIT1/SDAT
BIT2/SCLK
BIT3
OCOM
BIT4
BIT5
DENA
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO GROUND.
07584-028
DECB
OFSB
CCMB
VCMB
VPSOB
OPPB
OPMB
DENB
9
10
11
12
13
14
15
16
VPSIA
IPPA
IPMA
ENBL
ICOM
IPMB
IPPB
VPSIB
Figure 4. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 8, 13, 28
4
5, 20
Mnemonic
VPSIA, VPSIB, VPSOB,
VPSOA
IPPA, IPMA, IPMB,
IPPB
ENBL
ICOM, OCOM
9, 32
DECB, DECA
10, 31
OFSB, OFSA
11, 30
12, 29
CCMB, CCMA
VCMB, VCMA
14, 15, 26, 27
OPPB, OPMB, OPMA,
OPPA
DENB, DENA
2, 3, 6, 7
16, 17
18, 19, 21, 22, 23, 24
25
BIT5, BIT4, BIT3,
BIT2/SCLK, BIT1/SDAT,
BIT0/CS
SENB
EPAD
Description
Input and Output Stage Positive Supply Voltage (4.75 V to 5.25 V).
Differential Inputs.
Chip Enable. Pull this pin high to enable.
Input and Output Ground Pins. Connect these pins via the lowest possible impedance to
ground.
VPOS/2 Reference Decoupling Node. Connect a decoupling capacitor from these nodes to
ground.
Output Offset Correction Loop Compensation. Connect a capacitor from these nodes to
ground to enable the correction loop. Tie this pin to ground to disable.
Connect These Nodes to Ground.
Output Common-Mode Setpoint. These pins default to VPOS/2 if left open. Drive these pins
from a low impedance source to change the output common-mode voltage.
Differential Outputs.
Data Enable. Pull these pins high to address each or both channels for parallel gain
programming. These pins are not used in serial mode.
Parallel Data Path (When SENB Is Low). When SENB is high, BIT0 becomes a chip select (CS),
BIT1 becomes a serial data input (SDAT), and BIT2 becomes a serial clock (SCLK). BIT3 to BIT5
are not used in serial mode.
Serial Interface Enable. Pull this pin high for serial gain programming mode and pull this pin low
for parallel gain programming mode.
The exposed pad must be connected to ground.
Rev. B | Page 7 of 28
AD8366
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, ZS = 200 Ω, ZL = 200 Ω, f = 10 MHz, unless otherwise noted.
22
0.5
20
0.4
GAIN ERROR (dB)
16
14
12
10
0
–0.1
–0.3
6
–0.4
10
15
20
25
30
35
40
45
50
55
–0.5
07584-005
5
60
GAIN CODE
0
5
10
15
20
30
25
35
40
45
50
55
60
GAIN CODE
07584-006
–0.2
0
Figure 8. Gain Error vs. Gain Code, Error Normalized to 10 MHz
Figure 5. Gain vs. Gain Code at 500 kHz, 3 MHz, 10 MHz, and 50 MHz
21.0
25
20.8
GAIN CODE 63
20
20.6
GAIN CODE 48
15
20.4
10
GAIN CODE 16
5
GAIN CODE 00
GAIN (dB)
GAIN CODE 32
20.2
20.0
19.8
19.6
0
19.4
5
–10
100k
10M
1M
1G
100M
FREQUENCY (Hz)
19.0
–40 –30 –20 –10
PHASE MISMATCH (Degrees)
30
GAIN CODE
40
50
60
07584-008
20
30
40
50
60
70
80
Figure 9. Gain vs. Temperature at Maximum Gain at 10 MHz
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
10
20
TEMPERATURE (°C)
Figure 6. Frequency Response vs. Gain Code
0
10
0
07584-017
19.2
07584-007
GAIN CHANNEL A, GAIN CHANNEL B (dB)
0.1
8
4
AMPLITUDE MISMATCH (dB)
0.2
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
0
10
20
30
GAIN CODE
Figure 7. Channel A-to-Channel B Amplitude Mismatch vs. Gain Code,
2 V p-p Output
Rev. B | Page 8 of 28
40
50
60
07584-009
GAIN (dB)
0.3
TA = +85°C
TA = +25°C
TA = –40°C
18
FREQUENCY = 3MHz
FREQUENCY = 50MHz
TA = +85°C
TA = +25°C
TA = –40°C
Figure 10. Channel A-to-Channel B Phase Mismatch vs. Gain Code,
2 V p-p Output
20
20
18
18
16
16
16
14
14
14
14
12
12
12
12
10
10
10
10
8
8
8
8
6
6
6
6
4
4
4
4
2
2
2
2
0
0
5
10
15
20
25
30
35
40
45
50
55
OP1dB (dBm)
07584-030
0
OP1dB (dBVrms)
18
0
60
GAIN CODE
FREQUENCY (MHz)
Figure 14. OP1dB vs. Frequency at Gain Code 0 and Gain Code 63
60
50
45
55
45
40
50
40
35
45
35
30
40
25
35
20
30
15
25
15
20
10
15
5
10
0
5
FREQUENCY = 10MHz
FREQUENCY = 50MHz
0
0
5
10
15
20
25
30
35
40
45
50
55
OIP3 (dBm)
07584-039
TA = +85°C
TA = +25°C
TA = –40°C
OIP3 (dBVrms)
50
10
60
GAIN CODE
Figure 12. OIP3 vs. Gain Code at 10 MHz and 50 MHz Frequency, 2 V p-p
Composite Output
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
0
Figure 11. OP1dB vs. Gain Code at 500 kHz, 3 MHz, 10 MHz, and 50 MHz
GAIN CODE 63
GAIN CODE 32
30
25
20
GAIN CODE 0
TA = +85°C
TA = +25°C
TA = –40°C
0
TA = +85°C
TA = +25°C
TA = –40°C
CHANNEL A
CHANNEL B
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
FREQUENCY (MHz)
Figure 15. OIP3 vs. Frequency, Gain Code 0, Gain Code 32, and Gain Code 63,
2 V p-p Composite Output
0
–10
FREQUENCY = 10MHz
FREQUENCY = 50MHz
CHANNEL A
CHANNEL B
TA = +85°C
TA = +25°C
TA = –40°C
–10
–20
GAIN CODE 0
–30
–30
IMD3 (dBc)
–40
IMD3 (dBc)
–50
–60
–50
–70
–70
–80
GAIN CODE 32
GAIN CODE 63
–90
–90
–110
–110
0
5
10
15
20
25
30
35
GAIN CODE
40
45
50
55
60
10
20
30
40
50
60
70
80
90 100 110 120 130 140 150
FREQUENCY (MHz)
Figure 13. Two-Tone Output IMD3 vs. Gain Code at 10 MHz and 50 MHz
Frequency, 2 V p-p Composite Output
Rev. B | Page 9 of 28
Figure 16. Two-Tone Output IMD3 vs. Frequency at Gain Code 0,
Gain Code 32, and Gain Code 63, 2 V p-p Composite Output
07584-040
–100
07584-042
OIP3 (dBm)
GAIN CODE 0
GAIN CODE 63
TA = +85°C
TA = +25°C
TA = –40°C
16
18
OP1dB (dBm)
20
07584-029
TA = +85°C
TA = +25°C
TA = –40°C
07584-041
20
AD8366
OP1dB (dBVrms)
Data Sheet
AD8366
Data Sheet
100
100
100
90
90
90
80
80
80
70
70
70
60
60
50
50
40
40
30
30
30
20
20
20
10
10
0
0
5
10
FREQUENCY = 10MHz
FREQUENCY = 50MHz
20
15
25
30
35
40
45
50
55
OIP2 (dBm)
OIP2 (dBVrms)
0
50
40
60
GAIN CODE
0
10
20
30
40
CHANNEL A
CHANNEL B
50
60
70
80
90 100 110 120 130 140 150
Figure 20. OIP2 vs. Frequency at Gain Code 0 and Gain Code 63, 2 V p-p
Composite Output
0
0
FREQUENCY = 10MHz
FREQUENCY = 50MHz
–20
–30
–30
–40
–40
IMD2 (dBc)
–20
–60
–50
–60
–70
–70
–80
–80
–90
–100
10
15
20
25
30
35
40
45
50
55
60
GAIN CODE
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
FREQUENCY (MHz)
Figure 21. Two-Tone Output IMD2 vs. Frequency,
Gain Code 0 and Gain Code 63, 2 V p-p Composite Output
Figure 18. Two-Tone Output IMD2 vs. Gain Code at 10 MHz and 50 MHz
Frequency, 2 V p-p Composite Output
0
GAIN CODE 0
–10 GAIN CODE 32
GAIN CODE 63
–20
GAIN CODE 63
0
HD2
HD3
–10
–20
HD2, GAIN CODE 0 (dBc)
–30
–40
–50
–60
–70
–80
–90
CHANNEL A
CHANNEL B
TA = +85°C
TA = +25°C
TA = –40°C
0
–10
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–90
–80
–110
–100
–90
–120
–110
1.0
1
10
100
FREQUENCY (MHz)
1000
07584-032
–100
Figure 19. Harmonic Distortion vs. Frequency at Gain Code 0, Gain Code 32,
and Gain Code 63, 2 V p-p Output
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
HD3, GAIN CODE 0 (dBc)
5
07584-045
–90
–100
0
GAIN CODE 0
07584-052
–50
CHANNEL A
CHANNEL B
TA = +85°C
TA = +25°C
TA = –40°C
–10
–100
3.0
VCMA, VCMB (V)
Figure 22. HD3/HD2 vs. VOCM at 10 MHz, Gain Code 0, 2 V p-p Output
Rev. B | Page 10 of 28
07584-023
TA = +85°C
TA = +25°C
TA = –40°C
–10
IMD2 (dBc)
TA = +85°C
TA = +25°C
TA = –40°C
FREQUENCY (MHz)
Figure 17. OIP2 vs. Gain Code at 10 MHz and 50 MHz Frequency,
2 V p-p Composite Output
HD2, HD3 (dBc)
GAIN CODE 0
07584-043
TA = +85°C
TA = +25°C
TA = –40°C
10
60
07584-044
OIP2 (dBm)
GAIN CODE 63
Data Sheet
AD8366
0
60
–10
50
TA = +85°C
TA = +25°C
TA = –40°C
GAIN CODE 0
GAIN CODE 63
–20
–30
–40
IMD3 (dBc)
OIP3 (dBm)
40
30
–50
–60
–70
20
–80
–90
–2
–100
GAIN CODE 0
GAIN CODE 63
–1
0
1
2
3
5
4
POUT PER TONE (dBm)
Figure 23. OIP3 vs. Output Power (POUT) at Minimum and Maximum Gain
Codes, 10 MHz Frequency
0
90
–10
80
–20
70
–30
60
–40
40
0
2
1
3
4
5
Figure 26. IMD3 vs. Output Power (POUT) at Minimum-to-Maximum Gain
Codes, 10 MHz Frequency
100
50
–1
–2
POUT PER TONE (dBm)
IMD2 (dBc)
GAIN CODE 0
GAIN CODE 63
TA = +85°C
TA = +25°C
TA = –40°C
–50
–60
–70
30
–80
20
0
–8
–7
–6
–5
–90
GAIN CODE 0
GAIN CODE 63
–4
–3
–2
–1
0
1
2
3
4
5
POUT PER TONE (dBm)
Figure 24. OIP2 vs. Output Power (POUT) at Minimum and Maximum Gain
Codes, 10 MHz Frequency
–60
–7
–6
–5
–4
–3
–2
–1
0
1
3
2
4
5
POUT PER TONE (dBm)
Figure 27. IMD2 vs. Output Power (POUT) at Minimum and Maximum Gain
Codes, 10 MHz Frequency
–60
TA = +85°C
TA = +25°C
TA = –40°C
–65
–100
–8
07584-060
10
TA = +85°C
TA = +25°C
TA = –40°C
07584-062
OIP2 (dBm)
–110
–3
07584-061
0
–3
TA = +85°C
TA = +25°C
TA = –40°C
07584-055
10
GAIN CODE 0
GAIN CODE 63
–65
TA = +85°C
TA = +25°C
TA = –40°C
GAIN CODE 0
GAIN CODE 63
–70
–70
–75
–80
–80
HD3 (dBc)
HD2 (dBc)
–75
–85
–90
–85
–90
–95
–100
–95
–105
–100
–120
–5
–5
–4
–3
–2
–1
0
1
2
POUT (dBm)
3
4
5
6
7
8
07584-053
–115
–110
Figure 25. HD2 vs. Output Power (POUT) at Gain Code 0 and Gain Code 63,
10 MHz Frequency
–4
–3
–2
–1
0
1
POUT (dBm)
2
3
4
5
07584-054
–110
–105
Figure 28. HD3 vs. Output Power (POUT) for Gain Code 0 and Gain Code 63,
10 MHz Frequency
Rev. B | Page 11 of 28
AD8366
Data Sheet
60
300
TA = +85°C
TA = +25°C
TA = –40°C
55
NOISE SPECTRAL DENSITY (nV/√Hz)
280
240
220
200
180
160
140
GAIN CODE 63
50 GAIN CODE 47
GAIN CODE 48
45 GAIN CODE 31
GAIN CODE 32
GAIN CODE 15
40 GAIN CODE 16
GAIN CODE 0
35
30
25
20
10
15
20
25
35
30
40
45
50
55
60
GAIN CODE
10
0.1
1
30
30
28
24
FREQUENCY = 0.5MHz
FREQUENCY = 0.5MHz
FREQUENCY = 3MHz
FREQUENCY = 3MHz
FREQUENCY = 10MHz
FREQUENCY = 10MHz
FREQUENCY = 50MHz
FREQUENCY = 50MHz
22
20
18
16
GAIN CODE 0
GAIN CODE 15
26 GAIN CODE 16
GAIN CODE 31
24 GAIN CODE 32
GAIN CODE 47
22 GAIN CODE 48
GAIN CODE 63
20
18
16
14
14
12
12
10
0
5
10
15
20
25
30
35
40
CHANNEL A
CHANNEL B
28
45
50
55
60
GAIN CODE
10
0.1
07584-011
NOISE FIGURE (dB)
26
B,
A,
B,
A,
B,
A,
B,
A,
NOISE FIGURE (dB)
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
CHANNEL
240
2.7
37
2.4
34
2.1
1.8
OUTPUT RESISTANCE (Ω)
250
40
6.0
5.7
19
5.4
0.9
200
0.6
16
0.3
13
0
20
40
60
80
100
120
140
160
180
FREQUENCY (MHz)
6.6
22
210
0
200
6.9
25
1.2
180
7.2
6.3
1.5
190
7.5
28
220
CHANNEL A: C IN, GAIN CODE 32
CHANNEL B: C IN, GAIN CODE 0
CHANNEL B: C IN, GAIN CODE 63
1000
CHANNEL A: R OUT, GAIN CODE 0
CHANNEL A: R OUT, GAIN CODE 63
CHANNEL B: R OUT, GAIN CODE 32
CHANNEL A: L OUT, GAIN CODE 0
CHANNEL A: L OUT, GAIN CODE 63
CHANNEL B: L OUT, GAIN CODE 32
CHANNEL A: R OUT, GAIN CODE 32
CHANNEL A: R OUT, GAIN CODE 0
31
230
07584-013
INPUT RESISTANCE (Ω)
260
100
10
Figure 33. Noise Figure vs. Frequency
3.0
INPUT CAPACITANCE (pF)
270
1
FREQUENCY (kHz)
Figure 30. Noise Figure vs. Gain Code at 0.5 MHz, 3 MHz, 10 MHz, and 50 MHz
CHANNEL A: R IN, GAIN CODE 0
CHANNEL A: R IN, GAIN CODE 63
CHANNEL B: R IN, GAIN CODE 32
CHANNEL A: C IN, GAIN CODE 0
CHANNEL A: C IN, GAIN CODE 63
CHANNEL B: C IN, GAIN CODE 32
CHANNEL A: R IN, GAIN CODE 32
CHANNEL A: R IN, GAIN CODE 0
CHANNEL B: R IN, GAIN CODE 63
1000
Figure 32. Noise Spectral Density vs. Frequency
Figure 29. Supply Current vs. Gain Code at 10 MHz
280
100
10
FREQUENCY (kHz)
07584-012
5
CHANNEL
CHANNEL
CHANNEL
CHANNEL
10
0
20
40
5.1
B: R OUT, GAIN CODE 63
A: L OUT, GAIN CODE 32
B: L OUT, GAIN CODE 0
B: L OUT, GAIN CODE 63
60
80
100
120
OUTPUT INDUCTNACE (nH)
0
07584-038
100
07584-010
15
120
4.8
140
160
180
4.5
200
FREQUENCY (MHz)
Figure 34. Differential Series Output Resistance and Inductance vs.
Frequency
Figure 31. Differential Parallel Input Resistance and Capacitance vs.
Frequency
Rev. B | Page 12 of 28
07584-014
SUPPLY CURRENT (mA)
260
CHANNEL A
CHANNEL B
Data Sheet
AD8366
0
140
PSRR GAIN CODE 0
PSRR GAIN CODE 63
–10
130
120
110
–20
100
90
SFDR (dB)
PSRR (dB)
–30
–40
–50
80
70
60
50
–60
40
–70
30
TA = +85°C
TA = +25°C
TA = –40°C
10
20
30
40
50
60
70
80
90 100 110 120 130 140 150
FREQUENCY (MHz)
0
07584-036
–90
10
0
80
30
35
40
45
50
55
60
GAIN CODE 63
70
1.4
60
1.2
CMRR (dB)
1.0
0.8
GAIN CODE 32
50
40
30
0.6
GAIN CODE 0
20
0.4
20
30
40
50
60
70
80
90 100 110 120 130 140 150
FREQUENCY (MHz)
0
1M
07584-021
0
10
0
MEASURED CHANNEL AT GAIN CODE 63
MEASURED CHANNEL AT GAIN CODE 32
MEASURED CHANNEL AT GAIN CODE 0
PIN = +10dBm
PIN = +5dBm
PIN = 0dBm
PIN = –5dBm
PIN = –10dBm
FORWARD LEAKAGE (dBm)
–20
–60
–80
1G
Figure 39. Common-Mode Rejection Ratio (CMRR) vs. Frequency
0
–40
100M
FREQUENCY (Hz)
Figure 36. Group Delay vs. Frequency at Gain Code 0, Gain Code 32, and
Gain Code 63
–20
10M
07584-016
10
0.2
–40
–60
–80
–100
–120
–100
–140
–120
1
10
100
FREQUENCY (MHz)
1000
07584-034
DRIVEN CHANNEL AT GAIN CODE 0
–160
1
10
100
1000
FREQUENCY (MHz)
Figure 40. Forward Leakage vs. Frequency, Part Disabled
Figure 37. Channel-to-Channel Isolation vs. Frequency,
Channel A Driven, Channel B Measured
Rev. B | Page 13 of 28
07584-031
GROUP DELAY (ns)
25
20
90
1.6
ISOLATION (dB)
15
Figure 38. SFDR vs. Gain Code at 10 MHz and 50 MHz,
1 Hz Analysis Bandwidth
GAIN CODE 32
GAIN CODE 0
GAIN CODE 63
1.8
10
GAIN CODE
Figure 35. Power Supply Rejection Ratio (PSRR) vs. Frequency
2.0
5
FREQUENCY = 10MHz
FREQUENCY = 50MHz
07584-037
20
–80
AD8366
Data Sheet
1.2
1.4
1.0
0.8
0.8
OUTPUT VOLTAGE (V)
10pF
0.4
0.2
0
–0.2
–0.4
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–0.8
–1.0
–1.0
–4
–3
–2
–1
0
1
2
3
4
5
TIME (ns)
Figure 41. Large Signal Pulse Response, Gain Code 0, Input Signal 1.2 V p-p,
0 pF and 10 pF Capacitive Loading Conditions
10pF
0.6
–0.6
–1.2
–5
07584-067
OUTPUT VOLTAGE (V)
0.6
–1.2
–5
0pF
1.2
0pF
–4
–3
–2
–1
0
1
2
3
4
5
TIME (ns)
07584-068
1.0
Figure 44. Large Signal Pulse Response, Gain Code 63, Input Signal 240 mV p-p,
0 pF and 10 pF Capacitive Loading Conditions
1
2
5GS/s A CH1
100k pts
1.60V
M 200ns 250MS/s
CH3 50mV Ω
CH4 1V Ω
0
–20
–60
–80
–100
10
100
FREQUENCY (MHz)
1000
07584-033
S12 MAG (dB)
–40
1
A CH4
2.48V
Figure 45. Gain Step Time Domain Response, Minimum-to-Maximum Gain
(Time Scale 200 ns/division), CH4 = Digital Control Inputs
Figure 42. ENBL Time Domain Response
–120
0.1
4.0ns/pt
07584-064
CH1 1V Ω CH2 100mV Ω M1µs
T
4.02µs
07584-065
3
Figure 43. Reverse Isolation (S12) vs. Frequency
Rev. B | Page 14 of 28
Data Sheet
AD8366
CIRCUIT DESCRIPTION
The AD8366 is a dual, differential, digitally controlled VGA
with 600 MHz of 3 dB bandwidth and a gain range of 4.5 dB to
20.25 dB adjustable in 0.25 dB steps. Using a proprietary variable
gain architecture, the AD8366 is able to achieve excellent linearity
(45 dBm) and noise performance (11.7 nV/√Hz) at 10 MHz at
minimum gain. Intended for use in direct conversion systems, the
part also includes dc offset correction that can be disabled easily
by grounding either OFSA or OFSB. In addition, the part offers
an adjustable output common-mode range of 1.6 V to 3 V.
The main signal path is shown in Figure 46. It consists of an
input transconductance, a variable-gain cell, and an output
transimpedance amplifier.
AI
12.5Ω
f 3dB ,HP (kHz ) =
OUTP
Z
INM
OUTM
100Ω
To prevent significant levels of offset from appearing at the
outputs of the AD8366, each digitally controlled VGA has a
differential offset correction loop, as shown in Figure 47. This
loop senses any differential offset at the output and corrects for
it by injecting an opposing current at the input differential ground.
The loop is able to correct for input dc offsets of up to ±20 mV.
Because the loop automatically nulls out any dc or low frequency
offset, the effect of the loop is to introduce a high-pass corner into
the transfer function of the digitally controlled VGA. The
location of this high-pass corner depends on both the gain
setting and the value of the capacitor connected to the OFSx pin
(OFSA for DVGA A and OFSB for DVGA B) and is given by
VIRTUAL
GROUND
VIRTUAL 12.5Ω
GROUND
Figure 46. Main Signal Path
The input transconductance provides a broadband 200 Ω
differential termination and converts the input voltage to a
current. This current is fed into the variable current-gain cell.
The output of this cell goes into the transimpedance stage, which
generates the output voltage. The transimpedance is fixed at 500 Ω,
with a roughly 25 Ω differential output impedance.
4300(1.037 )GC + 4000
2π(COFS + 10 )
where:
GC is the gain code (a value from 0 to 63).
COFS is the value of the capacitance connected to OFSA or OFSB,
in picofarads (pF).
The offset correction loop can be disabled by grounding either
OFSA or OFSB.
VARIABLE-GAIN
STAGE
OUTPUT
BUFFER
OUTP
AI
INPUTS
Z
OUTM
The inputs to the digitally-controlled VGAs in the AD8366 are
differential and can be either ac- or dc-coupled. The AD8366
synthesizes a 200 Ω (differential) input impedance, with a return
loss (re: 200 Ω) of better than 10 dB to 200 MHz. The nominal
common-mode input voltage to the part is VPOS/2, but the AD8366
can be dc-coupled to parts with lower common modes if these
parts can sink current. The amount of current sinking required
depends on the input common-mode level and is given by
INP
gm2
gm1
INM
COFS
OFFSET
COMPENSATION
LOOP
07584-073
100Ω
07584-071
INP
VARIABLE
CURRENT-GAIN OUTPUT
STAGE
BUFFER
OUTPUT DIFFERENTIAL OFFSET CORRECTION
Figure 47. Differential Offset Correction Loop
OUTPUT COMMON-MODE CONTROL
ISINK (per leg) = (VPOS/2 − VICM)/100
The input common-mode range is 1.5 V to VPOS/2.
OUTPUTS
The outputs of the digitally-controlled VGAs are differential and
can be either ac- or dc-coupled. The AD8366 synthesizes a 25 Ω
differential output impedance, with a return loss (re: 25 Ω) of
better than 10 dB to 120 MHz. The nominal common-mode
output voltage is VPOS/2; however, it can be lowered or raised by
driving the VCMA or VCMB pins.
To interface to ADCs that require different input common-mode
voltages, the AD8366 has an adjustable output common-mode
level. The output common-mode level is normally set to VPOS/2;
however, it can be changed between 1.6 V and 3 V by driving
the VCMA pin or the VCMB pin. The input equivalent circuit
for the VCMA pin is shown in Figure 48; the VCMB pin has the
same input equivalent circuit.
VPOS/2
4kΩ
500Ω
07584-072
VCMA
Figure 48. Input Equivalent Circuit for VCMA
Rev. B | Page 15 of 28
25.0
1.0
The AD8366 provides two methods of digital gain control:
serial or parallel. When the SENB pin is pulled low, the part
is in parallel gain control mode. In this mode, the two digitally
controlled VGAs can be programmed simultaneously, or one at
a time, depending on the levels at DENA and DENB. If the SENB
pin is pulled high, the part is in serial gain control mode, with
Pin 24, Pin 23, and Pin 22 corresponding to the CS, SDAT, and
SCLK signals, respectively.
22.5
0.8
20.0
0.6
17.5
0.4
15.0
0.2
12.5
0
10.0
–0.2
7.5
–0.4
5.0
–0.6
2.5
–0.8
The voltage gain of the AD8366 is well approximated by
Gain (dB) = GainCode × 0.253 + 4.5
GAIN (dB)
GAIN CONTROL INTERFACE
0
Note that at several major transitions (15 to 16, 31 to 32, and 47 to
48), the gain changes significantly less (0 dB step) or significantly
more (0.5 dB step) than the desired 0.25 dB step. This is inherent
in the design of the part and is related to the partitioning of the
variable gain block into a fine-gain and a coarse-gain section.
Rev. B | Page 16 of 28
–1.0
0
5
10
15
20
25
30
35
40
45
50
55
60
GAIN CODE
Figure 49. Gain and Gain Step Error vs. Gain Code at 10 MHz
GAIN STEP ERROR (dB)
Data Sheet
07584-063
AD8366
Data Sheet
AD8366
APPLICATIONS INFORMATION
The output buffers of the AD8366 are low impedance around
25 Ω designed to drive ADC inputs. The output common-mode
voltage defaults to VPOS/2; however, it can be adjusted by applying a
desired external voltage to VCMA/VCMB. The common-mode
voltage can be adjusted from 1.6 V to 3.0 V without significant
harmonic distortion degradation.
BASIC CONNECTIONS
Figure 50 shows the basic connections for operating the AD8366.
A voltage from 4.75 V to 5.25 V must be applied to the supply
pins. Each supply pin must be decoupled with at least one low
inductance, surface-mount ceramic capacitor of 0.1 µF placed as
close as possible to the device.
To enable the AD8366, the ENBL pin must be pulled high. Taking
ENBL low disables the device, reducing current consumption to
approximately 3 mA at ambient temperature.
The differential input impedance is 200 Ω and sits at a nominal
common-mode voltage of VPOS/2. The inputs can be dc-coupled
or ac-coupled. If using direct dc coupling, the common-mode
voltage, VCM, can range from 1.5 V to VPOS/2.
VPOS
0.01µF
8200pF
CHANNEL A
OUTPUT
0.01µF
0.01µF
CHANNEL A
INPUT
VPOS
0.1µF
CHANNEL B
INPUT
VPOS
0.1µF
AD8366
BIT0/CS
BIT1/SDAT
BIT2/SCLK
BIT3
OCOM
BIT4
BIT5
DENA
0.1µF
0.01µF
CHANNEL B
OUTPUT
0.01µF
0.01µF
8200pF
0.01µF
VPOS
Figure 50. Basic Connections
Rev. B | Page 17 of 28
07584-046
0.1µF
VPSIA
IPPA
IPMA
ENBL
ICOM
IPMB
IPPB
VPSIB
PARALLEL/SERIAL
CONTROL INTERFACE (PCI)
0.1µF
DECB
OFSB
CCMB
VCMB
VPSOB
OPPB
OPMB
DENB
0.1µF
DECA
OFSA
CCMA
VCMA
VPSOA
OPPA
OPMA
SENB
VPOS
AD8366
Data Sheet
LC LOWPASS
FILTER
ADL5523
0
RF
LO
90
TO
ADC
ADF4350
ADL5523
LC LOWPASS
FILTER
ADL5380
LC LOWPASS
FILTER
AD8366
07584-047
PAD
FILTER
BALUN
MATCHING
NETWORK
LC LOWPASS
FILTER
Figure 51. Direct Conversion Receiver Block Diagram
DIRECT CONVERSION RECEIVER DESIGN
A direct conversion receiver directly demodulates an RF modulated
carrier to baseband frequencies, where the signals can be detected
and the conveyed information recovered. Eliminating the IF
stages and directly converting the signal to effectively zero IF
results in reduced component count. The image problems
associated with the traditional superheterodyne architectures
can be ignored as well. However, there are different challenges
associated with direct conversion that include LO leakage, dc
offsets, quadrature imperfections, and image rejection. LO
leakage causes self mixing that results in squaring of the LO
waveform which generates a dc offset that falls in band for the
direct conversion receiver. Residual dc offsets create a similar
interfering signal that falls in band. I/Q amplitude and phase
mismatch lead to degraded SNR performance and poor image
rejection in the direct conversion system. Figure 51 shows the
block diagram for a direct conversion receiver system.
The image rejection ratio is the ratio of the intermediate frequency
(IF) signal level produced by the desired input frequency to that
produced by the image frequency. The image rejection ratio is
expressed in decibels (dB). Appropriate image rejection is critical
because the image power can be much higher than that of the
desired signal, thereby plaguing the downconversion process.
Amplitude and phase balance between the I/Q channels are
critical for high levels of image rejection. Image rejection of
greater than 47 dB was measured for the combined ADL5380
and the AD8366 for a 5 MHz baseband frequency, as seen in
Figure 53. This level of image rejection corresponds to a ±0.5°
phase mismatch and a ±0.05 dB of amplitude mismatch for the
combined ADL5380 and AD8366. Looking back to Figure 7 and
Figure 10, the AD8366 exhibits only ±0.05 dB of amplitude mismatch
and ±0.05o of phase mismatch, thus implying that the AD8366
does not introduce additional amplitude and phase imbalance.
55
QUADRATURE ERRORS AND IMAGE REJECTION
45
35
30
25
20
15
10
5
–65
–55
–45
–35
–25
–15
INPUT POWER (dBm)
–5
5
07584-048
SNR (dB)
40
35
30
25
900
1100 1300 1500 1700 1900 2100 2300 2500 2700 2900
RF FREQUENCY (MHz)
Figure 53. Image Rejection vs. RF Frequency
40
0
–75
45
Figure 52. SNR vs. RF Input Power Level
Rev. B | Page 18 of 28
07584-049
An overall RF-to-baseband EVM performance was measured
with the ADL5380 IQ demodulator preceding the AD8366, as
shown in Figure 56. In this setup, no LC low-pass filters were used
between the ADL5380 and AD8366. A 1900 MHz W-CDMA RF
signal with a 3.84 MHz symbol rate was used. The local oscillator
(LO) is set at 1900 MHz to obtain a zero IF baseband signal.
The gain of the AD8366 is set to maximum gain (~20.25 dB).
Figure 52 shows the SNR vs. the input power of the cascaded
system for a 5 MHz analysis bandwidth. The broad input power
range over which the system exhibits strong SNR performance
reflects the superior dynamic range of the AD8366.
IMAGE REJECTION (dB)
50
Data Sheet
AD8366
–20
LOW FREQUENCY IMD3 PERFORMANCE
GC63
GC0
To measure the IMD3 data at low frequencies, wideband
transformer baluns from North Hills Signal Processing Corp.
were used, specifically the 0301BB and the 0520BB. Figure 55
shows the IMD3 performance vs. frequency for a 2 V p-p
composite output. The IMD3 performance was also measured
for the combined ADL5380 and AD8366 system, as shown in
Figure 56, with an FFT spectrum analyzer. An FFT spectrum
analyzer works very similar to a typical ADC, the input signal
is digitized at a high sampling rate that is then passed through an
antialiasing filter. The resulting signal is transformed to the
frequency domain using fast Fourier transforms (FFT).
–30
IMD3 (dBc)
–40
–50
–60
–70
–90
0.5
The single-ended RF signal from the source generator is converted
to a differential signal using a balun that gets demodulated and
down converted to differential IF signals through the ADL5380.
This differential IF signal drives the AD8366, thus eliminating
the need for low frequency baluns. Figure 54 shows the IMD3
performance vs. frequency over the 500 kHz to 5 MHz range
for minimum and maximum gain code setting on the AD8366.
During the measurements, the output was set to 2 V p-p composite.
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (MHz)
07584-018
–80
Figure 54. System IMD3 vs. Frequency, 2 V p-p Composite at
the Output of the AD8366
–10
40
–20
35
–30
30
–40
25
–50
20
–60
15
–70
10
–80
5
–90
–100
0
0
5
10
15
20
25
30
35
40
45
50
55
60
GAIN CODE
Figure 55. OIP3 on Low Frequency, 2 V p-p Composite
Rev. B | Page 19 of 28
IMD3 (dBc)
OIP3 (dBm)
0
FREQUENCY = 1MHz
FREQUENCY = 3MHz
45
07584-035
50
AD8366
Data Sheet
RFIN
BALUN
100pF
100pF
VPOS
VPOS
24
23
22
21
20
19
GND
RFIP
RFIN
GND
ADJ
100pF
VCC
0.1µF
1 GND
GND 18
2 GND
GND 17
3 IHI
QHI 16
ADL5380
NC
VCC 13
GND
6 VCC
LOIN
GND 14
LOIP
5 GND
GND
QLO 15
ENBL
VPOS
4 ILO
7
8
9
10
11
12
100pF
0.1µF
100pF
VPOS
100pF
0.1µF
100pF
BALUN
LO
VPOS
VPOS
VPOS
0.1µF
0.1µF
0.1µF
CCMA
0.01µF
VPOS
VPSOA
I CHANNEL
0.01µF
0.1µF
SENB
BIT1
BIT2
BIT3
OCOM
OPMA
BIT4
OPMB
BIT5
OPPA
200Ω
Q CHANNEL
PARALLEL/SERIAL
CONTROL INTERFACE
Figure 56. ADL5380 and AD8366 Interface Block Diagram
Rev. B | Page 20 of 28
07584-050
DENB
200Ω
COFS
VCMA
AD8366
OPPB
DENA
0.01µF
DECA
CCMB
VPSOB
0.1µF
VPSIA
IPPA
IPMA
ICOM
OFSA
VCMB
VPOS
ENBL
IPMB
OFSB
BIT0
COFS
0.01µF
IPPB
0.01µF
DECB
VPSIB
0.01µF
Data Sheet
AD8366
In most direct-conversion receiver designs, it is desirable to select a
wanted carrier within a specified band. The desired channel can be
demodulated by tuning the LO to the appropriate carrier frequency.
If the desired RF band contains multiple carriers of interest, the
adjacent carriers would also be down converted to a lower IF
frequency. These adjacent carriers can be a problem if they are
large relative to the desired carrier because they can overdrive
the baseband signal detection circuitry. As a result, it is often
necessary to insert a filter to provide sufficient rejection of the
adjacent carriers.
The order and type of filter network depends on the desired high
frequency rejection required, pass-band ripple, and group delay.
Figure 57 shows the schematic for a typical fourth-order, Chebyshev,
low-pass filter. Table 4 shows the typical values of the filter
components for a fourth-order, Chebyshev, low-pass filter with
a differential source impedance of 25 Ω and a differential load
impedance of 200 Ω.
L3
L1
ZSOURCE
It is necessary to consider the overall source and load impedance
presented by the AD8366 and the ADC input to design the
filter network. The differential baseband output impedance of
the AD8366 is 25 Ω and is designed to drive a high impedance
ADC input. It may be desirable to terminate the ADC input down
to the lower impedance by using a terminating resistor, such as
500 Ω. The terminating resistor helps to better define the input
impedance at the ADC input at the cost of a slightly reduced gain.
L2
C1
C2
ZLOAD
07584-051
BASEBAND INTERFACE
L4
Figure 57. Schematic of a Fourth-Order, Chebyshev, Low-Pass Filter
Table 4. Typical Values for Fourth-Order, Chebyshev, Low-Pass Filter
3 dB Corner (MHz)
5
10
28
ZSOURCE (Ω)
25
25
25
ZLOAD (Ω)
200
200
200
L1 (µH)
6.6
3.3
1.2
L2 (µH)
6.6
3.3
1.2
Rev. B | Page 21 of 28
L3 (µH)
6.0
3
1
L4 (µH)
6.0
3
1
C1 (pF)
220
110
39
C2 (pF)
180
90
33
AD8366
Data Sheet
CHARACTERIZATION SETUPS
Figure 58 and Figure 59 are characterization setups used
extensively to characterize the AD8366. Characterization was
done on single-ended and differential evaluation boards. The
bulk of the characterization was done using an automated VEE
program to control the equipment as shown in Figure 58. This
setup was used to measure P1dB, OIP3, OIP2, IMD2, IMD3,
harmonic distortion, gain, gain error, supply current, and noise
density. All measurements were done with a 200 Ω load. All balun,
output matching network, and filter losses were de-embedded.
Gain error was measured with constant input power. All other
measurements were done on 2 V p-p (4 dBm, re: 200 Ω) on
the output of the device under test (DUT), and 2 V p-p composite
output for two-tone measurements. To measure harmonic
distortion, band-pass and band-reject filters were used on
the input and output of the DUT.
Figure 59 shows the setup used to make differential measurements.
All measurements on this setup were done in a 50 Ω system and
post processed to reference the measurements to a 200 Ω system.
Gain and phase mismatch were measured with 2 V p-p on the
output, and small signal frequency responses were measured
with −30 dBm on the input of the DUT.
Rev. B | Page 22 of 28
IEEE
IEEE
AD8366
IEEE
Data Sheet
AGILENT E8251D
SIGNAL GENERATOR
AGILENT E8251A
SIGNAL GENERATOR
AGILENT E4440A
SPECTRUM ANALYZER
COMBINER
RF SWITCH
MATRIX
KEITHLEY
IEEE
RF SWITCH
MATRIX
KEITHLEY
IEEE
BAND REJECT
BAND PASS
CH2
RF IN
CH1
RF IN
CH2
RF OUT
CH1
RF OUT
AD8366
EVALUATION BOARD
Figure 58. Characterization Setup, Single-Ended Measurements
Rev. B | Page 23 of 28
07584-069
AGILENT 34401A DMM
(IN DC I MODE FOR SUPPLY
CURRENT MEASUREMENT)
IEEE
AGILENT E3631A POWER
SUPPLY
IEEE
IEEE
AGILENT 34980A
MULTIFUNCTION SWITCH
(WITH 34950 AND 34921 MODULES)
AD8366
Data Sheet
Rohde & Schwarz ZVA8
RF SWITCH
MATRIX
KEITHLEY
CH2
IP
CH2
IP
CH2
IM
CH2
IM
CH1
OM
CH2
OP
CH2
OM
AGILENT E3631A
POWER SUPPLY
07584-070
CH1
OP
AD8366
EVALUATION BOARD
Figure 59. Characterization Setup, Differential Measurements
Rev. B | Page 24 of 28
Data Sheet
AD8366
EVALUATION BOARD
VPSI_A
VPSI_A
S5
R57
R53
C29
R73
R80
C31
R72
R68
DENA
OPMA
DENB
BIT5
BIT4
BIT3
OCOM
BIT2
BIT1
BIT0
SENB
VCMB
BIT2
R64
R41
R61
C33
R31
C25
S7
VPSI_A
VPSI_A
S10
S9
R36
R33
R74
R65
R38
R37
R69
R40
R70
R67
T4
S2
VPSI_A
R29
C24
S4
R30
VPSI_A
R34
VPSI_A
R42
R39
T3
R35
C27
R43
S6
C26
R71
S8
VPSI_A
The schematic for the AD8366 evaluation board is shown in Figure 60. The board can be used for single-ended or differential baseband
analysis. The default configuration of the board is for single-ended baseband analysis.
OPMB
OPPA
C9
VPSOB
AD8366
VCMA
VCMB
CCMA
CCMB
OFSA
OFSB
VPSO_B
VCMB
C10
S12
R50
VPSI_B
C20
T1
IPPB
IPMB
ICOM
ENBL
VPSIB
DECB
VPSI_A
C5
T2
R17
R58
R47
R15
R16
R12
C18
C23
R20
R21
R19
C21
R32
S1
BIT2
C1
VPOS
VPSI_A
C14
R4
R3
R79
C13
R62
R46
R14
R13
R18
C30
IPMA
R48 R63
R44
Figure 60. Evaluation Board Schematic
Rev. B | Page 25 of 28
07584-056
VPSI_A
R45
ENBL
IPPA
DECA
R54
C3
VPSI_B
ENBL
C16
R6
VPSI_A
R5
C15
VPSI_A
C12
R26
R10
R22
C22
C11
VPSO_B
VPSO_A
C2
VPSIA
VCMA
S11
U1
R24
VCMA
VPSI_B
OPPB
VPSOA
VPSO_A
S3
R28
C28
Data Sheet
07584-058
07584-059
AD8366
Figure 61. AD8366 Evaluation Board Printed Circuit Board (PCB), Top Side
Figure 62. AD8366 Evaluation Board PCB, Bottom Side
Table 5. Evaluation Board Configuration Options
Components
C1, C13 to C16, R3 to R6
T1, T2, C5, C18, C20, C21,
R12 to R21, R44 to R48,
R50, R54, R58, R62, R63
T3, T4, C24 to C27, R29 to
R31, R33 to R39, R65, R67
to R74, R80
Function
Power supply decoupling. Nominal supply decoupling consists of a
0.1 µF capacitor to ground followed by 0.01 µF capacitors to ground
positioned as close to the device as possible.
Input interface. The default configuration of the evaluation board is
for single-ended operation. T1 and T2 are 4:1 impedance ratio baluns to
transform a 50 Ω single-ended input into a 200 Ω balanced differential
signal. R12 to R14 and R15, R16, and R19 are populated for appropriate
balun interface. R44 to R48 and R50, R54, R58, R62, and R63 are
provided for generic placement of matching components. C5, C18,
C20, and C21 are balun decoupling capacitors. R17, R18, R20, and
R21 can be populated with 0 Ω, and the balun interfacing resistors
can be removed to bypass T1 and T2 for differential interfacing.
Output interface. The default configuration of the evaluation board
is for single-ended operation. T3 and T4 are 4:1 impedance ratio
baluns to transform a 50 Ω single-ended output into a 200 Ω balanced
differential load. R29 to R31, R33, R38, and R39 are populated for
appropriate balun interface. R65, R67 to R74, and R80 are provided
for generic placement of matching components. C24, C25, C26, and
C27 are balun decoupling capacitors. R34 to R37 can be populated
with 0 Ω, and the balun interfacing resistors can be removed to
bypass T3 and T4 for differential interfacing.
Rev. B | Page 26 of 28
Default Conditions
C1 = 0.1 µF (size 0603),
C13 to C16 = 0.01 µF (size 0402),
R3 to R6 = 0 Ω (size 0603)
T1, T2 = ADT4-6T+ (Mini-Circuits),
C5, C20 = 0.1 µF (size 0402),
C18, C21 = do not install,
R12 to R16, R19, R44 to R47 = 0 Ω
(size 0402),
R17, R18, R20, R21,R48, R50, R54,
R58, R62, and R63 = open (size 0402)
T3, T4 = ADT4-6T+ (Mini-Circuits),
C24, C25 = 0.1 µF (size 0402),
C26, C27 = do not install,
R29 to R31, R33, R38, R39, R65, R67,
R68, R80 = 0 Ω (size 0402),
R34 to R37, R69 to R74 = open (size 0402)
Data Sheet
Components
S1, S5, S7, R53, R57, R79,
C29, C30, C31
S2, S3, S4, S6, S8, S9, S10
R26, R32, R40 to R43, R61,
R64, C23, C33, U1
S11, S12, C9, C10
R10, R22, R24, R28, C22,
C28
C2, C3, C11, C12
AD8366
Function
Enable interface includes device enable and data enable.
Device enable. The AD8366 is enabled by applying a logic high
voltage to the ENBL pin. The device is enabled when the S1 switch is
set in the down position (high), connecting the ENBL pin to VPSI_A.
Data enable. DENA and DENB are used to enable the data path for
Channel A and Channel B, respectively. Channel A is enabled when
the S5 switch is set in the down position (high), connecting the DENA
pin to VPSI_A. Likewise, Channel B is enabled when the S7 switch is
set in the down position (high), connecting the DENB pin to VPSI_A.
Both channels are disabled by setting the switches to the up position,
connecting the DENA and DENB pins to GND.
Serial/parallel interface control. SENB is used to set the data control
either in parallel or serial mode. The parallel interface is enabled when
S4 is in the up position (low). The serial interface is enabled when S4
is in the down position (high).
For SENB pulled low, BIT0 (S9) sets 0.25 dB gain, BIT1 (S2) sets 0.5 dB
gain, BIT2 (S3) sets 1 dB gain, BIT3 (S6) sets 2 dB gain, BIT4 (S8) sets
4 dB gain, and BIT5 (S10) sets 8 dB gain.
For SENB pulled high, BIT0 becomes a chip select (CS), BIT1 becomes
a serial data input (SDAT), and BIT2 becomes serial clock (SCLK). BIT3 to
BIT5 are not used in serial mode. U1 is used to deglitch the SCLK signal.
DC offset correction loop compensation.
The dc offset correction loop is enabled (high) with S11 and S12 for
Channel A and Channel B, respectively, when the enabled pins, OFSA/
OFSB, are connected to ground through the C9 and C10 capacitors.
When disabled (low), OFSA/OFSB are connected to ground directly.
Output common-mode setpoint. The output common mode on
Channel A and Channel B can be set externally when applied to
VCMA and VCMB. The resistive change through the potentiometer
sets a variable VCMA voltage. If left open, the output common mode
defaults to VPOS/2.
Reference output decoupling capacitor to circuit common.
Rev. B | Page 27 of 28
Default Conditions
S1, S5, S7 = installed,
R53, R57 = 5.1 kΩ (size 0603),
R79 = 10 kΩ (size 0402),
C30 = 0.01 µF (size 0402),
C29, C31 = 1500 pF (size 0402)
S2, S3, S4, S6, S8, S9, S10 = installed,
R26 = 698 kΩ (size 0603),
R32, R40 to R43, R61, R64 = 5.1 kΩ
(size 0603),
C23, C33 = 1500 pF (size 0603),
U1 = SN74LVC2G14 inverter chip
S11, S12 = installed,
C9, C10 = 8200 pF (size 0402)
R10, R24 = 10 kΩ potentiometers,
R22, R28 = 0 Ω,
C22, C28 = 0.1 µF (size 0402)
C2, C3 = 0.1 µF (size 0402),
C11, C12 = 0.01 µF (size 0402)
AD8366
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
0.30
0.25
0.18
32
25
24
1
0.50
BSC
PIN 1
INDICATOR
2.85
2.70 SQ
2.55
EXPOSED
PAD
17
8
0.80
0.75
0.70
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PKG-004332
SEATING
PLANE
9
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-2.
08-22-2013-A
TOP VIEW
0.50
0.40
0.30
Figure 63. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-21)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD8366ACPZ-R7
AD8366-EVALZ
1
Temperature Range
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2010–2017 Analog Devices, Inc. All rights reserved. Trademarks
and
registered trademarks are the property of their respective owners.
D07584-0-8/17(B)
Rev. B | Page 28 of 28
Package Option
CP-32-21