AD ADL5562-EVALZ 3.3 ghz ultralow distortion rf/if differential amplifier Datasheet

3.3 GHz Ultralow Distortion
RF/IF Differential Amplifier
ADL5562
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
−3 dB bandwidth of 3.3 GHz (AV = 6 dB)
Pin-strappable gain adjust: 6 dB, 12 dB, 15.5 dB
Differential or single-ended input to differential output
Low noise input stage: 2.1 nV/√Hz RTI at AV = 12 dB
Low broadband distortion (AV = 6 dB)
10 MHz: −91 dBc HD2, −98 dBc HD3
70 MHz: −102 dBc HD2, −90 dBc HD3
140 MHz: −104 dBc HD2, −87 dBc HD3
250 MHz: −80 dBc HD2, −94 dBc HD3
IMD3s of −94 dBc at 250 MHz center
Slew rate: 9.8 V/ns
Fast settling of 2 ns and overdrive recovery of 3 ns
Single-supply operation: 3 V to 3.6 V
Power-down control
Fabricated using the high speed XFCB3 SiGe process
VCC
RF
ENBL
VIP2
VIP1
RG2
VON
RG1
VCOM
RG1
VIN1
VIN2
RG2
VOP
RF
GND
ADL5562
08003-001
FEATURES
Figure 1.
APPLICATIONS
Differential ADC drivers
Single-ended to differential conversion
RF/IF gain blocks
SAW filter interfacing
GENERAL DESCRIPTION
The ADL5562 is a high performance differential amplifier
optimized for RF and IF applications. The amplifier offers low
noise of 2.1 nV/√Hz and excellent distortion performance over
a wide frequency range, making it an ideal driver for high speed
8-bit to 16-bit ADCs.
The ADL5562 provides three gain levels of 6 dB, 12 dB, and
15.5 dB through a pin-strappable configuration. For the singleended input configuration, the gains are reduced to 5.6 dB,
11.1 dB, and 14.1 dB. Using an external series input resistor
expands the amplifier gain flexibility and allows for any gain
selection from 0 dB to 15.5 dB.
The quiescent current of the ADL5562 is typically 80 mA and,
when disabled, consumes less than 3 mA, offering excellent
input-to-output isolation.
Rev. F
The device is optimized for wideband, low distortion
performance. These attributes, together with its adjustable gain
capability, make this device the amplifier of choice for generalpurpose IF and broadband applications where low distortion,
noise, and power are critical. This device is optimized for the
best combination of slew speed, bandwidth, and broadband
distortion. These attributes allow it to drive a wide variety of
analog-to-digital converters (ADCs) and make it ideally suited
for driving mixers, pin diode attenuators, SAW filters, and
multi-element discrete devices.
Fabricated on an Analog Devices, Inc., high speed SiGe process,
the ADL5562 is supplied in a compact 3 mm × 3 mm, 16-lead
LFCSP package and operates over the temperature range of
−40°C to + 85°C.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADL5562
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Basic Structure ............................................................................ 13
Applications ....................................................................................... 1
Applications Information .............................................................. 14
Functional Block Diagram .............................................................. 1
Basic Connections ...................................................................... 14
General Description ......................................................................... 1
Input and Output Interfacing ................................................... 15
Revision History ............................................................................... 2
Gain Adjustment and Interfacing ............................................ 16
Specifications..................................................................................... 3
ADC Interfacing ......................................................................... 16
Absolute Maximum Ratings............................................................ 6
Layout Considerations ............................................................... 18
ESD Caution .................................................................................. 6
Soldering Information ............................................................... 19
Pin Configuration and Function Descriptions ............................. 7
Evaluation Board ........................................................................ 19
Typical Performance Characteristics ............................................. 8
Outline Dimensions ....................................................................... 21
Circuit Description ......................................................................... 13
Ordering Guide .......................................................................... 21
REVISION HISTORY
9/2017—Rev. E to Rev. F
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
1/2014—Rev. D to Rev. E
Changes to ENBL Threshold Parameter, Table 1 ......................... 3
4/2013—Rev. C to Rev. D
Changes to Table 1 ............................................................................ 3
Changes to Figure 6 and Figure 7 ................................................... 8
7/2011—Rev. B to Rev. C
Changes to Figure 28 and Figure 29 ............................................. 12
Added Figure 30 and Figure 31; Renumbered Sequentially ..... 12
Changes to Ordering Guide .......................................................... 21
3/2010—Rev. A to Rev. B
Changes to Figure 43...................................................................... 19
Updated Outline Dimensions ....................................................... 21
Changes to Ordering Guide .......................................................... 21
9/2009—Rev. 0 to Rev. A
Changes to Features Section ............................................................1
Changes to Table 1.............................................................................3
Changes to Figure 5 ...........................................................................8
Changes to Figure 9 and Figure 10..................................................9
Changes to Figure 32, Equation 1, and Figure 34 ...................... 15
Changes to Equation 2 ................................................................... 16
Changes to Figure 38, Figure 39, Figure 40, and Table 9........... 17
Changes to Figure 43...................................................................... 19
Moved Table 14 to .......................................................................... 19
5/2009—Revision 0: Initial Version
Rev. F | Page 2 of 21
Data Sheet
ADL5562
SPECIFICATIONS
VCC = 3.3 V, VCOM = 1.65 V, RL = 200 Ω differential, AV = 6 dB, CL = 1 pF differential, f = 140 MHz, TA = 25°C.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth for 0.1 dB Flatness
Gain Accuracy
Gain Supply Sensitivity
Gain Temperature Sensitivity
Slew Rate
Settling Time
Overdrive Recovery Time
Reverse Isolation (S12)
INPUT/OUTPUT CHARACTERISTICS
Output Common Mode
Voltage Adjustment Range
Maximum Output Voltage Swing
Output Common-Mode Offset
Output Common-Mode Drift
Output Differential Offset Voltage
CMRR
Output Differential Offset Drift
Input Bias Current
Input Resistance (Differential)
Input Resistance (Single-Ended) 1
Input Capacitance (Single-Ended)
Output Resistance (Differential)
POWER INTERFACE
Supply Voltage
ENBL Threshold
ENBL Input Bias Current
Quiescent Current
Conditions
Min
AV = 6 dB, VOUT ≤ 1.0 V p-p
AV = 12 dB, VOUT ≤ 1.0 V p-p
AV = 15.5 dB, VOUT ≤ 1.0 V p-p
AV = 6 dB, VOUT ≤ 1.0 V p-p
AV = 12 dB, VOUT ≤ 1.0 V p-p
AV = 15.5 dB, VOUT ≤ 1.0 V p-p
AV = 6 dB, RL = open
AV = 12 dB, RL = open
AV = 15.5 dB, RL = open
VCC ± 5%
−40°C to +85°C, AV = 15.5 dB
Rise, AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V step
Fall, AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V step
2 V step to 1%
VIN = 4 V to 0 V step, VOUT ≤ ±10 mV
1 dB compressed
Referenced to VCC/2
−40°C to +85°C
−40°C to +85°C
AV = 6 dB
AV = 12 dB
AV = 15.5 dB
AV = 5.6 dB, RS = 50 Ω
AV = 11.1 dB, RS = 50 Ω
AV = 14.1 dB, RS = 50 Ω
3
Device disabled, ENBL low
Device enabled, ENBL high
ENBL high
ENBL low
ENBL high
ENBL low
Rev. F | Page 3 of 21
Typ
Max
3300
3900
1900
220
270
270
0.17
0.05
0.06
−0.005
0.32
9.8
10.1
2
3
60
MHz
MHz
MHz
MHz
MHz
MHz
dB
dB
dB
dB/V
mdB/°C
V/ns
V/ns
ns
ns
dB
VCC/2
1.4 to 1.8
4.9
60
285
1
65
15
3
400
200
133
307
179
132
0.3
12
V
V
V p-p
mV
µV/°C
mV
dB
µV/°C
µA
Ω
Ω
Ω
Ω
Ω
Ω
pF
Ω
3.3
3.6
0.5
1.5
75.5
Unit
−27
−300
80
3.5
84.5
V
V
V
µA
µA
mA
mA
ADL5562
Parameter
10 MHz NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic Distortion
Output Third-Order Intercept/Third-Order
Intermodulation Distortion
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
70 MHz NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic Distortion
Output Third-Order Intercept/Third-Order
Intermodulation Distortion
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
140 MHz NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic Distortion
Output Third-Order Intercept/Third-Order
Intermodulation Distortion
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
Data Sheet
Conditions
Min
Typ
Max
Unit
AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p
AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 6 dB
AV = 12 dB
AV = 15.5 dB
AV = 6 dB
AV = 12 dB
AV = 15.5 dB
−91/−98
−95/−98
−96/−92
+42/−97
dBc
dBc
dBc
dBm/dBc
+43/−93
dBm/dBc
+43/−91
dBm/dBc
3
2.1
1.6
13.5
13.4
13
nV/√Hz
nV/√Hz
nV/√Hz
dBm
dBm
dBm
AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p
AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 6 dB
AV = 12 dB
AV = 15.5 dB
AV = 6 dB
AV = 12 dB
AV = 15.5 dB
−102/−90
−97/−85
−93/−83
+46/−96
dBc
dBc
dBc
dBm/dBc
+44/−93
dBm/dBc
+43/−91
dBm/dBc
3
2.1
1.6
13.2
13.2
12.6
nV/√Hz
nV/√Hz
nV/√Hz
dBm
dBm
dBm
−104/−87
−82/−81
−80/−80
+47/−100
dBc
dBc
dBc
dBm/dBc
+45/−95
dBm/dBc
+43/−92
dBm/dBc
3
2.1
1.6
13.4
13.3
12.4
nV/√Hz
nV/√Hz
nV/√Hz
dBm
dBm
dBm
AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p
AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 6 dB
AV = 12 dB
AV = 15.5 dB
AV = 6 dB
AV = 12 dB
AV = 15.5 dB
Rev. F | Page 4 of 21
Data Sheet
Parameter
250 MHz NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic Distortion
Output Third-Order Intercept/Third-Order
Intermodulation Distortion
Noise Spectral Density (RTI)
1 dB Compression Point (RTO)
500 MHz NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic Distortion
Output Third-Order Intercept/Third-Order
Intermodulation Distortion
Noise Spectral Density (RTI)
1000 MHz NOISE/HARMONIC PERFORMANCE
Second/Third Harmonic Distortion
Output Third-Order Intercept/Third-Order
Intermodulation Distortion
Noise Spectral Density (RTI)
1
ADL5562
Conditions
Min
AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p
AV = 6 dB, RL = 200 Ω, VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 12 dB, RL = 200 Ω, VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 15.5 dB, RL = 200 Ω, VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 6 dB
AV = 12 dB
AV = 15.5 dB
AV = 6 dB
AV = 12 dB
AV = 15.5 dB
AV = 6 dB, RL = 200 Ω, VOUT = 1 V p-p
AV = 12 dB, RL = 200 Ω, VOUT = 1 V p-p
AV = 15.5 dB, RL = 200 Ω, VOUT = 1 V p-p
AV = 6 dB, RL = 200 Ω, VOUT = 1 V p-p composite
(2 MHz spacing)
AV = 12 dB, RL = 200 Ω, VOUT = 1 V p-p composite
(2 MHz spacing)
AV = 15.5 dB, RL = 200 Ω, VOUT = 1 V p-p composite
(2 MHz spacing)
AV = 6 dB
AV = 12 dB
AV = 15.5 dB
AV = 6 dB, RL = 200 Ω, VOUT = 1 V p-p
AV = 12 dB, RL = 200 Ω, VOUT = 1 V p-p
AV = 15.5 dB, RL = 200 Ω, VOUT = 1 V p-p
AV = 6 dB, RL = 200 Ω, VOUT = 1 V p-p composite
(2 MHz spacing)
AV = 12 dB, RL = 200 Ω, VOUT = 1 V p-p composite
(2 MHz spacing)
AV = 15.5 dB, RL = 200 Ω, VOUT = 1 V p-p composite
(2 MHz spacing)
AV = 6 dB
AV = 12 dB
AV = 15.5 dB
See the Applications Information section for a discussion of single-ended input, dc-coupled operation.
Rev. F | Page 5 of 21
Typ
Max
Unit
−80/−94
−74/−86
−74/−84
+43/−94
dBc
dBc
dBc
dBm/dBc
+41/−87
dBm/dBc
+40/−86
dBm/dBc
3.2
2.2
1.6
13
13
12
nV/√Hz
nV/√Hz
nV/√Hz
dBm
dBm
dBm
−75/−69
−69/−73
−72/−75
+40/−98
dBc
dBc
dBc
dBm/dBc
+39/−97
dBm/dBc
+38/−93
dBm/dBc
3.7
2.2
1.6
nV/√Hz
nV/√Hz
nV/√Hz
−70/−60
−69/−61
−66/−59
+24/−65
dBc
dBc
dBc
dBm/dBc
+24/−66
dBm/dBc
+25/−66
dBm/dBc
4.7
2.2
1.6
nV/√Hz
nV/√Hz
nV/√Hz
ADL5562
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage (VCC)
VIP1, VIP2, VIN1, VIN2
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
3.6 V
VCC + 0.5 V
310 mW
98.3°C/W
125°C
−40°C to +85°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. F | Page 6 of 21
Data Sheet
ADL5562
VCC 8
9 VCOM
NOTES
1. EXPOSED PADDLE. CONNECT TO A LOW
IMPEDANCE THERMAL AND ELECTRICAL
GROUND PLANE.
08003-031
14 GND
10 VON
VCC 7
11 VOP
TOP VIEW
(Not to Scale)
VCC 5
VIN2 4
12 ENBL
ADL5562
VCC 6
VIN1 3
13 GND
PIN 1
INDICATOR
VIP2 1
VIP1 2
15 GND
16 GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
VIP2
2
VIP1
3
VIN1
4
VIN2
5, 6, 7, 8
9
VCC
VCOM
10
11
12
13, 14, 15, 16
VON
VOP
ENBL
GND
EPAD
Description
Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for AV = 12 dB gain, strapped to
VIP1 for AV = 15.5 dB.
Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for AV = 6 dB gain, strapped to
VIP2 for AV = 15.5 dB.
Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for AV = 6 dB gain, strapped to
VIN2 for AV = 15.5 dB.
Balanced Differential Input. Biased to VCOM, typically ac-coupled. Input for AV = 12 dB gain, strapped to
VIN1 for AV = 15.5 dB.
Positive Supply.
Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the input and
output. Typically decoupled to ground with a 0.1 μF capacitor. With no reference applied, input and
output common mode floats to midsupply (VCC/2).
Balanced Differential Output. Biased to VCOM, typically ac-coupled.
Balanced Differential Output. Biased to VCOM, typically ac-coupled.
Enable. Apply positive voltage (1.0 V < ENBL < VCC) to activate device.
Ground. Connect to low impedance ground.
Exposed Pad. Connect to a low impedance thermal and electrical ground plane.
Rev. F | Page 7 of 21
ADL5562
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VCOM = 1.65 V, RL = 200 Ω differential, AV = 6 dB, CL = 1 pF differential, f = 140 MHz, T = 25°C.
16
MAXIMUM GAIN
15
–40°C
+25°C
+85°C
14
13
14
12
11
MID GAIN
10
10
8
9
8
7
6
MAX GAIN –40°C
MAX GAIN +25°C
MAX GAIN +85°C
MID GAIN –40°C
MID GAIN +25°C
MID GAIN +85°C
MIN GAIN –40°C
MIN GAIN +25°C
MIN GAIN +85°C
5
4
3
MINIMUM GAIN
2
1
1G
100M
10G
FREQUENCY (Hz)
0
08003-002
4
10M
Figure 3. Gain vs. Frequency Response for 200 Ω Differential Load,
AV = 6 dB, AV = 12 dB, and AV = 15.5 dB over Temperature
MAXIMUM GAIN
MID GAIN
8
6
MAX GAIN –40°C
MAX GAIN +25°C
MAX GAIN +85°C
MID GAIN –40°C
MID GAIN +25°C
MID GAIN +85°C
MIN GAIN –40°C
MIN GAIN +25°C
MIN GAIN +85°C
4
MINIMUM GAIN
2
6
100M
1G
10G
FREQUENCY (Hz)
0
08003-003
4
10M
0
50
100
150
200
250
FREQUENCY (MHz)
08003-016
OP1dB (dBm)
GAIN (dB)
250
10
8
Figure 7. Output P1dB (OP1dB) vs. Frequency at AV = 6 dB, AV = 12 dB, and
AV = 15.5 dB over Temperature, 1 kΩ Differential Load
Figure 4. Gain vs. Frequency Response for 1 kΩ Differential Load,
AV = 6 dB, AV = 12 dB, and AV = 15.5 dB over Temperature
16
8
NOISE SPECTRAL DENSITY (nV/√Hz)
AV MAXIMUM
AV MID
AV MINIMUM
12
10
8
6
4
2
100
FREQUENCY (MHz)
1000
08003-004
NOISE FIGURE (dB)
200
12
10
0
10
150
14
14
14
100
Figure 6. Output P1dB (OP1dB) vs. Frequency at AV = 6 dB, AV = 12 dB, and
AV = 15.5 dB over Temperature, 200 Ω Differential Load
–40°C
+25°C
+85°C
18
12
50
FREQUENCY (MHz)
20
16
0
7
AV MAXIMUM
AV MID
AV MINIMUM
6
5
4
3
2
1
0
10M
100M
FREQUENCY (Hz)
Figure 8. Noise Spectral Density vs. Frequency
at AV = 6 dB, AV = 12 dB, and AV = 15.5 dB
Figure 5. Noise Figure vs. Frequency at
AV = 6 dB, AV = 12 dB, and AV = 15.5 dB
Rev. F | Page 8 of 21
1G
08003-005
6
08003-017
OP1dB (dBm)
GAIN (dB)
12
ADL5562
–40
60
AV MAXIMUM
AV MID
AV MINIMUM
55
–60
IMD3, RL = 200Ω (dBc)
50
OIP3 (dBm)
45
40
35
30
25
20
0
AV MAXIMUM
AV MID
AV MINIMUM
–20
IMD3, RL = 1kΩ (dBc)
Data Sheet
–80
–40
–100
–60
–120
–80
–140
–100
0
50
100
150
250
200
FREQUENCY (MHz)
–160
50
0
100
150
–120
250
200
08003-020
10
08003-018
15
FREQUENCY (MHz)
Figure 9. Output Third-Order Intercept at Three Gains, Output Level at 2 V p-p
Composite, RL = 200 Ω
Figure 12. Two-Tone Output IMD vs. Frequency, Output Level
at 2 V p-p Composite, RL = 200 Ω and RL = 1 kΩ
60
50
+85°C
+25°C
–40°C
45
50
40
35
OIP3 (dBm)
OIP3 (dBm)
40
30
30
25
20
20
15
10
10
50
100
150
200
250
FREQUENCY (MHz)
0
–2
08003-019
0
–1
1
0
2
3
5
4
POUT/TONE (dBm)
08003-028
5
0
Figure 13. Output Third-Order Intercept (OIP3) vs. Power (POUT),
Frequency 140 MHz, AV = 15.5 dB
Figure 10. Output Third-Order Intercept vs. Frequency, Over Temperature,
Output Level at 2 V p-p Composite, RL = 200 Ω
–70
60
AV MAXIMUM
AV MID
AV MINIMUM
55
AV MAXIMUM
AV MID
AV MINIMUM
–75
–80
IMD (dBc)
–85
45
–90
–95
40
–100
35
–110
30
0
50
100
150
200
FREQUENCY (MHz)
250
0
50
100
150
200
FREQUENCY (MHz)
Figure 14. IMD vs. Frequency (Single-Ended Input)
Figure 11. OIP3 vs. Frequency (Single-Ended Input)
Rev. F | Page 9 of 21
250
08003-007
–105
08003-006
OIP3 (dBm)
50
Data Sheet
–40
–100
–60
–120
–80
–140
–100
–120
250
–160
50
100
150
200
HARMONIC DISTORTION HD2 (dBc)
–20
–80
0
HARMONIC DISTORTION HD3 (dBc)
–60
–40
FREQUENCY (MHz)
–40
–100
–60
–120
–80
–140
–100
–20
–80
–40
–100
–60
–120
–80
–100
–140
50
150
100
–120
250
200
Figure 18. Harmonic Distortion (HD2/HD3) vs. Frequency at Av = 6 dB,
Av = 12 dB, and Av = 15.5 dB, Output Level at 2 V p-p, RL = 1 kΩ
–20
–30
HARMONIC DISTORTION (dBc)
–60
–20
–80
0
+85°C
+25°C
–40°C
0
FREQUENCY (MHz)
HARMONIC DISTORTION HD3 (dBc)
HARMONIC DISTORTION HD2 (dBc)
–60
0
Figure 15. Harmonic Distortion (HD2/HD3) vs. Frequency at AV = 6 dB,
AV = 12 dB, and AV = 15.5 dB, Output Level at 2 V p-p, RL = 200 Ω
–40
AV MAXIMUM
AV MID
AV MINIMUM
–160
08003-021
HARMONIC DISTORTION HD2 (dBc)
AV MAXIMUM
AV MID
AV MINIMUM
HARMONIC DISTORTION HD3 (dBc)
0
–40
08003-024
ADL5562
–40
–50
–60
–70
HD2
–80
HD3
100
150
200
–120
250
FREQUENCY (MHz)
–100
–2
0
–40
–100
–60
–120
–80
–100
0
50
100
150
FREQUENCY (MHz)
200
–120
250
HARMONIC DISTORTION HD2 (dBc)
–80
HARMONIC DISTORTION HD3 (dBc)
–20
–160
2
3
–60
4
5
–50
AV MAXIMUM
AV MID
AV MINIMUM
–65
–60
–140
1
Figure 19. Harmonic Distortion (HD2/HD3) vs. Power (POUT),
Frequency 140 MHz, AV = 15.5 dB
08003-023
HARMONIC DISTORTION HD2 (dBc)
+85°C
+25°C
–40°C
0
POUT (dBm)
Figure 16. Harmonic Distortion (HD2/HD3) vs. Frequency,
Three Temperatures, Output Level at 2 V p-p, RL = 200 Ω
–40
–1
08003-029
50
Figure 17. Harmonic Distortion (HD2/HD3) vs. Frequency, Over Temperature,
Output Level at 2 V p-p, RL = 1 kΩ
–55
–70
–60
–75
–65
–80
–70
–85
–75
–90
–80
–95
–85
–100
–90
–105
–95
–110
0
50
100
150
FREQUENCY (MHz)
200
–100
250
HARMONIC DISTORTION HD3 (dBc)
0
08003-008
–160
08003-022
–90
Figure 20. Harmonic Distortion (HD2/HD3) vs. Frequency (Single-Ended Input)
Rev. F | Page 10 of 21
Data Sheet
ADL5562
–70
–100
–80
–110
–90
–120
100
200
300
400
500
600
700
800
900
–130
1000
RLOAD (Ω)
–75
–75
–80
–80
–85
–85
–90
–90
–95
–95
–100
–100
–105
–105
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
–110
1.9
VCOM (V)
Figure 21. Harmonic Distortion (HD2/HD3) vs. RLOAD
Figure 24. Harmonic Distortion (HD2/HD3) vs. VCOM
0
1.0
AV MAXIMUM
AV MID
AV MINIMUM
08003-030
VOLTAGE (V)
GROUP DELAY (ns)
0.9
0.8
–40
0.7
–60
0.6
–80
0.5
–100
0.4
–120
0.3
–140
0.2
–160
0.1
TIME (2.5ns/DIV)
–20
0
100
200
300
400
500
600
700
800
900
PHASE (Degrees)
0
–70
–180
1000
08003-011
–100
–70
HARMONIC DISTORTION HD3 (dBc)
–90
–65
–65
08003-010
–60
HARMONIC DISTORTION HD2 (dBc)
–80
HARMONIC DISTORTION HD3 (dBc)
–50
AV MAXIMUM
AV MID
AV MINIMUM
–60
–70
08003-009
–40
–60
–55
–60
AV MAXIMUM
AV MID
AV MINIMUM
FREQUENCY (MHz)
Figure 22. ENBL Time Domain Response
Figure 25. Group Delay and Phase vs. Frequency
80
110
RL = 1kΩ
100
AV MAXIMUM
AV MID
AV MINIMUM
70
2V p-p OUTPUT
50
RL = 200Ω
70
40
60
30
50
20
40
10
30
10M
100M
0
1G
FREQUENCY (Hz)
Figure 26. Common-Mode Rejection Ratio (CMRR) vs. Frequency
Figure 23. Large Signal Pulse Response, AV = 15.5 dB
Rev. F | Page 11 of 21
08003-012
CMRR (dB)
08003-036
TIME (2.5ns/DIV)
80
CMRR (dB)
60
90
VOLTAGE (V)
HARMONIC DISTORTION HD2 (dBc)
–30
ADL5562
Data Sheet
800
8
AV MAXIMUM
AV MID
AV MINIMUM
0
700
7
S12 (dB)
–30
–40
–50
–60
ENABLED
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (GHz)
6
500
5
400
4
300
3
200
2
100
1
0
10M
08003-013
–70
600
FREQUENCY (Hz)
Figure 27. Reverse Isolation (S12) vs. Frequency
AV MAXIMUM
AV MID
AV MINIMUM
10
16
10
14
800
0
12
700
–10
600
–20
500
–30
400
–40
300
–50
200
–60
AV MAXIMUM
AV MID
AV MINIMUM
RESISTANCE (Ω)
8
PHASE (Degrees)
900
IMPEDANCE MAGNITUDE (Ω)
Figure 30. Input Resistance and Capacitance vs. Frequency
20
1000
0
1G
100M
08003-051
RESISTANCE (Ω)
DISABLED
10
6
8
4
6
INDUCTANCE (nH)
–20
CAPACITANCE (pF)
–10
4
2
2
100M
–80
1G
08003-014
0
10M
FREQUENCY (Hz)
Figure 28. Input Impedance vs. Frequency
16
12
30
10
25
8
20
6
15
4
10
2
5
0
10M
100M
FREQUENCY (Hz)
0
1G
PHASE (Degrees)
35
08003-015
IMPEDANCE MAGNITUDE (Ω)
14
100M
1G
0
2G
FREQUENCY (Hz)
Figure 31. Output Resistance and Inductance vs. Frequency
40
AV MAXIMUM
AV MID
AV MINIMUM
0
10M
Figure 29. Output Impedance vs. Frequency
Rev. F | Page 12 of 21
08003-052
–70
100
Data Sheet
ADL5562
CIRCUIT DESCRIPTION
BASIC STRUCTURE
The ADL5562 is a low noise, fully differential amplifier/ADC
driver that uses a 3.3 V supply. It provides three gain options
(6 dB, 12 dB, and 15.5 dB) without the need for external resistors
and has wide bandwidths of 2.6 GHz for 6 dB, 2.3 GHz for 12 dB,
and 2.1 GHz for 15.5 dB. Differential input impedance is 400 Ω
for 6 dB, 200 Ω for 12 dB, and 133 Ω for 15.5 dB. It has a
differential output impedance of 10 Ω and a common-mode
adjust voltage of 1.25 V to 1.85 V.
0.1µF
400Ω
+
5Ω
VIP2 100Ω
1/ R
2 S
VIP1 200Ω
VIN1 200Ω
1/ R
2 S
VIN2 100Ω
RL
5Ω
400Ω
+
0.1µF
Figure 32. Basic Structure
08003-032
AC
The ADL5562 is composed of a fully differential amplifier with
on-chip feedback and feed-forward resistors. The two feed-forward
resistors on each input set this pin-strappable amplifier in three
different gain configurations of 6 dB, 12 dB, and 15.5 dB. The
amplifier is designed to provide high differential open-loop gain
and an output common-mode circuit that enables the user to
change the common-mode voltage from a VCOM pin. The
amplifier is designed to provide superior low distortion at
frequencies up to and beyond 300 MHz with low noise and
low power consumption. The low distortion and noise are
realized with a 3.3 V power supply at 80 mA.
The ADL5562 is very flexible in terms of I/O coupling. It can
be ac-coupled or dc-coupled at the inputs and/or the outputs
within the specified input and output common-mode levels.
The input of the device can be configured as single-ended or
differential with similar distortion performance. Due to the
internal connections between the inputs and outputs, keep the
output common-mode voltage between 1.25 V and 1.85 V for
the best distortion. For a dc-coupled input, the input common
mode must be between 1 V and 2.3 V for the best distortion.
The device has been characterized using 2 V p-p into 200 Ω. If
the inputs are ac-coupled, the input and output common-mode
voltages are set by VCC/2 when no external circuitry is used.
The ADL5562 provides an output common-mode voltage set by
VCOM, which allows driving an ADC directly without external
components, such as a transformer or ac coupling capacitors,
provided the VCOM of the amplifier is within the VCOM of the
ADC. For dc-coupled requirements, the input VCM must be set
by the VCOM pin in all three gain settings.
Rev. F | Page 13 of 21
ADL5562
Data Sheet
APPLICATIONS INFORMATION
Pin 1 to Pin 4, Pin 10, and Pin 11 are biased at 1/2 VCC above
ground and can be dc-coupled (if within the specified input or
output common-mode voltage levels) or ac-coupled as shown
in Figure 33.
BASIC CONNECTIONS
Figure 33 shows the basic connections for operating the ADL5562.
VCC must be 3.3 V with each supply pin decoupled with at least
one low inductance surface-mount ceramic capacitor of 0.1 μF
placed as close as possible to the device. The VCOM pin (Pin 9)
must also be decoupled using a 0.1 μF capacitor.
To enable the ADL5562, the ENBL pin must be pulled high.
Pulling the ENBL pin low puts the ADL5562 in sleep mode,
reducing the current consumption to 3 mA at ambient.
The gain of the part is determined by the pin-strappable input
configuration. When Input A is applied to VIP1 and Input B is
applied to VIN1, the gain is 6 dB (minimum gain, see Equation 1
and Equation 2). When Input A is applied to VIP2 and Input B
is applied to VIN2, the gain is 12 dB (middle gain). When
Input A is applied to VIP1 and VIP2 and Input B is applied to
VIN1 and VIN2, the gain is 15.5 dB (maximum gain).
VCC
RS/2
0.1µF
15
GND
14
GND
2 VIP1
AC
13
GND
ENBL 12
VOP 11
ADL5562
3 VIN1
0.1µF B
VCC
BALANCED
LOAD
VON 10
VCOM 9
4 VIN2
VCC
5
RL
VCC
6
10µF
VCC
7
0.1µF
Figure 33. Basic Connections
Rev. F | Page 14 of 21
VCC
8
0.1µF
08003-033
A
RS/2
BALANCED
SOURCE
16
GND
1 VIP2
Data Sheet
ADL5562
INPUT AND OUTPUT INTERFACING
Single-Ended Input to Differential Output
The ADL5562 can be configured as a differential-input to
differential-output driver, as shown in Figure 34. The differential
broadband input is provided by the ETC1-1-13 balun transformer,
and the two 34.8 Ω resistors provide a 50 Ω input match for the
three input impedances that change with the variable gain
strapping. The input and output 0.1 μF capacitors isolate the VCC/2
bias from the source and balanced load. The load must equal 200 Ω
to provide the expected ac performance (see the Specifications
section and the Typical Performance Characteristics section).
The ADL5562 can also be configured in a single-ended input
to differential output driver, as shown in Figure 36. In this
configuration, the gain of the part is reduced due to the application
of the signal to only one side of the amplifier. The strappable
gain values are listed in Table 6 with the required terminations
to match to a 50 Ω source using R1 and R2. Note that R1 must
equal the parallel value of the source and R2. The input and
output 0.1 μF capacitors isolate the VCC/2 bias from the source
and the balanced load. The performance for this configuration
is shown in Figure 11, Figure 14, and Figure 20.
3.3V
RL
2
0.1µF
VIN2
50Ω
VIN1
08003-043
R2 (Ω)
28.7
33.2
40.2
Figure 36. Single-Ended Input to Differential Output Configuration
Table 6. Single-Ended Termination Values for Figure 36
Gain (dB)
5.6
11.1
14.1
The differential gain of the ADL5562 is dependent on the
source impedance and load, as shown in Figure 35.
400Ω
AC
VIN1 200Ω
5Ω
0.1µF
VIP2 100Ω
VIP1 200Ω
+
08003-044
400Ω
RS
0.1µF
Figure 37. Single-Ended Input Loading Circuit
(1)
RIN (Ω)
200
100
66.7
Rev. F | Page 15 of 21
0.1µF
RL
2
400Ω
R1
Table 5. Values of RIN for Differential Gain
Gain (dB)
6
12
15.5
5Ω
RL
2
+
400
RL

RIN 10  RL
VIN2 100Ω
+
The differential gain can be determined using the following
formula. The values of RIN for each gain configuration are
shown in Table 5.
0.1µF
VIN1 200Ω
AC
Figure 35. Differential Input Loading Circuit
AV 
R2
5Ω
+
0.1µF
R2 (Ω)
60
69
77
400Ω
RL
2
+
VIN2 100Ω
0.1µF
RL
2
+
1/ R
2 S
0.1µF
+
VIP1 200Ω
R1 (Ω)
27
29
30
The single-ended gain configuration of the ADL5562 is dependent
on the source impedance and load, as shown in Figure 37.
+
5Ω
VIP2 100Ω
1/ R
2 S
0.1µF
NOTES
1. FOR 5.6dB GAIN (AV = 1.9), CONNECT INPUT A TO VIP1
AND INPUT B TO VIN1.
2. FOR 11.1dB GAIN (AV = 3.6), CONNECT INPUT A TO VIP2
AND INPUT B TO VIN2.
3. FOR 14.1dB GAIN (AV = 5.1), CONNECT INPUT A TO BOTH
VIP1 AND VIP2 AND INPUT B TO BOTH VIN1 AND VIN2.
Table 4. Differential Termination Values for Figure 34
0.1µF
RL
2
R1
Figure 34. Differential-Input to Differential-Output Configuration
R1 (Ω)
28.7
33.2
40.2
+
0.1µF
VIN2
RL
2
+
AC
Gain (dB)
6
12
15.5
VIP1
B
NOTES
1. FOR 6dB GAIN (AV = 2), CONNECT INPUT A TO VIP1 AND INPUT B TO VIN1.
2. FOR 12dB GAIN (AV = 4), CONNECT INPUT A TO VIP2 AND INPUT B TO VIN2.
3. FOR 15.5dB GAIN (AV = 6), CONNECT INPUT A TO BOTH VIP1 AND VIP2
AND INPUT B TO BOTH VIN1 AND VIN2.
0.1µF
VIP2
A
R2
+
R1
0.1µF
+
VIN1
B
+
AC
RL
2
+
0.1µF
VIP1
08003-046
+
50Ω
+
A
R2
3.3V
0.1µF
VIP2
08003-045
0.1µF
ETC1-1-13
ADL5562
Data Sheet
The necessary shunt component, RSHUNT, to match to the source
impedance, RS, can be expressed as
The single-ended gain can be determined using the following
formula. The values of RIN and RX for each gain configuration
are shown in Table 7.
R + RS
400
R2
RL
×
× X
×
RX
10 + RL
 RS × R2  RS + R2

RIN + 

 RS + R2 
(2)
1
RIN (Ω)
200
100
66.7
RX (Ω)
R2 || 3071
R2 || 1791
R2 || 1321
Table 8. Gain Adjustment Using Series Resistor
These values based on a 50 Ω input match.
Il (dB)
2
4
2
4
2
2
4
2
4
2
4
2
GAIN ADJUSTMENT AND INTERFACING
The effective gain of the ADL5562 can be reduced using a number
of techniques. A matched attenuator network can reduce the
effective gain; however, this requires the addition of a separate
component that can be prohibitive in size and cost. Instead, a
simple voltage divider can be implemented using the combination
of additional series resistors at the amplifier input and the input
impedance of the ADL5562, as shown in Figure 38. A shunt
resistor is used to match to the impedance of the previous stage.
AC
1/ R
2 S
0.1µF 1/2 RSERIES
VIN1
VIN2
1/ R
2 SHUNT
0.1µF 1/2 RSERIES
ADL5562
VIP1
VIP2
1/ R
2 SHUNT
Figure 38 shows a typical implementation of the divider concept
that effectively reduces the gain by adding attenuation at the input.
For frequencies less than 100 MHz, the input impedance of
the ADL5562 can be modeled as a real 133 Ω, 200 Ω, or 400 Ω
resistance (differential) for maximum, middle, and minimum
gains, respectively. Assuming that the frequency is low enough
to ignore the shunt reactance of the input and high enough so
that the reactance of moderately sized ac coupling capacitors
can be considered negligible, the insertion loss, Il, due to the
shunt divider can be expressed as




RS (Ω)
50
50
50
50
50
200
200
200
200
50
50
50
RSERIES (Ω)
105
232
51.1
115
34.8
102
232
51.1
115
105
232
51.1
For optimum performance, drive the ADL5562 differentially
using an input balun. Figure 39 uses a wideband 1:1 transmission
line balun followed by two 34.8 Ω resistors in parallel with the three
input impedances (which change with the gain selection of the
ADL5562) to provide a 50 Ω differential input impedance. This
provides a wideband match to a 50 Ω source. The ADL5562 is
ac-coupled from the AD9445 to avoid common-mode dc loading.
The 33 Ω series resistors help to improve the isolation between
the ADL5562 and any switching currents present at the analog-todigital sample-and-hold input circuitry. The AD9445 input presents
a 2 kΩ differential load impedance and requires a 2 V p-p
differential input swing to reach full scale (VREF = 1 V).
(3)
3.3V
VOP
VIP1
0.1µF B
VIN1
VIN2
0.1µF
ADL5562
33Ω
VON
VIN+
AD9445
0.1µF
+
34.8Ω
VIP2
+
34.8Ω
0.1µF A
+
AC
ETC1-1-13
+
50Ω
RSHUNT (Ω)
54.9
54.9
61.9
59
71.5
332
294
976
549
54.9
54.9
61.9
The ADL5562 is a high output linearity amplifier that is optimized
for ADC interfacing. There are several options available to the
designer when using the ADL5562. Figure 39 shows a simplified
wideband interface with the ADL5562 driving the AD9445. The
AD9445 is a 14-bit, 125 MSPS ADC with a buffered wideband input.
Figure 38. Gain Adjustment Using a Series Resistor

RIN
Il(dB) = 20 log 
R
 SERIES + RIN
RIN (Ω)
400
400
200
200
133
400
400
200
200
400
400
200
ADC INTERFACING
08003-037
1/ R
2 S
(4)
The insertion loss and the resultant power gain for multiple
shunt resistor values are summarized in Table 8. The source
resistance and input impedance need careful attention when using
Equation 3 and Equation 4. The reactance of the input impedance
of the ADL5562 and the ac coupling capacitors must be considered
before assuming that they make a negligible contribution.
Table 7. Values of RIN and RX for Single-Ended Gain
Gain (dB)
5.6
11.1
14.1
1
1
1
−
RS RSERIES + RIN
33Ω
VIN–
Figure 39. Wideband ADC Interfacing Example Featuring the AD9445
Rev. F | Page 16 of 21
14
14-BIT ADC
08003-038
AV 1 =
RSHUNT =
Data Sheet
ADL5562
This circuit provides variable gain, isolation, and source matching
for the AD9445. Using this circuit with the ADL5562 in a gain
of 6 dB, an SFDR performance of 87 dBc is achieved at 140 MHz,
and a −3 dB bandwidth of 760 MHz, as indicated in Figure 40
and Figure 41.
The wideband frequency response is an advantage in broadband applications, such as predistortion receiver designs and
instrumentation applications. However, by designing for a wide
analog input frequency range, the cascaded SNR performance is
somewhat degraded due to high frequency noise aliasing into
the wanted Nyquist zone.
0
ADL5562 DRIVING THE AD9445 14-BIT ADC
GAIN = 6dB
INPUT = 140MHz
SNR = 66.25dBc
SFDR = 87.44dBc
NOISE FLOOR = –109.5dB
FUND = –1.081dBFS
SECOND = –84.54dBc
THIRD = –84.54dBc
–10
–20
–30
–40
–50
(dBFS)
–60
An alternative narrow-band approach is presented in Figure 42.
By designing a narrow band-pass antialiasing filter between the
ADL5562 and the target ADC, the output noise of the ADL5562
outside of the intended Nyquist zone can be attenuated, helping
to preserve the available SNR of the ADC. In general, the SNR
improves several decibels when including a reasonable order antialiasing filter. In this example, a low loss 1:1 input transformer is
used to match the ADL5562 balanced input to a 50 Ω unbalanced
source, resulting in minimum insertion loss at the input.
–70
–80
–90
–100
–110
–120
Figure 42 is optimized for driving some of the Analog Devices
popular unbuffered ADCs, such as the AD9246, AD9640,
and AD6655. Table 9 includes antialiasing filter component
recommendations for popular IF sampling center frequencies.
Inductor L5 works in parallel with the on-chip ADC input
capacitance and a portion of the capacitance presented by C4 to
form a resonant tank circuit. The resonant tank helps to ensure
that the ADC input looks like a real resistance at the target center
frequency. The L5 inductor shorts the ADC inputs at dc, which
introduces a zero into the transfer function. In addition, the ac
coupling capacitors introduce additional zeros into the transfer
function. The final overall frequency response takes on a bandpass characteristic, helping to reject noise outside of the intended
Nyquist zone. Table 9 provides initial suggestions for prototyping
purposes. Some empirical optimization may be needed to help
compensate for actual PCB parasitics.
–130
–140
0
6.25 12.50 18.75 25.00 31.25 37.50 43.75 50.00 56.25 62.50
FREQUENCY (MHz)
08003-026
–150
Figure 40. Measured Single-Tone Performance of the
Circuit in Figure 39 for a 100 MHz Input Signal
0
–1
–2
–3
(dBFS)
–4
–5
–6
–7
–9
FIRST POINT = –1.02dBFS
END POINT = –5.69dBFS
MID POINT = –1.09dBFS
MIN = –5.69dBFS
MAX = –0.88dBFS
–10
2.00
81.90
161.80
321.60
481.40
641.20
801.00
241.70
401.50
561.30
721.10
FREQUENCY (MHz)
08003-025
–8
Figure 41. Measured Frequency Response of the Wideband
ADC Interface Depicted in Figure 39
L1
L3
105Ω
ADL5562
C4
C2
1nF 4Ω
L1
L3
CML
AD9246
AD9640
AD6655
L5
105Ω
08003-039
1nF 4Ω
Figure 42. Narrow-Band IF Sampling Solution for an Unbuffered ADC Application
Table 9. Interface Filter Recommendations for Various IF Sampling Frequencies
Center Frequency (MHz)
96
140
170
211
1 dB Bandwidth (MHz)
30
33
32
33
L1 (nH)
3.3
3.3
3.3
3.3
Rev. F | Page 17 of 21
C2 (pF)
47
47
56
47
L3 (nH)
27
27
27
27
C4 (pF)
75
33
22
18
L5 (nH)
100
120
110
56
ADL5562
Data Sheet
LAYOUT CONSIDERATIONS
minimized. In many board designs, the signal trace widths must
be minimal where the driver/receiver is more than one-eighth of
the wavelength from the amplifier. This nontransmission line
configuration requires that underlying and adjacent ground and
low impedance planes be dropped from the signal lines.
High-Q inductive drives and loads, as well as stray transmission
line capacitance in combination with package parasitics, can
potentially form a resonant circuit at high frequencies, resulting
in excessive gain peaking or possible oscillation. If RF transmission
lines connecting the input or output are used, they must be
designed such that stray capacitance at the input/output pins is
R3
R1
VIP2
0.1µF
R4
ETC1-1-13
0.1µF
VIP1
VOP
R9
R7
ETC1-1-13
ADL5562
R5
VIN1
R2
0.1µF
SPECTRUM
ANALYZER
R8
VON
0.1µF
R6
R10
08003-034
VIN2
Figure 43. General Purpose Characterization Circuit
Table 10. Gain Setting and Input Termination Components for Figure 43
AV (dB)
6
12
15.5
R1 (Ω)
29
33
40.2
R2 (Ω)
29
33
40.2
R3 (Ω)
Open
0
0
R4 (Ω)
0
Open
0
R9 (Ω)
34.8
25
R10 (Ω)
34.8
25
R5 (Ω)
0
Open
0
R6 (Ω)
Open
0
0
Table 11. Output Matching Network for Figure 43
RL (Ω)
200
1k
R7 (Ω)
84.5
487
R8 (Ω)
84.5
487
R3
VIP2
R1
R4
PORT 1
VIP1
R9
VOP
R7
PORT 2
ADL5562
R5
PORT 3
R8
VIN1
R2
PORT 4
VON
R10
R6
08003-035
VIN2
Figure 44. Differential Characterization Circuit Using Agilent E8357A 4-Port PNA
Table 12. Gain Setting and Input Termination Components for Figure 44
AV (dB)
6
12
15.5
R1 (Ω)
67
100
200
R2 (Ω)
67
100
200
R3 (Ω)
Open
0
0
R4 (Ω)
0
Open
0
R9 (Ω)
Open
61.9
R10 (Ω)
Open
61.9
Table 13. Output Matching Network for Figure 44
RL (Ω)
200
1k
R7 (Ω)
50
475
R8 (Ω)
50
475
Rev. F | Page 18 of 21
R5 (Ω)
0
Open
0
R6 (Ω)
Open
0
0
Data Sheet
ADL5562
SOLDERING INFORMATION
To realize the minimum gain (6 dB into a 200 Ω load), Input 1
(VIN1 and VIP1) must be used by installing 0 Ω resistors at R3
and R4, leaving R5 and R6 open. R1 and R2 must be 33 Ω for a
50 Ω input impedance.
On the underside of the chip scale package, there is an exposed
compressed paddle. This paddle is internally connected to the
ground of the chip. Solder the paddle to the low impedance
ground plane on the PCB to ensure the specified electrical
performance and to provide thermal relief. To further reduce
thermal impedance, it is recommended that the ground planes
on all layers under the paddle be stitched together with vias.
Likewise, driving Input 2 (VIN2 and VIP2) realizes the middle
gain (12 dB into a 200 Ω load) by installing 0 Ω at R5 and R6
and leaving R3 and R4 open. R1 and R2 must be 29 Ω for a
50 Ω input impedance.
For the maximum gain (15.5 dB into a 200 Ω load), both inputs
are driven by installing 0 Ω resistors at R3, R4, R5, and R6. R1
and R2 must be 40.2 Ω for a 50 Ω input impedance.
EVALUATION BOARD
Figure 45 shows the schematic of the ADL5562 evaluation board.
The board is powered by a single supply in the 3 V to 3.6 V range.
The power supply is decoupled by 10 µF and 0.1 µF capacitors.
The balanced input and output interfaces are converted to
single ended with a pair of baluns (M/A-COM ETC1-1-13).
The balun at the input, T1, provides a 50 Ω single-ended-todifferential transformation. The output balun, T2, and the
matching components are configured to provide a 200 Ω to 50 Ω
impedance transformation with an insertion loss of about 17 dB.
Table 14 details the various configuration options of the evaluation
board. Figure 46 and Figure 47 show the component and circuit
layouts of the evaluation board.
GND
T1
J1
R1
40.2Ω
C12
0.1µF
C2
0.01µF
R2
40.2Ω
R4
0Ω
R6
0Ω
14
13
GND
GND
GND
GND
VIP2
ENBL 12
2
VIP1
VOP 11
3
VIN1
ADL5562
C9
0.01µF
VON 10
VIN2
VCC
5
VCC
VCC
6
7
C8
0.1µF
AGND
C10
0.01µF
4
ENBL
VPOS
P1
1
R5
0Ω
R3
0Ω
15
VOCM 9
VCC
8
T2
R7
84.5Ω
R9
34.8Ω
R8
84.5Ω
R10
34.8Ω
C4
0.1µF
C5
0.1µF
C6
0.1µF
J3
C13
0.1µF
C11
0.1µF
J2
VPOS
C3
10µF
R11
OPEN
C7
0.1µF
08003-040
C1
0.01µF
16
Figure 45. Evaluation Board Schematic
Table 14. Evaluation Board Configuration Options
Component
VPOS, GND
C3, C4, C5,
C6, C7, C11
J1, R1, R2, R3,
R4, R5, R6, C1,
C2, C12, T1
J3, R7, R8, R9,
R10, R11, C9,
C10, C13, T2
ENBL, P1, C8
Description
Ground and supply vector pins.
Power supply decoupling. The supply decoupling consists of a 10 µF capacitor (C3)
to ground. C4 to C7 are bypass capacitors. C11 ac couples VREF to ground.
Input interface. The SMA labeled J1 is the input. T1 is a 1-to-1 impedance ratio balun
to transform a single-ended input into a balanced differential signal. C1 and C2
provide ac coupling. C12 is a bypass capacitor. R1 and R2 provide a differential 50 Ω
input termination. R3 to R6 are used to select the input for the pin-strappable gain.
Maximum gain: R3, R4, R5, R6 = 0 Ω; and R1, R2 = 40.2 Ω. Middle gain: R5, R6 = 0 Ω; and R3,
R4 = open; R1, R2 = 33 Ω. Minimum gain: R3, R4 = 0 Ω; and R5, R6 = open; R1, R2 = 29 Ω.
Output interface. The SMA labeled J3 is the output. T2 is a 1-to-1 impedance ratio
balun to transform a balanced differential signal to a single-ended signal. C13 is a
bypass capacitor. R7, R8, R9, and R10 are provided for generic placement of matching
components. The evaluation board is configured to provide a 200 Ω to 50 Ω impedance
transformation with an insertion loss of 17 dB. C9 and C10 provide ac coupling.
Device enable. C8 is a bypass capacitor. When the P1 jumper is set toward the VPOS label,
the ENBL pin is connected to the supply, enabling the device. In the opposite direction,
toward the GND label, the ENBL pin is grounded, putting the device in power-down mode.
Rev. F | Page 19 of 21
Default Condition
VPOS, GND = installed
C3 = 10 µF (Size D),
C4, C5, C6, C7, C11 = 0.1 µF (Size 0402)
J1 = installed,
R1, R2 = 40.2 Ω (Size 0402),
R3, R4, R5, R6 = 0 Ω (Size 0402),
C1, C2 = 0.01 µF (Size 0402),
C12 = 0.1 µF (Size 0402)
T1 = ETC1-1-13 (M/A-COM)
J3 = installed,
R7, R8 = 84.5 Ω (Size 0402),
R9, R10 = 34.8 Ω (Size 0402),
R11 = open (Size 0402),
C9, C10 = 0.01 µF (Size 0402),
C13 = 0.1 µF (Size 0402)
T2 = ETC1-1-13 (M/A-COM)
ENBL, P1= installed,
C8 = 0.1 µF (Size 0402)
Data Sheet
08003-042
08003-041
ADL5562
Figure 47. Layout of Evaluation Board, Circuit Side
Figure 46. Layout of Evaluation Board, Component Side
Rev. F | Page 20 of 21
Data Sheet
ADL5562
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.23
0.18
0.50
BSC
13
PIN 1
INDICATOR AREA OPTIONS
16
(SEE DETAIL A)
12
1
1.75
1.60 SQ
1.45
EXPOSED
PAD
9
TOP VIEW
0.80
0.75
0.70
SIDE VIEW
PKG-005138
SEATING
PLANE
0.50
0.40
0.30
4
8
5
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
02-23-2017-E
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
Figure 48. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADL5562ACPZ-R7
ADL5562ACPZ-WP
ADL5562-EVALZ
1
Temperature
Range
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead Lead Frame Chip Scale Package [LFCSP], 7” Tape and Reel
16-Lead Lead Frame Chip Scale Package [LFCSP], Waffle Pack
Evaluation Board
Z = RoHS Compliant Part.
©2009–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08003-0-9/17(F)
Rev. F | Page 21 of 21
Package
Option
CP-16-22
CP-16-22
Branding
Q1Q
Q1Q
Ordering
Quantity
1,500
50
Similar pages