AS4C1M16E5 ® 5V 1M×16 CMOS DRAM (EDO) Features • 1024 refresh cycles, 16 ms refresh interval • Organization: 1,048,576 words × 16 bits • High speed - RAS-only or CAS-before-RAS refresh Read-modify-write • TTL-compatible, three-state DQ • JEDEC standard package and pinout - 45/50/60 ns RAS access time - 20/20/25 ns hyper page cycle time - 10/12/15 ns CAS access time - 400 mil, 42-pin SOJ - 400 mil, 44/50-pin TSOP II • Low power consumption • 5V power supply (AS4C1M16E5) • 3V power supply (AS4LC1M16E5) - Active: 740 mW max (AS4C1M16E5-60) - Standby: 5.5 mW max, CMOS DQ • Extended data out • Industrial and commercial temperature available Pin arrangement Pin designation TSOP II SOJ Vcc DQ1 DQ2 DQ3 DQ4 Vcc DQ5 DQ6 DQ7 DQ8 NC NC WE RAS NC NC A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS VCC DQ1 DQ2 DQ3 DQ4 VCC DQ5 DQ6 DQ7 DQ8 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS DQ16 DQ15 DQ14 DQ13 VSS DQ12 DQ11 DQ10 DQ9 NC NC NC WE RAS NC NC A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS Pin(s) Description A0 to A9 Address inputs RAS Row address strobe DQ1 to DQ16 Input/output OE Output enable WE Write enable UCAS Column address strobe, upper byte LCAS Column address strobe, lower byte VCC Power VSS Ground Selection guide Symbol -45 -50 -60 Unit Maximum RAS access time tRAC 45 50 60 ns Maximum column address access time tAA 23 25 30 ns Maximum CAS access time tCAC 10 12 15 ns Maximum output enable (OE) access time tOEA 12 13 15 ns Minimum read or write cycle time tRC 75 80 100 ns Minimum hyper page mode cycle time tHPC 20 20 25 ns Maximum operating current ICC1 155 145 135 mA Maximum CMOS standby current ICC5 1.0 1.0 1.0 mA 4/11/01; v.1.0 Alliance Semiconductor P. 1 of 22 Copyright ©Alliance Semiconductor. All rights reserved. AS4C1M16E5 ® Functional description The AS4C1M16E5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as 1,048,576 words × 16 bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory in personal and portable PCs, workstations, and multimedia and router switch applications. The AS4C1M16E5 features hyper page mode operation where read and write operations within a single row (or page) can be executed at very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs, respectively. Also, RAS is used to make the column address latch transparent, enabling application of column addresses prior to xCAS assertion. The AS4C1M16E5 provides dual UCAS and LCAS for independent byte control of read and write access. Extended data out (EDO), also known as 'hyper-page mode,' enables high speed operation. In contrast to 'fast-page mode' devices, data remains active on outputs after xCAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of RAS and xCAS going high. Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using: • RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence. • Hidden refresh: xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data. • CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally. Outputs are high-impedence (OE and WE are don't care). • Normal read or write cycles refresh the row being accessed. The AS4C1M16E5 is available in the standard 42-pin plastic SOJ and 44/50-pin TSOP II packages, respectively. The AS4C1M16E5 device operates with a single power supply of 5V ± 0.5V and provides TTL compatible inputs and outputs. GND RAS UCAS RAS clock generator A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CAS clock generator LCAS WE WE clock generator Column decoder Sense amp Data DQ buffers DQ1 to DQ16 OE Row decoder VCC Address buffers Refresh controller Logic block diagram 1024 × 1024 × 16 Array (16,777,216) Substrate bias generator Recommended operating conditions Parameter Supply voltage Input voltage Ambient operating temperature †V IL Commercial Industrial Symbol Min Nominal Max Unit VCC 4.5 5.0 5.5 V GND 0.0 0.0 0.0 V VIH 2.4 – VCC V VIL –0.5† – 0.8 V 0 – 70 -40 – 85 TA °C min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unless otherwise specified. 4/11/01; v.1.0 Alliance Semiconductor P. 2 of 22 AS4C1M16E5 ® Absolute maximum ratings Parameter Symbol Min Max Unit Input voltage Vin -1.0 +7.0 V Input voltage (DQs) VDQ -1.0 VCC + 0.5 V Power supply voltage VCC -1.0 +7.0 V Storage temperature (plastic) TSTG -65 +150 °C Soldering temperature × time TSOLDER – 260 × 10 o Power dissipation PD – 1 W Short circuit output current Iout – 50 mA C × sec Truth table Addresses RAS LCAS UCAS WE OE tR tC DQ0 to DQ15 Standby H H to X H to X X X X X High-Z Word read L L L H L ROW COL Data out Lower byte read L L H H L ROW COL Lower byte, Upper byte, Data out Upper byte read L H L H L ROW COL Lower byte, Data out, Upper byte Word (early) write L L L L X ROW COL Data in Lower byte (early) write L L H L X ROW COL Lower byte, Data in, Upper byte, High-Z Upper byte (early) write L H L L X ROW COL Lower byte, High-Z, Upper byte, Data in Read write L L L H to L L to H ROW COL Data out, Data in 1,2 1st cycle L H to L H to L H L ROW COL Data out 2 2nd cycle L H to L H to L H L n/a COL Data out 2 Any cycle L L to H L to H H L n/a n/a Data out 2 1st cycle L H to L H to L L X ROW COL Data in 1 EDO write 2nd cycle L H to L H to L L X n/a COL Data in 1 EDO read write 1st cycle L H to L H to L H to L L to H ROW COL Data out, Data in 1,2 2nd cycle L H to L H to L H to L L to H n/a COL Data out, Data in 1,2 L H H X X ROW n/a High Z H to L L L H X X X High Z Operation EDO read RAS only refresh CBR refresh 4/11/01; v.1.0 Alliance Semiconductor Notes 3 P. 3 of 22 AS4C1M16E5 ® DC electrical characteristics -45 Parameter Symbol Test conditions -50 -60 Min Max Min Max Min Max Unit Notes Input leakage current IIL 0V ≤ Vin ≤ VCC (max) Pins not under test = 0V -5 +5 -5 +5 -5 +5 µA Output leakage current IOL DOUT disabled, 0V ≤ Vout ≤ VCC (max) -5 +5 -5 +5 -5 +5 µA Operating power supply current ICC1 RAS, UCAS, LCAS, Address cycling; tRC=min – 155 – 145 – 135 mA TTL standby power supply current ICC2 RAS = UCAS = LCAS ≥ VIH, all other inputs at VIH or VIL – 2.0 – 2.0 – 2.0 mA Average power supply current, RAS refresh mode or CBR ICC3 RAS cycling, UCAS = LCAS ≥ VIH, tRC = min of RAS low after XCAS low. – 145 – 135 – 125 mA 4 EDO page mode average power supply current ICC4 RAS = VIL, UCAS or LCAS, address cycling: tHPC = min – 130 – 120 – 110 mA 4, 5 CMOS standby power supply current ICC5 RAS = UCAS = LCAS = VCC - 0.2V, F=0 – 1.0 – 1.0 – 1.0 mA VOH IOUT = -5.0 mA 2.4 – 2.4 – 2.4 – V VOL IOUT = 4.2 mA – 0.4 – 0.4 – 0.4 V ICC6 RAS, UCAS or LCAS cycling, tRC = min – 155 – 145 – 135 mA Output voltage CAS before RAS refresh current 4/11/01; v.1.0 Alliance Semiconductor 4,5 P. 4 of 22 AS4C1M16E5 ® AC parameters common to all waveforms -45 -50 -60 Symbol Parameter Min Max Min Max Min Max Unit Notes tRC Random read or write cycle time 75 – 80 – 100 – ns tRP RAS precharge time 30 – 30 – 40 – ns tRAS RAS pulse width 45 10K 50 10K 60 10K ns tCAS CAS pulse width 8 10K 8 10K 10 10K ns tRCD RAS to CAS delay time 15 35 15 35 15 43 ns 9 tRAD RAS to column address delay time 8 25 9 25 10 30 ns 10 tRSH CAS to RAS hold time 10 – 10 – 10 – ns tCSH RAS to CAS hold time 40 – 40 – 50 – ns tCRP CAS to RAS precharge time 5 – 5 – 5 – ns tASR Row address setup time 0 – 0 – 0 – ns tRAH Row address hold time 8 – 8 – 10 – ns tT Transition time (rise and fall) 1 50 1 50 1 50 ns 7,8 tREF Refresh period – 16 – 16 – 16 ms 6 tCP CAS precharge time 8 – 8 – 10 – ns tRAL Column address to RAS lead time 25 – 25 – 30 – ns tASC Column address setup time 0 – 0 – 0 – ns tCAH Column address hold time 8 – 8 – 10 – ns Read cycle -45 Symbol Parameter tRAC -50 -60 Min Max Min Max Min Max Unit Access time from RAS – 45 – 50 – 60 ns 9 tCAC Access time from CAS – 10 – 12 – 15 ns 9,16 tAA Access time from address – 23 – 25 – 30 ns 10,16 tRCS Read command setup time 0 – 0 – 0 – ns tRCH Read command hold time to CAS 0 – 0 – 0 – ns 12 tRRH Read command hold time to RAS 0 – 0 – 0 – ns 12 4/11/01; v.1.0 Alliance Semiconductor Notes P. 5 of 22 AS4C1M16E5 ® Write cycle -45 Symbol Parameter tWCS -50 -60 Min Max Min Max Min Max Unit Notes Write command setup time 0 – 0 – 0 – ns 14 tWCH Write command hold time 10 – 10 – 10 – ns 14 tWP Write command pulse width 10 – 10 – 10 – ns tRWL Write command to RAS lead time 10 – 10 – 10 – ns tCWL Write command to CAS lead time 8 – 8 – 10 – ns tDS Data-in setup time 0 – 0 – 0 – ns 15 tDH Data-in hold time 8 – 8 – 10 – ns 15 Read-modify-write cycle -45 -50 -60 Symbol Parameter Min Max Min Max Min Max Unit Notes tRWC Read-write cycle time 105 – 113 – 135 – ns tRWD RAS to WE delay time 65 – 67 – 77 – ns 14 tCWD CAS to WE delay time 30 – 32 – 35 – ns 14 tAWD Column address to WE delay time 40 – 42 – 47 – ns 14 Refresh cycle -45 Symbol Parameter tCSR -50 -60 Min Max Min Max Min Max Unit CAS setup time (CAS-before-RAS) 5 – 5 – 5 – ns 6 tCHR CAS hold time (CAS-before-RAS) 8 – 8 – 10 – ns 6 tRPC RAS precharge to CAS hold time 0 – 0 – 0 – ns tCPT CAS precharge time (CBR counter test) 10 – 10 – 10 – ns 4/11/01; v.1.0 Alliance Semiconductor Notes P. 6 of 22 AS4C1M16E5 ® Hyper page mode cycle -45 -50 -60 Symbol Parameter Min Max Min Max Min Max Unit tCPWD CAS precharge to WE delay time 45 – 45 – 52 – ns tCPA Access time from CAS precharge – 28 – 28 – 35 ns tRASP RAS pulse width 45 100K 50 100K 60 100K ns tDOH Previous data hold time from CAS 5 – 5 – 5 – ns tREZ Output buffer turn off delay from RAS 0 13 0 13 0 15 ns tWEZ Output buffer turn off delay from WE 0 13 0 13 0 15 ns tOEZ Output buffer turn off delay from OE 0 13 0 13 0 15 ns tHPC Hyper page mode cycle time 20 – 20 – 25 – ns tHPRWC Hyper page mode RMW cycle 47 – 47 – 56 – ns tRHCP RAS hold time from CAS 30 – 30 – 35 – ns Notes 16 Output enable -45 Symbol Parameter tCLZ -50 -60 Min Max Min Max Min Max Unit CAS to output in Low Z 0 – 0 – 0 – ns tROH RAS hold time referenced to OE 8 – 8 – 10 – ns tOEA OE access time – 13 – 13 – 15 ns tOED OE to data delay 13 – 13 – 15 – ns tOEZ Output buffer turnoff delay from OE 0 13 0 13 0 15 ns tOEH OE command hold time 10 – 10 – 10 – ns tOLZ OE to output in Low Z 0 – 0 – 0 – ns tOFF Output buffer turn-off time 0 13 0 13 0 15 ns 4/11/01; v.1.0 Alliance Semiconductor Notes 11 11 11,13 P. 7 of 22 AS4C1M16E5 ® Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Write cycles may be byte write cycles (either LCAS or UCAS active). Read cycles may be byte read cycles (either LCAS or UCAS active). One CAS must be active (either LCAS or UCAS). ICC1, ICC3, ICC4, and ICC6 are dependent on frequency. ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after extended periods of bias without clocks (greater than 8 ms). AC Characteristics assume tT = 2 ns. All AC parameters are measured with a load as described in AC test conditions below. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA. Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent). Either tRCH or tRRH must be satisfied for a read cycle. tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD ≥ tRWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles. Access time is determined by the longest of tCAA or tCAC or tCPA tASC ≥ tCP to achieve tPC (min) and tCPA (max) values. These parameters are sampled and not 100% tested. These characteristics apply to AS4C1M16E5 5V devices. AC test conditions - Access times are measured with output reference levels of VOH = 2.4V and VOL = 0.4V, VIH = 2.4V and VIL = 0.8V - Input rise and fall times: 2 ns Dout 100 pF* +5V +3.3V R1 = 828Ω R2 = 295Ω R1 = 828Ω Dout 50 pF* GND Figure A: Equivalent output load (AS4C1M16E5) R2 = 295Ω *including scope and jig capacitance GND Figure B: Equivalent output load (AS4LC1M16E5) Key to switching waveforms Rising input 4/11/01; v.1.0 Falling input Undefined output/don’t care Alliance Semiconductor P. 8 of 22 AS4C1M16E5 ® Read waveform tRC tRAS tRCD tRSH tRP RAS tCSH tCRP tCAH tCAS tASC tRCS UCAS LCAS tRAD Address tRAL tRAH tASR Row address Column address tRRH tRCH WE tROH tWEZ tROH OE tOEZ tRAC tAA tOFF (see note 11) tOEA tCAC tREZ tCLZ DQ Data out tOLZ Upper byte read waveform tRC tRAS tRP RAS tRCD tRSH tCSH tCRP tCRP tCAS UCAS tRPC tCRP LCAS tRAH tRAL tRAD tASC tASR Address Row tCAH Column tRCH tRRH tRCS WE tROH tWEZ OE tOLZ tRAC tOEA tREZ tOEZ tAA tCAC tCLZ Upper DQ tOFF Data out Lower DQ 4/11/01; v.1.0 Alliance Semiconductor P. 9 of 22 AS4C1M16E5 ® Lower byte read waveform tRC tRAS tRP RAS tRCD tRSH tCSH tCRP tCRP tCAS LCAS tCRP tRPC UCAS tASC tRAH tRAL tRAD tASR tCAH Address Row Column tRCH tRRH tRCS WE tROH tWEZ OE Upper DQ tRAC tREZ tOEA tOLZ tOEZ tAA tCAC tOFF tCLZ Lower DQ Data out Early write waveform tRC tRAS tRP RAS tCSH tRSH tCRP tRCD tCAS UCAS, tRAD LCAS tRAL tASC tASR Address tRAH tCAH Row address Column address tCWL tRWL tWP tWCS tWCH WE OE tDS DQ 4/11/01; v.1.0 tDH Data in Alliance Semiconductor P. 10 of 22 AS4C1M16E5 ® Upper byte early write waveform tRC tRAS tRP RAS tASR tRAD tRAL tRAH Address Row address Column address tCAH tRSH tASC tRCD tCSH tCRP tCAS tCRP UCAS tCRP tRPC LCAS tCWL tWCH tWCS tRWL tWP WE OE tDS tDH Upper DQ Data in Lower DQ Lower byte early write waveform tRC tRAS tRP RAS tRAD tASR Address tRAL tRAH Row address Column address tCRP tRPC UCAS tASC tRCD tCAH tCAS tCSH tRSH tCRP tCRP LCAS tRWL tCWL tWCH tWP tWCS WE OE Upper DQ tDS Lower DQ 4/11/01; v.1.0 tDH Data in Alliance Semiconductor P. 11 of 22 AS4C1M16E5 ® Write waveform OE controlled tRC tRAS tRP RAS tCSH tRSH tCRP tRCD tCAS UCAS, LCAS tRAL tRAD tRAH tASR tASC tCAH Row address Address Column address tRWL tCWL tWP WE tOEH OE tDS tOED tDH Data in DQ Upper byte write waveform OE controlled tRC tRAS tRP RAS tRAD tASR tRAL tRAH Address Row address Column address tCSH tRSH tRCD tCAH tCRP tCAS tASC tCRP UCAS tCRP tRPC LCAS tCWL tRWL tWP WE tOEH OE tDS Upper DQ tDH Data in tOED Lower DQ 4/11/01; v.1.0 Alliance Semiconductor P. 12 of 22 AS4C1M16E5 ® Lower byte write waveform OE controlled tRC tRAS tRP RAS tRAD tASR tRAL tRAH Address Row address Column address tCAH tCAS tRCD tCSH tCRP tACS tRSH tCRP LCAS tCRP tRPC UCAS tCWL tRWL tWP WE tOEH OE Upper DQ tDH tDS Lower DQ Data in Read-modify-write waveform tRWC tRAS tRP RAS tCAS tCRP tRCD tRSH tCSH UCAS LCAS tAR tRAL tRAD tRAH tASR Address tASC tCAH Row address Column address tRWD tRWL tAWD tRCS WE tCWL tCWD tOEA tOEZ tWP tOED OE tRAC tAA tCAC tCLZ Data out DQ tDS tDH Data in tOLZ 4/11/01; v.1.0 Alliance Semiconductor P. 13 of 22 AS4C1M16E5 ® Upper byte read-modify-write waveform tRWC tRAS tRP RAS tCSH tRCD tCAS tRSH tCRP UCAS tCRP tCRP tRPC LCAS tASR tRAD tACS tRAL tCAH tRAH Address Column address tRWD Row tCWL tRWL tAWD tCWD tRCS WE tWP tOEA OE Upper input tDS tOED tOLZ tCLZ tCAC tAA tDH Data in tOEZ tRAC Upper output Data out tOED Lower input Lower output Lower byte read-modify-write waveform tRWC tRAS tRP RAS tCRP tRPC UCAS tCSH tCAS tRSH tRCD tCRP tCRP LCAS tRAD tRAL tACS tASR tCAH tRAH Address Row Column address tCWL tRWD tRWL tWP tAWD tRCS tCWD WE tOEA OE Upper input Upper output tOLZ tOED tDH tDS tOED Lower input tRAC tAA tCAC tCLZ Data in tOEZ Lower output Data out 4/11/01; v.1.0 Alliance Semiconductor P. 14 of 22 AS4C1M16E5 ® Hyper page mode read waveform tRASP tRP RAS tRHCP tCSH tCRP tRCD tCAS UCAS, LCAS tCP tRSH tHPC tAR tRAL tRAD tRAH tASR Address tASC Row tCAH Col address Col address Col address tRCS tRCH tRRH WE tOEA tOEA OE tRAC tCPA tCLZ tCAC tAA DQ tOEZ tOEZ tOFF tCPA Data out Data out tOLZ Data out tCLZ tCLZ Hyper page mode byte write waveform tRASP tRP RAS tCSH UCAS tRCD tCRP tCRP tRSH tCAS tCAS tHPC tCP tHPC tCRP tCAS Address tCAH tRAH tRAD tASC tASR Row tRAL tCAH Column 1 tRPC tCP LCAS tCAH tASC tASC Column 2 Column n tRCH tRCS WE tOEA tOEA tRRH tOEA OE tCAC tCLZ tAA tOLZ tCPA tOEZ Lower DQ Data out 2 tAA tRAC tCAC tCLZ tOLZ tOEZ tCAC tCLZ tAA tCPA tOFF tOEZ Upper DQ Data out 1 Data out n tOLZ 4/11/01; v.1.0 Alliance Semiconductor P. 15 of 22 AS4C1M16E5 ® Hyper page mode early write waveform tRASP tRAH tRWL RAS tCRP tRCD tPC tCSH tCAS UCAS, LCAS tCAH tASC tCP tWCS tRSH tRAL tAR tASR Address tRAD Col address Row address Col address Col address tCWL tWP tWCH tOEH WE OE tHDR tOED tDH tDS DQ Data in Data In Data in Hyper page mode byte early write waveform tRASP tRP RAS tCSH tCRP tRCD tRSH tCAS tCAS tCRP UCAS tCP tCP tHPC tHPC tCAS tCRP tRPC LCAS tRAD tRAH tASR Address Row tRAL tCAH tCAH tASC tASC Column 1 Column 2 tCAH tASC Column n tRWL tWCH tWCH tWCS tWCH tWCS tWCS tWP tCWL tWP tCWL tWP tCWL WE OE tDS Lower DQ tDH Data In 2 tDS tDH tDS tDH Upper DQ Data in 1 4/11/01; v.1.0 Alliance Semiconductor Data in n P. 16 of 22 AS4C1M16E5 ® Hyper page mode read-modify-write waveform tRASP tRP RAS tHPRWC tCSH tRCD UCAS, LCAS tCAS tCRP tRAD tASR tRAH tASC Address tCP tASC tCAH Row ad Col ad Col ad tRWD tRCS tRAL tASC tCAH tCAH Col address tCPWD tCWL tCWD tCWD tRWL tCWD tAWD tCWL tAWD tWP WE tOEA tOEZ tOED tOEA OE tAA tDH tRAC tCPA tDS tDS tCLZ tCLZ tCAC tCLZ tCAC DQ Data in tCAC Data in Data out Data out Data in Data out CAS before RAS refresh waveform WE = VIH tRC tRP tRAS RAS tRPC tCHR tCP tCSR UCAS, LCAS OPEN DQ RAS only refresh waveform WE = OE = VIH or VIL tRC tRAS tRP RAS UCAS, LCAS Address 4/11/01; v.1.0 tCRP tASR tRPC tRAH Row address Alliance Semiconductor P. 17 of 22 AS4C1M16E5 ® Hyper page mode byte read-modify-write waveform tRASP tRP RAS tCSH tRCD tCRP tRSH tCAS tCAS tCRP UCAS tCP tCP tCAS LCAS tRAL tRAD tCAH tCAH tASR tASC Address tCAH tAWD tRAH R tASC tASC C1 Cn C2 tAWD tCPWD tAWD tCWD tCAH tAWD tCPWD tCWD tCWL tRWD tWP tRWL tCWD tCWL tAWD tCWL tWP tWP WE tOEA tOEA tOEA OE tDH tOED tDH tOED tDS tDS Upper input Data in 1 tRAC tAA tCAC tCLZ tCPA Data in n tAA tCAC tOEZ tOEZ tCLZ Upper output Data out 1 tDH tOED Data out n tDS Lower input Data in 2 tCPA tAA tOEZ tCAC tCLZ Lower output Data out 2 4/11/01; v.1.0 Alliance Semiconductor P. 18 of 22 AS4C1M16E5 ® Hidden refresh waveform (read) tRC tRC tRAS tRP tRAS tRP RAS tCRP tCHR tRCD tRSH tCRP CAS tAR tRAD tCAH tRAH tASC tASR Row Address Col address tRCS tRRH WE tOEA OE tRAC tOFF tAA tCAC tCLZ tOEZ Data out DQ Hidden refresh waveform (write) tRC tRAS tRP RAS tCRP tRCD tRSH tCHR UCAS, LCAS tAR tRAD tRAL tRAH tASR Address tASC tCAH Row address Col address tRWL tWCR tWP tWCS tWCH WE tDS tDH tDHR DQ Data in OE 4/11/01; v.1.0 Alliance Semiconductor P. 19 of 22 AS4C1M16E5 ® CAS before RAS refresh counter test waveform tRAS tRSH tRP RAS tCSR UCAS, tCPT tCAS tCHR LCAS tRAL tASC tCAH Address Col address tAA tCAC tCLZ tOFF tOEZ Read cycle DQ Data out tRRH tRCH tRCS WE tROH tOEA OE tRWL tCWL tWP tWCH Write cycle tWCS WE tDH tDS DQ Data in OE tRWL tRCS tWP tCWD tCWL tAWD Read-Write cycle WE tOEA tOED OE t AA tCLZ tDH tOEZ tCAC DQ 4/11/01; v.1.0 tDS Data out Alliance Semiconductor Data in P. 20 of 22 AS4C1M16E5 ® Package dimensions D e c SOJ A A1 A2 B b c D E E1 E2 e E1 E2 Pin 1 E B A2 A A1 Seating Plane b c 36 35 34 33 32 31 30 29 28 27 26 50 49 48 47 46 45 44 43 42 41 40 42-pin SOJ Min Max 0.128 0.148 0.025 0.105 0.115 0.026 0.032 0.015 0.020 0.007 0.013 1.070 1.080 0.370 NOM 0.395 0.405 0.435 0.445 0.050 NOM 50-pin TSOP II Min (mm) TSOP II A E He 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 d l 1.2 A1 0.05 A2 0.95 1.05 b 0.30 0.45 c 0.12 0.21 d 20.85 21.05 E 10.03 10.29 He 11.56 11.96 e A2 A 0.80 (typical) l A1 b Input capacitance DQ capacitance 4/11/01; v.1.0 0.40 0.60 0–5° e Capacitance 15 Parameter Max (mm) ƒ = 1 MHz, Ta = Room temperature Symbol Signals Test conditions Max Unit CIN1 A0 to A9 Vin = 0V 5 pF CIN2 RAS, UCAS, LCAS, WE, OE Vin = 0V 7 pF CDQ DQ0 to DQ15 Vin = Vout = 0V 7 pF Alliance Semiconductor P. 21 of 22 AS4C1M16E5 ® AS4C1M16E5 ordering information Package \ RAS access time 45 ns 50 ns 60 ns Plastic SOJ, 400 mil, 42-pin AS4C1M16E5-45JC AS4C1M16E5-50JC AS4C1M16E5-50JI AS4C1M16E5-60JC AS4C1M16E5-60JI TSOP II, 400 mil, 44/50-pin AS4C1M16E5-45TC AS4C1M16E5-50TC AS4C1M16E5-50TI AS4C1M16E5-60TC AS4C1M16E5-60TI AS4C1M16E5 part numbering system AS4 C 1M16E5 –XX X DRAM prefix C = 5V CMOS LC = 3.3V CMOS Device number RAS access time Package: Temperature range J = 42-pin SOJ 400 mil C=Commercial, 0°C to 70 °C T = 44/50-pin TSOP II 400 mil I=Industrial, -40°C to 85°C 4/11/01; v.1.0 Alliance Semiconductor X P. 22 of 22 © Copyright Alliance Semiconductor Corporation. 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