PortMakerII AAL5 Firmware C X 2 74 7 0 Traffic Stream Processor OC-12 Adaptation Layer 5 SAR PortMakerII firmware provides proven, reliable and fully supported binary applications for the CX27470 Traffic Stream Processor. The ATM adaptation layer 5 (AAL5) application provides a bi-directional OC-12 throughput > K E Y F E AT U R E S > Bi-directional OC-12 throughput >∑ITU I.363.5 compliant AAL5 SAR > Reassembly time-out > ATM Forum TM 4.1 traffic shaping ITU I.363.5 SAR, traffic shaping and a rich feature set. The firmware is also available with a source code license to allow customization and product differentiation. AAL5 Segmentation and Reassembly (SAR) The PortMakerII AAL5 firmware application complies with the ITU I.363.5 standard, and also conforms to the ATM Forum PICS Proforma for the AAL Type 5 tests. The firmware provides OC-12 throughput with 32K connections > Encapsulation/ De-encapsulation > Per VC queuing > Choice of segmenter queue admission policies: - Weighted random early detection (WRED), - Per VC flow control - Per VC early packet discard (EPD) > VP and VC tunnels > Support for raw cells (AAL0) > Per PHY and per connection statistics > Host control via PCI bus and software API > Traffic shaping rates configurable from 0.006% to 100% of line rate, with 1% accuracy > Supports 32K bi-directional connections in bi-directional mode. It can also be configured in a uni-directional configuration (i.e., two chip solution) with 2xOC-12 throughput and 64K connections. ATM cell traffic uses the UTOPIA interface on the CX27470, while packet traffic can use either the UTOPIA/POS interface for streaming mode operation, or the PCI bus for shared memory operation. Host based management of the SAR is accomplished via the PCI bus using commands, acknowledgements, indications, and alarms. forum traffic management 4.1 specification. The host selects the shaping parameters and priority on a per VC basis at open channel time. A four level strict priority scoreboard based mechanism is used to schedule cells for transmission, allowing quality of service (QoS) level guarantees. Shaping rates are available from 0.006% to 100% of line rate, with 1% accuracy. Traffic Shaping Buffer Management Traffic shaping is provided at the output of the segmen- Two pools of buffers are supported: internal buffers and tation function. Each connection has two generic cell host buffers. Internal buffers occupy local SDRAM and rate algorithms (GCRAs) that support the CBR.1, VBR.1, are 64 bytes in length. Internal buffers are allocated to UBR.1 and UBR.2 conformance definitions in the ATM one of 16 buffer classes during initialization. > PortMakerII AAL5 Firmware Host buffers are configurable in size and can be placed VC Tunnels with Weighted Fair Queuing either in local SDRAM or in host memory on the PCI bus. A segmenter VC tunnel provides up to 8 class of service (CoS) Host buffers are optionally used for packets output from queues, allowing packets from each CoS queue to be multi- the reassembler, when the shared memory mode of operation plexed onto a single channel. The CoS queues are serviced is used. Up to 256 Mbytes of local SDRAM are supported for using a weighted fair queuing (WFQ) algorithm. Fairness is both internal and host buffers. measured on a per cell basis, however full packets are transmitted at a time. The tunnel itself is then shaped in the same Congestion Control manner as ordinary VCs. Segmenter packets are stored in per VC queues. Queue admission is controlled by one of three methods selected at Encapsulation/De-encapsulation open channel time: 1) weighed random early discard (WRED), 2) The segmenter offers optional 8- or 10-byte encapsulation, per VC flow control, or 3) per VC early packet discard (EPD). intended to support routed IPv4 and Ethernet PDUs as The WRED algorithm discards packets in a manner that opti- defined in RFC 2684. The reassembler offers optional strip- mizes the overall network performance of TCP/IP connections. ping of 0 to 31 bytes. All encapsulation and de-encapsulation Up to 128 sets of WRED parameters are supported, selected parameters are determined on a per channel basis. on a per packet basis. The per VC flow control option sends indications to the host when a configurable high and low Statistics threshold are crossed (with hysteresis). Per VC EPD is similar The segmenter provides the following counters on both a per to flow control except that packets are dropped when the channel and per port basis: bytes transmitted, packets trans- high threshold is exceeded, and no indications are sent. mitted, packets discarded during queue admission, and packets discarded due to error conditions. Both the segmenter and reassembler provide per buffer class EPD when a configurable threshold is exceeded, and partial The reassembler provides the following counters on both a packet discard (PPD) when the buffer class is exhausted. per channel and per port basis: bytes received, packets received, packets discarded during queue admission, and VP Tunnels with Weighted Round Robin packets discarded due to error conditions. A segmenter VP tunnel consists of a group of VCs, each of which gains access to the tunnel using a weighted round robin Memory Requirements scheme. This allows proportional bandwidth sharing among the The PortMakerII AAL5 application supports up to 256 Mbytes VCs. The tunnel itself is then shaped in the same manner as of SDRAM used for data buffers. Program and context storage ordinary VCs. require 4 or 8 Mbytes of SRAM to support either 16K or 32K connections, respectively. C X 2 74 7 0 developers wishing to customize or enhance existing applica- Applications tions. The modular PortMakerII architecture also facilitates The PortMakerII AAL5 firmware is intended for use in enter- the addition of completely new features, allowing developers prise, aggregation, edge, and core routers, multi-service edge to concentrate their efforts on the value added functions of switches, optical edge equipment, and DSLAMS. A typical their application. application using the CX27470 running PortMakerII AAL5 firmware is shown below. Control and Management Switch or Router UTOPIA POS packets ™ MindSpeed CX27470 Traffic Stream Processor cells PHY Layer OC-12 4xOC-3 API TSP Software Development Kit Communications Processing Applications Off-the-Shelf Customized Applications Mindspeed Applications Custom Applications Network Function Library Shell (e.g. CX29704) Communications Processor PCI Mgmt µP Management & packets Modular PortMakerII Architecture Application Block Diagram Development Tools The TSP software development kit (SDK) is intended for source code developers. It provides a full-featured set of Source Code Development Environment hardware and software co-development tools for the TSP PortMakerII AAL5 is based on a modular architecture using a product family. A significant reduction in design cycle time is system management kernel (or ‘shell’), and a set of transfer achieved by enabling hardware integration, software integra- functions. The shell communicates with external host proces- tion, and debugging to start early in the product development sors, dispatches commands and performs background task cycle. The SDK consists of a hardware and software co-simu- scheduling. The transfer functions consist of initialization lator, an assembler/linker, a debugger and TSP board devel- routines, command handlers and event handlers, which opers kit (BDK). provide the segmentation and reassembly processing. An event driven architecture is used to dispatch the appro- The BDK is intended for both source and binary customers. It priate handler to service incoming data or commands. provides hardware simulation models (SWIFT and Verilog), test benches, bus functional models, IBIS models and a reference The Network function library contains the source code design. Reference code is provided to facilitate host application modules used to implement the off-the-shelf transfer func- integration. A comprehensive set of diagnostics is provided to tions. These fully tested routines are available to source code assist with testing. > Product Features Functions • ITU I.363.5 AAL5 SAR • OC-12 throughput • 32K bi-directional connections • Traffic shaping - dual GCRA per connection • Supports the following traffic shaping conformance definitions: • VP tunnels with WRR access • VC tunnels with WFQ access • Congestion control: - Weighted random early detection (WRED) - Per VC flow control - Per VC early packet discard (EPD) • Reassembly time-out - CBR.1 • Encapsulation/De-encapsulation - VBR.1 • Support for raw cells (AAL0) - UBR.1 • Host control via PCI bus • Per connection and per port statistics - Bytes transmitted/received - Packets transmitted/received - Packets discarded due to resource exhaustion Ordering Information - Packets discarded due to error conditions • Source: MXA-pm2a5-sc • Memory requirements: – 16 to 256 Mbytes of SDRAM – 4 Mbytes of SRAM - UBR.2 www.mindspeed.com/salesoffices General Information: U.S. and Canada: (800) 854-8099 International: (949) 483-6996 Headquarters – Newport Beach 4000 MacArthur Blvd., East Tower Newport Beach, CA 92660-3007 27470-BRF-002-A M03-0806 See the CX27470 data sheet for a description of the hardware interfaces and device characteristics. © 2003 Mindspeed Technologies™. All rights reserved. Mindspeed and the Mindspeed logo are trademarks of Mindspeed Technologies. All other trademarks are the property of their respective owners. Although Mindspeed Technologies strives for accuracy in all its publications, this material may contain errors or omissions and is subject to change without notice. This material is provided as is and without any express or implied warranties, including merchantability, fitness for a particular purpose and noninfringement. Mindspeed Technologies shall not be liable for any special, indirect, incidental or consequential damages as a result of its use. • Binary: MXA-pm2a5-bn