AD ADA4891-1ARJZ-RL Low cost cmos, high speed, rail-to-rail amplifier Datasheet

Low Cost CMOS, High Speed,
Rail-to-Rail Amplifiers
ADA4891-1/ADA4891-2
FEATURES
CONNECTION DIAGRAMS
NC 1
8
NC
–IN 2
7
+VS
+IN 3
6
VOUT
–VS 4
5
NC
NC = NO CONNECT
08054-026
ADA4891-1
Low cost
High speed and fast settling
−3 dB bandwidth: 240 MHz (G = +1)
Slew rate: 170 V/μs
Settling time to 0.1%: 28 ns
Video specifications (G = +2, RL = 150 Ω)
0.1 dB gain flatness: 25 MHz
Differential gain error: 0.05%
Differential phase error: 0.25°
Single-supply operation
Wide supply range: 2.7 V to 5.5 V
Output swings to within 50 mV of supply rails
Low distortion: 79 dBc SFDR @ 1 MHz
Linear output current: 150 mA @ −50 dBc
Low power of 4.4 mA per amplifier
Figure 1. 8-Lead SOIC (R-8)
ADA4891-1
VOUT 1
5
+VS
4
–IN
+IN 3
08054-001
–VS 2
Figure 2. 5-Lead SOT-23 (RJ-5)
APPLICATIONS
Imaging
Consumer video
Active filters
Coaxial cable drivers
Clock buffers
Photodiode preamp
Contact image sensor and buffers
8
+VS
–IN1 2
7
OUT
+IN1 3
6
–IN2
–VS 4
5
+IN2
NC = NO CONNECT
08054-027
ADA4891-2
OUT1 1
Figure 3. 8-Lead SOIC (R-8) and 8-Lead MSOP (RM-8)
GENERAL DESCRIPTION
The ADA4891 family of amplifiers are ideal for imaging applications,
such as consumer video, CCD buffers, and contact image sensor
buffers. Low distortion and fast settling time also make them
ideal for active filter applications.
The ADA4891-1/ADA4891-2 are available in a wide variety of
packages. The ADA4891-1 is available in 8-lead SOIC and
5-lead SOT-23 packages. The ADA4891-2 is available in 8-lead
SOIC and 8-lead MSOP packages. The amplifiers are specified to
operate over the extended temperature range of −40°C to +125°C.
0
–1
–2
G = +2
RF = 604Ω
G = +1
RF = 0Ω
–3
–4
–5
G = +5
RF = 604Ω
–6
–7
–8
VS = +5V
–9 RL = 150Ω
VOUT = 2V p-p
–10
0.1
1
10
100
1k
FREQUENCY (MHz)
08054-069
In spite of their low cost, the ADA4891 family provides high
performance and versatility. The rail-to-rail output stage enables
the output to swing within 50 mV of each rail, enabling maximum
dynamic range.
1
NORMALIZED CLOSED-LOOP GAIN (dB)
The ADA4891-1 (single) and ADA4891-2 (dual) are CMOS, high
speed amplifiers that offer high performance at a low cost. The
amplifiers feature true single-supply capability, with an input
voltage range that extends 300 mV below the negative rail.
Figure 4. Large Signal Frequency Response vs. Gain, VS = 5 V
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2010 Analog Devices, Inc. All rights reserved.
ADA4891-1/ADA4891-2
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Values ............................................................... 12
Applications ....................................................................................... 1
Effect of RF on 0.1 dB Gain Flatness ........................................ 13
Connection Diagrams ...................................................................... 1
Driving Capacitive Loads .......................................................... 14
General Description ......................................................................... 1
Terminating Unused Amplifiers .............................................. 15
Revision History ............................................................................... 2
Video Reconstruction Filter ...................................................... 15
Specifications..................................................................................... 3
Layout, Grounding, and Bypassing .............................................. 16
Absolute Maximum Ratings............................................................ 5
Power Supply Bypassing ............................................................ 16
Maximum Power Dissipation ..................................................... 5
Grounding ................................................................................... 16
ESD Caution .................................................................................. 5
Input and Output Capacitance ................................................. 16
Typical Performance Characteristics ............................................. 6
Input-to-Output Coupling ........................................................ 16
Applications Information .............................................................. 12
Leakage Currents ........................................................................ 16
Using the ADA4891 ................................................................... 12
Outline Dimensions ....................................................................... 17
Wideband, Noninverting Operation........................................ 12
Ordering Guide .......................................................................... 18
Wideband, Inverting Gain Operation ..................................... 12
REVISION HISTORY
6/10—Rev. 0 to Rev. A
Changes to Figure 26 ........................................................................ 9
Changes to Figure 33 and Figure 34 ............................................. 10
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
2/10—Revision 0: Initial Version
Rev. A | Page 2 of 20
ADA4891-1/ADA4891-2
SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 1 kΩ to 2.5 V, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate (tR/tF)
Large Signal Frequency Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Harmonic Distortion, HD2/HD3
Harmonic Distortion, HD2/HD3
Input Voltage Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
DC PERFORMANCE
Input Offset Voltage
Test Conditions
Min
MHz
MHz
MHz
V/μs
MHz
ns
fC = 1 MHz, VO = 2 V p-p, G = +1
fC = 1 MHz, VO = 2 V p-p, G = −1
f = 1 MHz
G = +2, RL = 150 Ω to 2.5 V
G = +2, RL = 150 Ω to 2.5 V
f = 5 MHz, G = +2, VO = 2 V p-p
−79/−93
−75/−91
10
0.05
0.25
−80
dBc
dBc
nV/√Hz
%
Degrees
dB
RL = 150 Ω to 2.5 V
±2.5
±3.2
6
+2
83
71
GΩ
pF
V
VCM = 0 V to 3.0 V
5
3.2
−VS − 0.3 to
+VS − 0.8
71
RL = 1 kΩ to 2.5 V
RL = 150 Ω to 2.5 V
1% THD with 1 MHz, 2 V p-p output
Sourcing
Sinking
G = +1, <30% overshoot
0.005 to 4.985
0.065 to 4.9
150
250
225
15
V
V
mA
mA
mA
pF
−50
77
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Positive Power Supply Rejection Ratio (PSRR)
Negative Power Supply Rejection Ratio (PSRR)
OPERATING TEMPERATURE RANGE
Unit
240
90
25
170/210
40
28
Offset Drift
Input Bias Current
Open-Loop Gain
Output Current
Short-Circuit Current
Max
G = +1, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p, RL = 150 Ω to 2.5 V, RF = 604 Ω
G = +2, VO = 2 V p-p, RL = 150 Ω to 2.5 V, RF = 604 Ω
G = +2, VO = 2 V step
G = +2, VO = 2 V p-p, RL = 150 Ω
G = +2, VO = 2 V step
TMIN to TMAX
Common-Mode Rejection Ratio (CMRR)
OUTPUT CHARACTERISTICS
Output Voltage Swing
Typ
2.7
+50
−40
mV
mV
μV/°C
pA
dB
dB
dB
5.5
4.4
65
63
+VS = 5 V to 5.25 V, −VS = 0 V
+VS = 5 V, −VS = −0.25 V to 0 V
Rev. A | Page 3 of 20
±10
+125
V
mA
dB
dB
°C
ADA4891-1/ADA4891-2
TA = 25°C, VS = 3.0 V, RL = 1 kΩ to 1.5 V, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate (tR/tF)
Large Signal Frequency Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
DC PERFORMANCE
Input Offset Voltage
Test Conditions
Min
MHz
MHz
MHz
V/μs
MHz
ns
fC = 1 MHz, VO = 2 V p-p, G = −1
f = 1 MHz
G = +2, RL = 150 Ω to 0.5 V, +VS = 2 V, −VS = −1 V
G = +2, RL = 150 Ω to 0.5 V, + VS = 2 V, −VS = −1 V
f = 5 MHz, G = +2
−70/−89
10
0.23
0.77
−80
dBc
nV/√Hz
%
Degrees
dB
RL = 150 Ω to 1.5 V
±2.5
±3.2
6
+2
76
65
GΩ
pF
V
VCM = 0 V to 1.5 V
5
3.2
−VS − 0.3 to
+VS − 0.8
68
RL = 1 kΩ to 1.5 V
RL = 150 Ω to 1.5 V
1% THD with 1 MHz, 2 V p-p output
Sourcing
Sinking
G = +1
0.005 to 2.985
0.095 to 2.965
50
150
95
15
V
V
mA
mA
mA
pF
−50
72
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current per Amplifier
Positive Power Supply Rejection Ratio (PSRR)
Negative Power Supply Rejection Ratio (PSRR)
OPERATING TEMPERATURE RANGE
Unit
190
75
18
140/230
40
30
Offset Drift
Input Bias Current
Open-Loop Gain
Output Current
Short-Circuit Current
Max
G = +1, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p, RL = 150 Ω to 2.5 V, RF = 604 Ω
G = +2, VO = 2 V p-p, RL = 150 Ω to 2.5 V, RF = 604 Ω
G = +2, VO = 2 V step
G = +2, VO = 2 V p-p, RL = 150 Ω
G = +2, VO = 2 V step
TMIN to TMAX
Common-Mode Rejection Ratio (CMRR)
OUTPUT CHARACTERISTICS
Output Voltage Swing
Typ
2.7
+50
−40
mV
mV
μV/°C
pA
dB
dB
dB
5.5
3.5
76
72
+VS = 3 V to 3.15 V, −VS = 0 V
+VS = 3 V, −VS = −0.15 V to 0 V
Rev. A | Page 4 of 20
±10
+125
V
mA
dB
dB
°C
ADA4891-1/ADA4891-2
ABSOLUTE MAXIMUM RATINGS
Rating
6V
−VS − 0.5 V to +VS
±VS
−65°C to +125°C
−40°C to +125°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
ADA4891-1/ADA4891-2 is limited by the associated rise in
junction temperature. The maximum safe junction temperature
for plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit can cause a shift in parametric
performance due to a change in the stresses exerted on the die
by the package. Exceeding a junction temperature of 175°C for
an extended period can result in device failure.
The still-air thermal properties of the package (θJA), the ambient
temperature (TA), and the total power dissipated in the package
(PD) can be used to determine the junction temperature of the die.
PD = (VS × IS) + (VS − VOUT) × VOUT/RL
where:
VS is the positive supply rail.
IS is the quiescent current.
VOUT is the output of the amplifier.
RL is the output load of the amplifier.
To ensure proper operating, it is necessary to observe the
maximum power derating curve in Figure 5, where it is derived
by setting TJ = 150°C in Equation 1. Figure 5 shows the maximum
safe power dissipation in the package vs. the ambient temperature
for the 5-lead SOT-23 (146°C/W), the 8-lead SOIC (115°C/W),
and the 8-Lead MSOP (133°C/W) on a JEDEC standard
4-layer board.
2.0
TJ = 150 °C
8-LEAD MSOP
1.5
8-LEAD SOIC
1.0
5-LEAD SOT-23
0.5
0
–55
–35
–15
The junction temperature can be calculated as
TJ = TA + (PD × θJA)
(2)
5
25
45
65
85
105
125
AMBIENT TEMPERAURE (°C)
Figure 5. Maximum Power Dissipation vs. Ambient Temperature
(1)
ESD CAUTION
Rev. A | Page 5 of 20
08054-002
Parameter
Supply Voltage
Input Voltage (Common Mode)
Differential Input Voltage
Storage Temperature Range (R)
Operating Temperature Range (A Grade)
Lead Temperature (Soldering, 10 sec)
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. It can be calculated by
MAXIMUM POWER DISSIPATION (W)
Table 3.
ADA4891-1/ADA4891-2
TYPICAL PERFORMANCE CHARACTERISTICS
4
6
CLOSED-LOOP GAIN (dB)
0
–1
G = –1
OR +2
–2
G = +1
–3
–4
G = +10
G = +5
–5
–6
0
–40°C
–3
–6
–7
100
1000
–12
0.1
VS = 3V
VS = 5V
–3
–6
–9
G = +1
VOUT = 200mV p-p
RL = 1kΩ
0
VS = 3V
VOUT = 2V p-p
–0.1
VS = 5V
VOUT = 1.4V p-p
–0.2
–0.4
100
1000
08054-029
10
FREQUENCY (MHz)
4
–40°C
–1
–2
–3
–4
–5
–6
–7
VS = 5V
G = +1
VOUT = 200mV p-p
RL = 1kΩ
1
10
100
1000
FREQUENCY (MHz)
08054-030
–9
10
100
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
1
0
1
0.2
+125°C
2
VS = 3V
VOUT = 1.4V p-p
Figure 10. 0.1 dB Gain Flatness vs. Frequency, G = +2
+25°C
0°C
+85°C
3
–10
0.1
G = +2
RF = 604Ω
RL = 150Ω
0.1
Figure 7. Small Signal Frequency Response vs. Supply Voltage
–8
VS = 5V
VOUT = 2V p-p
–0.3
–0.5
1
1000
0.1
VS = 2.7V
0
–15
0.1
100
Figure 9. Small Signal Frequency Response vs. Temperature, VS = 3 V
3
–12
10
FREQUENCY (MHz)
NORMALIZED CLOSED-LOOP GAIN (dB)
6
1
08054-019
10
VS = 3V
G = +1
VOUT = 200mV p-p
RL = 1kΩ
08054-031
–9
RF = 649Ω
RF = 604Ω
0.1
RF = 698Ω
0
RF = 549Ω
–0.1
–0.2
–0.3
VS = +5V
G = +2
VOUT = 2V p-p
RL = 150Ω
–0.4
0.1
1
10
FREQUENCY (MHz)
Figure 11. 0.1 dB Gain Flatness vs. RF, VS = 5 V
Figure 8. Small Signal Frequency Response vs. Temperature, VS = 5 V
Rev. A | Page 6 of 20
100
08054-020
VS = 5V
–8 VOUT = 200mV p-p
RF = 604Ω
–9
RL = 1kΩ
–10
0.1
1
Figure 6. Small Signal Frequency Response vs. Gain, VS = 5 V
CLOSED-LOOP GAIN (dB)
+125°C
3
1
08054-028
NORMALIZED CLOSED-LOOP GAIN (dB)
2
FREQUENCY (MHz)
CLOSED-LOOP GAIN (dB)
+25°C
0°C
+85°C
3
ADA4891-1/ADA4891-2
–40
0.1
VS = 5V
RL = 1kΩ
VOUT = 2V p-p
–50
–60
RF = 604Ω
–0.2
RF = 549Ω
–0.3
G = +1
SECOND HARMONIC
–80
–90
–100
VS = 3V
G = +2
VOUT = 2V p-p
RL = 150Ω
–0.4
0.1
G = +2
THIRD HARMONIC
–110
1
10
100
FREQUENCY (MHz)
G = +1
THIRD HARMONIC
–120
0.1
1
10
FREQUENCY (MHz)
Figure 15. Harmonic Distortion (HD2, HD3) vs. Frequency, VS = 5 V
Figure 12. 0.1 dB Gain Flatness vs. RF, VS = 3 V
–30
1
VS = 3V
RL = 1kΩ
VOUT = 2V p-p
0
G = +2
RF = 604Ω
–2
–40
G = +1
RF = 0Ω
DISTORTION (dBc)
–1
–3
–4
G = +5
RF = 604Ω
–5
G = –1
RF = 604Ω
–6
G = +1
THIRD HARMONIC
G = +1
SECOND HARMONIC
–50
G = +2
SECOND HARMONIC
–60
+VS = 2V
–70
–7
OUT
G = +2
THIRD HARMONIC
–80
VS = +5V
–9 RL = 150Ω
VOUT = 2V p-p
–10
0.1
1
10
100
1k
FREQUENCY (MHz)
–VS = –1V
1
10
FREQUENCY (MHz)
Figure 16. Harmonic Distortion (HD2, HD3) vs. Frequency, VS = 3 V
–40
4
–50
G = –1
VOUT = 2V p-p
2
1
–60
–1
–2
DISTORTION (dBc)
G = +1
VOUT = 1V p-p
0
G = +2
VOUT = 2V p-p
–3
–4
G = +5
VOUT = 2V p-p
–5
–6
G = –1
SECOND HARMONIC
–70
–80
–90
–100
G = +1
THIRD HARMONIC
–7
G = –1
THIRD HARMONIC
10
100
1000
FREQUENCY (MHz)
08054-037
–120
1
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V p-p)
Figure 17. Harmonic Distortion vs. Output Voltage, VS = 5 V
Figure 14. Large Signal Frequency Response vs. Gain, VS = 3 V
Rev. A | Page 7 of 20
08054-040
–110
VS = 3V
RF = 604Ω
RL = 150Ω
–10
0.1
G = +1
SECOND HARMONIC
VS = 5V
RF = 604Ω
RL = 1kΩ
fC = 1MHz
3
–8
1kΩ
G = +1 CONFIGURATION
–90
0.1
Figure 13. Large Signal Frequency Response vs. Gain, VS = 5 V
–9
IN
50Ω
08054-039
–8
08054-036
NORMALIZED CLOSED-LOOP GAIN (dB)
–70
08054-038
DISTORTION (dBc)
RF = 649Ω
–0.1
–0.5
NORMALIZED CLOSED-LOOP GAIN (dB)
G = +2
SECOND HARMONIC
0
08054-021
NORMALIZED CLOSED-LOOP GAIN (dB)
RF = 698Ω
ADA4891-1/ADA4891-2
–40
6
G = –1
SECOND HARMONIC
+VS = +1.8V
CL = 47pF
4
1kΩ
–70
–VS = –1.2V
–80
G = –1
THIRD HARMONIC
G = +1
SECOND HARMONIC
–90
–100
3
CL = 22pF
CL = 10pF
2
1
0
CL = 0pF
–1
–2
VS = 3V
FOR G = –1, RF = 604Ω,
fC = 1MHz
–120
0.5
0
1.0
1.5
2.0
2.5
3.0
OUTPUT VOLTAGE (V p-p)
–3
–4
0.1
08054-041
G = +1
THIRD HARMONIC
–110
10
100
1k
Figure 21. Small Signal Frequency Response vs. CLOAD (CL)
0.06
VS = 3V
THIRD HARMONIC
–60
0.04
0.02
0
–0.02
–0.04
–0.06
VS = 5V
SECOND HARMONIC
–80
DIFFERENTIAL
PHASE ERROR (Degrees)
–70
VS = 5V
THIRD HARMONIC
–100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V p-p)
–54
50
–72
40
–90
30
–108
20
–126
10
–144
0
–162
0.1
1
10
100
FREQUENCY (MHz)
–180
1k
VOLTAGE NOISE (nV/√Hz)
–36
60
0.01
5TH
6TH
7TH
8TH
9TH 10TH
3RD 4TH 5TH 6TH 7TH 8TH
MODULATING RAMP LEVEL (IRE)
9TH 10TH
0.1
0
–0.1
–0.2
–0.3
VS = 5V, G = +2
RF = 604Ω, RL =150Ω
1ST
2ND
–18
70
–10
0.001
4TH
1k
0
PHASE (Degrees)
80
3RD
Figure 22. Differential Gain and Phase Errors
08054-043
VS = 5V
RL = 1kΩ
2ND
0.2
Figure 19. Harmonic Distortion vs. Output Voltage, G = +2
90
1ST
0.3
08054-042
–90
VS = 5V, G = +2
RF = 604Ω, RL =150Ω
Figure 20. Open-Loop Gain and Phase vs. Frequency
100
10
1
10
VS = 5V
G=1
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 23. Input Voltage Noise vs. Frequency
Rev. A | Page 8 of 20
10M
08054-045
–50
VS = 3V
SECOND HARMONIC
DIFFERENTIAL
GAIN ERROR (%)
G = +2
RF = 604Ω
RL = 150Ω
fC = 1MHz
08054-060
–40
DISTORTION (dBc)
1
FREQUENCY (MHz)
Figure 18. Harmonic Distortion vs. Output Voltage, VS = 3 V
OPEN-LOOP GAIN (dB)
VS = 5V
G = +2
RL = 150Ω
VOUT = 200mV p-p
08054-044
IN
50Ω
CLOSED-LOOP GAIN (dB)
OUT
–60
DISTORTION (dBc)
5
G = +1
CONFIGURATION
–50
ADA4891-1/ADA4891-2
100
VS = 5V
G = +1
VS = 5V
G = +1
VOUT = 2V p-p
RL = 1kΩ
1
OUTPUT VOLTAGE (mV)
OUTPUT IMPEDANCE (Ω)
10
1
RL = 150Ω
0
0.1
5ns/DIV
0.1
1
10
100
FREQUENCY (MHz)
08054-046
0.5V/DIV
0.01
0.01
Figure 27. Large Signal Step Response, VS = 5 V
Figure 24. Closed-Loop Output Impedance vs. Frequency
G=1
VOUT = 200mV p-p
RL = 1kΩ
VS = 3V
G = +1
VOUT = 1V p-p
RL = 1kΩ
0.5
100
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
VS = 3V
08054-049
–1
VS = 5V
0
RL = 150Ω
0
–100
5ns/DIV
Figure 25. Small Signal Step Response, G = +1
1
0.30
VS = +5V
G = +2
RF = 604Ω
RL = 150Ω
VOUT = 2V p-p
0.20
SETTLING (%)
VS = 3V
RL = 150Ω
0
VS = 5V
RL = 150Ω
0.10
0
–0.10
0.5V/DIV
10ns/DIV
–0.20
0.10%/DIV
5ns/DIV
–0.30
0
Figure 26. Large Signal Step Response, G = +2
25
30
35
40
Figure 29. Short-Term Settling Time to 0.1%
Rev. A | Page 9 of 20
08054-061
VS = 3V
RL = 1kΩ
1
08054-047
OUTPUT VOLTAGE (V)
Figure 28. Large Signal Step Response, VS = 3 V
G = +2
VOUT = 2V p-p
RF = 604Ω
VS = 5V
RL = 1kΩ
5ns/DIV
0.5V/DIV
08054-050
50mV/DIV
08054-048
–0.5
45
ADA4891-1/ADA4891-2
3
200
VS = 5V
G = +2
RL = 150Ω
190
VS = ±2.5V
G = –2
RL = 1kΩ
OUTPUT
2
AMPLITUDE (V)
170
160
1
INPUT
0
–1
RISING EDGE
150
–2
140
1.0
–3
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT STEP AMPLITUDE (V)
08054-051
1V/DIV
Figure 33. Output Overdrive Recovery from Positive Rail
Figure 30. Slew Rate vs. Output Step
3
3
VS = ±2.5V
G = +1
RL = 1kΩ
INPUT
5ns/DIV
VS = ±2.5V
G = –2
RL = 1kΩ
INPUT
2
OUTPUT
AMPLITUDE (V)
AMPLITUDE (V)
2
08054-070
SLEW RATE (V/µs)
FALLING EDGE
180
1
1
0
–1
1V/DIV
5ns/DIV
–1
08054-071
–2
1V/DIV
5ns/DIV
–3
Figure 31. Input Overdrive Recovery From Positive Rail
Figure 34. Output Overdrive Recovery from Negative Rail
1
–20
VS = ±2.5V
G = +1
RL = 1kΩ
VS = 5V
–30
INPUT
0
CMRR (dB)
–40
–1
–50
–60
–2
OUTPUT
5ns/DIV
–80
0.1
1
10
FREQUENCY (MHz)
Figure 32. Input Overdrive Recovery from Negative Rail
Figure 35. CMRR vs. Frequency
Rev. A | Page 10 of 20
100
08054-053
1V/DIV
–3
–70
08054-063
AMPLITUDE (V)
OUTPUT
08054-052
0
ADA4891-1/ADA4891-2
6.0
Vs = 5V
G = +1
VS = 5V
QUIESCENT SUPPLY CURRENT (mA)
–20
PSRR (dB)
–30
–40
+PSRR
–50
–60
–PSRR
–70
0.1
1
10
100
FREQUENCY (MHz)
5.0
4.5
4.0
3.5
3.0
–40
08054-054
–80
0.01
5.5
40
60
80
100
120
4.4
QUIESCENT SUPPLY CURRENT (mA)
Vs = 5V
G = +2
RL = 1 kΩ
VOUT = 2V p-p
–30
CROSSTALK (dB)
20
Figure 39. Supply Current per Amplifier vs. Temperature
0
–20
0
TEMPERATURE (ºC)
Figure 36. PSRR vs. Frequency
–10
–20
08054-057
–10
–40
–50
–60
–70
–80
4.2
4.0
3.8
3.6
3.4
3.2
1
10
100
1000
FREQUENCY (MHz)
Figure 37. ADA4891-2 (SOIC) Crosstalk (Output-to-Output) vs. Frequency
OUTPUT SATURATION VOLTAGE (V)
1.0
VS = 5V
0.9 G = –2
RF = 604Ω
0.8
0.7
VOH, +125°C
VOH, +25°C
VOH, –40°C
VOL, +125°C
VOL, +25°C
VOL, –40°C
0.6
0.5
0.4
0.3
0.2
0.1
0
10
20
30
40
50
60
ILOAD (mA)
70
80
90
100
08054-056
0
Figure 38. Output Saturation Voltage vs. Load Current vs. Temperature
Rev. A | Page 11 of 20
3.0
2.7
3.0
3.3
3.6
3.9
4.2
4.5
4.8
SUPPLY VOLTAGE (V)
Figure 40. Supply Current per Amplifier vs. Supply Voltage
5.1
08054-058
–100
0.1
08054-072
–90
ADA4891-1/ADA4891-2
APPLICATIONS INFORMATION
WIDEBAND, INVERTING GAIN OPERATION
USING THE ADA4891
+VS
Understanding the subtleties of the ADA4891 family gives users
insight into how to exact its peak performance. In this section, how
the gain, component values, and parasitics affect the performance
of the ADA4891 are discussed. The wideband, noninverting
configuration of the ADA4891 is shown in Figure 41, while the
wideband, inverting configuration of the ADA4891 is shown
in Figure 42.
0.1µF
10µF
VO
ADA4891-1
50Ω
SOURCE
WIDEBAND, NONINVERTING OPERATION
RL
RG
RF
VI
RT
+VS
0.1µF
08054-024
0.1µF
10µF
10µF
50Ω
SOURCE
–VS
VI
Figure 42. Inverting Configuration
VO
ADA4891-1
RT
Figure 42 shows the inverting gain configuration. To match the
input source impedance for the inverting gain configuration, set
the parallel combination of RT//RG to match that of the input
source impedance.
RL
RF
RG
Note that a bias current cancellation resistor is not required in
the noninverting input of the amplifier because the input bias
current of the ADA4891 is very low (less than 10 pA). Therefore,
the dc errors caused by the bias current are negligible.
10µF
08054-023
0.1µF
–VS
Figure 41. Noninverting Configuration
In Figure 41, RF and RG denote the feedback and the gain resistor,
respectively. Together, RF and RG determine the noise gain of the
amplifier, and the value of RF defines the 0.1 dB bandwidth. The
effect of RF on the 0.1 dB gain flatness is discussed in the Effect
of RF on 0.1 dB Gain Flatness section. Typical RF values range
from 549 Ω to 698 Ω.
For both configurations, it is often useful to increase the RF value
to decrease the loading on the output. Increasing the RF value
improves the harmonic distortion at the expense of reducing
the 0.1 dB bandwidth of the amplifier. This effect is discussed
further in the Effect of RF on 0.1 dB Gain Flatness section.
In a controlled impedance signal path, RT is used as the input
termination resistor designed to match that of the input source
impedance. Note that it is not required for normal operation.
RT is generally set to match the input source impedance.
Table 4 provides a handy reference for various configurations
and shows the effect of gain on the −3 dB small signal bandwidth,
slew rate, and peaking of the ADA4891-1/ADA4891-2. Note
that as the gain increases, the small signal bandwidth decreases
as is expected from the gain bandwidth product relationship. In
addition, the phase margin improves with higher gains, and the
amplifier becomes more stable. As a result, the peaking in the
frequency response is reduced (see Figure 6).
RECOMMENDED VALUES
Table 4. Recommended Values for the ADA4891-1/ADA4891-2 Performance
Gain
−1
+1
+2
+5
+10
Feedback Network Values
RF
RG
604
604
0
0
604
604
604
151
604
67.1
−3 dB Small Signal Bandwidth (MHz)
VOUT = 200 mV p-p
118
236
120
32.5
12.7
Rev. A | Page 12 of 20
Slew Rate (V/μs)
tR
tF
188
192
154
263
178
204
149
154
71
72
Peaking (dB)
1.3
2.6
1.4
0
0
ADA4891-1/ADA4891-2
EFFECT OF RF ON 0.1 dB GAIN FLATNESS
Gain flatness is an important specification in video applications.
It represents the maximum allowable deviation in the signal
amplitude within the pass band. Tests have revealed that the
human eye is unable to distinguish brightness variations of
less than 1%, which translates into a 0.1 dB signal drop within
the pass band, or put simply, 0.1 dB gain flatness.
The PCB layout configuration and bond pads of the chip often
contribute to stray capacitance. The stray capacitance at the
inverting input forms a pole with the feedback and gain resistor.
This additional pole adds phase shift and reduces phase margin
in the closed-loop phase response, causing instability in the
amplifier and peaking in the frequency response.
The feedback capacitor, CF, forms a zero with the feedback resistor,
which cancels out the pole formed by the input stray capacitance
and the gain and feedback resistor. For a first pass in determining
the CF value, use the equation RG × CS = RF × CF, where RG is the
gain resistor, CS is the input stray capacitance, RF is the feedback
resistor, and CF is the feedback capacitor. This is the condition
where the original closed-loop frequency response of the amplifier
is restored as if there is no stray input capacitance. Most often,
however, the value of CF is determined empirically.
Figure 44 shows the effect of using various values for the feedback
capacitors to reduce peaking. In this case, RF = RG = 604 Ω. The
input stray capacitance, together with the board parasitics, is
approximately 2 pF.
RG = RF = 698Ω
0
RG = RF = 549Ω
–0.1
CF = 1pF
0
CF = 3.3pF
0.1
0.2
VS = 5V
G=2
RF = 604Ω
RL = 150Ω
VOUT = 2V p-p
0.3
0.1
1
10
FREQUENCY (MHz)
–0.2
Figure 44. 0.1 dB Gain Flatness vs. CF, VS = 5 V
–0.3
VS = +5V
G = +2
VOUT = 2V p-p
RL = 150Ω
–0.4
0.1
1
10
FREQUENCY (MHz)
100
08054-022
NORMALIZED GAIN (dB)
RG = RF = 649Ω
RG = RF = 604Ω
0.1
CF = 0pF
0.1
Figure 43. Noninverting Configuration
To get the desired 0.1 dB bandwidth, adjust the feedback
resistor, RF, as shown in Figure 43. If RF cannot be adjusted, a
small capacitor can be placed in parallel with RF to reduce
peaking.
Rev. A | Page 13 of 20
100
08054-025
0.2
NORMALIZED CLOSED-LOOP GAIN (dB)
0.2
Figure 43 shows the effect of using various values of Feedback
Resistor RF on the 0.1 dB gain flatness. Note that a larger RF value
causes more peaking because the additional pole formed by RF,
and the input stray capacitance, shifts down in frequency and
interacts significantly with the internal poles of the amplifier.
ADA4891-1/ADA4891-2
8
VS = 5V
VOUT = 200mV p-p
G = +1
RL = 1kΩ
CL = 6.8pF
6
4
2
RS = 0Ω
0
RS = 100Ω
–2
–4
VIN
200mV
STEP
–6
–8
RS
VOUT
RL
CL
50Ω
–10
0.1
1
8
10
100
FREQUENCY (MHz)
Figure 47. Capacitive Load Drive vs. Closed-Loop Gain
6
4
VS = 5V
G = +1
RL = 1kΩ
CL = 6.8pF
RS = 100Ω
2
–4
–6
–8
VS = 5V
VOUT = 200mV p-p
G = +1
RL = 1kΩ
CL = 6.8pF
–10
0.1
1
10
100
FREQUENCY (MHz)
Figure 45. Closed-Loop Frequency Response, CL = 6.8 pF
100
0
C1
–100
50mV/DIV
50ns/DIV
Figure 48. 200 mV Step Response, CL = 50 pF
VS = 5V
G = +1
RL = 1kΩ
CL = 6.8pF
100
0
–100
C1
50mV/DIV
50ns/DIV
Figure 46. 200 mV Step Response, CL = 6.8 pF
Rev. A | Page 14 of 20
08054-035
–2
OUTPUT VOLTAGE (mV)
0
08054-032
•
Figure 48 shows that the transient response is also much improved
by the snub resistor RS = 100 Ω, compared to that of Figure 46.
08054-034
•
MAGNITUDE (dB)
•
Reducing the output resistive load. This pushes the pole
further away and, hence, improves the phase margin.
Increase the phase margin with higher noise gains. As
the closed-loop gain is increased, the larger phase margin
allows for large capacitor loads with less peaking.
Adding a parallel capacitor, CF with RF, from −IN to the
output. This adds a zero in the closed-loop frequency
response, which tends to cancel out the pole formed by
the capacitive load and output impedance of the amplifier.
Refer to the Effect of RF on 0.1 dB Gain Flatness section for
more details.
Putting a small value resistor, RS, in series with the output
to isolate the load capacitor from the output stage of
the amplifier.
OUTPUT VOLTAGE (mV)
•
08054-033
A highly capacitive load reacts with the output impedance of
the amplifiers, causing a loss of phase margin and subsequent
peaking or even oscillation, as is shown in Figure 45 and
Figure 46. Four methods that minimize the output capacitive
loading effect include:
Figure 47 shows the effect of using a snub resistor (RS) on reducing
the peaking in the worst-case frequency response (gain of +1).
Using RS = 100 Ω reduces the peaking by 3 dB, with the tradeoff
that the closed-loop gain is reduced by 0.9 dB due to attenuation at
the output. RS can be adjusted from 0 Ω to 100 Ω to maintain an
acceptable level of peaking and closed-loop gain, as shown in
Figure 48.
MAGNITUDE (dB)
DRIVING CAPACITIVE LOADS
ADA4891-1/ADA4891-2
TERMINATING UNUSED AMPLIFIERS
Terminating unused amplifiers in a multiamplifier package is an
important step to ensuring proper operation of the functional
amplifier. Unterminated amplifiers can oscillate and draw excessive
power if left unattended. The recommended procedure for
terminating unused amplifiers is to connect any unused amplifiers
in a unity-gain configuration and connect the noninverting input
to midsupply voltage. With symmetrical bipolar power supplies,
this means connecting the noninverting input to ground, as shown
in Figure 49. In single power supply applications, a synthetic
midsupply source must be created. This can be accomplished
with a simple resistive voltage divider. Figure 50 shows the
proper connection for terminating an unused amplifier in a
single-supply configuration.
An example of a 15 MHz, 3-pole Sallen-Key, low-pass, video
reconstruction filter is shown in Figure 51. This circuit features
a gain of 2, has a 0.1 dB bandwidth of 7.3 MHz, and over 17 dB
attenuation at 29.7 MHz (see Figure 52). The filter has three poles;
two are active with a third passive pole (R6 and C4) placed at
the output. C3 improves the filter roll-off. R6, R7, and R8 comprise
the video load of 150 Ω. Components R6, C4, R7, R8, and the
input termination of the network analyzer form a 6 dB attenuator;
therefore, the reference level is roughly 0 dB, as shown in Figure 52.
C2
51pF
R2
R3
47Ω 125Ω
VIN
+5V
R1
08054-064
R8
75Ω
C3
15pF
08054-062
R5
1kΩ
Figure 51. 13 MHz Video Reconstruction Filter Schematic
0
Figure 49. Terminating Unused Amplifier with
Symmetrical Bipolar Power Supplies
–3
–6
+VS
MAGNITUDE (dB)
–9
2.5kΩ
ADA4891-2
08054-065
2.5kΩ
C4
1nF
R4
1kΩ
ADA4891-2
R7
68.1Ω
VOUT
+VS
–VS
R6
6.8Ω
C1
51pF
–12
–15
–18
–21
–24
–27
–30
Figure 50. Terminating Unused Amplifier with Single Power Supply
–33
VIDEO RECONSTRUCTION FILTER
For active filters, a good rule of thumb is that the amplifiers
−3 dB bandwidth be at least 10 times higher than the corner
frequency of the filter. This ensures that no initial roll-off is
introduced by the amplifier and that the pass band is flat until
the cutoff frequency.
Rev. A | Page 15 of 20
–39
0.03
0.1
1
10
100
FREQUENCY (MHz)
Figure 52. Video Reconstruction Filter Frequency Performance
08054-059
–36
A common application for active filters is at the output of video
digital-to-analog converters (DACs)/encoders. The filter, or more
appropriately, the video reconstruction filter, is used at the output
of a video DAC/encoder to eliminate the multiple images that
are created during the sampling process within the DAC. For
portable video applications, the ADA4891 is an ideal choice
due to its lower power requirements and high performance.
ADA4891-1/ADA4891-2
LAYOUT, GROUNDING, AND BYPASSING
POWER SUPPLY BYPASSING
INPUT-TO-OUTPUT COUPLING
Power supply pins are additional op amp inputs, and care must be
taken so that a noise-free stable dc voltage is applied. The purpose
of bypass capacitors is to create a low impedance path from the
supply to ground over a range of frequencies, thereby shunting
or filtering the majority of the noise to ground. Bypassing is
also critical for stability, frequency response, distortion, and PSRR
performance.
To minimize capacitive coupling between the inputs and output
and to avoid any positive feedback, the input and output signal
traces should not be parallel. In addition, the input traces should
not be close to each other. A minimum of 7 mils between the
two inputs is recommended.
Chip capacitors of 0.1 μF (X7R or NPO) are critical and should
be as close as possible to the amplifier package. The 0508 case
size for such a capacitor is recommended because it offers low
series inductance and excellent high frequency performance.
Larger chip capacitors, such as 0.1 μF capacitors, can be shared
among a few closely spaced active components in the same
signal path. A 10 μF tantalum capacitor is less critical for high
frequency bypassing, but does provide additional bypassing for
lower frequencies.
GROUNDING
When possible, ground and power planes should be used. Ground
and power planes reduce the resistance and inductance of the
power supply feeds and ground returns. If multiple planes are
used, they should be stitched together with multiple vias. The
returns for the input, output terminations, bypass capacitors,
and RG should all be kept as close to the ADA4891 as possible.
Ground vias should be placed at the very end of the component
mounting pads to provide a solid ground return. The output load
ground and the bypass capacitor grounds should be returned
to a common point on the ground plane to minimize parasitic
inductance that can help improve distortion performance.
INPUT AND OUTPUT CAPACITANCE
Parasitic capacitance can cause peaking and instability and,
therefore, should be minimized to ensure stable operation.
LEAKAGE CURRENTS
In extremely low input bias current amplifier applications, stray
leakage current paths must be kept to a minimum. Any voltage
differential between the amplifier inputs and nearby traces sets
up a leakage path through the PCB. Consider a 1 V signal and
100 GΩ to ground present at the input of the amplifier. The
resultant leakage current is 10 pA; this is 5× the typical input
bias current of the amplifier. Poor PCB layout, contamination,
and the board material can create large leakage currents. Common
contaminants on boards are skin oils, moisture, solder flux, and
cleaning agents. Therefore, it is imperative that the board be
thoroughly cleaned and the board surface be free of contaminants
to take full advantage of the low input bias currents of the ADA4891.
To significantly reduce leakage paths, a guard-ring/shield should be
used around the inputs. The guard-ring circles the input pins
and is driven to the same potential as the input signal, thereby
reducing the potential difference between pins. For the guard
ring to be completely effective, it must be driven by a relatively
low impedance source and should completely surround the
input leads on all sides, above, and below, using a multilayer
board (see Figure 53). The SOT-23-5 package presents a challenge
in keeping the leakage paths to a minimum. The pin spacing is
very tight, so extra care must be used when constructing the guard
ring (see Figure 54 for recommended guard-ring construction).
GUARD RING
In addition, all ground and power planes under the pins of
the ADA4891 should be cleared of copper to prevent parasitic
capacitance between the input and output pins to ground. This is
because a single mounting pad on a SOIC footprint can add as
much as 0.2 pF of capacitance to ground if the ground or power
plane is not cleared under the ADA4891 pins. In fact, the ground
and power planes should be kept at a distance of at least 0.05 mm
from the input pins on all layers of the board.
Rev. A | Page 16 of 20
08054-067
GUARD RING
NONINVERTING
INVERTING
Figure 53. Guard-Ring Configurations
VOUT
+V
VOUT
ADA4891
ADA4891
+V
–V
–V
+IN
–IN
INVERTING
+IN
–IN
NONINVERTING
Figure 54. Guard-Ring Layout SOT-23-5
08054-068
High speed amplifiers are sensitive to parasitic capacitance between
the inputs and ground. A few picofarads of capacitance reduces
the input impedance at high frequencies, in turn increasing the
gain of the amplifier and causing peaking of the frequency
response or even oscillations, if severe enough. It is recommended
that the external passive components, which are connected to
the input pins, be placed as close as possible to the inputs to
avoid parasitic capacitance.
ADA4891-1/ADA4891-2
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
5
1
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
3.00
2.90
2.80
1.70
1.60
1.50
5
1
4
2
3.00
2.80
2.60
3
0.95 BSC
1.90
BSC
1.45 MAX
0.95 MIN
0.15 MAX
0.05 MIN
0.50 MAX
0.35 MIN
0.20 MAX
0.08 MIN
SEATING
PLANE
10°
5°
0°
0.20
BSC
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 56. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
Rev. A | Page 17 of 20
0.55
0.45
0.35
121608-A
1.30
1.15
0.90
ADA4891-1/ADA4891-2
3.20
3.00
2.80
8
3.20
3.00
2.80
1
5.15
4.90
4.65
5
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.40
0.25
6°
0°
0.80
0.55
0.40
0.23
0.09
100709-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 57. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADA4891-1ARZ
ADA4891-1ARZ-RL
ADA4891-1ARZ-R7
ADA4891-1ARJZ-R7
ADA4891-1ARJZ-RL
ADA4891-2ARZ
ADA4891-2ARZ-RL
ADA4891-2ARZ-R7
ADA4891-2ARMZ
ADA4891-2ARMZ-RL
ADA4891-2ARMZ-R7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N, 13” Tape and Reel
8-Lead SOIC_N, 7” Tape and Reel
5-Lead SOT-23, 7” Tape and Reel
5-Lead SOT-23, 13” Tape and Reel
8-Lead SOIC_N
8-Lead SOIC_N, 13” Tape and Reel
8-Lead SOIC_N, 7” Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
Z = RoHS Compliant Part.
Rev. A | Page 18 of 20
Package Option
R-8
R-8
R-8
RJ-5
RJ-5
R-8
R-8
R-8
RM-8
RM-8
RM-8
Branding
H1W
H1W
H1U
H1U
H1U
ADA4891-1/ADA4891-2
NOTES
Rev. A | Page 19 of 20
ADA4891-1/ADA4891-2
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08054-0-6/10(A)
Rev. A | Page 20 of 20