Cypress CY8C21334-24PVXA Automotive psocâ® programmable system-on-chipâ ¢ Datasheet

CY8C21334, CY8C21534
Automotive PSoC®
Programmable System-on-Chip™
Features
■
■
Automotive Electronics Council (AEC) Q100 qualified
Powerful Harvard-architecture processor
❐ M8C processor speeds up to 24 MHz
❐ Low power at high speed
❐ Operating voltage: 3.0 V to 5.25 V
❐ Automotive temperature range: –40 °C to +85 °C
®
■ Advanced peripherals (PSoC blocks)
❐ Four analog Type E PSoC blocks provide:
• Two comparators with digital-to-analog converter (DAC)
references
• Up to 10-bit single or dual, 24 channel analog-to-digital
converters (ADC)
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse width modulators
(PWMs)
• Cyclical redundancy check (CRC) and pseudo-random
sequence (PRS) modules
• Full- or half-duplex UART
• SPI master or slave
• Connectable to all general purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
• Capacitive sensing application capability
■ Flexible on-chip memory
❐ 8 KB flash program storage
❐ 512 bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
■ Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Precision, programmable clocking
❐ Internal ±5% 24 MHz oscillator
❐ Internal low-speed, low-power oscillator for Watchdog and
Sleep functionality
❐ Optional external oscillator, up to 24 MHz
■
Cypress Semiconductor Corporation
Document Number: 001-12550 Rev. *H
•
■
■
Programmable pin configurations
❐ 25 mA sink, 10 mA drive on all GPIOs
❐ Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIOs
❐ Analog input on all GPIOs
❐ Configurable interrupt on all GPIOs
Versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O combinations
Additional system resources
2
❐ Inter-Integrated Circuit (I C™) master, slave, or multi-master
operation up to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection (LVD)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
Logic Block Diagram
198 Champion Court
•
San Jose, CA 95134-1709
• 408-943-2600
Revised January 31, 2011
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Contents
PSoC Functional Overview .............................................. 3
The PSoC Core ........................................................... 3
The Digital System ...................................................... 3
The Analog System ..................................................... 4
Additional System Resources ..................................... 4
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 5
Application Notes ........................................................ 5
Development Kits ........................................................ 5
Training ....................................................................... 5
CYPros Consultants .................................................... 5
Solutions Library .......................................................... 5
Technical Support ....................................................... 5
Development Tools .......................................................... 6
PSoC Designer Software Subsystems ........................ 6
Designing with PSoC Designer ....................................... 7
Select Components ..................................................... 7
Configure Components ............................................... 7
Organize and Connect ................................................ 7
Generate, Verify, and Debug ....................................... 7
Pinouts .............................................................................. 8
20-Pin Part Pinout ...................................................... 8
28-Pin Part Pinout ....................................................... 9
Registers ......................................................................... 10
Register Conventions ................................................ 10
Register Mapping Tables .......................................... 10
Electrical Specifications ................................................ 13
Document Number: 001-12550 Rev. *H
Absolute Maximum Ratings ....................................... 14
Operating Temperature ............................................. 14
DC Electrical Characteristics ..................................... 15
AC Electrical Characteristics ..................................... 18
Packaging Information ................................................... 23
Packaging Dimensions .............................................. 23
Thermal Impedances ................................................ 24
Solder Reflow Peak Temperature ............................. 24
Tape and Reel Information ........................................ 25
Development Tool Selection ......................................... 27
Software .................................................................... 27
Development Kits ...................................................... 27
Evaluation Tools ........................................................ 27
Device Programmers ................................................. 28
Accessories (Emulation and Programming) .............. 28
Ordering Information ...................................................... 29
Ordering Code Definitions ......................................... 29
Reference Information ................................................... 30
Acronyms .................................................................. 30
Reference Documents ............................................... 30
Document Conventions ............................................. 31
Glossary .................................................................... 31
Document History Page ................................................. 36
Sales, Solutions, and Legal Information ...................... 37
Worldwide Sales and Design Support ....................... 37
Products .................................................................... 37
PSoC Solutions ......................................................... 37
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PSoC Functional Overview
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple
traditional microcontroller unit (MCU)-based system
components with one, low-cost single-chip programmable
component. A PSoC device includes configurable blocks of
analog and digital logic, and programmable interconnect. This
architecture makes it possible for you to create customized
peripheral configurations, to match the requirements of each
individual application. Additionally, a fast CPU, flash program
memory, SRAM data memory, and configurable I/O are included
in a range of convenient pinouts.
The PSoC architecture, as illustrated in the “Logic Block
Diagram” on page 1, comprises of four main areas: the core, the
system resources, the digital system, and the analog system.
Configurable global bus resources allow all the device resources
to be combined into a complete custom system. Each
CY8C21x34 PSoC device includes four digital blocks and four
analog blocks. Depending on the PSoC package, up to 24
GPIOs are also included. The GPIOs provide access to the
global digital and analog interconnects.
The PSoC Core
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep, and watchdog timers, and an internal
main oscillator (IMO) and internal low-speed oscillator (ILO). The
CPU core, called the M8C, is a powerful processor with speeds
up to 24 MHz. The M8C is a four-million instructions per second
(MIPS) 8-bit Harvard-architecture microprocessor.
which are called user modules. Digital peripheral configurations
include those listed.
■
PWMs (8- to 32-bit)
■
PWMs with dead band (8- to 24-bit)
■
Counters (8- to 32-bit)
■
Timers (8- to 32-bit)
■
Full or half-duplex 8-bit UART with selectable parity
■
SPI master and slave
■
I2C master, slave, or multi-master (implemented in a dedicated
I2C block)
■
Cyclical redundancy checker/generator (16-bit)
■
Infrared Data Association (IrDA)
■
PRS generators (8- to 32-bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Figure 1. Digital System Block Diagram
Port 3
Port 1
Port 2
Digital Clocks
From Core
System Resources provide additional capability, such as digital
clocks for increased flexibility, I2C functionality for implementing
an I2C master, slave, or multi-master, an internal voltage
reference that provides an absolute value of 1.3 V to a number
of PSoC subsystems, and various system resets supported by
the M8C.
The Analog System is composed of four analog PSoC blocks,
supporting comparators and analog-to-digital conversion with up
to 10 bits of precision.
The Digital System
The digital system is composed of four digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8-, 16-, 24-, and 32-bit peripherals,
Document Number: 001-12550 Rev. *H
To Analog
System
To System Bus
DIGITAL SYSTEM
Row Input
Configuration
Digital PSoC Block Array
Row 0
DBB00
DBB01
DCB02
4
Row Output
Configuration
The Digital System is composed of an array of digital PSoC
blocks, which can be configured into any number of digital
peripherals. The digital blocks can be connected to the GPIO
through a series of global buses that can route any signal to any
pin. This frees designs from the constraints of a fixed peripheral
controller.
Port 0
DCB03
4
8
8
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in Table 1 on page 5.
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The Analog System
The Analog System is composed of four configurable blocks,
allowing the creation of complex analog signal flows. Analog
peripherals are very flexible and can be customized to support
specific application requirements. Some of the common PSoC
analog functions for this device (most available as user modules)
are listed.
■
ADCs (single or dual, with up to 10-bit resolution)
■
Pin-to-pin comparator
■
Single-ended comparators (up to two) with absolute (1.3 V)
reference or 8-bit DAC reference
■
1.3 V reference (as a system resource)
In most PSoC devices, analog blocks are provided in columns of
three, which includes one continuous time (CT) and two switched
capacitor (SC) blocks. The CY8C21x34 devices provide limited
functionality Type E analog blocks. Each column contains one
CT Type E block and one SC Type E block. Refer to the PSoC
Programmable System-on-Chip Technical Reference Manual for
detailed information on the CY8C21x34’s Type E analog blocks.
Figure 2. Analog System Block Diagram
From Port 0
The Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins can
be connected to the bus individually or in any combination. The
bus also connects to the analog system for analysis with
comparators and ADCs. An additional 8:1 analog input
multiplexer provides a second path to bring Port 0 pins to the
analog array.
Switch-control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
Track pad, finger sensing.
■
Chip-wide mux that allows analog input from any I/O pin.
■
Crosspoint connection between any I/O pin combination.
Additional System Resources
System resources, some of which have been previously listed,
provide additional capability useful for complete systems. Brief
statements describing the merits of each system resource are
presented.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
The I2C module provides communication up to 400 kHz over
two wires. Slave, master, and multi-master modes are all
supported.
■
LVD interrupts can signal the application of falling voltage
levels, while the advanced power-on reset (POR) circuit
eliminates the need for a system supervisor.
■
An internal 1.3 V voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
■
Versatile analog multiplexer system.
Array Input
Configuration
ACI0[1:0]
ACI1[1:0]
All IO
ACOL1MUX
Analog Mux Bus
Array
ACE00
ACE01
ASE10
ASE11
Document Number: 001-12550 Rev. *H
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PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have a varying number of digital and analog
blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is highlighted
in Table 1
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
CY8C29x66[1]
up to 64
4
16
up to 12
4
4
12
2K
32 K
CY8C28xxx
up to 44
up to 3
up to 12
up to 44
up to 4
up to 6
up to
12 + 4[2]
1K
16 K
CY8C27x43
up to 44
2
8
up to 12
4
4
12
256
16 K
CY8C24x94[1]
up to 56
1
4
up to 48
2
2
6
1K
16 K
CY8C24x23A[1]
up to 24
1
4
up to 12
2
2
6
256
4K
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
CY8C22x45[1]
up to 38
2
8
up to 38
0
4
6[2]
1K
16 K
[1]
up to 24
1
4
up to 24
0
4
6[2]
512
8K
CY8C21x34[1]
up to 28
1
4
up to 28
0
2
4[2]
512
8K
CY8C21x23
up to 16
1
4
up to 8
0
2
4[2]
256
4K
24
0
0
1[2]
512
8K
CY8C21x45
CY8C21x12[1]
up to 24
1
1[2]
CY8C20x34[1]
up to 28
0
0
up to 28
0
0
3[2,3]
512
8K
CY8C20xx6
up to 36
0
0
up to 36
0
0
3[2,3]
up to 2 K
up to 32 K
Getting Started
For in-depth information, along with detailed programming
details, see the PSoC® Technical Reference Manual.
CYPros Consultants
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
Application Notes
Solutions Library
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
Notes
1. Automotive qualified devices available in this group.
2. Limited analog functionality.
3. Two analog blocks and one CapSense® block.
Document Number: 001-12550 Rev. *H
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Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
■
Integrated source-code editor (C and assembly)
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
■
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up to four full-duplex universal asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are ADCs, DACs, amplifiers, and filters. Configure
the user modules for your chosen application and connect them
to each other and to the proper pins. Then generate your project.
This prepopulates your project with APIs and libraries that you
can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this allows you to use more than 100 percent
of PSoC's resources for an application.
Document Number: 001-12550 Rev. *H
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and are
linked with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also allows you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an online support Forum
to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Organize and Connect
The PSoC development process can be summarized in the
following four steps:
1. Select User Modules
2. Configure User Modules
3. Organize and Connect
4. Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the "Generate
Configuration Files" step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
Select Components
PSoC Designer provides a library of pre-built, pre-tested
hardware peripheral components called "user modules." User
modules make selecting and implementing peripheral devices,
both analog and digital, simple.
Configure Components
Each of the User Modules you select establishes the basic
register settings that implement the selected function. They also
provide parameters and properties that allow you to tailor their
precise configuration to your particular application. For example,
a PWM User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by
selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the User Module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
Document Number: 001-12550 Rev. *H
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Generate, Verify, and Debug
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer's Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
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Pinouts
The CY8C21x34 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are not
capable of digital I/O.
20-Pin Part Pinout
Table 2. 20-Pin Part Pinout (shrink small-outline package (SSOP))
Type
Pin
Name
No. Digital Analog
Description
1
I/O
I, M
P0[7]
Analog column mux input
2
I/O
I, M
P0[5]
Analog column mux input
3
I/O
I, M
P0[3]
Analog column mux input, CMOD capacitor pin
4
I/O
I, M
P0[1]
Analog column mux input, CMOD capacitor pin
VSS
Ground connection
5
Power
6
I/O
M
P1[7]
I2C serial clock (SCL)
7
I/O
M
P1[5]
I2C serial data (SDA)
8
I/O
M
P1[3]
9
I/O
M
P1[1]
I2C SCL, ISSP-SCLK[4]
VSS
Ground connection
I2C SDA, ISSP-SDATA[4]
10
Power
11
I/O
M
P1[0]
12
I/O
M
P1[2]
13
I/O
M
P1[4]
14
I/O
M
P1[6]
15
Input
XRES
Active high external reset with internal
pull-down
I/O
I, M
P0[0]
Analog column mux input
17
I/O
I, M
P0[2]
Analog column mux input
18
I/O
I, M
P0[4]
Analog column mux input
19
I/O
I, M
P0[6]
Analog column mux input
VDD
Supply voltage
Power
AI, M, P0[7] 1
AI, M, P0[5] 2
AI, M, P0[3] 3
AI, M, P0[1] 4
VSS 5
I2C SCL, M, P1[7] 6
I2C SDA, M, P1[5] 7
M, P1[3] 8
I2C SCL, M, P1[1] 9
VSS 10
SSOP
20
19
18
17
16
15
14
13
12
11
VDD
P0[6], M, AI
P0[4], M, AI
P0[2], M, AI
P0[0], M, AI
XRES
P1[6], M
P1[4], M, EXTCLK
P1[2], M
P1[0], M, I2C SDA
Optional external clock input (EXTCLK)
16
20
Figure 3. CY8C21334 20-Pin PSoC Device
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Note
4. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details.
Document Number: 001-12550 Rev. *H
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28-Pin Part Pinout
Table 3. 28-Pin Part Pinout (SSOP)
Type
Pin
No.
Digital
Analog
1
I/O
I, M
P0[7]
Analog column mux input
2
I/O
I, M
P0[5]
Analog column mux input
3
I/O
I, M
P0[3]
Analog column mux input, CMOD capacitor pin
4
I/O
I, M
P0[1]
Analog column mux input, CMOD capacitor pin
5
I/O
M
P2[7]
6
I/O
M
P2[5]
7
I/O
M
P2[3]
8
I/O
M
P2[1]
Name
Description
VSS
Ground connection
10
I/O
M
P1[7]
I2C SCL
11
I/O
M
P1[5]
I2C SDA
12
I/O
M
P1[3]
13
I/O
M
P1[1]
I2C SCL, ISSP-SCLK[5]
VSS
Ground connection
I2C SDA, ISSP-SDATA[5]
9
14
Power
Power
15
I/O
M
P1[0]
16
I/O
M
P1[2]
17
I/O
M
P1[4]
18
I/O
M
P1[6]
19
Input
AI, M, P0[7]
AI, M, P0[5]
AI, M, P0[3]
AI, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
VSS
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
M, P1[3]
I2C SCL, M, P1[1]
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
P0[6], M, AI
P0[4], M, AI
P0[2], M, AI
P0[0], M, AI
P2[6], M
P2[4], M
P2[2], M
P2[0], M
XRES
P1[6], M
P1[4], M, EXTCLK
P1[2], M
P1[0], M, I2C SDA
Optional EXTCLK
XRES Active high external reset with internal
pull-down
20
I/O
M
P2[0]
21
I/O
M
P2[2]
22
I/O
M
P2[4]
23
I/O
M
P2[6]
24
I/O
I, M
P0[0]
Analog column mux input
25
I/O
I, M
P0[2]
Analog column mux input
26
I/O
I, M
P0[4]
Analog column mux input
27
I/O
I, M
P0[6]
Analog column mux input
VDD
Supply voltage
28
Figure 4. CY8C21534 28-Pin PSoC Device
Power
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Note
5. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details.
Document Number: 001-12550 Rev. *H
Page 9 of 37
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CY8C21334, CY8C21534
Registers
Register Conventions
Register Mapping Tables
This section lists the registers of the CY8C21x34 PSoC device.
For detailed register information, refer to the PSoC Technical
Reference Manual.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks, bank 0 and bank 1. The XIO bit in the
Flag register (CPU_F) determines which bank the user is
currently in. When the XIO bit is set to ‘1’, the user is in bank 1.
The register conventions specific to this section are listed in the
following table.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-12550 Rev. *H
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Page 10 of 37
[+] Feedback
CY8C21334, CY8C21534
Table 4. Register Map 0 Table: User Space
Addr
Access
Name
(0,Hex)
PRT0DR
00
RW
PRT0IE
01
RW
PRT0GS
02
RW
PRT0DM2
03
RW
PRT1DR
04
RW
PRT1IE
05
RW
PRT1GS
06
RW
PRT1DM2
07
RW
PRT2DR
08
RW
PRT2IE
09
RW
PRT2GS
0A
RW
PRT2DM2
0B
RW
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
AMUX_CFG
DBB00DR2
22
RW
PWM_CR
DBB00CR0
23
#
DBB01DR0
24
#
CMP_CR0
DBB01DR1
25
W
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
DCB02DR0
28
#
ADC0_CR
DCB02DR1
29
W
ADC1_CR
DCB02DR2
2A
RW
DCB02CR0
2B
#
DCB03DR0
2C
#
TMP_DR0
DCB03DR1
2D
W
TMP_DR1
DCB03DR2
2E
RW
TMP_DR2
DCB03CR0
2F
#
TMP_DR3
30
31
32
ACE00CR1
33
ACE00CR2
34
35
36
ACE01CR1
37
ACE01CR2
38
39
3A
3B
3C
3D
3E
3F
Blank fields are Reserved and must not be accessed.
Name
Document Number: 001-12550 Rev. *H
Addr
(0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
#
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
Addr
(0,Hex)
ASE10CR0
80
81
82
83
ASE11CR0
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Name
Access
Name
RW
RW
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_CR0
DEC_CR1
RW
RW
RW
RW
RW
RW
RW
CPU_F
DAC_D
CPU_SCR1
CPU_SCR0
Addr
(0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RW
RW
RL
RW
#
#
Page 11 of 37
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CY8C21334, CY8C21534
Table 5. Register Map 1 Table: Configuration Space
Addr
Access
Name
(1,Hex)
PRT0DM0
00
RW
PRT0DM1
01
RW
PRT0IC0
02
RW
PRT0IC1
03
RW
PRT1DM0
04
RW
PRT1DM1
05
RW
PRT1IC0
06
RW
PRT1IC1
07
RW
PRT2DM0
08
RW
PRT2DM1
09
RW
PRT2IC0
0A
RW
PRT2IC1
0B
RW
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
DBB00FN
20
RW
CLK_CR0
DBB00IN
21
RW
CLK_CR1
DBB00OU
22
RW
ABF_CR0
23
AMD_CR0
DBB01FN
24
RW
CMP_GO_EN
DBB01IN
25
RW
DBB01OU
26
RW
AMD_CR1
27
ALT_CR0
DCB02FN
28
RW
DCB02IN
29
RW
DCB02OU
2A
RW
2B
CLK_CR3
DCB03FN
2C
RW
TMP_DR0
DCB03IN
2D
RW
TMP_DR1
DCB03OU
2E
RW
TMP_DR2
2F
TMP_DR3
30
31
32
ACE00CR1
33
ACE00CR2
34
35
36
ACE01CR1
37
ACE01CR2
38
39
3A
3B
3C
3D
3E
3F
Blank fields are Reserved and must not be accessed.
Name
Document Number: 001-12550 Rev. *H
Addr
(1,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Addr
(1,Hex)
ASE10CR0
80
81
82
83
ASE11CR0
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Name
Access
Name
RW
RW
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
ADC0_TR
ADC1_TR
IMO_TR
ILO_TR
BDG_TR
ECO_TR
RW
RW
RW
RW
RW
RW
RW
CPU_F
DAC_CR
CPU_SCR1
CPU_SCR0
Addr
(1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
W
W
RW
W
RL
RW
#
#
Page 12 of 37
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CY8C21334, CY8C21534
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C21x34 PSoC device. For the most up-to-date electrical
specifications, visit the Cypress website at http://www.cypress.com.
Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C as specified, except where noted. Refer to Table 12 on page 18 for
the electrical specifications for the IMO using slow IMO (SLIMO) mode.
Figure 5. Voltage versus CPU Frequency
Figure 6. IMO Frequency Trim Options
5.25
5.25
lid ing
Va rat n
e io
Op eg
R
SLIMO
Mode = 0
SLIMO
Mode = 1
SLIMO
Mode = 0
4.75
VDD Voltage (V)
VDD Voltage (V)
4.75
SLIMO
Mode = 1
3.0
3.6
3.0
0
0
93 kHz
12 MHz
CPU Frequency
(nominal setting)
Document Number: 001-12550 Rev. *H
24 MHz
6 MHz
12 MHz
24 MHz
IMO Frequency
Page 13 of 37
[+] Feedback
CY8C21334, CY8C21534
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested
Symbol
TSTG
Description
Storage temperature
TBAKETEMP Bake temperature
tBAKETIME
Bake time
TA
Ambient temperature with power
applied
Supply voltage on VDD relative to VSS
DC input voltage
DC voltage applied to tri-state
Maximum current into any port pin
Electrostatic discharge voltage
Latch up current
VDD
VIO
VIOZ
IMIO
ESD
LU
Min
–55
Typ
25
Max
+100
Units
Notes
°C
Higher storage temperatures reduce
data retention time. Recommended
storage temperature is +25 °C ±
25 °C. Time spent in storage at a
temperature greater than 65 °C
counts toward the FlashDR electrical
specification in Table 11 on page 17.
°C
–
125
See
package
label
–40
–
See
package
label
72
Hours
–
+85
°C
–0.5
VSS – 0.5
VSS – 0.5
–25
2000
–
–
–
–
–
–
–
+6.0
VDD + 0.5
VDD + 0.5
+50
–
200
V
V
V
mA
V
mA
Min
–40
–40
Typ
–
–
Max
+85
+100
Human Body Model ESD
Operating Temperature
Symbol
TA
TJ
Description
Ambient temperature
Junction temperature
Document Number: 001-12550 Rev. *H
Units
Notes
°C
°C
The temperature rise from ambient to
junction is package specific. See
Thermal Impedances on page 24. The
user must limit the power consumption
to comply with this requirement.
Page 14 of 37
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CY8C21334, CY8C21534
DC Electrical Characteristics
DC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C
and are for design guidance only.
Table 6. DC Chip Level Specifications
Symbol
VDD
Description
Supply voltage
Min
3.0
Typ
–
Max
5.25
IDD
Supply current, IMO = 24 MHz
–
4
6
IDD3
Supply current, IMO = 6 MHz using
SLIMO mode
–
2
4
ISB1
Sleep (mode) current with POR, LVD,
sleep timer, WDT, and ILO active
Sleep (mode) current with POR, LVD,
sleep timer, WDT, and ILO active
Reference voltage (Bandgap)
–
2.8
7
–
5
15
μA
VDD = 5.25 V, –40 °C ≤ TA ≤ 85 °C
1.28
1.30
1.32
V
Trimmed for appropriate VDD range
ISB2
VREF
Units
Notes
V
See table titled DC POR and LVD Specifications on page 16
mA Conditions are VDD = 5.25 V, CPU =
3 MHz, 48 MHz disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz
mA Conditions are VDD = 3.3 V, CPU =
3 MHz, 48 MHz disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz
μA
VDD = 3.3 V, –40 °C ≤ TA ≤ 85 °C
DC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C
and are for design guidance only.
Table 7. DC GPIO Specifications
Symbol
RPU
RPD
Description
Pull-up resistor
Pull-down resistor
Min
4
4
Typ
5.6
5.6
Max
8
8
VOH
High output level
VDD – 1.0
–
–
VOL
Low output level
–
–
0.75
IOH
High level source current
10
–
–
IOL
Low level sink current
25
–
–
VIL
Input low level
–
–
0.8
VIH
VH
IIL
CIN
Input high level
Input hysteresis
Input leakage (absolute value)
Capacitive load on pins as input
2.1
–
–
–
–
60
1
3.5
–
–
10
V
mV
nA
pF
COUT
Capacitive load on pins as output
–
3.5
10
pF
Document Number: 001-12550 Rev. *H
Units
Notes
kΩ
kΩ Also applies to the internal pull-down
resistor on the XRES pin
V
IOH = 10 mA, VDD = 4.75 to 5.25 V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5]))
V
IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5]))
mA VOH ≥ VDD – 1.0 V, see the limitations of
the total current in the note for VOH
mA VOL ≤ 0.75 V, see the limitations of the
total current in the note for VOL
V
Gross tested to 1 μA.
Package and pin dependent
Temp = 25 °C
Package and pin dependent
Temp = 25 °C
Page 15 of 37
[+] Feedback
CY8C21334, CY8C21534
DC Operational Amplifier Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C
and are for design guidance only.
Table 8. DC Operational Amplifier Specifications
Symbol
VOSOA
TCVOSOA
IEBOA[6]
CINOA
VCMOA
GOLOA
ISOA
Description
Input offset voltage (absolute value)
Average input offset voltage drift
Input leakage current (Port 0 analog pins)
Input capacitance (Port 0 analog pins)
Min
–
–
–
–
Typ
2.5
10
200
4.5
Common mode voltage range
Open loop gain
Supply current
3.0 V ≤ VDD ≤ 3.6 V
4.75 V ≤ VDD ≤ 5.25 V
0.0
–
–
80
–
–
30
35
Max
15
–
–
9.5
Units
Notes
mV
μV/°C
pA
Gross tested to 1 μA
pF
Package and pin dependent
Temp = 25 °C
VDD – 1
V
–
dB
–
–
μA
μA
DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C
and are for design guidance only.
Table 9. DC Analog Mux Bus Specifications
Symbol
RSW
RVDD
Description
Switch resistance to common analog bus
Resistance of initialization switch to VDD
Min
–
–
Typ
–
–
Max
400
800
Units
Ω
Ω
Notes
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C
and are for design guidance only.
Table 10. DC POR and LVD Specifications
Symbol
Description
VPPOR0
VPPOR1
VPPOR2
VDD value for precision POR (PPOR) trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VDD value for LVD trip
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
Notes
VDD must be greater than or
equal to 2.5 V during startup,
reset from the XRES pin, or reset
from watchdog.
–
–
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.99[7]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
Notes
6. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25 °C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 pA.
7. Always greater than 50 mV above VPPOR1 (PORLEV[1:0] = 01b) for falling supply.
Document Number: 001-12550 Rev. *H
Page 16 of 37
[+] Feedback
CY8C21334, CY8C21534
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C
and are for design guidance only.
Table 11. DC Programming Specifications
Symbol
VDDP
Description
VDD for programming and erase
Min
4.5
Typ
5
Max
5.5
Units
V
VDDLV
Low VDD for verify
3.0
3.1
3.2
V
VDDHV
High VDD for verify
5.1
5.2
5.3
V
3.0
–
5.25
V
5
–
–
–
25
0.8
–
0.2
mA
V
V
mA
–
1.5
mA
–
0.75
V
–
VDD
V
–
–
–
–
–
–
–
–
Years
VDDIWRITE Supply voltage for flash write operation
IDDP
VILP
VIHP
IILP
Supply current during programming or verify
–
Input low voltage during programming or verify
–
Input high voltage during programming or verify
2.2
Input current when applying VILP to P1[0] or
–
P1[1] during programming or verify
IIHP
Input current when applying VIHP to P1[0] or
–
P1[1] during programming or verify
VOLV
Output low voltage during programming or
–
verify
VOHV
Output high voltage during programming or
VDD – 1.0
verify
FlashENPB Flash endurance (per block)[8, 9]
1,000
FlashENT Flash endurance (total)[9, 10]
128,000
FlashDR
Flash data retention
15
Notes
This specification applies to
the functional requirements of
external programmer tools
This specification applies to
the functional requirements of
external programmer tools
This specification applies to
the functional requirements of
external programmer tools
This specification applies to
this device when it is
executing internal flash writes
Driving internal pull-down
resistor
Driving internal pull-down
resistor
Erase/write cycles per block
Erase/write cycles
Notes
8. The erase/write cycle limit per block (FlashENPB) is only guaranteed if the device operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to
5.25 V.
9. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the temperature
argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
10. The maximum total number of allowed erase/write cycles is the minimum FlashENPB value multiplied by the number of flash blocks in the device.
Document Number: 001-12550 Rev. *H
Page 17 of 37
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CY8C21334, CY8C21534
AC Electrical Characteristics
AC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C
and are for design guidance only.
Table 12. AC Chip Level Specifications
Symbol
FIMO24
Description
IMO frequency for 24 MHz
Min
22.8[11]
Typ
24
Max
25.2[11]
Units
MHz
Notes
Trimmed for 5 V or 3.3 V
operation using factory trim
values. See Figure 6 on page 13.
SLIMO mode = 0.
FIMO6
IMO frequency for 6 MHz
5.5[11]
6
6.5[11]
MHz
Trimmed for 5 V or 3.3 V
operation using factory trim
values. See Figure 6 on page 13.
SLIMO mode = 1.
FCPU1
FCPU2
FBLK5
CPU frequency (5 V VDD nominal)
CPU frequency (3.3 V VDD nominal)
Digital PSoC block frequency0(5 V VDD
nominal)
Digital PSoC block frequency (3.3 V VDD
nominal)
0.089[11]
0.089[11]
0
24
12
48
25.2[11]
12.6[11]
50.4[11,12]
MHz
MHz
MHz
24 MHz only for SLIMO mode = 0
0
24
25.2[11, 12]
MHz
FBLK33.
Refer to the AC Digital Block
Specifications below
Refer to the AC Digital Block
Specifications below
F32K1
ILO frequency
15
32
64
kHz
This specification applies when
the ILO has been trimmed
F32KU
ILO untrimmed frequency
5
–
100
kHz
After a reset and before the M8C
processor starts to execute, the
ILO is not trimmed.
External reset pulse width
24 MHz duty cycle
ILO duty cycle
24 MHz trim step size
48 MHz output frequency
Maximum frequency of signal on row
input or row output
SRPOWERUP Power supply slew rate
tPOWERUP
Time between end of POR state and
CPU code execution
[13]
tJIT_IMO
24 MHz IMO cycle-to-cycle jitter (RMS)
24 MHz IMO long term N cycle-to-cycle
jitter (RMS)
24 MHz IMO period jitter (RMS)
10
40
20
–
45.6[11]
–
–
50
50
50
48.0
–
–
60
80
–
50.4[11]
12.6
μs
%
%
kHz
MHz
MHz
–
–
–
16
250
100
V/ms
ms
–
–
200
300
700
900
ps
ps
–
100
400
ps
tXRST
DC24M
DCILO
Step24M
Fout48M
FMAX
VDD slew rate during power-up
Power-up from 0 V.
N = 32
Notes
11. Accuracy derived from IMO with appropriate trim for VDD range.
12. See the individual user module datasheets for information on maximum frequencies for user modules.
13. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-12550 Rev. *H
Page 18 of 37
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CY8C21334, CY8C21534
AC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C
and are for design guidance only.
Table 13. AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO operating frequency
Rise time, normal strong mode, Cload = 50 pF
Fall time, normal strong mode, Cload = 50 pF
Rise time, slow strong mode, Cload = 50 pF
Fall time, slow strong mode, Cload = 50 pF
Min
0
2
2
7
7
Typ
–
6
6
27
22
Max
12.6
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal Strong Mode
VDD = 4.75 to 5.25 V, 10% to 90%
VDD = 4.75 to 5.25 V, 10% to 90%
VDD = 3 to 5.25 V, 10% to 90%
VDD = 3 to 5.25 V, 10% to 90%
Figure 7. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
TFallF
TFallS
AC Operational Amplifier Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C
and are for design guidance only.
Table 14. AC Operational Amplifier Specifications
Symbol
tCOMP
Description
Comparator mode response time, 50
mV overdrive
Document Number: 001-12550 Rev. *H
Min
–
Typ
75
Max
100
Units
ns
Notes
Page 19 of 37
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CY8C21334, CY8C21534
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C
and are for design guidance only.
Table 15. AC Digital Block Specifications
Function
All functions
Timer
Counter
Dead Band
CRCPRS
(PRS Mode)
Description
Block input clock frequency
VDD ≥ 4.75 V
VDD < 4.75 V
Input clock frequency
No capture, VDD ≥ 4.75 V
No capture, VDD < 4.75 V
With capture
Capture pulse width
Input clock frequency
No enable input, VDD ≥ 4.75 V
No enable input, VDD < 4.75 V
With enable input
Enable input pulse width
Kill pulse width
Asynchronous restart mode
Synchronous restart mode
Disable mode
Input clock frequency
VDD ≥ 4.75 V
VDD < 4.75 V
Input clock frequency
VDD ≥ 4.75 V
VDD < 4.75 V
Input clock frequency
CRCPRS
(CRC Mode)
SPIM
Input clock frequency
SPIS
Transmitter
Receiver
Input clock (SCLK) frequency
Width of SS_Negated between transmissions
Input clock frequency
VDD ≥ 4.75 V, 2 stop bits
VDD ≥ 4.75 V, 1 stop bit
VDD < 4.75 V
Input clock frequency
VDD ≥ 4.75 V, 2 stop bits
VDD ≥ 4.75 V, 1 stop bit
VDD < 4.75 V
Min
Typ
Max
Units
Notes
–
–
–
–
50.4[15]
25.2[15]
MHz
MHz
–
–
–
50[14]
–
–
–
–
50.4[15]
25.2[15]
25.2[15]
–
MHz
MHz
MHz
ns
–
–
–
50[14]
–
–
–
–
50.4[15]
25.2[15]
25.2[15]
–
MHz
MHz
MHz
ns
20
50[14]
50[14]
–
–
–
–
–
–
ns
ns
ns
–
–
–
–
50.4[15]
25.2[15]
MHz
MHz
–
–
–
–
–
–
50.4[15]
25.2[15]
25.2[15]
MHz
MHz
MHz
–
–
8.4[15]
–
–
4.2[15]
50[14]
–
–
–
–
–
–
–
–
50.4[15]
25.2[15]
25.2[15]
MHz The SPI serial clock (SCLK)
frequency is equal to the input
clock frequency divided by 2.
MHz The input clock is the SPI SCLK
in SPIS mode.
ns
The baud rate is equal to the input
MHz clock frequency divided by 8.
–
–
–
–
–
–
50.4[15]
25.2[15]
25.2[15]
MHz
MHz
The baud rate is equal to the input
MHz clock frequency divided by 8.
MHz
MHz
Notes
14. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
15. Accuracy derived from IMO with appropriate trim for VDD range.
Document Number: 001-12550 Rev. *H
Page 20 of 37
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CY8C21334, CY8C21534
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C
and are for design guidance only.
Table 16. 5-V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High period
20.6
–
5300
ns
–
Low period
20.6
–
–
ns
–
Power-up IMO to switch
150
–
–
μs
Notes
Table 17. 3.3-V AC External Clock Specifications
Min
Typ
Max
Units
Notes
FOSCEXT
Symbol
Frequency with CPU clock divide by 1
Description
0.093
–
12.3
MHz
Maximum CPU frequency is 12 MHz
at 3.3 V. With the CPU clock divider
set to 1, the external clock must
adhere to the maximum frequency
and duty cycle requirements.
FOSCEXT
Frequency with CPU clock divide by 2 or
greater
0.186
–
24.6
MHz
If the frequency of the external clock
is greater than 12 MHz, the CPU clock
divider must be set to 2 or greater. In
this case, the CPU clock divider
ensures that the fifty percent duty
cycle requirement is met.
–
High period with CPU clock divide by 1
41.7
–
5300
ns
–
Low period with CPU clock divide by 1
41.7
–
–
ns
–
Power-up IMO to switch
150
–
–
μs
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C
and are for design guidance only.
Table 18. AC Programming Specifications
Symbol
tRSCLK
tFSCLK
tSSCLK
tHSCLK
tSCLK
tERASEB
tWRITE
tDSCLK
tDSCLK3
tPRGH
tPRGC
Description
Rise time of SCLK
Fall time of SCLK
Data setup time to falling edge of SCLK
Data hold time from falling edge of SCLK
Frequency of SCLK
Flash block erase time
Flash block write time
Data out delay from falling edge of SCLK
Data out delay from falling edge of SCLK
Total flash block program time
(tERASEB + tWRITE), hot
Total flash block program time
(tERASEB + tWRITE), cold
Min
1
1
40
40
0
–
–
–
–
–
Typ
–
–
–
–
–
10
40
38
44
–
Max
20
20
–
–
8
40[16]
160[16]
45
50
100[16]
Units
ns
ns
ns
ns
MHz
ms
ms
ns
ns
ms
–
–
200[16]
ms
Notes
3.6 < VDD
3.0 ≤ VDD ≤ 3.6
TJ ≥ 0 °C
TJ < 0 °C
Note
16. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
Document Number: 001-12550 Rev. *H
Page 21 of 37
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AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C
and are for design guidance only.
Table 19. AC Characteristics of the I2C SDA and SCL Pins
Symbol
Standard Mode
Description
Fast Mode
Units
Min
Max
Min
Max
0
100[17]
0
400[17]
kHz
FSCLI2C
SCL clock frequency
tHDSTAI2C
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
4.0
–
0.6
–
μs
tLOWI2C
LOW period of the SCL clock
4.7
–
1.3
–
μs
tHIGHI2C
HIGH period of the SCL clock
4.0
–
0.6
–
μs
tSUSTAI2C
Setup time for a repeated START condition
4.7
–
0.6
–
μs
tHDDATI2C
Data hold time
0
–
0
–
μs
250
–
100[18]
–
ns
tSUDATI2C
Data setup time
tSUSTOI2C
Setup time for STOP condition
4.0
–
0.6
–
μs
tBUFI2C
Bus free time between a STOP and START
condition
4.7
–
1.3
–
μs
tSPI2C
Pulse width of spikes are suppressed by the
input filter.
–
–
0
50
ns
Notes
Figure 8. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
TSUDATI2C
THDSTAI2C
TSPI2C
THDDATI2CTSUSTAI2C
TBUFI2C
I2C_SCL
THIGHI2C TLOWI2C
S
START Condition
TSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
Notes
17. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the
FSCLI2C specification adjusts accordingly
18. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSUDATI2C ≥ 250 ns must then be met. This is automatically the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax +tSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-12550 Rev. *H
Page 22 of 37
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Packaging Information
This section illustrates the packaging specifications for the CY8C21x34 PSoC device, along with the thermal impedances for each
package.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Packaging Dimensions
Figure 9. 20-Pin (210-Mil) SSOP
51-85077 *D
Document Number: 001-12550 Rev. *H
Page 23 of 37
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CY8C21334, CY8C21534
Figure 10. 28-Pin (210-Mil) SSOP
51-85079 *D
Thermal Impedances
Solder Reflow Peak Temperature
Table 20. Thermal Impedances per Package
Table 21 shows the solder reflow temperature limits that need to
be met for preventing device damage.
Package
20-Pin SSOP
28-Pin SSOP
Typical θJA [19]
117 °C/W
96 °C/W
Typical θJC
41 °C/W
39 °C/W
Table 21. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at
Peak Temperature
20-Pin SSOP
260 °C
20 s
28-Pin SSOP
260 °C
20 s
Note
19. TJ = TA + Power x θJA
Document Number: 001-12550 Rev. *H
Page 24 of 37
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Tape and Reel Information
Figure 11. 20-Pin SSOP Carrier Tape Drawing
51-51101 *A
Document Number: 001-12550 Rev. *H
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Figure 12. 28-Pin SSOP Carrier Tape Drawing
51-51100 *B
Table 22. Tape and Reel Specifications
Package
Cover Tape
Width (mm)
Hub Size
(inches)
Minimum Leading
Empty Pockets
20-Pin SSOP
28-Pin SSOP
13.3
13.3
4
7
42
42
Document Number: 001-12550 Rev. *H
Minimum
Trailing Empty
Pockets
25
25
Standard Full Reel
Quantity
2000
1000
Page 26 of 37
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Development Tool Selection
This section presents the development tools available for the CY8C21x34 family.
Software
PSoC Designer
At the core of the PSoC development software suite is
PSoC Designer. Utilized by thousands of PSoC developers, this
robust software has been facilitating PSoC designs for years.
PSoC Designer is available free of charge at
http://www.cypress.com. PSoC Designer comes with a free C
compiler.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube in-circuit emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com.
pre-defined control circuitry and plug-in hardware. The kit comes
with a control boards for CY8C20x34 and CY8C21x34 devices
as well as a breadboard module and a button(5)/slider module.
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, an RS-232 port, and
plenty of breadboarding space to meet all of your evaluation
needs. The kit includes:
■
Evaluation board with LCD module
■
MiniProg programming unit
■
Two 28-Pin CY8C29466-24PXI PDIP PSoC device samples
■
PSoC Designer software CD
■
Getting Started guide
CY3215-DK Basic Development Kit
■
USB 2.0 cable
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation, and the software
interface allows you to run, halt, and single step the processor,
and view the contents of specific memory locations. Advanced
emulation features are also supported through PSoC Designer.
The kit includes:
CY3235-ProxDet
Development Kits
All development kits can be purchased from the Cypress Online
Store. The online store also has the most up-to-date information
on kit contents, descriptions, and availability.
The CY3235 CapSense Proximity Detection Demonstration Kit
allows quick and easy demonstration of a PSoC
CapSense-enabled device (CY8C21x34) to accurately sense
the proximity of a hand or finger along the length of a wire
antenna. The kit includes:
■
ICE-Cube unit
■
28-Pin PDIP emulation pod for CY8C29466-24PXI
■
Two 28-Pin CY8C29466-24PXI PDIP PSoC device samples
■
PSoC designer software CD
■
ISSP cable
■
MiniEval socket programming and evaluation board
■
Backward compatibility cable (for connecting to legacy pods)
■
Universal 110/220 power supply (12 V)
■
European plug adapter
CY3210-21X34 Evaluation Pod (EvalPod)
■
USB 2.0 cable
■
Getting Started guide
■
Development kit registration form
The CY3210-21X34 PSoC EvalPods are pods that connect to
the ICE in-circuit emulator (CY3215-DK kit) to allow debugging
capability. They can also function as a standalone device without
debugging capability. The EvalPod has a 28-pin DIP footprint on
the bottom for easy connection to development kits or other
hardware. The top of the EvalPod has prototyping headers for
easy connection to the device's pins. CY3210-21X34 provides
evaluation of the CY8C21x34 PSoC device family.
CY3280-BK1
The CY3280-BK1 Universal CapSense Control Kit is designed
for easy prototyping and debug of CapSense designs with
Document Number: 001-12550 Rev. *H
■
Proximity detection demo board w/antenna
■
I2C to USB debugging/communication bridge
■
USB cable (6 feet)
■
Supporting software CD
■
CY3235-ProxDet Quick Start guide
■
One CY8C24894 PSoC device on I2C-USB bridge
■
One CY8C21434 PSoC device on proximity detection demo
board
Page 27 of 37
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Device Programmers
CY3207ISSP In-System Serial Programmer (ISSP)
All device programmers can be purchased from the Cypress
Online Store.
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production-programming environment.
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg programming unit
■
MiniEval socket programming and evaluation board
■
28-Pin CY8C29466-24PXI PDIP PSoC device sample
■
PSoC Designer software CD
■
Getting Started guide
■
USB 2.0 cable
Note CY3207ISSP needs special software and is not
compatible with PSoC Programmer. This software is free and
can be downloaded from http://www.cypress.com. The kit
includes:
■
CY3207 programmer unit
■
PSoC ISSP software CD
■
110 ~ 240 V power supply, European plug adapter
■
USB 2.0 cable
Accessories (Emulation and Programming)
Table 23. Emulation and Programming Accessories
Part Number
Pin Package
Pod Kit[20]
Foot Kit[21]
CY8C21334-24PVXA
20-Pin SSOP
CY3250-21X34
CY3250-20SSOP-FK
CY8C21534-24PVXA
28-Pin SSOP
CY3250-21X34
CY3250-28SSOP-FK
Adapter[22]
Adapters are available at
http://www.emulation.com.
Notes
20. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.
21. Foot kit includes surface mount feet that can be soldered to the target PCB.
22. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters are available at
http://www.emulation.com.
Document Number: 001-12550 Rev. *H
Page 28 of 37
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Ordering Information
The following table lists the CY8C21x34 PSoC device’s key package features and ordering codes.
SRAM
(Bytes)
Temperature
Range
Digital
Blocks
Analog
Blocks
Digital I/O
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
8K
512
–40 °C to +85 °C
4
4
16
16
0
Yes
20-Pin (210-Mil) SSOP CY8C21334-24PVXAT
(Tape and Reel)
8K
512
–40 °C to +85 °C
4
4
16
16
0
Yes
28-Pin (210-Mil) SSOP CY8C21534-24PVXA
8K
512
–40 °C to +85 °C
4
4
24
24
0
Yes
28-Pin (210-Mil) SSOP CY8C21534-24PVXAT
(Tape and Reel)
8K
512
–40 °C to +85 °C
4
4
24
24
0
Yes
Ordering
Code
20-Pin (210-Mil) SSOP CY8C21334-24PVXA
Package
Flash
(Bytes)
Table 24. PSoC Device Key Features and Ordering Information
Ordering Code Definitions
CY 8 C 21 xxx-24xx
Package Type:
PX = PDIP Pb-free
SX = SOIC Pb-free
PVX = SSOP Pb-free
LFX = QFN Pb-free
AX = TQFP Pb-free
Thermal Rating:
A = Automotive –40 °C to +85 °C
C = Commercial
I = Industrial
E = Automotive Extended –40 °C to +125 °C
CPU Speed: 24 MHz
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Document Number: 001-12550 Rev. *H
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Reference Information
Acronyms
Table 25 lists the acronyms that are used in this document.
Table 25. Acronyms Used in this Datasheet
Acronym
AC
Description
Acronym
alternating current
Description
MIPS
million instructions per second
AEC
Automotive Electronics Council
PCB
printed circuit board
ADC
analog-to-digital converter
PDIP
plastic dual in-line package
API
application programming interface
PLL
phase-locked loop
CPU
central processing unit
POR
power-on reset
CRC
cyclic redundancy check
CSD
capsense sigma delta
CT
DAC
DC
PRS
PSoC®
continuous time
digital-to-analog converter
PWM
direct current or duty cycle
EEPROM
electrically erasable programmable read-only
memory
EXTCLK
external clock
GPIO
PPOR
SC
precision power-on reset
pseudo-random sequence
Programmable System-on-Chip
pulse width modulator
switched capacitor
SCL / SCLK
serial clock
SDA
serial data
general-purpose I/O
SLIMO
slow internal main oscillator
I2C
Inter-Integrated Circuit
SMP
switch mode pump
ICE
in-circuit emulator
SOIC
small-outline integrated circuit
IDE
integrated development environment
SPI
serial peripheral interface
ILO
internal low-speed oscillator
SRAM
static random access memory
IMO
internal main oscillator
SROM
supervisory read-only memory
I/O
input/output
SSOP
shrink small-outline package
IrDA
Infrared Data Association
TQFP
thin quad flat pack
ISSP
in-system serial programming
UART
universal asynchronous reciever /
transmitter
LCD
liquid crystal display
USB
universal serial bus
LED
light-emitting diode
WDT
watchdog timer
LVD
low voltage detect
XRES
external reset
MCU
microcontroller unit
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,
CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Understanding Data Sheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503)
Document Number: 001-12550 Rev. *H
Page 30 of 37
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CY8C21334, CY8C21534
Document Conventions
Units of Measure
The following table lists the units of measure that are used in this document.
Table 26. Units of Measure
Symbol
°C
dB
KB
Kbit
kHz
kΩ
Mbaud
Mbps
MHz
μA
μs
Unit of Measure
degree Celsius
decibels
1024 bytes
1024 bits
kilohertz
kilohm
megabaud
megabits per second
megahertz
microampere
microsecond
Symbol
μV
mA
ms
mV
nA
ns
Ω
pA
pF
ps
V
Unit of Measure
microvolts
milliampere
millisecond
millivolts
nanoampere
nanosecond
ohm
picoampere
picofarad
picosecond
volts
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are in decimal format.
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital
converter (ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
a voltage to a digital number. The digital-to-analog converter (DAC) performs the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create
software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
Document Number: 001-12550 Rev. *H
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Glossary (continued)
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to
‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric
crystal is less sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift
check (CRC)
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog
converter (DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital
converter (ADC) performs the reverse operation.
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
Document Number: 001-12550 Rev. *H
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Glossary (continued)
external reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
flash
An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
off.
flash block
The smallest amount of flash ROM space that may be programmed at one time and the smallest amount of flash
space that may be protected.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). It is used to connect
low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery
control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses
only two bi-directional pins, clock and data, both running at the VDD suppy voltage and pulled high with resistors.
The bus operates up to100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the CPU receives a hardware interrupt. Many
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls below a selected threshold.
(LVD)
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
Document Number: 001-12550 Rev. *H
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Glossary (continued)
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitted data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port
A group of pins, usually eight.
power-on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware
reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied value.
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a known state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
slave device
A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
Document Number: 001-12550 Rev. *H
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Glossary (continued)
SRAM
An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform flash operations. The functions of the SROM may be accessed in normal user code,
operating from flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules
Pre-built, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level analog and digital PSoC blocks. User modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Document Number: 001-12550 Rev. *H
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Document History Page
Document Title: CY8C21334, CY8C21534 Automotive PSoC® Programmable System-on-Chip™
Document Number:001-12550
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
646436
HMT
See ECN
New silicon and document (Revision **)
*A
2526170
PYRS
07/03/08
Corrected ordering information, Converted from Preliminary to Final.
*B
2618175 OGNE/PYRS
12/09/08
Added Note in Ordering Information section.
Changed Title from PSoC® Mixed-Signal Array to PSoC® Programmable
System-on-Chip™
Updated ‘Development Tools’ and ‘Designing with PSoC Designer’ sections on
pages 5 and 6
*C
2714723
BTK/AESA
06/04/09
Updated Getting Started section. Replaced Designing with User Modules section
with Designing with PSoC Designer section. Updated Features list and PSoC
Functional Overview section. Updated some AC Specification values to conform to
a ±5% accurate IMO (no order of magnitude changes). Added a note to I2C specifications section to clarify the I2C SysClk dependency. Added the Development Tool
Selection section. Deleted some inapplicable or redundant information. Changed
the title. Updated the PDF Bookmarks. Fixed FIMO6, TRSCLK, and TFSCLK specifications to be correct.
*D
2822792
BTK/AESA
12/07/2009 Added TPRGH, TPRGC, IOL, IOH, F32KU, DCILO, and TPOWERUP electrical specifications. Updated the footnotes for Table 11, “DC Programming Specifications,” on
page 17. Added maximum values and updated typical values for TERASEB and
TWRITE electrical specifications. Replaced TRAMP electrical specification with
SRPOWERUP electrical specification. Added “Sales, Solutions, and Legal Information” on page 37. This revision fixes CDT 63984.
*E
2888007
NJF
03/30/2010 Updated Cypress website links.
Updated Designing with PSoC Designer.
Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings.
Removed the following sections:
DC Low Power Comparator Specifications, AC Analog Mux Bus Specifications, AC
Low Power Comparator Specifications, Third Party Tools, and Build a PSoC
Emulator into your Board.
Updated links in Sales, Solutions, and Legal Information.
*F
3023789
BTK/AESA
09/06/2010 Conversion to new datasheet editing system. Merged the 5 V and 3.3 V operational
amplifier electrical specifications into the Table 8 (with no changes to data). Updated
datasheet as per Cypress Style guide and new datasheet template.
*G
3094401
3023788
BTK
*H
3157921
BTK/NJF
11/23/2010 Added tape and reel packaging information. Refer to CDT 88767.
01/31/2011 Updated I2C timing diagram to improve clarity (CDT 92817).
Updated wording, formatting, and notes of the AC Digital Block Specifications table
to improve clarify (CDT 92819).
Added VDDP, VDDLV, and VDDHV electrical specifications to give more information
for programming the device (CDT 92822).
Updated solder reflow temperature specifications to give more clarity (CDT 92828).
Updated the jitter specifications (CDT 92831).
Updated PSoC Device Characteristics table (CDT 92832).
Updated the F32KU electrical specification (CDT 92994).
Updated DC POR and LVD Specifications to add specs for all POR levels (CDT
86716).
Updated note for RPD electrical specification (CDT 90944).
Updated Reference Information Section.
Package diagram spec 51-51100 revised from *A to *B.
Document Number: 001-12550 Rev. *H
Page 36 of 37
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-12550 Rev. *H
Revised January 31, 2011
Page 37 of 37
PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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