Anpec APL5551 Dual channel 500ma/500ma regulator reset ic Datasheet

APL5551
Dual Channel 500mA/500mA Regulator + Reset IC
Features
General Description
•
Low Quiescent Current : 110µA (No load)
The APL5551 is a dual-channel regulator with reset
•
Low Dropout Voltage :
function (specific voltage monitoring), and internal
VDROP1 = 450mV @ 500mA
delay circuit, set to detect 3.9V. Maximum input volt-
VDROP2 = 500mV @ 500mA
age is 6V, and both output1 and output2 can deliver up
•
to 450mA. The typical dropout voltage of both channel
Fixed Output Voltage :
is 500mV at 500mA loading. Design with an internal
VOUT1 = 3.3V/500mA
P-channel MOSFET pass transistor, the APL5551 main-
VOUT2 = 2.8V/500mA
tains a low supply current. Other features include, ther-
•
Stable with 4.7µF Output Capacitor
mal-shutdown protection, current limit protection to
•
Stable with Aluminum, Tantalum or Ceramic
ensure specified output current. The APL5551 comes
Capacitors
in miniature SOP-8 and SOP-8-P packages.
•
Built in Thermal Protection
•
Fast Transient Response
•
Short Setting Time
•
SOP-8, SOP-8-P with Thermal Pad Packages
•
Adjustment-free Reset Detection Voltage :
Pin Configuration
SOP-8 (Top View)
SOP-8-P( Top View)
3.9V typ
•
Easy to Set Delay Time from Voltage
Detection to Reset Release
•
Lead Free Available (RoHS Compliant)
1
8
CONT
2
7
GND
Cd
3
6
RESET
V DET
4
5
V OUT2
V IN
1
8
CONT
V OUT1
2
7
GND
Cd
3
6
RESET
V DET
4
5
V OUT2
= Thermal Pad
(connected to GND plane for better heat
dissipation)
Applications
•
V IN
V OUT1
Optical Storage System
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Oct., 2005
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APL5551
Ordering and Marking Information
Package Code
K : SOP-8
Temp. Range
I : -40 to 85 ° C
Handling Code
TR : Tape & Reel
Lead Free Code
L : Lead Free Device
APL5551
Lead Free Code
Handling Code
Temp. Range
Package Code
Detection Voltage
APL5551 K / KA:
APL5551
XXXXX
KA : SOP-8-P
Blank : Original Device
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate
termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldiering
operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C
for MSL classification at lead-free peak reflow temperature.
Pin Description
PIN
I/O
Description
No.
Name
1
VIN
I
Voltage supply input pin.
2
VOUT1
O
Regulator output pin.
3
Cd
O
Delay time capacitor pin, RESET pin output delay time can be set by
the capacitor connected to the Cd pin. tPLH = 130000∗C, tPLH :
transmission delay time (s), C:capacitor value (F)
4
VDET
I
Input pin of voltage detection.
5
VOUT2
O
Regulator output pin.
6
RESET
O
Input voltage detection output pin , high = VDET<VS , low = VDET>VS
7
GND
8
CONT
GND pin
I
VOUT1 on/off-control pin, VOUT1 will be turn off when CONT pull to low.
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
VIN, VOUT
Input Voltage or Out Voltage
6.5
V
CONT
VOUT1 Shutdown Control Pin
6.5
V
VDET
RESET Pin Supply Voltage
6.5
V
RTH,JA
Thermal Resistance – Junction to Ambient
SOP-8
SOP-8-P
150
80
°C/W
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APL5551
Absolute Maximum Ratings (Cont.)
Symbol
RTH,JC
PD
TJ
TSTG
Parameter
Rating
Unit
30
5
°C/W
0.7
1.4
W
Control Section
0 to 125
°C
Power Transistor
0 to 170
Thermal Resistance – Junction to Case
SOP-8
SOP-8-P
Power Dissipation at TA = 55°C (Note)
SOP-8
SOP-8-P
Operating Junction Temperature
Storage Temperature Range
TL
Lead Temperature (Soldering, 10 second)
-65 to +150
°C
260
°C
Note: When mounted on a (Copper foil area 60%, 60x45x1.6tmm) glass exoxy board.
Electrical Characteristics
Unless otherwise noted these specifications apply over full temperature , VIN = 5V, CIN = 1µF, COUT1 = 4.7µF,
COUT2 = 4.7µF, CONT = VIN, TA = -40 to 85°C . Typical values refer to TA = 25°C .
Symbol
VIN
IQ
ICONT
VCONT
ICCQ
Parameter
Test Conditions
APL5551
Min.
Typ.
Input Voltage
Max.
Unit
6
V
Quiescent Current
IOUT1 = 0mA, IOUT2 = 0mA
100
200
µA
Shutdown Supply
Current
CONT = low,
IOUT2 = 0mA
70
140
µA
Shutdown Input Bias
current
VCONT = VIN
0.1
µA
High Threshold Voltage
1.6
VIN+0.3
Low Threshold Voltage
-0.3
0.4
VDET Input Current
VDET = 5V
V
20
40
µA
3.3
3.366
V
Regulator1
VOUT1
Output Voltage
VIN = 5V
ILIMIT
Circuit Current Limit
VIN = 5V
IOUT
Load Current
3.234
800
mA
500
mA
REGLINE Line Regulation
VOUT+0.5V< VIN<6.0V, IOUT = 10mA
4
6
mV
REGLOAD Load Regulation
VIN = 5V, 0mA < IOUT < IMAX
25
60
mV
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APL5551
Electrical Characteristics (Cont.)
Unless otherwise noted these specifications apply over full temperature , VIN = 5V, CIN = 1µF, COUT1 = 4.7µF,
COUT2 = 4.7µF, CONT = VIN, TA = -40 to 85°C . Typical values refer to TA = 25°C .
Symbol
Parameter
Test Conditions
APL5551
Min.
Unit
Typ.
Max.
450
600
(Note)
VDROP
Dropout Voltage
(VOUT (Nominal) =
3.3V Version)
IOUT = 500mA
PSRR
Ripple Rejection
F
OTS
TC
COUT
Over Temperature
Shutdown
Over Temperature
Shutdown Hysteresis
≤ 1kHz, 1Vpp at I OUT = 50mA
45
55
dB
155
170
°C
15
°C
Hysteresis
Output Voltage
T = -20 ~ 80°C
Temperature Coefficient a
100
Output Capacitor
4.7
ESR
mV
0.01
200
ppm/°C
µF
1
Ω
2.856
V
Regulator2
VOUT2
Output Voltage
V IN = 5V
ILIMIT
Circuit Current Limit
V IN = 5V
IOUT
Load Current
2.744
2.8
800
mA
500
REG LINE Line Regulation
mA
V OUT +0.5V< VIN<6.0V, I OUT = 10mA
4
6
mV
V IN =5V, 0mA< IOUT < IMAX
25
60
mV
Dropout Voltage
(VOUT (Nominal) =
2.8V Version)
IOUT = 500mA
500
650
mV
Ripple Rejection
F ≤1kHz, 1Vpp at I OUT = 50mA
REG LOAD Load Regulation
(Note)
VDROP
PSRR
OTS
TC
COUT
Over Temperature
Shutdown
Over Temperature
Shutdown Hysteresis
45
Hysteresis
55
dB
170
°C
15
°C
Output Voltage
T = -20 ~ 80°C
Temperature Coefficient a
100
Output Capacitor
4.7
ESR
0.01
200
ppm/°C
µF
1
Ω
3.978
V
RESET / RESET
VS
△VS/△T
△VS
Detection Voltage
V DET = HàL
Vs Temperature
Coefficient
T a = -20~+80°C
Hysteresis Voltage
V DET = HàL
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Oct., 2005
3.822
3.9
100
130
4
180
ppm/°C
230
mV
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APL5551
Electrical Characteristics (Cont.)
Unless otherwise noted these specifications apply over full temperature , VIN = 5V, CIN = 1µF, COUT1 = 4.7µF,
COUT2 = 4.7µF, CONT = VIN, TA = -40 to 85°C . Typical values refer to TA = 25°C .
Symbol
Parameter
Test Conditions
APL5551
Min.
Typ.
Max.
Unit
RESET / RESET
V OL
Low-level Output Voltage
VDET = 3.9V, RL = 4.7kΩ
22
60
mV
IOH
Output Leakage Current
VDET = 5V
0.5
1
µA
IOL1
Output Current1
VDET = 3.9V, V RESET = 0.4V
10
14
mA
IOL2
Output Current2
VDET = 3.9V, VRESET = 0.4V
T A = -20 ~ +80°C
8
14
mA
tPLH
“H” Transmission Delay Time Cd = 0µ F
tPLH1
Reset Delay Time
tPHL
“L” Transmission Delay Time Cd = 0µ F
VOPL
Threshold Operating Voltage VRESET = 0.4V
VDET = 3.7Và5V, Cd = 0.1µ F
8
42
90
µs
13
18
ms
4
90
µs
0.95
1.25
V
Application Circuit
VOUT1
VIN
1µF
RL
4.7kΩ
VDET
RESET
Cd
APL5551
GND
COUT2
4.7µF
0.1µF
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Rev. A.2 - Oct., 2005
COUT1
4.7µF
VOUT2
CONT
5
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APL5551
Timing Chart
VIN. VDET
5V
Vs
Vs
RESET
5V
tPLH + tPLH1
0V
CONT
H
L
VOUT1
5V
0V
VOUT2
5V
0V
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APL5551
Typical Characteristics
Quiescent Current vs. Output Current
Quiescent Current vs. Input Voltage
450
160
IOUT1=IOUT2=0mA
400
Quiescent Current (µA)
Quiescent Current (µA)
140
120
100
80
60
40
VIN = 4V
350
300
250
200
150
100
50
20
0
0
0
1
2
3
4
5
0
6
100
Input Voltage (V)
300
400
500
Output Current (mA)
Output Voltage vs. Input Voltage
Output Voltage vs. Input Voltage
3
3.5
IOUT2 =0mA
IOUT1 =0mA
3
2.5
2.5
Output Voltage(V)
Output Voltage (V)
200
V OUT1
2
1.5
1
V OUT2
2
1.5
1
0.5
0.5
0
0
0
1
2
3
4
0
5
Input Voltage (V)
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4
6
Input Voltage(V)
7
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APL5551
Typical Characteristics
Output Voltage vs .Temperature
Output Voltage vs .Temperature
2.81
3.305
2.805
3.3
2.8
2.795
VOUT2(V)
VOUT1(V)
3.295
3.29
3.285
2.79
2.785
2.78
2.775
3.28
2.77
3.275
2.765
-30
-10
10
30
50
70
90
-40
110 130 150
-20
0
40
60
80
100 120 140 160
Ambient Temperature(°C)
Ambient Temperature(°C)
Dropout Voltage vs. Output Current
PSRR vs. Frequency
600
+0
-10
500
VIN = 5V
IOUT1 = IOUT2 = 50mA
-20
400
VOUT2
PSRR (dB)
Dropout Voltage (mV)
20
300
VOUT1
200
-30
-40
-50
VOUT1 ,V OUT2
-60
100
-70
0
0
100
200
300
400
-80
10
500
Rev. A.2 - Oct., 2005
1k
10k
100k
Frequency (Hz)
Output Current (mA)
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APL5551
Typical Characteristics
Load-Transient Response
Load-Transient Response
VOUT1 (200mV/div)
VOUT2 (200mV/div)
IL1=1mA ~ 500mA
COUT1=4.7µF(Aluminum)
Tr=1µs
IL2=1mA ~ 500mA
COUT2=4.7µF(Aluminum)
Tr=1µs
Time (0.1m/div)
Time(0.1m/div)
Line-Transient Response
Shutdown Response
RLOAD = 100 Ω
VIN = 4.5 ~ 5.5V
VOUT1 (2v/div)
VOUT1 (20mV/div)
IOUT1=10mA
COUT1=4.7uF
VOUT2
CONT(2v/div)
VOUT2 (20mV/div)
IOUT2=10mA
COUT2=4.7uF
Time(20µs/div)
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Time (1ms/div)
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APL5551
Typical Characteristics
Power On
Power Dissipation vs. Ambient Temperature
2
VIN(2V/diV)
Cd=0.1uF
Power Dissipation(W)
1.8
1.6
1.4
VOUT1 (2V/div)
1.2
SOP-8-P
1
0.8
SOP-8
0.6
VOUT2 (2V/div)
0.4
0.2
RESET(5V/div)
0
25
50
75
100
125
150
175
Time(5ms/div)
Ambient Temperature (°C)
Power Off
VIN(2V/diV)
Cd=0.1uF
VOUT1 (2V/div)
VOUT2 (2V/div)
RESET(5V/div)
Time(0.2s/div)
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APL5551
Application Information
Capacitor Selection and Regulator Stability
properly reset and powers up into a known condition
after a power failure. RESET will remain valid with VIN
as low as 0.95V. The RESET output is a simple opendrain N channel MOSET structure. A pull-up resistor
must be used to pull this output up to some voltage.
For most application, this voltage will be the same
power supply that supplies VIN to the APL5551. The
APL5551is relatively immune to negative-going glitches
below the reset threshold. Typically reset delay time
is 13ms while using 0.1µF at Cd pin. If more transient
immunity is needed, a Cd capacitor can be placed as
larger as possible.
The APL5551 uses at least a 1µF capacitor on the
input. This capacitor can use Aluminum, Tantalum or
Ceramic capacitors. Input capacitor with large value
and low ESR provides better PSRR and line-transient
response. The output capacitor also can use Aluminum,
Tantalum or Ceramic capacitors, and it’s minimum
values is recommended 4.7µF, ESR muse be above
0.01Ω. Large output capacitor values can reduce noise
and improve load-transient response, stability, and
PSRR. Note that some ceramic dielectrics exhibit large
capacitance and ESR variation with Temperature. If use
this capacitor, it may be necessary to use 4.7µF or
more to ensure stability at temperature below -10°C.
Input-Output (Dropout) Voltage
The minimun input-output voltage differential (dropout)
determines the lowest usable supply voltage. The
dropout voltage is a function of drain-to-source on
resistance multiplied by the load current.
Load-Transient Considerations
The APL5551 load-transient response graphs in Typical
Characteristics show the transient response. A step
change in the load current from 1mA to 500mA at 1µ
second will cause less than 200mV transient spike.
Large output capacitor’s value and low ESR can reduce
transient spike.
Current Limit
APL5551 includes two separate current-limit circuitry
for each linear regulator. The current limit protection,
which sense the current flows the P-channel MOSFET,
and controls the output voltage. The point where
limiting occurs is I OUT=800mA. The output can be
shorted to ground for an indefinite amount of time
without damaging to the part.
Shutdown/Enable
The APL5551 has an active high enable function. Force
CONT high (>1.6V) enables the VOUT1, CONT low
(<0.4V) disables the VOUT1 and VOUT2 can not be affected
by CONT. In shutdown mode, the quiescent current
can reduce to 70µA. The CONT pin cannot be floating,
a floating CONT pin may cause an indeterminate state
on the output. If it is no use, connect to VIN for normal
operation.
Thermal Protection
Thermal protection limits total power dissipation in the
APL5551. When the junction temperature exceeds
TJ=+170°C, the thermal sensor generate a logic signal
to turn off the pass transistor and let IC to cool. When
the IC’s junction temperature cools by 15°C, the
thermal sensor will turn the pass transistor on again,
resulting in a pulsed output during continuous thermal
protection. Thermal protection is designed to protect
the IC in the event of fault conditions. For continual
RESET
The RESET pin is asserted whenever VDET falls below
the reset threshold voltage or if CONT is forced low at
some special IC (refer timing chart and pin description).
The reset function ensures the microprocessor is
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APL5551
Application Information
Thermal Protection (Cont.)
applications. The thermal pad is soldered to the top
ground pad and is connected to the internal or bottom
ground plane by several vias. The printed circuit board
(PCB) forms a heat sink and dissipates most of the
heat into ambient air. The vias are recommended to
have proper size to retain solder, helping heat
conduction.
operation, do not exceed the junction temperature
rating of TJ=+150°C.
Operating Region and Power Dissipation
The thermal resistance of the case and circuit board,
ambient and junction air temperature, and the rate of
air flow all control the APL5551 maximum power
dissipation. The power dissipation across the device
is P = IOUT (VIN-VOUT). The maximum power dissipation
is:
102 mil
PMAX = (TJ-TA) / (θJB +θBA )
118 mil
SOP-8-P
where TJ-TA is the temperature difference between the
junction and ambient air.
θJB is the thermal resistance of the package, θBA is the
thermal resistance through the printed circuit board,
copper traces, and other materials to the surrounding
air. The GND pin provides an electrical connection to
ground and channeling heat away. Connect the GND
pin to ground using a large pad or ground plane as a
heat sink, it can improve maximize thermal dissipation.
Die
Thermal
pad
Top
ground
pad
Ambient
Air
Vias
For example:
Internal
ground
plane
Printed
circuit
board
Figure 1
The SOP8 package has maximum power dissipation
0.7W at T A= 55°C and 1.4W at SOP-8-P (see Power
dissipation vs Ambient Temperature).
VIN = 5V, IOUT = 250mA, VOUT1 = 3.3V, VOUT2 = 2.8V,
PD = [(5-3.3)V+(5-2.8)V] x 250mA = 0.975W
the PD = 0.975W
According the power dissipation issue, we should adapt
the SOP-8-P package. It could reduce the thermal
resistance to maintain the IC longer life.
See figure 1. The SOP-8-P utilizes a bottom thermal
pad to minimize the thermal resistance of the package,
making the package suitable for high current
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APL5551
Packaging Information
E
e1
0.015X45
SOP-8 pin ( Reference JEDEC Registration MS-012)
H
e2
D
A1
A
1
L
0.004max.
Dim
Millimeters
Inches
Min.
Max.
Min.
Max.
A
A1
1.35
0.10
1.75
0.25
0.053
0.004
0.069
0.010
D
E
4.80
3.80
5.00
4.00
0.189
0.150
0.197
0.157
H
L
5.80
0.40
6.20
1.27
0.228
0.016
0.244
0.050
e1
e2
0.33
0.51
0.013
φ1
0°
1.27BSC
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Oct., 2005
0.020
0.50BSC
8°
13
0°
8°
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APL5551
Packaging Information
E1
E
0.015X45
SOP-8-P pin ( Reference JEDEC Registration MS-012)
H
D1
e1
e2
D
A1
1
L
0.004max.
Dim
A
Millimeters
Inches
Min.
Max.
Min.
Max.
A
1.35
1.75
0.053
0.069
A1
D
0
4.80
0.15
5.00
0
0.189
0.006
0.197
D1
E
3.00REF
3.80
0.118REF
4.00
0.150
2.60REF
0.157
E1
H
0.102REF
5.80
6.20
0.228
0.244
L
e1
0.40
0.33
1.27
0.51
0.016
0.013
0.050
0.020
e2
1.27BSC
0.50BSC
φ1
8°
8°
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APL5551
Physical Specifications
Terminal Material
Lead Solderability
Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn
Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
tp
TP
Critical Zone
T L to T P
Temperature
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
t 25 °C to Peak
Time
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Preheat
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
- Time (tL)
Peak/Classificatioon Temperature (Tp)
Time within 5°C of actual
Peak Temperature (tp)
Ramp-down Rate
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
183°C
60-150 seconds
217°C
60-150 seconds
See table 1
See table 2
10-30 seconds
20-40 seconds
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package .Measured on the body surface.
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APL5551
Classification Reflow Profiles (Cont.)
Table 1. SnPb Entectic Process – Package Peak Reflow Temperature s
3
3
Package Thickness
Volume mm
Volume mm
<350
≥350
<2.5 mm
240 +0/-5°C
225 +0/-5°C
≥2.5 mm
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
3
3
3
Package Thickness
Volume mm
Volume mm
Volume mm
<350
350-2000
>2000
<1.6 mm
260 +0°C*
260 +0°C*
260 +0°C*
1.6 mm – 2.5 mm
260 +0°C*
250 +0°C*
245 +0°C*
≥2.5 mm
250 +0°C*
245 +0°C*
245 +0°C*
*Tolerance: The device manufacturer/supplier shall assure process compatibility up to and
including the stated classification temperature (this means Peak reflow temperature +0°C.
For example 260°C+0°C) at the rated MSL level.
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TST
ESD
Latch-Up
Method
MIL-STD-883D-2003
MIL-STD-883D-1005.7
JESD-22-B,A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
Description
245°C, 5 SEC
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
Carrier Tape
t
D
P
Po
E
P1
Bo
F
W
Ko
Ao
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Oct., 2005
D1
16
www.anpec.com.tw
APL5551
Carrier Tape (Cont.)
T2
J
C
A
B
T1
Application
SOP- 8/-P
A
B
330 ± 1
62 +1.5
F
D
5.5± 1
C
J
12.75+ 0.15 2 ± 0.5
D1
Po
1.55 +0.1 1.55+ 0.25 4.0 ± 0.1
T1
T2
W
P
E
12.4 ± 0.2
2 ± 0.2
12± 0. 3
8± 0.1
1.75±0.1
P1
Ao
Bo
Ko
t
2.0 ± 0.1
6.4 ± 0.1
5.2± 0. 1
2.1± 0.1 0.3±0.013
(mm)
Cover Tape Dimensions
Application
SOP- 8/-P
Carrier Width
12
Cover Tape Width
9.3
Devices Per Reel
2500
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
7F, No. 137, Lane 235, Pac Chiao Rd.,
Hsin Tien City, Taipei Hsien, Taiwan, R. O. C.
Tel : 886-2-89191368
Fax : 886-2-89191369
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Oct., 2005
17
www.anpec.com.tw