Triple and Octal Channel Protectors ADG466/ADG467 a FEATURES Fault and Overvoltage Protection up to 640 V Signal Paths Open Circuit with Power Off Signal Path Resistance of RON with Power On 44 V Supply Maximum Ratings Low On Resistance ADG466/ADG467 60 V typ 1 nA Max Path Current Leakage @ +258C Low RON Match (5 V max) Low Power Dissipation 0.8 mW typ Latch-Up Proof Construction OBS APPLICATIONS ATE Equipment Sensitive Measurement Equipment Hot-Insertion Rack Systems GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS VDD VSS VDD VD1 VS1 VD1 VS1 VD2 VS2 VD2 VS2 VS3 VD3 VS3 VD8 VS8 VD3 ADG466 VIN VIN OLE The ADG466 and ADG467 are triple and octal channel protectors, respectively. The channel protector is placed in series with the signal path. The channel protector will protect sensitive components from voltage transience in the signal path whether the power supplies are present or not. Because the channel protection works whether the supplies are present or not, the channel protectors are ideal for use in applications where correct power sequencing can’t always be guaranteed (e.g., hot-insertion rack systems) to protect analog inputs. This is discussed further, and some example circuits are given in the “Applications” section of this data sheet. Each channel protector has an independent operation and consists of an n-channel MOSFET, a p-channel MOSFET and an n-channel MOSFET, connected in series. The channel protector behaves just like a series resistor during normal operation, i.e., (VSS + 2 V) < VIN < (VDD – 1.5 V). When a channel’s analog input exceeds the power supplies (including VDD and VSS = 0 V), one of the MOSFETs will switch off, clamping the output to either VSS + 2 V or VDD – 1.5 V. Circuitry and signal source protection is provided in the event of an overvoltage or power loss. The channel protectors can withstand overvoltage inputs from –40 V to +40 V. See the “Circuit Information” section of this data sheet. The ADG466 and ADG467 can operate off both bipolar and unipolar supplies. The channels are normally on when power is connected and open circuit when power is disconnected. With power supplies of ± 15 V, the on-resistance of the ADG466 and VSS ADG467 VDD VOUT VOUT VDD TE OUTPUT CLAMPED @ VDD – 1.5V ADG467 is 50 Ω typ with a leakage current of ± 1 nA max. When power is disconnected, the input leakage current is approximately ± 5 nA typ. The ADG466 is available in 8-lead DIP, SOIC and µSOIC packages. The ADG467 is available in an 18-lead SOIC package and a 20-lead SSOP package. PRODUCT HIGHLIGHTS 1. Fault Protection. The ADG466 and ADG467 can withstand continuous voltage inputs from –40 V to +40 V. When a fault occurs due to the power supplies being turned off or due to an overvoltage being applied to the ADG466 and ADG467, the output is clamped. When power is turned off, current is limited to the microampere level. 2. Low Power Dissipation. 3. Low RON. ADG466/ADG467 60 Ω typ. 4. Trench Isolation Latch-Up Proof Construction. A dielectric trench separates the p- and n-channel MOSFETs thereby preventing latch-up. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1996 ADG466/ADG467–SPECIFICATIONS Dual Supply1 (V DD = +15 V, VSS = –15 V, GND = 0 V, unless otherwise noted) Parameter ADG466 +258C B1 FAULT PROTECTED CHANNEL Fault-Free Analog Signal Range2 ±1 ±5 ± 0.04 ±1 ± 0.2 ±5 nA typ nA max ± 0.2 ±2 ± 0.4 ±5 ± 0.2 ±2 ± 0.4 ±5 nA typ nA max ±2 ±5 ± 0.5 ±2 ±2 ± 10 nA typ nA max ± 0.1 ± 0.5 ± 0.006 ± 0.015 ± 0.16 ± 0.5 µA typ µA max OBS POWER REQUIREMENTS IDD ISS VDD/VSS Output Open Circuit ± 0.1 ±1 3 4 Channel Input Leakage, ID(OFF) (with Power Off and Output S/C) V min V max Ω typ Ω max Ω max Ω max 5 ∆RON RON Match Channel Input Leakage, ID(OFF) (with Power Off and Fault) Test Conditions/Comments VSS + 1.2 VDD – 0.8 80 95 6 6 60 Channel Input Leakage, ID(ON) (with Fault Condition) Units VSS + 1.2 VDD – 0.8 75 80 4 6 RON LEAKAGE CURRENTS Channel Output Leakage, IS(ON) (without Fault Condition) ADG467 +258C B1 ± 0.5 ±1 ± 0.005 ± 0.015 ± 0.05 ± 0.5 ± 0.05 ± 0.5 0 ± 20 62 –10 V ≤ VS ≤ +10 V, IS = 1 mA –5 V ≤ VS ≤ +5 V VS = ± 10 V, IS = 1 mA VS = VD = ± 10 V OLE VS = ± 25 V VD = Open Circuit ±8 ±8 0 ± 20 ± 0.05 ± 0.5 ± 0.05 ± 0.5 0 ± 20 ±8 ±8 0 ± 20 µA typ µA max µA typ µA max V min V max VDD = 0 V, VSS = 0 V VS = ± 35 V, VD = Open Circuit VDD = 0 V, VSS = 0 V VS = ± 35 V, VD = 0 V TE NOTES 1 Temperature range is as follows: B Version: –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. –2– REV. 0 ADG466/ADG467 ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATIONS (TA = +25°C unless otherwise noted) 8-Lead DIP, SOIC and mSOIC VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +44 V VS, VD, Analog Input Overvoltage with Power ON2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS – 20 V to VDD + 20 V VS, VD, Analog Input Overvoltage with Power OFF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –35 V to +35 V Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 20 mA Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA (Pulsed at 1 ms, 10% Duty Cycle Max) Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +125°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Plastic DIP Package θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 125°C/W Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C SOIC Package θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C µSOIC Package θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C SSOP Package θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 130°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C 18-Lead SOIC 8 VDD VD1 1 18 VDD 7 VS1 VD2 2 17 VS1 TOP VIEW VD3 3 (Not to Scale) 6 VS2 VD3 3 16 VS2 VSS 4 VD4 4 VD1 1 VD2 2 ADG466 5 VS3 ADG467 15 VS3 VD5 5 TOP VIEW 14 VS4 (Not to Scale) VD6 6 13 VS5 12 VS6 VD7 7 OBS VD8 8 11 VS7 VSS 9 10 VS8 OLE 20-Lead SSOP VD1 1 20 NC VD2 2 19 VDD VD3 3 VD4 4 VD5 5 TE 18 VS1 17 VS2 ADG467 16 VS3 TOP VIEW 15 V S4 (Not to Scale) VD7 7 14 VS5 VD6 6 VD8 8 VSS 9 NC 10 NOTES 1 Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at S or D will be clamped by the channel protector, see “Circuit Information” section of the data sheet. 13 VS6 12 VS7 11 VS8 NC = NO CONNECT ORDERING GUIDE Model Temperature Range Package Description Package Option ADG466BN ADG466BR ADG466BRM ADG467BR ADG467BRS –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 8-Lead Plastic DIP 8-Lead Small Outline Package 8-Lead Micro Small Outline Package 18-Lead Small Outline Package 20-Lead Shrink Small Outline Package N-8 SO-8 RM-8 R-18 RS-20 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG466/ADG467 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE ADG466/ADG467–Typical Performance Characteristics ADG466 80 POSITIVE OVERVOLTAGE ON INPUT RLOAD = 100kΩ CLOAD = 100pF VDD = +10V VSS = –10V 75 70 65 VDD, VSS =65V RON – Ω 60 55 –5V TO +15V STEP INPUT 15V VDD, VSS =615V 10V VDD, VSS =610V 50 VDD, VSS =613.5V 5V 45 35 30 –10 –5V 616.5V OBS –5 0 VD – Volts 5 10 Ch1 VDD = +15V VSS = –15V 60 RON – Ω Ch2 1258C 50 45 35 –408C –5 0 VD – Volts 5 –5V 10 Ch1 RLOAD = 100kΩ CLOAD = 100pF VDD = +10V VSS = –10V 5.00V Ch2 CHANNEL PROTECTOR OUTPUT TE 5.00V 5V TO –15V STEP INPUT M50.0ns Ch1 500mV Figure 5. Negative Overvoltage Transience Response Figure 2. On Resistance as a Function of Temperature and VD (Input Voltage) ADG467 105 10V TO +10 V INPUT 95 65V 85 RON – Ω 500mV 0V 30 25 –10 Ch1 NEGATIVE OVERVOLTAGE ON INPUT –15V 258C M50.0ns 5V –10V 858C 40 5.00V OLE 70 55 5.00V Figure 4. Positive Overvoltage Transience Response Figure 1. On Resistance as a Function of VDD and VD (Input Voltage) 65 CHANNEL PROTECTOR OUTPUT 0V 40 RLOAD =100kΩ VDD=+5V VSS=–5V 20V 1→ 75 VCLAMP=4.5V 615V 65 OUTPUT 613.5V 610V 2→ 55 45 -10 –5 0 VD – Volts 5 VCLAMP=4V 616.5V 10 Ch1 Figure 3. On Resistance as a Function of VDD and VD (Input Voltage) 5.00V Ch2 5.00V M100µs Ch1 500mV Figure 6. Overvoltage Ramp –4– REV. 0 ADG466/ADG467 where ∆V is due to I × R voltage drop across the channels of the MOS devices (see Figure 9). As can be seen from Figure 9, the current during fault condition is determined by the load on the output (i.e., VCLAMP/RL ). However, if the supplies are off, the fault current is limited to the nano-ampere level. CIRCUIT INFORMATION Figure 7 below shows a simplified schematic of a channel protector circuit. The circuit is made up of four MOS transistors—two NMOS and two PMOS. One of the PMOS devices does not lie directly in the signal path but is used to connect the source of the second PMOS device to its backgate. This has the effect of lowering the threshold voltage and so increasing the input signal range of the channel for normal operation. The source and backgate of the NMOS devices are connected for the same reason. During normal operation the channel protectors have a resistance of 60 Ω typ. The channel protectors are very low power devices, and even under fault conditions the supply current is limited to sub micro-ampere levels. All transistors are dielectrically isolated from each other using a trench isolation method. This makes it impossible to latch up the channel protectors. For an explanation, see “Trench Isolation” section. Figures 8, 10 and 11 show the operating conditions of the signal path transistors during various fault conditions. Figure 8 shows how the channel protectors operate when a positive overvoltage is applied to the channel protector. VDD – VTN* (+13.5V) OBS VSS VDD (+15V) VSS (–15V) PMOS VDD (+15V) Figure 8. Positive Overvoltage on the Channel Protector The first NMOS transistor goes into a saturated mode of operation as the voltage on its Drain exceeds the Gate voltage (VDD) – the threshold voltage (VTN). This situation is shown in Figure 9. The potential at the source of the NMOS device is equal to VDD – VTN. The other MOS devices are in a nonsaturated mode of operations. VSS TE VDD When a negative overvoltage is applied to the channel protector circuit, the PMOS transistor enters a saturated mode of operation as the drain voltage exceeds VSS – VTP. See Figure 10 below. As in the case of the positive overvoltage, the other MOS devices are nonsaturated. Figure 7. The Channel Protector Circuit Overvoltage Protection When a fault condition occurs on the input of a channel protector, the voltage on the input has exceeded some threshold voltage set by the supply rail voltages. The threshold voltages are related to the supply rails as follows. For a positive overvoltage, the threshold voltage is given by VDD – VT where VTN is the threshold voltage of the NMOS transistor (1.5 V typ). In the case of a negative overvoltage the threshold voltage is given by VSS – VTP where VTP is the threshold voltage of the PMOS device (2 V typ). If the input voltage exceeds these threshold voltages, the output of the channel protector (no load) is clamped at these threshold voltages. However, the channel protector output will clamp at a voltage that is inside these thresholds if the output is loaded. For example with an output load of 1 kΩ, VDD = 15 V and a positive overvoltage. The output will clamp at VDD – VTN – ∆V = 15 V – 1.5 V – 0.6 V = 12.9 V VD VG NEGATIVE OVERVOLTAGE (–20V) NONSATURATED VDD (+15V) EFFECTIVE SPACE CHARGE REGION VT = 1.5V P– VSS (–15V) NMOS NONSATURATED VDD (+15V) Figure 10. Negative Overvoltage on the Channel Protector VS N CHANNEL SATURATED VSS – VTP* (–13V) *VTP = PMOS THRESHOLD VOLTAGE (–2V) ∆V (+13.5V) PMOS N+ PMOS NMOS NEGATIVE OVERVOLTAGE (–20V) (VDD =15V) (+20V) N+ N+ (VG – VT = 13.5V) NMOS NONSATURATED OPERATION VCLAMP RL IOUT Figure 9. Positive Overvoltages Operation of the Channel Protector REV. 0 NONSATURATED *VTN = NMOS THRESHOLD VOLTAGE (+1.5V) NMOS NMOS OVERVOLTAGE OPERATION (SATURATED) NONSATURATED SATURATED NMOS OLE PMOS VDD PMOS NMOS POSITIVE OVERVOLTAGE (+20V) –5– ADG466/ADG467 channel protector will not exceed the threshold voltages set by the supplies (see “Circuit Information”) when there is an overvoltage on the input. When the input voltage does not exceed these threshold voltages, the channel protector behaves like a series resistor (60 Ω typ). The resistance of the channel protector does vary slightly with operating conditions (see “Typical Performance Graphs”). The channel protector is also functional when the supply rails are down (e.g., power failure) or momentarily unconnected (e.g., rack system). This is where the channel protector has an advantage over more conventional protection methods such as diode clamping (see “Applications Information”). When VDD and VSS equal 0 V, all transistors are off and the current is limited to subnano-ampere levels (see Figure 11). The power sequencing protection is afforded by the fact that when the supplies to the channel protector are not connected, the channel protector becomes a high resistance device. Under this condition all transistors in the channel protector are off and the only currents that flow are leakage currents, which are at the µA level. (0V) NMOS PMOS NMOS POSITIVE OR NEGATIVE OVERVOLTAGE OFF OFF OFF OBS VDD (0V) VSS (0V) VDD (0V) EDGE CONNECTOR Figure 11. Channel Protector Supplies Equal to Zero Volts TRENCH ISOLATION +5V OLE ANALOG IN –2.5V TO +2.5V LOGIC CMOS devices are normally isolated from each other by Junction Isolation. In Junction Isolation, the N and P wells of the CMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode becomes forward biased. A Silicon-Controlled Rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. With Trench Isolation, this diode is removed; the result is a latch-up proof circuit. VG T R E N C H P+ N– LOGIC GND P+ T R E N C H N+ N-CHANNEL N+ P– CONTROL LOGIC Figure 13. Overvoltage and Power Supply Sequencing Protection Figure 13 shows a typical application that requires overvoltage and power supply sequencing protection. The application shows a Hot-Insertion rack system. This involves plugging a circuit board or module into a live rack via an edge connector. In this type of application it is not possible to guarantee correct power supply sequencing. Correct power supply sequencing means that the power supplies should be connected before any external signals. Incorrect power sequencing can cause a CMOS device to “latch up.” This is true of most CMOS devices regardless of the functionality. RC networks are used on the supplies of the channel protector (Figure 13) to ensure that the rest of the circuitry is powered up before the channel protectors. In this way, the outputs of the channel protectors are clamped well below VDD and VSS until the capacitors are charged. The diodes ensure that the supplies on the channel protector never exceed the supply rails of the board when it is being disconnected. Again this ensures that signals on the inputs of the CMOS devices never exceed the supplies. VD VS TE ADC ADG466 VG VD P-CHANNEL VSS –5V The MOS devices that make up the channel protector are isolated from each other by an oxide layer (trench) (see Figure 12). When the NMOS and PMOS devices are not electrically isolated from each other, there exists the possibility of “latchup” caused by parasitic junctions between CMOS transistors. Latch-up is caused when P-N junctions that are normally reverse biased become forward biased, causing large currents to flow, which can be destructive. VS VDD T R E N C H BURIED OXIDE LAYER SUBSTRATE (BACKGATE) Figure 12. Trench Isolation APPLICATIONS INFORMATION Overvoltage and Power Supply Sequencing Protection The ADG466 and ADG467 are ideal for use in applications where input overvoltage protection is required and correct power supply sequencing cannot always be guaranteed. The overvoltage protection ensures that the output voltage of the –6– REV. 0 ADG466/ADG467 VDD = +5V High Voltage Surge Suppression The ADG466 and ADG467 are not intended for use in high voltage applications like surge suppression. The ADG466 and ADG467 have breakdown voltages of VSS – 20 V and VDD + 20 V on the inputs when the power supplies are connected. When the power supplies are disconnected, the breakdown voltages on the input of the channel protector are ± 35 V. In applications where inputs are likely to be subject to overvoltages exceeding the breakdown voltages quoted for the channel protectors, transient voltage suppressors (TVSs) should be used. These devices are commonly used to protect vulnerable circuits from electric overstress such as that caused by electrostatic discharge, inductive load switching and induced lightning. However, TVSs can have a substantial standby (leakage) current (300 µA typ) at the reverse standoff voltage. The reverse standoff voltage of a TVS is the normal peak operating voltage of the circuit. Also TVS offer no protection against latch-up of sensitive CMOS devices when the power supplies are off. The best solution is to use a channel protector in conjunction with a TVS to provide the best leakage current specification and circuit protection. OBS ADC ADG466 TVSs BREAKDOWN VOLTAGE = 20V Figure 14. High Voltage Protection Figure 14 shows an input protection scheme that uses both a TVS and channel protector. The TVS is selected with a reverse standoff voltage that is much greater than operating voltage of the circuit (TVSs with higher breakdown voltages tend to have better standby leakage current specifications) but is inside the breakdown voltage of the channel protector. This circuit protects the circuitry whether the power supplies are present or not. OLE REV. 0 VSS = –5V TE –7– ADG466/ADG467 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 8-Lead Small Outline IC (SO-8) 5 0.280 (7.11) 0.240 (6.10) 4 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) PIN 1 0.0118 (0.30) 0.0040 (0.10) 0.1043 (2.65) 0.0926 (2.35) 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC 0.0196 (0.50) x 45° 0.0099 (0.25) 0.0098 (0.25) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) 20-Lead Shrink Small Outline Package (RS-20) 0.295 (7.50) 0.271 (6.90) 0.0291 (0.74) x 45° 0.0098 (0.25) 20 11 1 10 TE 0.07 (1.78) 0.066 (1.67) 0.078 (1.98) PIN 1 0.068 (1.73) 0.0500 (1.27) 0.0157 (0.40) 8° 0.0500 0.0192 (0.49) 0° (1.27) 0.0138 (0.35) SEATING 0.0125 (0.32) PLANE BSC 0.0091 (0.23) 0.0688 (1.75) 0.0532 (1.35) 0.311 (7.9) 0.301 (7.64) 9 0.4193 (10.65) 0.3937 (10.00) 1 0.2992 (7.60) 0.2914 (7.40) 0.4625 (11.75) 0.4469 (11.35) 10 SEATING PLANE 0.2440 (6.20) 0.2284 (5.80) OLE 18-Lead Small Outline IC (R-18) 18 4 0.0098 (0.25) 0.0040 (0.10) OBS SEATING PLANE 0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC 5 1 PIN 1 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 8 0.212 (5.38) 0.205 (5.21) 1 0.1574 (4.00) 0.1497 (3.80) 0.008 (0.203) 0.002 (0.050) 0.0256 (0.65) BSC SEATING 0.009 (0.229) PLANE 0.005 (0.127) 8° 0° 0.037 (0.94) 0.022 (0.559) 8-Lead Micro Small Outline IC (RM-8) 0.122 (3.10) 0.114 (2.90) 8 5 0.199 (5.05) 0.187 (4.75) 0.122 (3.10) 0.114 (2.90) 1 4 PRINTED IN U.S.A. 8 C2207–12–10/96 0.1968 (5.00) 0.1890 (4.80) 0.430 (10.92) 0.348 (8.84) PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.120 (3.05) 0.112 (2.84) 0.018 (0.46) 0.008 (0.20) 0.011 (0.28) 0.003 (0.08) –8– 33° 27° 0.028 (0.71) 0.016 (0.41) REV. 0