Cypress CY7C245A 2k x 8 reprogrammable registered prom Datasheet

CY7C245A
2K x 8 Reprogrammable Registered PROM
Features
Functional Description
The CY7C245A is a high-performance, 2K x 8, electrically
programmable, read-only memory packaged in a slim 300-mil
plastic or hermetic DIP. The ceramic package may be
equipped with an erasure window; when exposed to UV light
the PROM is erased and can then be reprogrammed. The
memory cells utilize proven EPROM floating-gate technology
and byte-wide intelligent programming algorithms.
• Windowed for reprogrammability
• CMOS for optimum speed/power
• High speed
— 15-ns address set-up
— 10-ns clock to output
• Low power
The CY7C245A replaces bipolar devices and offers the advantages of lower power, reprogrammability, superior performance and high programming yield. The EPROM cell requires
only 12.5V for the supervoltage, and low current requirements
allow gang programming. The EPROM cells allow each
memory location to be tested 100%, because each location is
written into, erased, and repeatedly exercised prior to encapsulation. Each PROM is also tested for AC performance to
guarantee that after customer programming the product will
meet AC specification limits.
— 330 mW (commercial) for -25 ns
— 660 mW (military)
• Programmable synchronous or asynchronous output
enable
• On-chip edge-triggered registers
• Programmable asynchronous register (INIT)
• EPROM technology, 100% programmable
• Slim, 300-mil, 24-pin plastic or hermetic DIP
• 5V ±10% VCC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
The CY7C245A has an asynchronous initialize function (INIT).
This function acts as a 2049th 8-bit word loaded into the
on-chip register. It is user programmable with any desired
word, or may be used as a PRESET or CLEAR function on the
outputs. INIT is triggered by a low level, not an edge.
Logic Block Diagram
Pin Configurations
INIT
DIP Top View
A0
7
A1
MULTIPLEXER
A4
A5
A6
ADDRESS
DECODER
A7
A8
A9
6
O
8-BIT
EDGETRIGGERED
REGISTER
5
O
4
O
3
O
COLUMN
ADDRESS
2
O
A10
1
D
CP
C
Q
VCC
A8
A9
A10
INIT
E/ES
CP
O7
O6
O5
O4
O3
A4
A3
A2
A1
A0
NC
O0
0
4 3 2 1 282726
25
5
24
6
23
7
22
8
21
9
20
10
19
11
12131415161718
A10
INIT
E/ES
CP
NC
O7
O6
O1
O2
GND
NC
O3
O4
O5
E/E S
24
23
22
21
20
19
18
17
16
15
14
13
LCC/PLCC (Opaque only) Top View
O
CP
PROGRAMMABLE
MULTIPLEXER
1
2
3
4
5
6
7
8
9
10
11
12
A5
A6
A7
NC
VCC
A8
A9
A3
O
PROGRAMMABLE
ARRAY
ROW
ADDRESS
PROGRAMMABLE
INITIALIZE WORD
A2
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
O
Selection Guide
7C245A-15
7C245A-18
Minimum Address Set-up Time
15
18
25
35
ns
Maximum Clock to Output
10
12
12
15
ns
120
120
90
90
mA
120
120
120
mA
Maximum Operating Current Standard
Commercial
Military
Cypress Semiconductor Corporation
Document #: 38-04007 Rev. *E
•
198 Champion Court
•
7C245A-25
7C245A-35
Unit
San Jose, CA 95134-1709
•
408-943-2600
Revised August 17, 2006
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CY7C245A
Operating Modes
The CY7C245A is a CMOS electrically programmable read
only memory organized as 2048 words x 8 bits and is a
pin-for-pin replacement for bipolar TTL fusible link PROMs.
The CY7C245A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined microprogrammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with a programmable synchronous (ES) or
asynchronous (E) output enable and asynchronous initialization (INIT).
Upon power-up the state of the outputs will depend on the
programmed state of the enable function (ES or E). If the
synchronous enable (ES) has been programmed, the register
will be in the set condition causing the outputs (O0–O7) to be
in the OFF or high-impedance state. If the asynchronous
enable (E) is being used, the outputs will come up in the OFF
or high-impedance state only if the enable (E) input is at a
HIGH logic level. Data is read by applying the memory location
to the address inputs (A0–A10) and a logic LOW to the enable
input. The stored data is accessed and loaded into the master
flip-flops of the data register during the address set-up time. At
the next LOW-to-HIGH transition of the clock (CP), data is
transferred to the slave flip-flops, which drive the output
buffers, and the accessed data will appear at the outputs
(O0–O7).
If the asynchronous enable (E) is being used, the outputs may
be disabled at any time by switching the enable to a logic
HIGH, and may be returned to the active state by switching the
enable to a logic LOW.
If the synchronous enable (ES) is being used, the outputs will
go to the OFF or high-impedance state upon the next positive
clock edge after the synchronous enable input is switched to
a HIGH level. If the synchronous enable pin is switched to a
logic LOW, the subsequent positive clock edge will return the
output to the active state. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
low-to-high transition of the clock. This unique feature allows
the CY7C245A decoders and sense amplifiers to access the
next location while previously addressed data remains stable
on the outputs.
System timing is simplified in that the on-chip edge triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C245A has an asynchronous initialize input (INIT).
The initialize function is useful during power-up and time-out
sequences and can facilitate implementation of other sophisticated functions such as a built-in “jump start” address. When
activated, the initialize control input causes the contents of a
user-programmed 2049th 8-bit word to be loaded into the
Document #: 38-04007 Rev. *E
on-chip register. Each bit is programmable and the initialize
function can be used to load any desired combination of 1s
and 0s into the register. In the unprogrammed state, activating
INIT will generate a register CLEAR (all outputs LOW). If all
the bits of the initialize word are programmed, activating INIT
performs a register PRESET (all outputs HIGH).
Applying a LOW to the INIT input causes an immediate load
of the programmed initialize word into the master and slave
flip-flops of the register, independent of all other inputs,
including the clock (CP). The initialize data will appear at the
device outputs after the outputs are enabled by bringing the
asynchronous enable (E) LOW.
Erasure Characteristics
Wavelengths of light less than 4000 Angstroms begin to erase
the 7C245A. For this reason, an opaque label should be
placed over the window if the PROM is exposed to sunlight or
fluorescent lighting for extended periods of time.
The recommended dose for erasure is ultraviolet light with a
wavelength of 2537 Angstroms for a minimum dose (UV
intensity multiplied by exposure time) of 25 Wsec/cm2. For an
ultraviolet lamp with a 12 mW/cm2 power rating the exposure
time would be approximately 35 minutes. The 7C245A needs
to be within 1 inch of the lamp during erasure. Permanent
damage may result if the PROM is exposed to high-intensity
UV light for an extended period of time. 7258 Wsec/cm2 is the
recommended maximum dosage.
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Bit Map Data
Programmer Address
RAM Data
Decimal
Hex
Contents
0
0
Data
.
.
.
.
.
.
.
.
.
2047
7FF
Data
2048
800
Init Byte
2049
801
Control Byte
Control Byte
00 Asynchronous output enable (default state)
01 Synchronous output enable
Page 2 of 13
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CY7C245A
Table 1. Mode Selection
Mode
Pin Function[1]
Read or Output Disable
A10–A4
A3
A2–A1
A0
CP
E, ES
INIT
O7–O0
A10–A4
A3
A2–A1
A0
PGM
VFY
VPP
D7–D0
Read
A10–A4
A3
A2–A1
A0
VIL/VIH
VIL
VIH
O7–O0
Output Disable
A10–A4
A3
A2–A1
A0
X
VIH
VIH
High Z
Other
Initialize
A10–A4
A3
A2–A1
A0
X
VIL
VIL
Init. Byte
Program
A10–A4
A3
A2–A1
A0
VILP
VIHP
VPP
D7–D0
Program Verify
A10–A4
A3
A2–A1
A0
VIHP
VILP
VPP
O7–O0
Program Inhibit
A10–A4
A3
A2–A1
A0
VIHP
VIHP
VPP
High Z
Intelligent Program
A10–A4
A3
A2–A1
A0
VILP
VIHP
VPP
D7–D0
Program Synchronous Enable
A10–A4
VIHP
A2–A1
VPP
VILP
VIHP
VPP
High Z
Program Initialization Byte
A10–A4
VILP
A2–A1
VPP
VILP
VIHP
VPP
D7–D0
Blank Check Zeros
A10–A4
A3
A2–A1
A0
VIHP
VILP
VPP
Zeros
Figure 1. Programming Pinouts
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A8
A9
A10
VPP
VFY
PGM
D7
D6
D5
D4
D3
A5
A6
A7
NC
VCC
A8
A9
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
LCC/PLCC (Opaque Only) Top View
A4
A3
A2
A1
A0
NC
D0
5
6
7
8
9
10
11
4 3 2 1 28 27 26
25
24
23
22
21
20
19
121314151617 18
A10
VPP
VFY
PGM
NC
D7
D6
D1
D2
GND
NC
D3
D4
D5
DIP Top View
MILITARY SPECIFICATIONS
Group A Subgroup Testing
SMD Cross Reference
DC Characteristics
5962-88735
033X
CY7C245A-25LMB
5962-88735
04LX
CY7C245A-25DMB
SMD Number
Parameter
Subgroups
VOH
1, 2, 3
VOL
1, 2, 3
VIH
1, 2, 3
VIL
1, 2, 3
IIX
1, 2, 3
IOZ
1, 2, 3
ICC
1, 2, 3
Suffix
Cypress Number
Switching Characteristics
Parameter
Subgroups
tSA
7, 8, 9, 10, 11
tHA
7, 8, 9, 10, 11
tCO
7, 8, 9, 10, 11
Note
1. X = “don’t care” but not to exceed VCC + 5%.
Document #: 38-04007 Rev. *E
Page 3 of 13
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CY7C245A
Maximum Ratings[2]
DC Program Voltage (Pins 7, 18, 20) ........................... 13.0V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State .....................................................−0.5V to +7.0V
DC Input Voltage .................................................−3.0V to +7.0V
UV Erasure ................................................... 7258 Wsec/cm2
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VCC
0°C to +70°C
5V ±10%
Military[3]
−55°C to +125°C
5V ±10%
Industrial
–40°C to +85°C
5V ±10%
Commercial
Electrical Characteristics Over the Operating Range[4,5]
Parameter
Description
Test Conditions
7C245A-15
Min.
VOH
Output HIGH Voltage
VCC = Min., IOH = −4.0 mA
VIN = VIH or VIL
VOL
Output LOW Voltage
VCC = Min., IOL = 16 mA
VIN = VIH or VIL
VIH
Input HIGH Level
Guaranteed Input Logical
HIGH Voltage for All Inputs
VIL
Input LOW Level
Guaranteed Input Logical
LOW Voltage for All Inputs
GND < VIN < VCC
7C245A-18
Max. Min. Max. Min.
2.4
2.4
VCC
0.4
2.0
VCC
0.8
−10
IIX
Input Leakage Current
VCD
Input Clamp Diode Voltage
IOZ
Output Leakage Current
GND < VO < VCC Output
Disabled[6]
−10
IOS
Output Short Circuit Current
VCC = Max., VOUT = 0.0V[7]
−20
ICC
Power Supply Current
VCC = Max.,
IOUT = 0 mA
VPP
Programming Supply Voltage
IPP
Programming Supply Current
VIHP
Input HIGH Programming Voltage
VILP
Input LOW Programming Voltage
2.0
0.8
Unit
Max.
2.4
0.4
2.0
7C245A-25
7C245A-35
7C245A-45
V
0.4
V
VCC
V
0.8
V
−10
+10
−10
+10
µA
+10
−10
+10
−10
+10
µA
−90
−20
−90
−20
−90
mA
90
mA
+10
Note 5
Com’l
120
120
Mil
120
12
13
12
13
50
3.0
120
12
50
3.0
13
V
50
mA
3.0
0.4
0.4
V
0.4
V
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
10
pF
10
pF
Notes
2. The voltage on any input or I/O pin cannot exceed the power pin during power-up.
3. TA is the “instant on” case temperature.
4. See page 3 of this data sheet for Group A subgroup testing information.
5. See the “Introduction to CMOS PROMs” section of the Cypress Data Book for general information on testing.
6. For devices using the synchronous enable, the device must be clocked after applying these voltages to perform this measurement.
7. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
Document #: 38-04007 Rev. *E
Page 4 of 13
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CY7C245A
AC Test Loads and Waveforms[4, 5]
R1 250Ω
5V
R1 250Ω
5V
OUTPUT
R2
167Ω
50 pF
R2
167Ω
5 pF
(a) Normal Load
90%
10%
90%
10%
GND
≤ 5 ns
≤ 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
3.0V
OUTPUT
(b) High Z Load
Equivalent to: TH ÉVENIN EQUIVALENT
100Ω
OUTPUT
2.0V
Switching Characteristics Over Operating Range[4, 5]
Parameter
7C245A-15
Description
7C245A-18
Min. Max. Min. Max.
7C245A-35
7C245A-25
7C245A-35
Min.
Min.
Min.
Max.
Max.
Max.
Unit
tSA
Address Set-Up to Clock HIGH
15
tHA
Address Hold from Clock HIGH
0
tCO
Clock HIGH to Valid Output
tPWC
Clock Pulse Width
10
12
15
20
20
ns
tSES
ES Set-Up to Clock HIGH
10
10
12
15
15
ns
tHES
ES Hold from Clock HIGH
5
tDI
Delay from INIT to Valid Output
tRI
INIT Recovery to Clock HIGH
10
12
15
20
20
ns
tPWI
INIT Pulse Width
10
12
15
20
25
ns
HIGH[8]
18
25
0
10
0
12
5
15
35
0
12
5
20
45
0
15
5
20
ns
ns
25
5
20
ns
ns
35
ns
tCOS
Valid Output from Clock
15
15
15
20
30
ns
tHZC
Inactive Output from Clock
HIGH[8]
15
15
15
20
30
ns
tDOE
Valid Output from E LOW[9]
12
15
15
20
30
ns
15
15
15
20
30
ns
tHZE
Inactive Output from
E HIGH[9]
Notes
8. Applies only when the synchronous (ES) function is used.
9. Applies only when the asynchronous (E) function is used.
Document #: 38-04007 Rev. *E
Page 5 of 13
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CY7C245A
Switching Waveforms[5]
tHA
tSA
tHA
tHES
tSES
tHES
A0 − A10
tSES
ES
tSES
tHES
tPWC
CP
tPWC
tPWC
tPWC
tPWC
tPWC
O0 − O7
tCO
tHZC
tCOS
tCO
tHZE
tDOE
E
tDI
tRI
INIT
tPWI
Document #: 38-04007 Rev. *E
Page 6 of 13
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CY7C245A
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.2
1.4
1.2
1.0
TA =25°C
f = fMAX
0.6
4.0
4.5
5.0
5.5
1.1
1.0
0.9
0.8
−55
6.0
SUPPLY VOLTAGE (V)
CLOCK TO OUTPUT TIME
vs. TEMPERATURE
NORMALIZED SET-UP TIME
1.2
1.0
0.8
0.6
−55
1.0
0.8
0.6
TA =25°C
0.4
4.0
125
25
4.5
5.0
5.5
30.0
25.0
DELTA t AA (ns)
0.98
0.96
0.94
0.92
20.0
15.0
10.0
TA =25°C
VCC =4.5V
5.0
0.90
0
25
50
75
1.2
1.0
0.8
TA =25°C
0.6
4.0
100
0.0
CLOCK PERIOD (ns)
0
200
400
600
800 1000
CAPACITANCE (pF)
4.5
5.0
5.5
6.0
NORMALIZED SET-UP TIME
vs. TEMPERATURE
1.6
1.4
1.2
1.0
0.8
125
25
AMBIENT TEMPERATURE (°C)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
1.02
VCC =5.5V
TA =25°C
1.4
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
1.00
1.6
0.6
−55
6.0
OUTPUT SINK CURRENT (mA)
1.4
CLOCK TO OUTPUT TIME
vs. VCC
SUPPLY VOLTAGE (V)
1.2
NORMALIZED SUPPLY CURRENT
vs. CLOCK PERIOD
NORMALIZED ICC
125
NORMALIZED SET-UP TIME
vs. SUPPLYVOLTAGE
1.6
0.88
25
AMBIENT TEMPERATURE (°C)
NORMALIZED SET-UP TIME
0.8
NORMALIZED CLOCK-TO-OUTPUT TIME
NORMALIZED I CC
NORMALIZED ICC
1.6
NORMALIZED CLOCK-TO-OUTPUT TIME
Typical DC and AC Characteristics
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
175
150
125
100
75
VCC =5.0V
TA =25°C
50
25
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
Ordering Information
Speed (ns)
tSA
tCO
ICC
(mA)
Ordering
Code
15
10
120
CY7C245A-15JC
J64
28-Lead Plastic Leaded Chip Carrier
Commercial
15
10
120
CY7C245A-15JI
J64
28-Lead Plastic Leaded Chip Carrier
Industrial
18
12
120
CY7C245A-18QMB
Q64
28-Pin Windowed Leadless Chip Carrier
Military
Document #: 38-04007 Rev. *E
Package
Type
Package Type
Operating
Range
Page 7 of 13
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CY7C245A
Ordering Information (continued)
Speed (ns)
tSA
tCO
ICC
(mA)
Ordering
Code
Package
Type
18
12
120
CY7C245A-18WMB
W14
24-Lead (300-Mil) Windowed CerDIP
Military
25
15
60
CY7C245A-25PC
P13
24-Lead (300-Mil) Molded DIP
Commercial
25
15
90
CY7C245A-25JC
J64
28-Lead Plastic Leaded Chip Carrier
Commercial
35
20
60
CY7C245A-35WC
W14
24-Lead (300-Mil) Windowed CerDIP
Commercial
120
CY7C245A-35QMB
Q64
28-Pin Windowed Leadless Chip Carrier
Military
Package Type
Operating
Range
f
Package Diagrams
Figure 2. 24-Lead (300-Mil) CerDIP D14
MIL-STD-1835 D- 9 Config.A
51-80031-**
Document #: 38-04007 Rev. *E
Page 8 of 13
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CY7C245A
Package Diagrams (continued)
Figure 3. 28-Lead Plastic Leaded Chip Carrier J64
51-85001-*A
Figure 4. 24-Lead (300-Mil) PDIP P13
51-85013-*B
Document #: 38-04007 Rev. *E
Page 9 of 13
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CY7C245A
Package Diagrams (continued)
Figure 5. 28-Pin Windowed Leadless Chip Carrier Q64
MIL–STD–1835 C–4
51-80102-**
Document #: 38-04007 Rev. *E
Page 10 of 13
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CY7C245A
Package Diagrams (continued)
Figure 6. 24-Lead (300-Mil) SOIC S13
NOTE :
PIN 1 ID
1. JEDEC STD REF MO-119
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT
DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE.
12
1
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE
3. DIMENSIONS IN INCHES
MIN.
MAX.
4. PACKAGE WEIGHT 0.65gms
0.291[7.391]
0.300[7.620]
*
0.394[10.007]
0.419[10.642]
13
24
PART #
S24.3 STANDARD PKG.
SZ24.3 LEAD FREE PKG.
0.026[0.660]
0.032[0.812]
SEATING PLANE
0.597[15.163]
0.615[15.621]
0.092[2.336]
0.105[2.667]
*
0.050[1.270]
TYP.
0.004[0.101]
0.0118[0.299]
0.013[0.330]
0.019[0.482]
Document #: 38-04007 Rev. *E
*
0.004[0.101]
0.015[0.381]
0.050[1.270]
0.0091[0.231]
0.0125[0.317]
51-85025-*C
Page 11 of 13
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CY7C245A
Package Diagrams (continued)
Figure 7. 24-Lead (300-Mil) Windowed CerDIP W14
MIL-STD-1835 D-9 Config. A
51-80086-**
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-04007 Rev. *E
Page 12 of 13
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C245A
Document History Page
Document Title: CY7C245A 2K x 8 Reprogrammable Registered PROM
Document Number: 38-04007
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
113863
3/6/02
DSG
Changed from Spec number: 38-00074 to 38-04007
*A
118894
10/09/02
GBI
Updated ordering information
*B
122248
12/27/02
RBI
Added power-up requirements to Operating Conditions information
*C
130688
10/30/03
LSY
Added CY7C245A-15JI part number
*D
130942
11/10/03
KKV
Minor change: soft copy became corrupted after sign off and before Tech
Pubs. Replaced with correct copy
*E
499542
See ECN
PCI
Updated ordering information
Document #: 38-04007 Rev. *E
Page 13 of 13
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