5-channel 3-LD Driver for Optical Disk Drive CXA2765ER Description The CXA2765ER is a laser driver IC that can drive optical disk lasers capable of writing the three formats of CD, DVD and BD. (Applications: Writable 3-wavelength optical disk drive) Features Supports power save mode with register setting LDOFF LD drivers Three LD drivers for CD, DVD and BD Maximum driving current y OUTBD: Total = 450mA (Each channel: 150mA, 200mA, 150mA, 50mA, 150mA) y OUT1, OUT2: Total = 800mA (Each channel: 180mA, 400mA, 300mA, 150mA, 180mA) Driver current noise: 0.4nA/ Hz (Read) 5-channel control allows generation of a 5-value recording waveform Register setting of high-frequency modulator (HFM) frequency and amplitude y Frequency: 200MHz to 600MHz, 8 bits y Amplitude: 0mAp-p to 100mAp-p, 8 bits IOP monitor using the VIOPMON pin (BD only) VOP monitor using the VIOPMON pin Register setting of HFM spectrum diffusion function (Modulation frequency: 2 bits, diffusion frequency: 2 bits) Package 32-pin VQFN (Plastic) Structure CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E06825C79 CXA2765ER Absolute Maximum Ratings Supply voltage VCC 6 V VCC_LDR 6 V VCC_LDB 10.0 V –65 to +150 °C Storage temperature Tstg Junction temperature Tjmax 150 °C OUTBD pin voltage OUTBD_OFF <7 V (When BD_LD is OFF) (When BD_LD is OFF) Operating Conditions Supply voltage VCC 4.5 to 6 V VCC_LDR 4.5 to 6 V VCC_LDB 5 to 9 V –10 ≤ Topr ≤ 150 – ΔTj °C <5 V Operating temperature Topr OUTBD pin voltage OUTBD_ON -2- (When BD_LD is ON) (When BD_LD is ON) CXA2765ER IR GND1 IIN5 IIN4 IIN3 IIN2 IINR Block Diagram and Pin Configuration 32 31 30 29 28 27 26 Bias VCC 1 OUTEN2 2 Current AMP Current AMP Current AMP Current AMP Current AMP 25 OUTBD To all blocks 24 VCC_LDB Driver xOUTEN2 23 GND_LD 3 IOP 7 OUTEN5 8 xOUTEN5 9 Driver Mode control To all blocks Serial interface and Status register HFM 10 11 12 19 OUT1 13 14 15 16 -3- 18 LDEN 17 SEN SCLK xOUTEN4 20 VCC_LDR SDIO 6 22 VIOPMON 21 OUT2 VD3 OUTEN4 Driver GND2 5 RDIS xOUTEN3 VOPMON xOSCEN 4 OSCEN OUTEN3 CXA2765ER Pin Description Pin No. Symbol 1 VCC 2 OUTEN2 I/O Pin voltage [V] Equivalent circuit — 4.5 to 6.0 — I — IIN2 setting current control signal input (positive logic): LVDS/CMOS Fix to GND when not used. Description Supply voltage for input signal, bias and timing blocks 3 xOUTEN2 I — IIN2 setting current control signal input (negative logic): LVDS Not used in single input mode. Fix to VCC when not used. 4 OUTEN3 I — IIN3 setting current control signal input (positive logic): LVDS/CMOS Fix to GND when not used. — IIN3 setting current control signal input (negative logic): LVDS Not used in single input mode. Fix to VCC when not used. 5 xOUTEN3 I VCC 1 6 7 OUTEN4 xOUTEN4 I I — — 2 3 4 5 6 7 8 9 IIN4 setting current control signal input (positive logic): LVDS/CMOS Fix to GND when not used. 500 IIN4 setting current control signal input (negative logic): LVDS Not used in single input mode. Fix to VCC when not used. 10 11 13 8 9 OUTEN5 xOUTEN5 I I GND2 — IIN5 setting current control signal input (positive logic): LVDS/CMOS Fix to GND when not used. — IIN5 setting current control signal input (negative logic): LVDS Not used in single input mode. Fix to VCC when not used. 10 OSCEN I — HFM control signal input (positive logic): LVDS Not used in single input mode. Fix to GND when not used. 11 xOSCEN I — HFM control signal input (negative logic): LVDS/CMOS Fix to VCC when not used. VCC 1 100k 12 RDIS I — IINR setting current control signal input (negative logic) (with pull-up resistor) 500 12 13 GND2 -4- CXA2765ER Pin No. 13 Symbol GND2 I/O Pin voltage [V] Equivalent circuit — — — Description Timing block GND VCC 1 14 VD3 — 3.3 Voltage decoupling for serial register circuit (Connect to GND through 0.1μF.) 10 14 13 GND2 VCC 1 14 15 SDIO I/O — 15 Serial register data I/O 500 13 GND2 VCC 1 14 16 SCLK I — Serial register clock input (with pull-down resistor) 500 16 50k 13 GND2 VCC 1 17 SEN I — 14 Serial register chip select input (with pull-down resistor) 500 17 18 50k 18 LDEN I — 13 GND2 -5- LDEN control (with pull-down resistor) High: LD enabled Low: Power save CXA2765ER Pin No. Symbol I/O Pin voltage [V] 19 OUT1 O — 20 VCC_LDR — 4.5 to 6.0 Equivalent circuit Description VCC_LDR 20 Laser driving output 1 Supply voltage for output stage 19 21 21 OUT2 O — 23 Laser driving output 2 GND_LD VCC_LDR 20 22 VIOPMON O — 500 Monitor output 22 200 23 GND_LD 23 GND_LD — VCC_LDR — 20 24 Output stage GND VCC_LDB 9k 24 VCC_LDB — 5 to 9 Supply voltage for blue-violet LD 25 20k 25 OUTBD O — 23 Laser driving output (for BD) GND_LD VCC 1 26 IINR I — 500 Current setting R 26 740 31 GND1 -6- CXA2765ER Pin No. Symbol I/O Pin voltage [V] 27 IIN2 I — 28 IIN3 I — Equivalent circuit Description VCC 1 500 Current setting 2 Current setting 3 27 28 29 29 IIN4 I 1k — 31 Current setting 4 GND1 VCC 1 30 IIN5 I — 500 Current setting 5 30 740 31 GND1 31 GND1 — — Input signal block and bias block GND — VCC 1 32 IR — 1.25 Reference current setting resistor connection (Connect to GND through 22kΩ.) 500 500 32 31 GND1 -7- CXA2765ER Electrical Characteristics (VCC = VCC_LDR = 5V, VCC_LDB = 8V, Ta = 25°C) TEST No. Item Symbol Min. Typ. Max. Unit Conditions 1.2 2.1 3.0 mA LDEN = Low or LDM = 00 mA LDEN = High and LDM = 01 or 02 IINR, 2, 3, 4, 5 = 0 RDIS = OSCEN = OUTEN2, 3, 4, 5 = Disable mA RDIS, OSCEN = Enable OUT1 or OUT2 = 40mA, modulation amplitude = 20mAp-p Current consumption excluding the OUT1 and OUT2 pin current. <Current Consumption> 1 Current consumption 1 (LDOFF) 2 Current consumption 2 (CD, DVD_STANDBY) 3 4 Current consumption 3 (CD, DVD_Read) Current consumption 4 (CD, DVD_Write) ICC1 ICC2 ICC3 ICC4 5 21 26 12 31 38 19 41 50 mA RDIS, OUTEN2, OUTEN3 = Enable (IOUTR, IOUT2, IOUT3) IOUTR = 40mA (Duty = 100%) IOUT2 = 240mA (Duty = 25%) IOUT3 = 120mA (Duty = 50%) Current consumption excluding the OUT1 and OUT2 pin current. 240mA 120mA 40mA 5 6 7 Current consumption 5 (BD_STANDBY) Current consumption 6 (BD_Read) Current consumption 7 (BD_Write) ICC5 ICC6 ICC7 7 14 16 10 20 23 13 26 30 mA LDEN = High and LDM = 03 IINR, 2, 3, 4, 5 = 0 RDIS = OSCEN = OUTEN2, 3, 4, 5 = Disable mA RDIS, OSCEN = Enable OUTBD = 40mA, modulation amplitude = 20mAp-p Current consumption excluding the OUTBD pin current. mA RDIS, OUTEN2, OUTEN3 = Enable (IOUTR, IOUT2, IOUT3) IOUTR = 40mA (Duty = 100%) IOUT2 = 60mA (Duty = 25%) IOUT3 = 30mA (Duty = 50%) Current consumption excluding the OUTBD pin current. 60mA 30mA 40mA -8- CXA2765ER TEST No. Item Symbol Min. Typ. Max. Unit Conditions <Serial Interface AC Characteristics> 8 SCLK operating range Fser — — 20 MHz 9 SCLK “H” pulse width Twhsc 13 — — ns 10 SCLK “L” pulse width Twlsc 13 — — ns 11 SEN “L” time Tel 26 — — ns 12 SEN rising edge to the first SCLK falling edge Tersf 15 — — ns 13 SDIO set up time Tcds 15 — — ns 14 SDIO hold time Tcdh 15 — — ns 15 Last SCLK rising edge to SEN falling edge Tsref 1/Fser — — s 16 SCLK cycle time1 Tcc 50 — — ns 17 SDIO output delay Tcdd — — 15 ns 18 SDIO output hold time Tedh — 5.1 — ns Tsref Tersf (HOST) SEN Tcc Twhsc Twlsc (HOST) SCLK Tel 50% 20% 20% 70% 50% Tcds 70% 20% Tcdh (HOST) SDIO Tedh Tcdd (CXA2765ER) SDIO Serial Interface Timing <CMOS Logic Input> 19 Input voltage High level VSH 2.1 — 3.6 V Pins 2, 4, 6, 8, 11, 12 and 15 to 18 20 Input voltage Low level VSL 0 — 0.6 V Pins 2, 4, 6, 8, 11, 12 and 15 to 18 21 Input current 1 (High level) ISH1 51 72 120 μA Pins 16 to 18 (VSH = 3.6V) 22 Input current 1 (Low level) ISL1 –10 — 10 μA Pins 16 to 18 (VSL = 0V) 23 Input current 2 IS2 –10 — 10 μA Pins 2, 4, 6, 8, 11 24 Input current 3 (High level) ISH3 –24 –14 –9 μA Pin 12 (VSH = 3.6V) 25 Input current 3 (Low level) ISL3 –84 –50 –35 μA Pin 12 (VSL = 0V) <CMOS Logic Output> 26 Output voltage High level VOSH 2.8 — 3.3 V Pin 15 (IOH = 3mA) 27 Output voltage Low level VOSL 0 — 0.4 V Pin 15 (IOL = 3mA) 28 VD3 voltage variance VVD3 3.1 — 3.5 V Pin 14 VDR 0 — 3 V Pins 2 to 11 <Differential Input> 29 Input voltage range 30 Differential input amplitude VDTH 0.2 — 1 V Pins 2 to 11 31 Input current ID –10 — 10 μA Pins 2 to 11 -9- CXA2765ER TEST No. Item Symbol Min. Typ. Max. Unit Conditions <LD Driver DC Characteristics> 32 Total maximum driving current (CD, DVD) IMAX 800 — — mA OUT1, 2 = 3.5V 33 IINR CH maximum driving current (CD, DVD) IMAXR 180 — — mA OUT1, 2 = 3.5V 34 IIN2 CH maximum driving current (CD, DVD) IMAX2 400 — — mA OUT1, 2 = 3.5V 35 IIN3 CH maximum driving current (CD, DVD) IMAX3 300 — — mA OUT1, 2 = 3.5V 36 IIN4 CH maximum driving current (CD, DVD) IMAX4 150 — — mA OUT1, 2 = 3.5V 37 IIN5 CH maximum driving current (CD, DVD) IMAX5 180 — — mA OUT1, 2 = 3.5V 38 Total minimum driving current (CD, DVD) IMIN — — 10 mA OUT1, 2 = 3.5V 39 IINR CH minimum driving current (CD, DVD) IMINR — — 4.3 mA OUT1, 2 = 3.5V 40 IIN2 CH minimum driving current (CD, DVD) IMIN2 — — 5.1 mA OUT1, 2 = 3.5V 41 IIN3 CH minimum driving current (CD, DVD) IMIN3 — — 4.0 mA OUT1, 2 = 3.5V 42 IIN4 CH minimum driving current (CD, DVD) IMIN4 — — 1.9 mA OUT1, 2 = 3.5V 43 IIN5 CH minimum driving current (CD, DVD) IMIN5 — — 3.6 mA OUT1, 2 = 3.5V 44 Total maximum driving current (BD) IMAX_BD 450 — — mA OUTBD = 1.5V 45 IINR CH maximum driving current (BD) IMAXR_BD 150 — — mA OUTBD = 1.5V 46 IIN2 CH maximum driving current (BD) IMAX2_BD 200 — — mA OUTBD = 1.5V 47 IIN3 CH maximum driving current (BD) IMAX3_BD 150 — — mA OUTBD = 1.5V 48 IIN4 CH maximum driving current (BD) IMAX4_BD 50 — — mA OUTBD = 1.5V 49 IIN5 CH maximum driving current (BD) IMAX5_BD 150 — — mA OUTBD = 1.5V 50 Total minimum driving current (BD) IMIN_BD –1.1 — 6.0 mA OUTBD = 1.5V 51 IINR CH minimum driving current (BD) IMINR_BD 0 — 2.3 mA OUTBD = 1.5V, measured value – (IOP when RDIS = OUTENx = Disable) 52 IIN2 CH minimum driving current (BD) IMIN2_BD 0 — 2.7 mA OUTBD = 1.5V, measured value – (IOP when RDIS = OUTENx = Disable) 53 IIN3 CH minimum driving current (BD) IMIN3_BD 0 — 2.0 mA OUTBD = 1.5V, measured value – (IOP when RDIS = OUTENx = Disable) 54 IIN4 CH minimum driving current (BD) IMIN4_BD 0 — 0.7 mA OUTBD = 1.5V, measured value – (IOP when RDIS = OUTENx = Disable) 55 IIN5 CH minimum driving current (BD) IMIN5_BD 0 — 3.0 mA OUTBD = 1.5V, measured value – (IOP when RDIS = OUTENx = Disable) 56 Read noise 1 (CD, DVD) RNS1 — 0.31 — nA/ Hz OUT1, 2 = 40mA, OSCEN = Disable 16.5MHz noise, HFMP = 32d - 10 - CXA2765ER TEST No. Item 57 Read noise 2 (CD, DVD) 58 Write noise 1 (CD, DVD) Symbol RNS2 WNS1 Min. Typ. Max. Unit — 0.42 — nA/ Hz OUT1, 2 = 40mA, OSCEN = Enable (20mAp-p, 350MHz) 16.5MHz noise, HFMP = 32d nA/ Hz RDIS, OUTEN2 = Enable IOUTR = 40mA (Duty = 100%) IOUT2 = 40mA (Duty = 50%) 16.5MHz noise — 2.4 — Conditions 59 Write noise 2 (CD, DVD) WNS2 — 2.8 — nA/ Hz OUTEN5, OUTEN2 = Enable IOUT5 = 40mA (Duty = 100%) IOUT2 = 40mA (Duty = 50%) 16.5MHz noise 60 Read noise 1 (BD) RNS1_BD — 0.46 — nA/ Hz OUTBD = 40mA, OSCEN = Disable 16.5MHz noise, HFMP = 79d 61 Read noise 2 (BD) RNS2_BD — 0.47 — nA/ Hz OUTBD = 40mA, OSCEN = Enable (20mAp-p, 350MHz) 16.5MHz noise, HFMP = 79d nA/ Hz RDIS, OUTEN2 = Enable IOUTR = 40mA (Duty = 100%) IOUT2 = 40mA (Duty = 50%) 16.5MHz noise OUTEN5, OUTEN2 = Enable IOUT5 = 40mA (Duty = 100%) IOUT2 = 40mA (Duty = 50%) 16.5MHz noise 62 63 Write noise 1 (BD) Write noise 2 (BD) WNS1_BD — 1.8 — WNS2_BD — 2.4 — nA/ Hz <LD Driver AC Characteristics> 64 Rise time (CD, DVD resistance load) Tr — 0.5 — ns 65 Fall time (CD, DVD resistance load) Tf — 0.5 — ns 66 Overshoot (CD, DVD resistance load) OVS+ — 10 — % 67 Propagation delay 1 (CD, DVD resistance load) DELAY1 — 5.6 — ns OUT1/2 output ON response time from OUTEN2/3/4/5 differential input 68 Propagation delay 2 (CD, DVD resistance load) DELAY2 — 5.3 — ns OUT1/2 output OFF response time from OUTEN2/3/4/5 differential input 69 Rise time (BD resistance load) Tr_BD — 0.5 — ns 70 Fall time (BD resistance load) Tf_BD — 0.5 — ns 71 Overshoot (BD resistance load) OVS+_BD — 10 — % 72 Propagation delay 1 (BD resistance load) DELAY1_BD — 4.6 — ns OUTBD output ON response time from OUTEN2/3/4/5 differential input 73 Propagation delay 2 (BD resistance load) DELAY2_BD — 4 — ns OUTBD output OFF response time from OUTEN2/3/4/5 differential input - 11 - 50mA to 100mA pulse, settling 10% to 90% Load = 5Ω//10pF 50mA to 100mA pulse, settling 10% to 90% Load = 10Ω//10pF CXA2765ER TEST No. Item Symbol Min. Typ. Max. Unit ZINR 518 740 962 Ω Conditions <I/O Characteristics> 74 Input resistance R, 5 IINR/5 input resistance 75 Input resistance 2, 3, 4 ZINW 700 1000 1300 Ω IIN2/3/4 input resistance 76 Input current R, 2, 3, 4, 5 IIN 0 — 1 mA IINR/2/3/4/5 input current 77 I/O band R FBANDR — 370 — kHz IINR = 200μA input 78 I/O band 2, 3, 4, 5 FBANDW — 2.35 — MHz IIN2/3/4/5 = 400μA input 79 I/O gain R (CD, DVD) GAINR 235 262 289 A/A Gain from IINR input to OUT1/2 output (IINR = 100μA to 200μA, OUT1/2 = 2.5V) 80 I/O gain 5 (CD, DVD) GAIN5 235 262 289 A/A Gain from IIN5 input to OUT1/2 output (IIN5 = 100μA to 200μA, OUT1/2 = 2.5V) 81 I/O gain 2 (CD, DVD) GAIN2 504 560 616 A/A Gain from IIN2 input to OUT1/2 output (IINR = 200μA, IIN2 = 100μA to 200μA, OUT1/2 = 2.5V) 82 I/O gain 3 (CD, DVD) GAIN3 405 450 495 A/A Gain from IIN3 input to OUT1/2 output (IINR = 200μA, IIN3 = 100μA to 200μA, OUT1/2 = 2.5V) 83 I/O gain 4 (CD, DVD) GAIN4 202 225 248 A/A Gain from IIN4 input to OUT1/2 output (IINR = 200μA, IIN4 = 100μA to 200μA, OUT1/2 = 2.5V) 84 I/O linearity 2, 3, 4 (CD, DVD) LINE –3 — 3 % Fix IINR to 200μA, and measure the offset at IIN2/3/4 = 600μA in reference to IIN2/3/4 = 100μA to 200μA, respectively. OUT1/2 = 2.5V 85 I/O gain ratio 1 (CD, DVD) GaRa1 0.9 1 1.1 — IIN5/IINR gain ratio 86 I/O gain ratio 2 (CD, DVD) GaRa2 0.72 0.8 0.88 — IIN3/IIN2 gain ratio 87 I/O gain ratio 3 (CD, DVD) GaRa3 0.36 0.4 0.44 — IIN4/IIN2 gain ratio 88 I/O gain R (BD) GAINR_BD 180 200 221 A/A Gain from IINR input to OUTBD output (IINR = 100μA to 200μA, OUTBD = 2.5V) 89 I/O gain 5 (BD) GAIN5_BD 180 200 221 A/A Gain from IIN5 input to OUTBD output (IIN5 = 100μA to 200μA, OUTBD = 2.5V) 90 I/O gain 2 (BD) GAIN2_BD 238 265 291 A/A Gain from IIN2 input to OUTBD output (IINR = 200μA, IIN2 = 100μA to 200μA, OUTBD = 2.5V) 91 I/O gain 3 (BD) GAIN3_BD 180 200 220 A/A Gain from IIN3 input to OUTBD output (IINR = 200μA, IIN3 = 100μA to 200μA, OUTBD = 2.5V) 92 I/O gain 4 (BD) GAIN4_BD 59 66 73 A/A Gain from IIN4 input to OUTBD output (IINR = 200μA, IIN4 = 100μA to 200μA, OUTBD = 2.5V) % Fix IINR to 200μA, and measure the offset at IIN2/3/4 = 600μA in reference to IIN2/3/4 = 100μA to 200μA, respectively. OUTBD = 2.5V 93 I/O linearity 2, 3, 4 (BD) LINE_BD –3 — 94 I/O gain ratio 1 (BD) GaRa1_BD 0.91 1 1.12 — IIN5/IINR gain ratio 95 I/O gain ratio 2 (BD) GaRa2_BD 0.67 0.75 0.83 — IIN3/IIN2 gain ratio 96 I/O gain ratio 3 (BD) GaRa3_BD 0.22 0.25 0.28 — IIN4/IIN2 gain ratio - 12 - 3 CXA2765ER TEST No. Item Symbol Min. Typ. Max. Unit Conditions <High-frequency Modulation (HFM)> 97 Frequency variable range VARIF 200 — 600 MHz HFMF = 0 to 255dec 98 Frequency variance FREQ –10 — 10 % HFMF = 80dec (@350MHz) 99 Frequency temperature coefficient TFREQ — –0.0035 — %/°C HFMF = 80dec (@350MHz) 100 Amplitude setting range (CD, DVD) VARIA 0 — 100 mAp-p HFMF = 80dec (@350MHz), HFMP = 0 to 255dec Load = 5Ω 101 Amplitude setting range (BD) VARIA_BD 0 — 70 mAp-p HFMF = 80dec (@350MHz), HFMP = 31 to 255dec, LDCR2 = 00 Load = 10Ω 102 OSCEN response time – ON OSCRES1 — — 11 ns OSCEN Disable → Enable 103 OSCEN response time – OFF OSCRES2 — — 11 ns OSCEN Enable → Disable <LDOFF> 104 LDOFF response time LDOFFRES — — 10 ns Time for the output current to fall to 10% when LDEN is changed from High to Low. 105 Power supply monitor circuit – LDOFF EMON 3.1 3.5 — V VCC and Vcc_LDR voltages at which LDOFF results. 106 Power supply monitor circuit – LDON EMOFF — 3.75 4.15 V VCC and Vcc_LDR voltages at which LDOFF is canceled. <VIMON> 107 VOP monitor upper limit (CD, DVD) VmoMax 4.90 5 5.05 V VIMON = 001 VIMON voltage when 5V is applied to OUT1/2. 108 VOP monitor lower limit (CD, DVD) VmoMin 0 0.7 1.1 V VIMON = 001 VIMON voltage when 0V is applied to OUT1/2. 109 VOP monitor DC accuracy (CD, DVD) VmoDC 3.9 4 4.1 V VIMON = 001 VIMON voltage when 4V is applied to OUT1/2. 110 VOP monitor pulse accuracy (CD, DVD) VmoPls 3.8 4 4.1 V VIMON output voltage when a 3V to 4V, duty 50%, 6ns pulse is input to OUT1/2. (Peak hold accuracy) 111 VOP monitor hold capability (CD, DVD) VmoHd –72 –53.5 –25 mV/μs 112 VOP monitor upper limit (BD) VmoMax_BD 2.4 2.5 2.6 V VIMON = 001 VIMON voltage when 5V is applied to OUTBD. 113 VOP monitor lower limit (BD) VmoMin_BD 0 — 0.15 V VIMON = 001 VIMON voltage when 0V is applied to OUTBD. 114 VOP monitor DC accuracy (BD) VmoDC_BD 0.4 0.5 0.6 V VIMON = 001 VIMON voltage when 1V is applied to OUTBD. 115 VOP monitor pulse accuracy (BD) VmoPls_BD 0.4 0.5 0.7 V VIMON output voltage when a 1V to 2V, duty 50%, 6ns pulse is input to OUTBD. (Bottom hold accuracy) 116 VOP monitor hold capability (BD) VmoHd_BD 23 54 73 mV/μs 117 Temperature monitor output voltage TmoVout — 1.34 — V 118 Temperature monitor temperature coefficient Tmotemp — 3.5 — mV/°C 119 IOP monitor current efficiency (BD only) Iratio_BD 0.914 1 1.053 % - 13 - VIMON = 001 VIMON = 001 VIMON = 010, Tj = 70°C VIMON = 010 VIMON = 100, IMON/IOUTBD current ratio when OUTBD = 40mA. VIOPMON = 2V CXA2765ER Example of Representative Characteristics High-frequency Modulation Characteristics Control characteristics of HFMF and modulation frequency HFMP = 80d LDCR = 255d 700 600 Modulation frequency [MHz] 500 400 300 200 100 0 0 32 64 96 128 160 192 Serial address 79h HFMF [dec] - 14 - 224 256 CXA2765ER 28 27 26 IIN3 IIN2 IINR 0.1µ 29 IIN4 0.1µ 30 IIN5 0.1µ 31 GND1 0.1µ 32 IR 0.1µ 22k Electrical Characteristics Measurement Circuit 0.1µ OUTBD 25 1 VCC 10 2 OUTEN2 VCC_LDB 24 3 xOUTEN2 GND_LD 23 100 0.1µ VIOPMON 22 4 OUTEN3 100 5 xOUTEN3 OUT2 21 CXA2765ER 5Ω VCC_LDR 20 6 OUTEN4 0.1µ 100 7 xOUTEN4 OUT1 19 8 OUTEN5 LDEN 18 5 LDEN 100 xOSCEN RDIS GND2 VD3 SDIO SCLK SEN 17 OSCEN 9 xOUTEN5 10 11 12 13 14 15 16 SCLK 0.1µ 50 SDIO 100 Serial data VCC 22µ VCC_LDR 1µ GND 22µ 1µ GND VCC_LDB 22µ 1µ GND - 15 - SEN (Serial data) CXA2765ER Serial Interface The CXA2765ER performs IC control via the serial interface. The serial interface specifications are shown below. Serial Address Bit Definition Bit A7 A6 to 0 Bit definition Read/write select bit 0: Serial interface write mode 1: Serial interface read mode Register address select bit Transmission and reception are performed in 16-bit units consisting of 8 address bits and 8 data bits. Both the address and data are MSB first. In the address, the A[7] bit switches between read and write mode, and the A[6:0] bits are the register address. The read/write timing charts are shown below. Timing Chart in Write Mode High SEN (Pin 17) Low 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 High SCLK (Pin 16) Low MSB SDIO (Pin 15) LSB MSB LSB A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Address High Low Data The data written in the register is reflected to the various IC internal functions at the rising edge of the 16th (last) SCLK signal. Timing Chart in Read Mode High SEN (Pin 17) Low 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 High SCLK (Pin 16) Low MSB SDIO (Pin 15) LSB A7 A6 A5 A4 A3 A2 A1 A0 MSB LSB High D7 D6 D5 D4 D3 D2 D1 D0 Low Address Data (Output data from the CXA2765ER) MSB Note) Depending on the flexible PC board condition, when the SDIO line and the SEN line use adjacent wiring, SDIO signal fluctuations may be transmitted to the SEN line and make the control status unstable, with the result that correct data cannot be read and written during serial transfer. - 16 - CXA2765ER Address Map (SDIO/SEN/SCLK) Address Name Definition 78 MODELDD LDD status (LDOFF/CD/DVD/BD) Transfer skew check, input logic selection, and power supply monitor circuit control 79 HFMP Modulation amplitude setting (CD/DVD: 0 to 100mAp-p, BD: 0 to 70mAp-p) 7A HFMF Modulation frequency setting (200MHz to 600MHz) 7B EMISEL HFM spectrum diffusion setting, monitor control 7C LDCR Output waveform adjustment 7D CHSEL Channel control method selection Bit Map Serial Address 78h Bit Symbol 7 — 6 EMVCCDIS Power supply monitor circuit disable 0: Enable 1: Disable 5 SEL_CH5 CH5 input logic level selection 0: Differential input 1: Single input 4 SEL_CH2-4 CH2 to CH4 input logic level selection 0: Differential input 1: Single input 3 SEL_OSC OSC CH input logic level selection 0: Differential input 1: Single input 2 SKEW Skew check function 0: Normal operation 1: Transfer skew check mode LDM LDD output selection 00: LDOFF (Power save) 01: LD1 10: LD2 11: BD 1-0 Bit definition Don’t care - 17 - CXA2765ER Serial Address 79h Bit definition Bit 7-0 Symbol HFMP HFM amplitude setting CD/DVD BD Resolution = 0.4mAp-p 0d: 0mAp-p to 128d: 50mAp-p to 255d: 100mAp-p Resolution = 0.3mAp-p 31d: 0mAp-p to 128d: 30mAp-p to 255d: 70mAp-p Serial Address 7Ah Bit 7-0 Symbol HFMF Bit definition HFM frequency setting 0d: 200MHz to 255d: 600MHz Serial Address 7Bh Bit Symbol Bit definition 7-5 VIMON V/I monitor output selection 000: OFF (monitor circuit power save) 001: VOP monitor output in accordance with LDM 010: Temperature sensor output 011: EMI countermeasure circuit period measurement mode 100: IOP output (BD_Read + MOD only) 101: MODFDAC measurement mode 110: MODADAC measurement mode 111: EMI countermeasure circuit spread measurement mode 4 EMIEN HFM spectrum diffusion circuit enable 0: Disable 1: Enable EMIP HFM spectrum diffusion – modulation frequency 00: 0.01% (350MHz conversion = 35kHz) 01: 0.02% (350MHz conversion = 70kHz) 10: 0.04% (350MHz conversion = 140kHz) 11: 0.08% (350MHz conversion = 280kHz) EMIS HFM spectrum diffusion – diffusion frequency 00: 0.2% (350MHz conversion = 0.7MHz) 01: 0.4% (350MHz conversion = 1.4MHz) 10: 0.8% (350MHz conversion = 2.8MHz) 11: 1.6% (350MHz conversion = 5.6MHz) 3-2 1-0 - 18 - CXA2765ER Serial Address 7Ch Bit Symbol Bit definition (BD) Bit definition (DVD/CD) 7 LDCR5 LDD buffer current 0: Small current 1: Large current (fast waveform) 6 LDCR4 LDD buffer signal current ratio 0: 1:4 1: 2:4 (fast waveform) — 5 LDCR3 LDD buffer bias current 0: Small bias current 1: Large bias current (fast waveform) — LDCR2 Snubber 2 (both Tr and Tf) 00: Slow waveform 01: ↓ 10: ↓ 11: Fast waveform — LDCR1 Snubber 1 (Tr only) 000: Slow waveform 001: ↓ 010: ↓ 011: ↓ 100: ↓ 101: ↓ 110: ↓ 111: Fast waveform 4-3 2-0 Ringing adjustment (Tr only) 0: Small 1: Large (fast waveform) Overshoot adjustment (Tr only) 000: Small 001: ↓ 010: ↓ 011: ↓ 100: ↓ 101: ↓ 110: ↓ 111: Large (fast waveform) Serial Address 7Dh Bit Symbol 7 — Bit definition — 6 CH5EN Channel 5 register control 0: OFF 1: ON 5 CH4EN Channel 4 register control 0: OFF 1: ON 4 CH3EN Channel 3 register control 0: OFF 1: ON 3 CH2EN Channel 2 register control 0: OFF 1: ON 2 REN Read channel register control 0: OFF 1: ON 1 OSCEN Channel OSC register control 0: OFF 1: ON 0 CH_CONT Channel control method selection 0: Normal (pin control) 1: Register control mode Note) When data is not written to address 78h to 7Dh after power-on, the registers at addresses 78h to 7Dh are undetermined. - 19 - CXA2765ER Description of Operation 1. Power-on and power-off sequences The following sequences are recommended to protect the laser when turning the power on and off. Power-on sequence VCC 5V power supply ON VCC_LDR 5V power supply ON (These power supplies may be turned on simultaneously or in any order.) (LDEN = Low) VCC_LDB 8V power supply ON (LDEN = Low) Register settings (LDEN = Low) LDEN = High Turn on the VCC_LDB 8V power supply after the VCC 5V and VCC_LDR 5V power supplies have risen to 1V or more. The IC control status is unstable when the VCC 5V and VCC_LDR 5V power supplies are less than 1V, so if the VCC_LDB 8V power supply rises to 7V or more in this condition, current of approximately 10mA may flow to the laser. Power-off sequence Select "00" with register LDM[1:0] or set LDEN = Low. VCC_LDB 8V power supply OFF VCC 5V power supply OFF VCC_LDR 5V power supply OFF When LDEN is Low, current does not flow to the laser for any power-off sequence, but the above sequence is recommended. Note) When the power is forcibly turned off during laser emission, current of the set level or more may flow to the laser. The conditions for current of the set level or more flowing to the laser are VCC < 3/5 × VCC_LDR and VCC_LDR ≥ 2V (shaded area in the figure below). To avoid problems, VCC_LDR should be turned off first, or VCC and VCC_LDR should be turned off at approximately the same time. In addition, current of the set level or more does not flow to the laser regardless of the VCC_LDB 8V power-off order. VCC_LDR VCC → Supply voltage [V] 5 VCC < 3/5 × VCC_LDR and VCC_LDR ≥ 2V 3 2 0 → Time Fig. 1. VCC and VCC_LDR Power-off - 20 - CXA2765ER 2. LD driving current setting The currents controlled by the current setting pins IINR, IIN2, IIN3, IIN4 and IIN5 are output from the OUT1, OUT2 and OUTBD pins. The output driving currents from the OUT pins can be set independently for IINR, IIN2, IIN3, IIN4 and IIN5 by RDIS, OUTEN and xOUTEN. Note that output switching for OUT1 (Pin 19), OUT2 (Pin 21) and OUTBD (Pin 25) is performed by serial address 78h bit[1:0] LDM. 3. Modulator circuit Output modulation is turned on and off by the OSCEN and xOSCEN pins. The modulation frequency can be varied by serial address 7Ah bit[7:0] HFMF, and the modulation amplitude can be varied by serial address 79h bit[7:0] HFMP. Modulation Amplitude Setting BD mode Modulation amplitude [mAp-p] Modulation amplitude [mAp-p] CD/DVD mode 0 0 HFMP DAC setting [dec] 31 HFMP DAC setting [dec] Modulation Level Adjustment BD mode CD/DVD mode Imod Iread Iread IINR input current [mA] 1/2Imod IINR input current [mA] 1/2Imod Iread < 1/2Imod Modulation level [mAp-p] Modulation level [mAp-p] Imod Iread < 1/2Imod Iread > 1/2Imod Iread > 1/2Imod 4. IR pin The IR pin external resistor should be fixed to 22kΩ. The IR pin aims to reduce variance in the modulation frequency that depends on the internal resistance, and is designed based on fixed resistance of 22kΩ. - 21 - CXA2765ER Description of Functions Logic Tables Output control (Differential input) (X: Don't care) LDEN RDIS OUTEN2 OUTEN3 OUTEN4 OUTEN5 XOSCEN L X X X X X X H H L L L L H OUT output (OUT1/OUT2 /OUTBD) PS OFF Power save LD OFF H L L L L L H H L L L L L L H L L L L L H H L L L L H H IINR IINR (Modulation IINR ON) IINR + IIN5 H L H L L H H H L H H L H H H L H L H H H H L H H H H H IINR + IIN5 + IINR + IIN5 + IINR + IIN5 + IINR + IIN5 + IIN2 + IIN3 + IIN2 IIN2 + IIN3 IIN2 + IIN4 IIN4 IIN3 IIN3 IIN4 IIN4 IIN2 OUT output IIN5 IINR 0mA Output control (Single input) (X: Don't care) LDEN RDIS OUTEN2 OUTEN3 OUTEN4 OUTEN5 XOSCEN L X X X X X X H H L L L L H OUT output (OUT1/OUT2 /OUTBD) PS OFF Power save LD OFF H L L L L X H H L L L L X L H L L L L X H IINR IINR (Modulation IINR ON) H H L L L H H H H H L L H H H H H H L H H IIN5 IIN5 + IIN2 H H H L H H H H H H H H H H IIN5 + IIN2 + IIN5 + IIN2 + IIN5 + IIN2 + IIN3 IIN4 IIN3 + IIN4 IIN3 IIN3 IIN4 IIN4 IIN2 OUT output IIN5 IINR 0mA Note) When serial address 78h bit[5] SEL_CH5 is set High (single input), the IINR channel and the IIN5 channel cannot be added to prevent glitches. - 22 - CXA2765ER Modulation control DVD/CD mode (X: Don't care) LDEN RDIS OUTEN2 OUTEN3 OUTEN4 OUTEN5 XOSCEN L X X X X X X Modulation output (OUT1/OUT2) PS H L H H H H H H L L L L L L H H H L L L L H H L H L L L H H L L H L L H H L L L H L BD mode (X: Don't care) L X X X X X X Modulation output (OUTBD) PS H H H H L L L Modulation Modulation Modulation Modulation Modulation Modulation Modulation Modulation ON ON ON ON OFF ON ON ON (IIN5) (IINR, IIN2) (IIN2, IIN3) (IIN4) (IINR) (IIN2) (IIN3) Note) 1. Modulation control is independent of the data timing signal. 2. Modulation is not output from the OUT pin without the input current to IINR. LDEN RDIS OUTEN2 OUTEN3 OUTEN4 OUTEN5 XOSCEN H L H L L L L H X X X X X H H L X X X X L Modulation Modulation OFF ON (IINR) Note) Modulation is not output from the OUT pin without the input current to IINR. - 23 - CXA2765ER Power Supply Monitor Circuit The CXA2765ER has a built-in power supply monitor circuit to ensure safe laser emission. This function monitors the two supply voltages VCC (Pin 1) and VCC_LDR (Pin 20). See the “Electrical Characteristics” table for the respective threshold values. When this function detects that either of these power supplies has dropped, it outputs the LDOFF (power save) signal and turns off the laser driving current. The power supply monitor circuit function can be enabled or disabled by serial address 78h bit[6] EMVCCDIS. VCC VCC_LDR (Pin 1) (Pin 20) LDOFF EMVCCDIS (Register) Power Supply Monitor Circuit Block Diagram VOP Monitor Function The VOP voltage at the laser end can be monitored. When serial address 7Bh bit[7:5] are set to “001”, the peak hold voltage (CD/DVD) or the bottom hold voltage (BD) is output from VIOPMON (Pin 22). LDEN1 DVD Driver OUT1 (Pin 19) VIOPMON (Register) LDEN2 VIOPMON (Pin 22) CD Driver OUT2 (Pin 21) Peak Hold VCC_LDB (Pin 24) BD Driver BDEN OUTBD (Pin 25) 10k Bottom Hold 10k VOP Monitor Block Diagram - 24 - CXA2765ER Skew Check Function Normal mode or skew check mode can be selected by serial address 78h bit[2] SKEW. The skew check mode is the function that detects the timing offset of recording signals input to the CXA2765ER that occurs between channels due to the effects of the flexible PC board and other factors. It can detect the timing offset between a total of 5 channels (4 write channels and one OSC channel). The AND of the recording signals for each channel input to the CXA2765ER is output from the IIN2 channel path. The AND is output, so when the timing is offset between channels, the recording waveform pulse width narrows and the output recording power drops. Adjust the timing of the recording signal for each channel to maximize the output recording power. LDD input (before adjustment) Write strategy generator (WSG) output OUTEN2 Transfer via Flexible PC Board OUTEN3 LDD input (after adjustment) OUTEN2 OUTEN2 OUTEN3 OUTEN3 LDD output IIN2 IIN3 IIN4 IIN5 HFM LDD output OUTEN2 2 In Skew Mode to Drive xOUTEN2 3 OUTEN3 4 xOUTEN3 5 Disable OUTEN4 6 xOUTEN4 7 Disable OUTEN5 8 xOUTEN5 9 Disable OSCEN 10 xOSCEN 11 Disable - 25 - CXA2765ER HFM Spectrum Diffusion Function HFM spectrum The HFM spectrum diffusion function is enabled by selecting “1” at Bit4 EMIEN of serial address 7Bh, and the HFM frequency is diffused as shown in the figure below. Frequency Modulation frequency + diffusion frequency (HFMF) (EMIS) HFM Spectrum Diffusion Frequency Measurement When serial address 7Bh bit[7:5] are set to “011” or “111”, the HFM spectrum diffusion modulation frequency (EMIP) and diffusion frequency (EMIS) can be measured at VIOPMON (Pin 22). Modulation frequency EMIS HFMF setting EMIP Time - 26 - CXA2765ER Channel control Pin control or bit[6:1] register control can be selected by serial address 7Dh bit[0] CH_CONT. CH_CONT (reg) SEL Low: A High: B A OSCEN (Pin 10) OSCEN (reg) SEL OSC_EN B A OUT_EN2 SEL B A OUT_EN3 SEL B A OUT_EN4 SEL B A SEL OUT_EN5 B OUTEN2 (Pin 2) CH2EN (reg) OUTEN3 (Pin 4) CH3EN (reg) OUTEN4 (Pin 6) CH4EN (reg) OUTEN5 (Pin 8) CH5EN (reg) SEL_CH5 (reg) A SEL A B SEL RDIS_EN B RDIS (Pin 12) REN (reg) Read channel and cool channel glitch countermeasures in single input mode When serial address 78h bit[5] SEL_CH5 is set High (single input), a timing signal which has had glitch countermeasures applied by the read channel and cool channel is output on OUT_EN5. Therefore, the read channel and cool channel cannot be added in single input mode. When set Low (differential input (LVDS)), the cool channel can be added to the read channel to generate the write power. - 27 - CXA2765ER Changes in the output waveform characteristics by the register settings The waveform characteristics (rise time (tr), fall time (tf), overshoot (OVS+), undershoot (OVS–)) of the output LD driving current change greatly according to the LDD, the LD and the LD load (in the mounted condition) connected to each output pin OUT1 (Pin 19), OUT2 (Pin 21) and OUTBD (Pin 25). The CXA2765ER can adjust the LDD output waveform characteristics by the register settings. These controls are performed by Serial Address 7Ch. However, in BD mode the current consumption of the 5V block increases as the LDCR5, LDCR4 and LDCR3 settings are increased (faster waveform). In addition, take care in LDCR2 setting because it affects high-frequency modulation amplitude. Modulation amplitude will be larger as LDCR2 setting changes from 00 to 11. In DVD/CD mode the current consumption of the 5 V block increases as the LDCR5 and LDCR1 settings are increased (faster waveform). <BD waveform adjustment> LDCR1 = 111 LDCR3 = 1 LDCR2 = 11 LDCR3 = 0 LDCR1 = 000 LDCR2 = 00 LDCR2 = 00 LDCR4 = 1 LDCR5 = 1 LDCR2 = 11 LDCR4 = 0 LDCR5 = 0 <DVD/CD waveform adjustment> LDCR1 = 111 LDCR5 = 1 LDCR5 = 0 LDCR1 = 000 - 28 - CXA2765ER Notes on Operation Make the wiring as short as possible between the output OUT pins (Pins 19, 21 and 25) and the laser diode, and between the VCC_LDR pin and the external decoupling capacitor. As the wiring length increases, the effects of the wiring inductance cause the output waveform overshoot and undershoot to increase. The VCC_LDR pin’s external decoupling capacitance ground can be grounded to the GND grounding the load from the OUT pin. This reverses the phase of the drive waveform at the OUT and VCC_LDR and moves in the direction that suppresses overshoots and undershoots. Place the external resistor connected to the IR pin as close to the IC as possible. As the wiring length between the IR pin and the external resistor increases, external disturbance easily enters the reference current generated by the IR pin, and may cause noise to worsen or other problems. In addition, when capacitance is applied to the IR pin, the phase margin with the internal circuits is reduced and oscillation easily occurs. Temperature guarantee Thermal resistance (θj-a) when the CXA2765ER is mounted on PWB varies according to the set (PWB) and because it is difficult to predict along with the tendency for higher power for power consumption (PO), the following points should be considered when using. Use in a range that the junction temperature (Tj) does not exceed 150°C (Tjmax). Also, Use with the thermal resistance (θj-a) of the PWB mounting lowered so that power consumption (PO) is below allowable power dissipation (PD). It is possible to lower the thermal resistance (θj-a) when mounted on PWB by widening the GND region with the set PWB or releasing heat to the set chassis, etc. Find the thermal resistance (θj-a) when mounted on PWB and power consumption (PO) using the following method. PO = (ICC × VCC) – (IOP × VOP): DVD/CD mode PO = (ICC × VCC) + (IOP × VOP): BD mode ICC: IC current consumption when operating (including IOP in DVD/CD mode) IOP: Output drive current flowed from the OUT pin to the laser diode VOP: Operating voltage of the laser diode Thermal resistance (θj-a) when mounted on PWB The thermal resistance (θc-a) is easily obtained by measuring the package surface temperature using a thermo couple or a radiation thermometer. In order to improve the precision of measurement, it is desired to calculate by the following formula. ΔPackage surface temperature when IOP is variable/ΔPO Assume the thermal resistance (θj-c) to be approximately 2°C/W. y Thermal resistance (θj-a) is θj-a = θj-c + θc-a y Allowable power dissipation (PD) ≥ PO [W] PD = (150°C – Ambient temperature)/θj-a - 29 - CXA2765ER Application Circuit 1 28 27 26 IIN3 IIN2 IINR 0.1µ 29 IIN4 0.1µ 30 IIN5 0.1µ 31 GND1 0.1µ 32 IR 22k 0.1µ Current DAC 0.1µ LD for BD OUTBD 25 1 VCC 2 OUTEN2 VCC_LDB 24 3 xOUTEN2 GND_LD 23 0.1µ 4 OUTEN3 Timing control logic (LVDS or CMOS) VIOPMON 22 5 xOUTEN3 OUT2 21 CXA2765ER LD for CD 6 OUTEN4 VCC_LDR 20 0.1µ 7 xOUTEN4 OUT1 19 LD for DVD 8 OUTEN5 LDEN 18 xOSCEN RDIS GND2 VD3 SDIO SCLK SEN 17 OSCEN 9 xOUTEN5 Mode control logic (CMOS) 10 11 12 13 14 15 16 0.1µ Serial interface Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 30 - CXA2765ER Application Circuit 2 28 27 26 IIN3 IIN2 IINR 0.1µ 29 IIN4 0.1µ 30 IIN5 0.1µ 31 GND1 0.1µ 32 IR 22k 0.1µ Current DAC 0.1µ LD for BD OUTBD 25 1 VCC 2 OUTEN2 VCC_LDB 24 3 xOUTEN2 GND_LD 23 0.1µ 4 OUTEN3 Timing control logic (LVDS or CMOS) VIOPMON 22 5 xOUTEN3 OUT2 21 CXA2765ER LD for CD 6 OUTEN4 VCC_LDR 20 7 xOUTEN4 0.1µ OUT1 19 LD for DVD 8 OUTEN5 Mode control logic (CMOS) xOSCEN RDIS GND2 VD3 SDIO SCLK SEN 17 OSCEN 9 xOUTEN5 LDEN 18 10 11 12 13 14 15 16 0.1µ Serial interface Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 31 - CXA2765ER Package Outline (Unit: mm) LEAD PLATING SPECIFICATIONS ITEM - 32 - SPEC. LEAD MATERIAL COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18μm Sony Corporation