Allegro A8437 Mobile phone xenon photoflash capacitor charger Datasheet

A8437
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
Features and Benefits
Description
▪ Low quiescent current draw (0.1 μA in shutdown mode)
▪ Primary-side output voltage sensing; no resistor divider
required
▪ User-adjustable current limit from 0.4 to 1.2 A
▪ 1.1 V logic (VHI(min)) compatibility
▪ Integrated IGBT driver with separate sink and source (CG
package) or common sink/source (EJ package)
▪ Flash dual trigger with interlock for increased noise
immunity
▪ Optimized for mobile phone, 1-cell Li+ battery applications
▪ No primary-side Schottky diode needed
▪ Zero-voltage switching for lower loss
▪ >75% efficiency
▪ Optional regulation feature to maintain the output voltage
▪ Charge complete indication
▪ Integrated 40 V DMOS switch
The Allegro® A8437 Xenon photoflash charger IC is designed
to meet the needs of ultra-low power, small form factor cameras,
particularly camera-phones.
The charge current time is adjustable by setting the charge
current limit from 0.4 to 1.2 A maximum. By using primaryside voltage sensing, the need for a secondary-side resistive
voltage divider is eliminated. This has the additional benefit
of reducing leakage currents on the secondary side of the
transformer. To extend battery life, the A8437 features very
low supply current draw—typically 0.1 μA in shutdown mode
and 10 μA in standby mode.
The A8437 has a flash dual trigger IGBT driver and flash
interlock to increase the device noise immunity. The IGBT
driver also has separate source and sink connections, for
flexibility in controlling IGBT rise and fall times. The charge
and trigger voltage logic thresholds are set at 1.1 VHI (min)
to support applications implementing low voltage control
logic.
The A8437 is available in a 10-pin, 3 mm × 3 mm DFN/MLP
package with exposed pad for enhanced thermal performance.
For an even smaller PCB footprint, a wafer-level chip scale
package (WLCSP) option is available.
Packages:
10-contact DFN/MLP
3 mm × 3 mm
0.75 nominal overall height
(Package EJ)
Applications include:
▪ Mobile phone flash
▪ Digital and film camera flash
12-ball WLCSP
1.205 mm × 1.635 mm
0.5 nominal overall height
(Package CG)
Typical Application
CG Package
EJ Package
1 : 10
1 : 10
C2
Battery Input +
2.3 to 5.5 V
C1
C2
COUT
100 μF
315 V
VIN
TLIM
Battery Input +
2.3 to 5.5 V
C1
VOUT Detect
VOUT Detect
SW
SW
ISET
RSET
ISET
Control
Block
ISW sense
RSET
Connect
to VIN
REG
CHARGE
DONE
VPULLUP
100 kΩ
Application 1. Typical application
without output voltage regulation.
Note: Application must
periodically restart the charging
cycle to recover lost charge on
the output capacitor.
Control
Block
ISW sense
DONE
IGBT Gate
DONE
TRIGGER1
VIN
IGBT Driver
IGBT Gate
GATE
TRIGGER2
GSINK
GND
A8437-DS, Rev. 1
VPULLUP
100 kΩ
GSOURCE
TRIGGER1
Connect
to VIN
REG
CHARGE
DONE
IGBT Driver
COUT
100 μF
315 V
VIN
TRIGGER2
GND
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
Selection Guide
Part Number
Package
Packing
A8437ECGLT*
12-ball WLCSP
Tape and reel, 4000 pieces per reel
A8437EEJTR-T
10-contact DFN/MLP
Tape and reel, 1500 pieces per reel
*Contact Allegro for additional ordering information.
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Units
–0.3 to 40
V
–0.3 to 6.0
V
–0.6 to VIN + 0.3 V
V
DC voltage.
SW Pin
VSW
VIN Pin
VIN
(VSW is self-clamped by internal active clamp
and is allowed to exceed 40 V during flyback
spike durations. Maximum repetitive energy
during flyback spike: 0.5 μJ at frequency
≤ 400 kHz.)
Care should be taken to limit the current when
–0.6 V is applied to these pins.
¯N̄¯Ē¯ Pins
CHARGE, TRIGGERx, D̄¯Ō
–0.3 to VIN + 0.3 V
V
–40 to 85
ºC
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
Remaining Pins
Operating Ambient Temperature
Maximum Junction
Storage Temperature
TA
Range E
Thermal Characteristics
Characteristic
Package Thermal Resistance2
Test Conditions1
Symbol
RθJA
Value
Units
CG package, on 4-layer PCB based on JEDEC standard
100
ºC/W
EJ package, on 2-layer PCB with 0.88 in.2 area of 2 oz. copper
each side, based on JEDEC standard
65
ºC/W
EJ package, on 4-layer PCB based on JEDEC standard
45
ºC/W
1Additional
2CG
thermal information available on Allegro website.
results preliminary.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
Functional Block Diagram
VIN
SW
VSW – VBAT
DCM
Detector
ISET
ISET Buffer
Control Logic
toff(max)
DMOS
18 μs
VDSref
OCP
HmL
Triggered Timer
S
Q
R
Q
ton(max)
18 μs
Enable
S
Q
R
Q
DONE
REG
1.2 V
0.96 V
VIN
VIN
GSOURCE
CHARGE
GATE
GSINK
TRIGGER1
EJ Package
GND
CG Package
TRIGGER2
GND
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
Pin-out Diagrams
(Contacts Down Views)
CG Package
EJ Package
A1 A2 A3 A4
B1 B2 B3 B4
C1 C2 C3 C4
ISET
1
GATE
2
VIN
3
GND
CHARGE
10 REG
9
DONE
8
TRIGGER1
4
7
SW
5
6
TRIGGER2
EP
Orientation mark
on ball side
Terminal List Table
Name
Number
CG
EJ
Function
ISET
C4
1
Sets the maximum switch current; connect an external resistor to GND to set the
desired peak current
GATE
–
2
IGBT gate drive – sink/source
GSOURCE
B3
–
IGBT gate drive – source
GSINK
C3
–
IGBT gate drive – sink
VIN
C2
3
Input voltage; connect to a 2.3 to 5.5 V bias supply
GND
C1
4
Ground connection
CHARGE
B1
5
Pull high to initiate charging; pull low to enter low-power standby mode
TRIGGER2
B2
6
IGBT input trigger 2
SW
A1
7
Drain connection of internal power MOSFET switch; connect to transformer
TRIGGER1
A2
8
IGBT input trigger 1
¯N̄¯Ē¯
D̄¯Ō
A3
9
Pulls low when output reaches target value and CHARGE pin is high; goes high during charging or whenever CHARGE pin is low
TLIM
A4
–
For production test only; connect to GND on PCB
REG
B4
10
Output voltage regulation pin; connect to external resistor and capacitor to regulate
output voltage, or connect to VIN pin to disable regulation (see Output Regulation
section for details)
EP
n.a.
–
Exposed pad for enhanced thermal dissipation; not connected electrically
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A8437
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
ELECTRICAL CHARACTERISTICS typical values valid at VIN = 3.6 V, RSET = 33 kΩ, ISWlim = 1.0 A, and TA=25°C, unless otherwise noted
Characteristics
VIN Voltage Range
UVLO Enable Threshold
UVLO Hysteresis
VIN Supply Current
Symbol
VIN
VINUV
VINUVhys
IIN
Test Conditions
VIN rising
Shutdown (CHARGE = 0 V,
TRIGGER1 and TRIGGER2 = 0 V)
Charging complete, regulation disabled (REG = VIN)
Charging complete, regulation enabled
Charging (CHARGE = VIN,
TRIGGER1 and TRIGGER2 = 0 V)
Min.
2.3
–
–
Typ.
–
2.05
150
Max.
5.5
2.2
–
Unit
V
V
mV
–
0.01
0.5
μA
–
–
10
0.5
50
–
μA
mA
–
2
–
mA
1.08
–
–
–
–
–
–
1.2
0.4
28
1.2
1000
0.25
–
1.32
–
–
–
–
–
2
A
A
kA/A
V
Ω
Ω
μA
–
–
0.5
μA
–
1.1
–
–
–
–
–
36
–
–
100
20
18
18
–
–
0.4
–
–
–
–
μA
V
V
kΩ
us
μs
μs
Current Limits
Switch Current Limit1
SW / ISET Current Ratio
ISET Pin Voltage While Charging
ISET Pin Internal Resistance
Switch On-Resistance
Switch Leakage Current2
ISWlimMAX
ISWlimMIN
ISW/ISET
VSET
RSET(INT)
RSWDS(on)
ISWlk
CHARGE Input Current
ICHARGE
CHARGE Input Voltage2
VCHARGE
CHARGE Pull-Down Resistor Value
CHARGE ON/OFF Delay
Maximum Switch-Off Timeout
Maximum Switch-On Timeout
VIN = 3.6 V, ID = 800 mA, TA = 25°C
VSW = VIN(max), over temperature range
Combined VIN and SW leakage current at TA=25°C
VIN= 5.5 V in Shutdown
VCHARGE = VIN
High, over input supply range
Low, over input supply range
RCHPD
tCH
toffMAX
tonMAX
¯N̄¯Ē¯ Output Leakage Current2
D̄¯Ō
IDONElk
¯N̄¯Ē¯ Output Low Voltage2
D̄¯Ō
VDONEL
Output Comparator Trip Voltage2
Output Comparator Overdrive
Minimum dV/dt for ZVS Comparator
Regulation
Maximum, RSET = 26.7 kΩ
Minimum, RSET = 85 kΩ
RSET = 33 kΩ, CHARGE = high
RSET = 33 kΩ, CHARGE = high
VOUTTRIP
VOUTOV
dV/dt
¯N̄¯Ē
¯ pin
32 μA into D̄¯Ō
Measured as VSW – VIN
Pulse width = 200 ns (90% to 90%)
Measured at SW pin
–
–
1
μA
–
31
–
–
–
31.5
200
20
100
32
400
–
mV
V
mV
V/μs
REG Voltage When Charging Completes
VREG(H)
¯N̄¯Ē¯ → low transition
CHARGE = high, at D̄¯Ō
1.15
1.2
1.25
V
REG Voltage Threshold for Regulation
VREG(L)
¯N̄¯Ē¯ = low
CHARGE = high, at D̄¯Ō
–
0.96
–
V
REG Output Current Drive Capability
IREG
¯N̄¯Ē¯ = high, VSW – VIN = 30 V,
CHARGE = high, at D̄¯Ō
VREG = 1.0 V
–
50
–
μA
REG Leakage Current While Not Charging
IREGlk
¯N̄¯Ē¯ = low, VREG = 1.2 V
CHARGE = high, at D̄¯Ō
–
0.1
–
μA
–
0.4
–
–
–
–
–
–
–
V
V
kΩ
Ω
Ω
ns
ns
ns
ns
IGBT Driver
VTRIG(H) Input = logic high, over input supply range
1.1
–
VTRIG(L) Input = logic low, over input supply range
–
–
TRIGGER, TRIGGER2 Pull-Down Resistor RTRIGPD
–
100
GSOURCE Resistance to VIN3
RSrcDS(on) VIN = 3.6 V, VGSOURCE =1.8 V
–
5
RSnkDS(on) VIN = 3.6 V, VGSINK = 1.8 V
–
6
GSINK Resistance to GND3
Propagation Delay (Rising)
tDr
–
30
Propagation Delay (Falling)
tDf
–
30
GSOURCE and GSINK tied together, measurement
taken at pin; RGATE = 12 Ω, CL= 6500 pF, VIN = 3.6 V
Output Rise Time
tr
–
70
Output Fall Time
tf
–
70
1Current limit guaranteed by design and correlation to static test. Refer to application section for peak current in actual circuits.
2Specifications over the range T = –40°C to 85°C; guaranteed by design and characterization.
A
3GSOURCE and GSINK tied together (GATE pin) in EJ package.
TRIGGER, TRIGGER2 Input Voltage2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
Timing and IGBT Interlock Function
The two TRIGGER signals are internally ANDed together. As
shown in the timing diagram, below, triggering is prohibited during the initial charging process. This prevents premature firing
of the flash before the output capacitor has been charged to its
target voltage. Refer to the section IGBT Gate Driver Interlock
for details.
VIN
CHARGE
SW
VOUT
DONE
A
B
D
C
TRIGGER
IGBTDRV
Case
Description
A
TRIGGER pulse arrives before first charging process is finished (CHARGE and
¯N̄¯Ē
¯ pins are both high). IGBTDRV is disabled in this case.
D̄¯Ō
B
Arrives during regulation mode, while not refreshing. IGBTDRV is enabled.
Charging resumes once TRIGGER is low again.
C
Arrives during regulation mode, while refreshing. Charging is stopped after
present cycle. IGBTDRV is enabled. Charging resumes after TRIGGER is low
again.
D
Arrives while IC is in low-power Standby mode (CHARGE pin is low).
IGBTDRV is always enabled in this case.
IGBT Drive Timing Definition
TRIGGER
50%
tDr
GSOURCE,
GSINK,
or GATE
50%
tr
tDf
90%
10%
tf
90%
10%
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
Performance Characteristics
Charging Time at Various Peak Current Levels
Common Parameters
Symbol
Parameter Units/Division
C1
VOUT
50 V
C2
VBAT
1V
C3
IIN
100 mA
t
time
200 ms
Conditions Parameter
Value
VBATT
3.6 V
COUT
20 μF
Conditions
Parameter
RSET
ISWlim
Value
26.7 kΩ
≈1.2 A
VOUT
VBAT
C1
C2
IIN
C1
C2
C3
C3
t
VOUT
C1
VBAT
Conditions
Parameter
RSET
ISWlim
Value
33.2 kΩ
≈1.0 A
C2
IIN
C1
C2
C3
C3
t
VOUT
C1
VBAT
Conditions
Parameter
RSET
ISWlim
Value
39 kΩ
≈0.9 A
C2
IIN
C1
C2
C3
C3
t
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
Efficiency versus Battery Voltage
Charge Time versus Battery Voltage
Transformer Lp= 8 μH, N = 10.2; COUT= 20 μF / 330 V UCC; TA=25°
Transformer Lp= 8 μH, N = 10.2; COUT= 20 μF / 330 V UCC; TA=25°
71
3.5
2.0
45
≈ 0.8
67
39
≈ 0.9
66
33.2
≈ 1.0
65
26.7
≈ 1.2
69
68
1.5
1.0
0.5
64
62
RSET
(kΩ)
55
IP
(A)
≈ 0.65
61
45
≈ 0.8
60
39
≈ 0.9
59
33.2
≈ 1.0
58
26.7
≈ 1.2
63
57
56
55
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.0
6.0
2.5
3.0
3.5
VBAT (V)
COUT= 20 μF. For larger or smaller capacitances, charging time
scales proportionally.
4.0
VBAT (V)
4.5
5.0
5.5
6.0
Special low-profile transformer with relatively low inductance
(Lp= 8 μH) and high winding resistance (Rp = 0.37 Ω). Higher efficiency can be achieved by using transformers with higher Lp, which reduces
switching frequency and therefore switching loses, and lower resistance,
which reduces conduction losses.
Average Input Current versus Battery Voltage
XFM Lp= 8 μH, N = 10.2, COUT= 20 μF 330 V UCC, TA=25°
0.55
0.50
0.45
0.40
IIN (A)
Time (s)
2.5
IP
(A)
≈ 0.65
Efficiency (%)
3.0
70
RSET
(kΩ)
55
0.35
0.30
RSET
(kΩ)
26.7
IP
(A)
≈ 1.2
33.2
≈ 1.0
39
≈ 0.9
45
≈ 0.8
55
≈ 0.65
0.25
0.20
0.15
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VBAT (V)
An increase in ISWlim with respect to VBAT actually keeps the average input current
roughly constant throughout the battery voltage range. Normally, if ISWlim is kept
constant, the average current will drop as VBAT goes higher.
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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8
A8437
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
Application Information
General Operation Overview
The CHARGE pin enables the part and starts charging.
¯ open-drain indicator is pulled low when
The ¯¯¯
D¯ Ō¯¯N̄¯Ē
CHARGE is high and target output voltage is reached.
Charging is reinitiated when the REG pin voltage falls
below the regulation threshold. Pulling the CHARGE
pin low stops charging and forces the chip into lowpower standby mode.
Output Voltage Regulation
When the REG pin is connected to VIN, the A8437
stops charging the output voltage after the reflected
voltage (VSW – VIN) reaches 31.5 V. In this mode,
charging can be reinitiated by cycling the CHARGE
signal through a low to high transition.
The A8437 can also be used to regulate output voltage
within a predetermined window. In this mode, connect a capacitor, CREG, and resistor, RREG, from the
REG pin to GND (refer to the figure Application 3).
When CHARGE is held high, the voltage monitoring
circuit of the A8437 is always active, irrespective of
the REG pin voltage level.
Voltage Regulation Using Predicitive Droop The A8437
uses a technique called Predictive Droop for regulating the output capacitor voltage after the completion
of a charging cycle. When the target output voltage
is reached, the converter stops charging and output
capacitor voltage droops due to leakage current. An
external resistor and capacitor connected from the
REG pin to ground will provide an RC discharge time
constant. This time constant can be selected to mirror
the droop rate of the output capacitor. When voltage at
the REG pin drops to 80% of the reference value, the
converter starts charging again and brings the output
capacitor back to target voltage again.
The time required for an RC network to discharge
from V0 to VT is given by:
T = R × C × ln (V0 / VT) .
(1)
For example, if C = 10 μF, R = 10 MΩ and V0 / VT =
1.25, then T = 22 seconds. Assuming that the RC-discharge characteristic of the output capacitor matches
that at the REG pin, we can predict that the output
voltage has drooped 20%, and therefore it is time to
recharge the output capacitor.
By implementing a Predictive Droop technique, no
additional leakage paths are introduced on the secondary side, which helps to keep power losses to a minimum. By intentionally making the RC discharge time
constant of the REG pin shorter than that of the output
capacitor, we can regulate the output voltage to a window tighter than the default 20% hysteresis.
Voltage Regulation Using Direct Sensing If
direct sensing from the secondary side is desired, connect the
REG pin to a resistor divider network across the output capacitor to enable output regulation. In this case,
the charging cut-off is still controlled by primary side
sensing (charging stops when reflected voltage reaches
31.5 V), but the regulation threshold is controlled by
the secondary side sensing. When the CHARGE pin
is high, and the sensed output voltage falls below the
lower VREG threshold, the flyback converter charges
the output capacitor again until the primary side sensing stops further charging. This cycle repeats till the
CHARGE pin is pulled low.
The benefit of this method is that a lower output voltage can be selected independently, simply by changing the resistor divider ratio. For example, given
R1=10 MΩ, R2= 33.2 kΩ, and VREG(L)= 0.96 V, then:
VOUT(Low) = VREG(L) × ( R1/ R2 + 1) = 290 V . (2)
Selection of Switching Current Limit
The A8437 features continuously adjustable peak
switching current between 0.4 and 1.2A. This is done
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115 Northeast Cutoff
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9
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
by selecting the value of an external resistor RSET,
connected from the ISET pin to GND, which determines the ISET bias current, and therefore the switching current limit, ISWlim.
where:
RSET(INT) is the internal resistance of the ISET pin
(1 kΩ typical),
RGND(INT) is the internal resistance of the bonding
wire for the GND pin (27 mΩ typical), and
To the first order approximation, ISWlim is related to
ISET and RSET according to the following equations:
ISWlim = ISET × K = VSET / RSET × K ,
K = (K′ + VIN × K″), with K′ = 24350 and K″ ≈
1040 at TA = 25°C. Then,
(3)
where K = 28000 when battery voltage is 3.6 V.
ISWlim = ISET × K + VBAT / LP × tD ,
In real applications, the actual switching current
limit is affected by input battery voltage, and also the
transformer primary inductance, Lp. If necessary, the
following expressions can be used to determine ISWlim
more accurately:
(5)
where tD is the delay in SW turn-off (0.1 μs typical).
The chart at the bottom of the page can be used to
determine the relationship between RSET and ISWlim at
various battery voltages.
ISET = VSET / (RSET + RSET(INT) – K × RGND(INT) ), (4)
Peak Current Limit versus ISET Resistance
VIN = VBAT, XFM Lp = 8 μH, TA=25°C
1.3
1.2
1.1
VIN = 5.5 V
VIN = 4.5 V
ISWlim (A)
1.0
VIN = 3.6 V
VIN = 3.0 V
0.9
VIN = 2.3 V
0.8
0.7
0.6
0.5
0.4
25
30
35
40
45
50
55
60
65
70
75
80
85
90
RSET (kΩ)
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
Smart Current Limit (Optional)
With the help of some simple external logic, the
user can change the charging current according to
the battery voltage. For example, assume that ISET is
normally 36 μA (for ISWlim = 1.0 A). Referring to the
following illustration, when the battery voltage drops
BL
RBL
period, 18 μs, off-time control. One advantage of
having Timer Mode is that it limits the initial battery
current surge and thus acts as a “soft-start.” A timeexpanded view of a Timer Mode interval is shown in
the following figure.
Timer Mode
ISET
VSW
RSET
VBAT
below 2.5 V, the signal at BL (battery-low) goes high.
The resistor RBL, connecting BL to the ISET pin,
then injects 10 μA into RSET. This effectively reduces
ISET current to 26 μA (for ISWLIM = 0.73 A). A disadvantage of the above method is that the 10 μA current
is always flowing whenever the BL signal goes high.
Timer Mode and Fast Charging Mode
The A8437 achieves fast charging times and high efficiency by operating in discontinuous conduction mode
(DCM) through most of the charging process. The
relationship of Timer Mode and Fast Charging Mode
is shown in the following figure.
VOUT
VOUT
ISW
VOUT≤ 14 V; t =2 μs/div; VBAT =3.6 V; RSET=33.2 kΩ
As soon as a sufficient voltage has built up at the
output capacitor, the IC enters Fast-Charging Mode.
In this mode, the next switching cycle starts after the
secondary side current has stopped flowing, and the
switch voltage has dropped to a minimum value. A
proprietary circuit is used to allow minimum-voltage
switching, even if the SW pin voltage does not drop to
0 V. This enables Fast-Charging Mode to start earlier
than previously possible, thereby reducing the overall
charging time. Minimum-voltage switching is shown
in the following figure.
Timer Mode
Fast Charging Mode
VBAT
IIN
t =200 ms/div; VOUT =50 V/div; VBAT =1 V/div.; IIN =100 mA/div.
VBAT =3.6 V; COUT =20 μF/330 V; RSET=46 kΩ (ISWlim≈0.75 A)
The IC operates in Timer Mode when beginning to
charge a completely discharged photoflash capacitor, usually when the output voltage, VOUT, is less
than approximately 15 to 20 V. Timer Mode is a fixed
Minimum Voltage
Switching
VSW
VBAT
VOUT
ISW
VOUT ≥ 15 V; t =1 μs/div; VBAT =3.6 V; RSET=33.2 kΩ
During Fast-Charging Mode, when VOUT is high
enough (over 50 V), true zero-voltage switching
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11
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
(ZVS) is achieved. This further improves efficiency
as well as reduces switching noise. A ZVS interval is
shown in the following figure.
VOUT
Zero Voltage
Switching
VSW
VSW
VBAT
VBAT
ISW
VOUT
ISW
VOUT = 120 V; t =0.2 μs/div; VBAT =3.6 V; RSET=33.2 kΩ
IGBT Gate Driver Interlock
The TRIGGER1and TRIGGER2 pins are ANDed
together inside the IC to control the IGBT gate driver.
If only one trigger signal is needed, tie both trigger
pins together and use as a single input.
triggering can be enabled, according to the following
chart:
Conditions
Resulting State
CHARGE
¯N̄¯Ē¯
D̄¯Ō
Low
Don’t Care
Enabled
High
High
Disabled
High
Low
Enabled
IGBT Gate Driver
After completion of the charging cycle, if the charge
pin is kept high and REG is enabled, the IC will
periodically recharge the output. If a trigger signal
comes in during a recharge cycle, charging will be
halted immediately and the IGBT gate driver will be
allowed to fire after a delay of less than 1 μs. Charging
resumes after the trigger signal is removed.
Red Eye Reduction
The IGBT gate driver is always enabled when
CHARGE is low. If the charge pin is disabled before
sufficient voltage has built up on the output capacitor,
the flash may not fire. In the case of red-eye reduction
Triggering is disabled (locked) during charging. This
is to prevent switching noise from interfering with the flashes, it is recommended to keep the CHARGE pin
IGBT driver. After the CHARGE pin goes high (at the low until completion of triggering pulses. This ensures
start of a charging cycle), the IC must wait for comple- that the IGBT gate driver will remain enabled regard¯¯¯¯ Ō¯¯N̄¯Ē
¯ goes low) before
¯ state.
tion of the charging cycle (D
less of the ¯¯¯
D¯ Ō¯¯N̄¯Ē
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12
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
can flow through the phototransistor. This forces the
voltage at TRIGGER2 pin to fall to 0.8 V or lower,
so it prohibits TRIGGER1 from firing the flash. The
exact threshold of ambient light required to prohibit
flash firing can be adjusted by RTGR1. The smaller this
resistance, the brighter the ambient light must be to
prohibit flash firing.
Ambient Light Sensing
Ambient Light Sensing (ALS) can be easily implemented for the A8437 using the TRIGGER2 pin plus
three external components. This configuration is
shown in the figure below.
The phototransistor current is proportional to the
intensity of the light that it receives. When there is
sufficient ambient light (for example, during daylight
outdoor photographing), a current of about 30 μA
When ambient conditions are dark, the current flowing through the phototransistor is in less than 1 μA.
Because the TRIGGER2 pin is biased at 1.4 V or
Battery Input
2.3 to 5.5 V
1 : 10
+
C1
C2
COUT
100 μF
315 V
VIN
TLIM
ISET
VOUT Detect
Control
Block
RSET
SW
ISW sense
Connect
to VIN
REG
CHARGE
DONE
DONE
A Bias Voltage
2.5 to 5.5 V
TRIGGER1
VIN
IGBT Driver
GSOURCE
IGBT Gate
RTGR1
100 kΩ
PNZ121S
Phototransistor
TRIGGER2
CTGR1
1 μF
GSINK
GND
A It is recommend to use a regulated system voltage for the bias.
If battery voltage is used, the ALS sensitivity will vary with
battery voltage, and there would be a small leakage current
even when the camera is turned off.
ALS typical application (CG package shown)
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13
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
higher, TRIGGER1 is allowed to activate the IGBT
gate driver (and thereby fire the flash).
The capacitor CTGR1 and resistor RTGR1 form an
integrator for light exposure. When the flash fires,
bright light bounces back from subject and enters the
phototransistor. In example A below, the flash terminates after just 30 μs, without fully discharging the
photoflash capacitor.
If the subject is far away, the reflected light intensity
is lower, so the phototransistor current is also lower.
In example B below, the flash stays on for longer time
(60 μs) and discharges more energy from the photoflash capacitor.
Using a larger CTGR1 causes the time constant of the
integrator to increase, so a longer pulse is required
before the flash is terminated.
Example A
VOUT
VTRIGGER2
C2
C1
C2
C3
VTRIGGER1
C3
VGATE
C1
C4
C4
t
Common Parameters
Symbol
Parameter Units/Division
C1
VOUT
50 V
C2
VTRIGGER2
1V
C3
VTRIGGER1
5V
5V
C4
VGATE
t
time
20 μs
Example B
VOUT
VTRIGGER2
VTRIGGER1
C2
C1
C2
C3
C3
VGATE
C1
C4
C4
t
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14
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
Transformer Selection
1. The transformer turns ratio, N, determines the output voltage:
N = NS / NP
VOUT = 31.5 × N – Vd ,
where 31.5 is the typical value of VOUTTRIP , and Vd is
the forward drop of the output diode.
The minimum pulse width for toff determines what
is the minimum LP required for the transformer. For
example, if ISWlim = 0.7 A, N = 10, and VOUT = 315 V,
then LP must be at least 9 μH in order to keep toff at
200 ns or longer. These relationships are illustrated in
the figure at the bottom of the page.
where R is the total resistance in the primary current
path (including RSWDS(on) and the DC resistance of the
transformer).
In general, choosing a transformer with a larger LP
results in higher efficiency (because a larger LP means
lower switch frequency and hence lower switching
loss). But transformers with a larger LP also require
more windings and larger magnetic cores. Therefore, a
trade-off must be made between transformer size and
efficiency.
If VIN is much larger than ISWlim × R, then ton can be
approximated by:
Component Selection
2. The primary inductance, LP , determines the on-time
of the switch:
ton = (–LP / R ) × ln (1 – ISWlim × R /VIN) ,
ton = ISWlim × LP /VIN .
Selection of the flyback transformer should be based
3. The secondary inductance, LS, determines the offtime of the switch. Given:
on the peak current, according to the following table:
IPeak Range
LS / LP = N × N , then
toff = (ISWlim / N) × LS /VOUT
= (ISWlim × LP × N) /VOUT .
ton
LP
(A)
Supplier
Part Number
(μH)
0.4 to 1.0
TDK
LDT565630T-002
14.5
0.6 to 1.2
TDK
LDT565630T-003
10.5
0.75 to 1.0
TDK
LDT565620ST-203
8.2
toff
VSW
ISW
Vr
tf
VIN
VIN
ISW
VSW
tneg
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15
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
Battery Input
2.3 to 5.5 V
Battery Input
2.3 to 5.5 V
1 : 10
1 : 10
+
+
C1
C2
TLIM
ISET
C2
COUT
100 μF
315 V
VIN
VOUT Detect
TLIM
SW
ISW sense
RSET
38.3 kΩ
ISET
VOUT Detect
Control
Block
CREG
10 MF
CHARGE
VPULLUP
DONE
100 kΩ
100 kΩ
DONE
DONE
TRIGGER1
VIN
IGBT Driver
GSOURCE
TRIGGER1
VIN
IGBT Driver
GSOURCE
IGBT Gate
IGBT Gate
TRIGGER2
RREG
10 MΩ
REG
VPULLUP
DONE
SW
ISW sense
RSET
REG
CHARGE
COUT
100 μF
315 V
VIN
10 MΩ
Control
Block
C1
GSINK
GND
Application 2. Maintaining output target voltage by directly
monitoring the output voltage (REG pin connected to a
secondary-side resistor divider). CG package shown.
TRIGGER2
GSINK
GND
Application 3. Maintaining output voltage by predicting the output
voltage droop (REG pin connected to primary-side RC network).
CG package shown.
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16
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
Package CG, 12-Ball WLCSP
1.645
1
A
1.215
2
3
4
1
2
3
4
A
A
B
B
C
C
0.40
X .17
0.40
SEATING
PLANE
B
PCB Layout Reference View
C
12X
0.05 C
0.550 MAX
0.19
C
All dimensions nominal, not for tooling use
Dimensions in millimeters
Dimensions exclusive of burrs
Exact configuration at supplier discretion within limits shown
0.2225
0.208
C
0.800
B
0.400
A
1
2
3
A Terminal #A1 mark area
B
Reference pad layout; all pads a minimum of 0.20 mm from
all adjacent pads; adjust as necessary to meet application
process requirements and PCB layout tolerances
C Die orientation mark
4
1.200
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17
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
Package EJ, 3 mm x 3 mm 10-Contact DFN/MLP
0.30
3.00 ±0.15
0.85
0.50
10
10
3.00 ±0.15
1.64
3.10
A
1
2
1
11X
D
SEATING
PLANE
0.08 C
+0.05
0.25 –0.07
C
C
2.38
PCB Layout Reference View
0.75 ±0.05
0.50
1
For Reference Only
(reference JEDEC MO-229WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
2
0.40 ±0.10
1.64
B
10
2.38
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference
IPC7351 SON50P300X300X80-11WEED3M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
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A8437
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
CG Package Marking
NN
YWW
Line 1:
Bump A1 mark
NN – last two digits of the device number (37)
Line 2: Date code
Y – last digit of year of manufacture
WW – week of manufacture
(Marks on substrate side, exact
appearance at supplier discretion)
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115 Northeast Cutoff
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19
Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
Typical Reflow Profile per J-STD-020D
Supplier Tp > Tc
-
-
User Tp < Tc
Tc
Tc -5°C
Supplier tp
User tp
Te m p e r a t u r e
Tp
Max. Ramp Up Rate = 3°C/s
Max. Ramp Down Rate = 6°C/s
TL
Tsmax
tp
Tc -5°C
tL
Preheat Area
Tsmin
ts
25
Time 25°C to Peak
Time
IPC-020d-5-1
JSTD020D-01, Figure 5-1 Classification Profile (Not to scale)
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Mobile Phone Xenon Photoflash Capacitor Charger
with IGBT Driver
A8437
Typical Reflow Profile per J-STD-020D
JSTD020D-01 Table 5-2 Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
Peak package body temperature (Tp)
For users Tp must not exceed the
Classification temp in Table 4-1.
For suppliers Tp must equal or exceed
the Classification temp in Table 4-1.
For users Tp must not exceed the
Classification temp in Table 4-2.
For suppliers Tp must equal or exceed
the Classification temp in Table 4-2.
Time (tp)* within 5 °C of the specified
classification temperature (Tc), see
Figure 5-1.
20* seconds
30* seconds
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat/Soak
Temperature Min (Tsmin)
Temperature Max (Tsmax)
Time (ts) from (Tsmin to Tsmax)
Ramp-up rate (TL to Tp)
Liquidous temperature (TL)
Time (tL) maintained above TL
Ramp-down rate (Tp to TL)
Time 25 °C to peak temperature
* Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum.
Note 1: All temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly reflow (e.g., live-bug). If
parts are reflowed in other than the normal live-bug assembly reflow orientation (i.e., dead-bug), Tp shall be within ± 2 °C of the live-bug Tp and still
meet the Tc requirements, otherwise, the profile shall be adjusted to achieve the latter. To accurately measure actual peak package body temperatures
refer to JEP140 for recommended thermocouple use.
Note 2: Reflow profiles in this document are for classification/preconditioning and are not meant to specify board assembly profiles. Actual board assembly
profiles should be developed based on specific process needs and board designs and should not exceed the parameters in Table 5-2.
For example, if Tc is 260 °C and time tp is 30 seconds, this means the following for the supplier and the user.
For a supplier: The peak temperature must be at least 260 °C. The time above 255 °C must be at least 30 seconds.
For a user: The peak temperature must not exceed 260 °C. The time above 255 °C must not exceed 30 seconds.
Note 3: All components in the test load shall meet the classification profile requirements.
Note 4: SMD packages classified to a given moisture sensitivity level by using Procedures or Criteria defined within any previous version of J-STD-020,
JESD22-A112 (rescinded), IPC-SM-786 (rescinded) do not need to be reclassified to the current revision unless a change in classification level or a
higher peak classification temperature is desired.
Copyright ©2006-2010, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
21