Low Cost 10-Bit, 6-Channel Output Decimating LCD DecDriver® AD8383 High voltage drive to within 1.3 V of supply rails Output short-circuit protection High update rates Fast, 100 Ms/s, 10-bit input data update rate Low static power dissipation: 0.7 W Includes STBY function Voltage-controlled video reference (brightness) and full-scale (contrast) output levels INV bit reverses polarity of video signal 3.3 V logic, 9 V to 18 V analog supplies High accuracy voltage outputs Laser trimming eliminates the need for adjustments Flexible logic STSQ/XFR allow parallel AD8383 operation at various resolutions Fast settling into capacitive loads 30 ns settling time to 0.25% into 150 pF load Slew rate 460 V/µs Available in 48-lead 7 mm × 7 mm LFCSP package FUNCTIONAL BLOCK DIAGRAM DB(0:9) 10 10 AD8383 STBY BYP DAC VID0 10 2-STAGE 10 LATCH DAC VID1 10 2-STAGE 10 LATCH DAC VID2 10 2-STAGE 10 LATCH DAC VID3 10 2-STAGE 10 LATCH DAC VID4 10 2-STAGE 10 LATCH DAC VID5 BIAS R/L E/O CLK STSQ XFR 10 2-STAGE 10 LATCH SEQUENCE CONTROL SCALING CONTROL VREFHI INV VREFLO V1 V2 04513-0-001 FEATURES Figure 1 APPLICATIONS LCD analog column driver PRODUCT DESCRIPTION The AD8383 provides a fast, 10-bit latched decimating digital input that drives six high voltage outputs. 10-bit input words are sequentially loaded into six separate, high speed, bipolar DACs. Flexible digital input format allows several AD8383s to be used in parallel for higher resolution displays. STSQ synchronizes sequential input loading, XFR controls synchronous output updating, and R/L controls the direction of loading as either left-to-right or right-to-left. Six channels of high voltage output drivers drive to within 1.3 V of the rail. For maximum flexibility, the output signal can be adjusted for dc reference, signal inversion. The AD8383 is fabricated on the 26 V, fast bipolar XFHV process developed by Analog Devices, Inc. This process provides fast input logic, bipolar DACs with trimmed accuracy and fast settling, high voltage, precision drive amplifiers on the same chip. The AD8383 dissipates 0.7 W nominal static power. The STBY pin reduces power to a minimum with fast recovery. The AD8383 is offered in a 48-lead, 7 mm × 7 mm × 0.85 mm LFCSP package and operates over the commercial temperature range of 0°C to 85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD8383 TABLE OF CONTENTS Specifications..................................................................................... 3 PCB Design for Good Thermal Performance ........................ 10 Absolute Maximum Ratings............................................................ 5 Thermal Pad Design .................................................................. 10 Maximum Power Dissipation ..................................................... 5 Thermal Via Structure Design.................................................. 11 Pin Configuration and Function Descriptions............................. 6 Solder Masking ........................................................................... 11 Timing Diagrams.............................................................................. 7 Reference PCB Design............................................................... 11 Theory of Operation ........................................................................ 8 Estimated Junction Temperature ............................................. 12 Transfer Function and Analog Output Voltage ........................ 8 Outline Dimensions ....................................................................... 14 Applications....................................................................................... 9 Ordering Guide .......................................................................... 14 External VBIAS Generation ........................................................ 9 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 16 AD8383 SPECIFICATIONS Table 1. @25°C, AVCC = 15.5 V, DVCC = 3.3 V, TMIN = 0°C, TMAX = 75°C, VFS = 5 V, VREFLO = V1 = V2 = 7 V, unless otherwise noted Parameter VIDEO DC PERFORMANCE1 VDE VCME REFERENCE INPUTS V1, V2 Range V2 to V1 Range V1 Input Current V2 Input Current VREFHI Range VREFLO Range VREFHI Input Resistance VREFLO Bias Current VREFHI Input Current VFS Range2 RESOLUTION Coding DIGITAL INPUT CHARACTERISTICS Maximum Input Data Update Rate3 CLK to Data Setup Time CLK to STSQ Setup Time CLK to XFR Setup Time CLK to Data Hold Time CLK to STSQ Hold Time CLK to XFR Hold Time CLK High Time CLK Low Time CIN IIH IIL IIL, CLK VIH VIL VTH VIDEO OUTPUT CHARACTERISTICS Output Voltage Swing CLK to VID Delay4 INV to VID Delay Output Current Output Resistance Conditions TMIN to TMAX, DAC Code 450 to 800 Min Typ Max Unit –7.5 –3.5 +7.5 +3.5 mV mV 5 –0.25 AVCC – 4 V V µA µA V V kΩ µA µA V +0.2 –7.5 VREFHI ≥ VREFLO VREFHI ≥ VREFLO To VREFLO VREFLO V1 – 0.5 AVCC AVCC – 1.3 20 –0.2 125 0 Binary 5.5 10 Bits 100 0 1 1 3 3 3 3 2.5 Ms/s ns ns ns ns ns ns ns ns pF µA µA µA V V V 3 0.05 0.6 1.2 2 0.8 1.5 AVCC – VOH, VOL – AGND 50% of VIDx 50% of VIDx 1 VDE = Differential Error Voltage = Common-Mode Error Voltage. See Theory of Operation section. VFS = 2 × (VREFHI – VREFLO). Maximum input transition time (10% to 90%) = 0.8/(2f) where f is the operating CLK rate. 4 Measured from 50% of falling CLK edge to 50% of output change. Measurement is made for both states of INV. 2 3 Rev. 0 | Page 3 of 16 10.0 10.4 1.1 12.0 12.4 100 22 1.3 14.0 14.4 V ns ns mA Ω AD8383 SPECIFICATIONS (continued) Parameter VIDEO OUTPUT DYNAMIC PERFORMANCE Data Switching Slew Rate Invert Switching Slew Rate Data Switching Settling Time to 1% Data Switching Settling Time to 0.25% Invert Switching Settling Time to 1% Invert Switching Settling Time to 0.25% Invert Switching Overshoot CLK and Data Feedthrough5 All-Hostile Crosstalk6 Amplitude Duration DAC Transition Glitch Energy POWER SUPPLY DVCC, Operating Range DVCC, Quiescent Current AVCC, Operating Range Total AVCC Quiescent Current STBY AVCC Current STBY = H STBY DVCC Current STBY = H OPERATING TEMPERATURE RANGE, TA AMBIENT TEMPERATURE RANGE7 OPERATING TEMPERATURE RANGE, TJ Conditions TC, MIN to TC, MAX, VO = 5 V Step, CL = 150 pF 20% to 80% 20% to 80% Min Typ 460 560 19 30 75 250 100 10 VO = 10 V Step VO = 10 V Step VO = 10 V Step 3 3.3 20 9 40 0.15 3.5 100% tested 5 24 50 120 500 200 40 20 0.3 Code 511 to Code 512 Ambient Temperature Max 0 0 25 Unit V/µs V/µs ns ns ns ns mV mV p-p mV p-p ns nV-s 3.6 28 18 48 0.45 5 75 85 125 V mA V mA mA mA °C °C °C Measured on two outputs differentially as CLK and DB(0:9) are driven and STSQ and XFR are held low. Measured on two outputs differentially as the other four outputs make a full-scale transition for both states of INV. 7 Operation at 85°C ambient temperature requires a thermally optimized PCB layout (see Application Notes), minimum airflow of 200 lfm, input clock rate not exceeding 100 MHz, black-to-white transition ≤4 V, CL ≤150 pF. 6 Rev. 0 | Page 4 of 16 AD8383 ABSOLUTE MAXIMUM RATINGS Table 2. AD8383 Stress Ratings Parameter Supply Voltages AVCCx – AGNDx DVCC – DGND Input Voltages Maximum Digital Input Voltages Minimum Digital Input Voltages Maximum Analog Input Voltages Minimum Analog Input Voltages Internal Power Dissipation8 LFCSP Package @ 25°C Ambient Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 10 sec) MAXIMUM POWER DISSIPATION Rating Junction Temperature 18 V 4.5 V DVCC + 0.5 V DGND – 0.5 V AVCC + 0.5 V AGND – 0.5 V 3.8 W 0°C to 85°C –65°C to +125°C 300°C Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum ratings for extended periods may reduce device reliability. 8 48-Lead LFCSP Package: θJA = 26°C/W (Still Air): JEDEC STD, 4-layer board with 0 CFM airflow θJC = 20°C/W ψJB = 11.0°C/W in Still Air The maximum power that can be safely dissipated by the AD8383 is limited by its junction temperature. The maximum safe junction temperature for plastic encapsulated devices as determined by the glass transition temperature of the plastic is approximately 150°C. Exceeding this limit temporarily may cause a shift in the parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. Overload Protection The AD8383 employs a 2-stage overload protection circuit that consists of an output current limiter and a thermal shutdown. The maximum current at any one output of the AD8383 is internally limited to 100 mA, average. In the event of a momentary short-circuit between a video output and a power supply rail (AVCC or AGND), the output current limit is sufficiently low to provide temporary protection. The thermal shutdown debiases the output amplifier when the junction temperature reaches the internally set trip point. In the event of an extended short-circuit between a video output and a power supply rail, the output amplifier current continues to switch between 0 mA and 100 mA typical with a period determined by the thermal time constant and the hysteresis of the thermal trip point. The thermal shutdown provides longterm protection by limiting the average junction temperature to a safe level. Operating Temperature Range Production testing guarantees a minimum thermal shutdown junction temperature (TJ) of at least 125°C. To ensure operation at TJ < 125°C, it is necessary to limit the maximum power dissipation as described in the Applications section. Exposed Paddle The die paddle must be soldered to AVCC for reliable electrical operation. See the Applications section for details regarding use of the exposed paddles to dissipate excess heat. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 16 AD8383 XFR STSQ NC NC V1 AVCCDAC AGNDDAC VREFHI VREFLO V2 AGND0 46 45 44 43 42 41 40 39 38 37 CLK 48 NC 1 47 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 36 VID0 PIN 1 INDICATOR DB0 2 35 AVCC0,1 DB1 3 34 VID1 DB2 4 33 AGND1,2 DB3 5 32 VID2 AD8383 DB4 6 31 AVCC2,3 TOP VIEW 7mm × 7mm (Not to Scale) DB5 7 DB6 8 30 VID3 29 AGND3,4 DB7 9 28 VID4 DB8 10 27 AVCC4,5 DB9 11 26 VID5 04513-0-002 NC 24 NC 23 BYP 21 STBY 20 NC 19 AGNDBIAS 22 NC = NO CONNECT AVCCBIAS 18 DVCC 17 DGND 16 INV 15 R/L 14 25 AGND5 E/O 13 NC 12 Figure 2. 48-Lead LFCSP Pin Configuration Table 3. Pin Function Descriptions Pin Name Function Description DB(0:9) Data Input 10-Bit Data Input. MSB = DB(0:9). CLK Clock Clock Input. STSQ Start Sequence The state of STSQ is detected on the active edge of CLK. A new data loading sequence begins on the next active edge of CLK after STSQ is detected HIGH. The active CLK edge is the rising edge when E/O is held HIGH. It is the falling edge when E/O is held LOW. R/L Right/Left Select A new data loading sequence begins on the left with Channel 0 when this input is LOW, and on the right with Channel 5 when this input is HIGH. E/O Even/Odd Select The active CLK edge is the rising edge when this input is held HIGH and the falling edge when this input is held LOW. Data is loaded sequentially on the rising edges of CLK when this input is HIGH and on the falling edges when this input is LOW. XFR Data Transfer XFR is detected and a data transfer is initiated on a rising CLK edge when this input is held HIGH. Data is transferred to the video outputs on the next rising CLK edge after XFR is detected. VID0–VID5 Analog Outputs These pins are directly connected to the analog inputs of the LCD panel. V1, V2 Reference Voltages The voltage applied between these pins set the reference levels of the analog outputs. VREFHI, VREFLO Full-Scale References The voltage applied between these pins sets the full-scale output voltage. INV Invert When this pin is HIGH, the analog output voltages are above VMID. When LOW, the analog output voltages are below VMID. VMID is a hypothetical reference level set by the voltages applied to V1 and V2. VMID is equal to (V1 + V2)/2. DVCC Digital Power Supply Digital Power Supply. DGND Digital Supply Return This pin is normally connected to the analog ground plane. AVCCx Analog Power Supplies Analog Power Supplies. AGNDx Analog Supply Returns Analog Supply Returns. BYP Bypass A 0.1 µF capacitor connected between this pin and AGND ensures optimum settling time. STBY Standby When HIGH, the internal circuits are debiased and the power dissipation drops to a minimum. Rev. 0 | Page 6 of 16 AD8383 TIMING DIAGRAMS tCLK HIGH VTH = 1.65V tSKEW tSETUP tHOLD VTH = 1.65V DB(0:9) tSETUP VTH = 1.65V STSQ VTH = 1.65V XFR tHOLD 04513-0-003 CLK tCLK LOW Figure 3. Timing Diagram, Even Mode (E/O = HIGH) tCLK LOW CLK tCLK HIGH VTH = 1.65V tSKEW tSETUP tHOLD VTH = 1.65V DB(0:9) tSETUP STSQ VTH = 1.65V XFR tSETUP VTH = 1.65V tHOLD Figure 4. Timing Diagram, Odd Mode (E/O = LOW) Rev. 0 | Page 7 of 16 04513-0-004 tHOLD AD8383 THEORY OF OPERATION TRANSFER FUNCTION AND ANALOG OUTPUT VOLTAGE The DecDriver has two regions of operation: where the video output voltages are either above or below a reference voltage VMID, and where VMID = (V1 + V2)/2. The transfer function defines the analog output voltage as the function of the digital input code as follows: To best correlate transfer function errors to image artifacts, the overall accuracy of the DecDriver is defined by two parameters, VDE and VCME. VDE, the differential error voltage, measures the difference between the rms value of the output and the rms value of the ideal. The defining expression is n ⎞ VIDx(n) = V1 – VFS × ⎛⎜1 – ⎟ for INV = LOW ⎝ 1023 ⎠ VDE(n) = n ⎞ VIDx(n) = V 2 +VFS × ⎛⎜1 – ⎟ for INV = HIGH ⎝ 1023 ⎠ [VOUTN (n) − V 2] − [VOUTP(n) − V 1] − ⎛1 − 2 ⎜ ⎝ n ⎞ ⎟ × VFS 1023 ⎠ VCME, the common-mode error voltage, measures ½ the dc bias of the output. The defining expression is where n = input code VFS = 2 × (VREFHI – VREFLO) VCME(n) = A number of internal limits define the usable range of the analog output voltages, VIDx, as shown in Figure 5. 1 ⎡1 (VOUTN (n) +VOUTP(n))– V 1 + V 2 ⎤⎥ 2 ⎢⎣ 2 2 ⎦ AVCC ≥ 1.3V 2VREFHI–VREFLO V2 + VFS INV = HIGH VIDx (V) 0 ≤ VFS ≤ 5.5V 9V ≤ AVCC ≤ 18V V2 VMID = (V1+V2)/2 VMID 5V ≤ V2 ≤ (AVCC – 4) V1 0 ≤ VFS ≤ 5.5V 5V ≤ V1 ≤ (AVCC – 4) INV = LOW V1 – VFS 0 1023 INPUT CODE INTERNAL LIMITS AND USABLE VOLTAGE RANGES 04513-0-005 ≥ 1.3V AGND Figure 5. Transfer Function, VIDx vs. Input Code, Internal Limits and Usable Output Voltage Range Rev. 0 | Page 8 of 16 AD8383 APPLICATIONS The V1 and V2 inputs in these systems are tied together and are normally connected to VCOM, as shown in Figure 6. AVCC = 15.5V VZ = 5.1V AD8383 V2 VCOM 1 04513-0-006 V1 V2 = 8V 5 V+ V2 2 VCOM AD8132 VCOM = 7V Figure 6. Standard Connection Diagram AD8383 3 –IN 8 R2 = 1kΩ +IN V– 4 V1 = 6V V1 The transfer function of the AD8383 is shown in Figure 7 for V2 = V1 = VCOM. 04513-0-008 6 R1 = 6kΩ DVCC = 3.3V Figure 8. High Accuracy Reference Circuit VFS = 5V VFS = 4V VBIAS = 1V VCOM 820 VBIAS = 1V 1023 V2 VBIAS = 1V VCOM VBIAS = 1V 1023 VFS = 4V 04513-0-009 Figure 7. Output Transfer Function for Standard Connection THE AD8383, IN THE APPLICATIONS CIRCUIT SHOWN, TYPICALLY PRODUCES A SYMMETRICAL OUTPUT AT 85°C WHEN ITS SUPPLY, (V+) – (V–), IS AT 7.2V. EXTERNAL VBIAS GENERATION In systems that require improved brightness resolution and higher accuracy, the V1 and V2 inputs, connected to external voltage references, provide the necessary VBIAS while allowing the full code range to be used for gamma correction. V1 = VCOM – VBIAS V2 = VCOM + VBIAS To ensure a symmetrical ac driving voltage, the difference between V2 and VCOM must be equal to the difference between VCOM and V1. 8.75 7.50 6.25 5.00 (V2 + V1)/2 – VCOM (mV) V1 sets the white drive voltage while INV = LOW and V2 sets the white drive voltage while INV = HIGH. V1 and V2 are defined as Figure 9. Transfer Function for High Accuracy Reference Applications 3.75 TA = 25°C TA = 85°C 2.50 1.25 0.00 –1.25 –2.50 –3.75 –5.00 –6.25 TYPICAL ASYMMETRY AT THE OUTPUTS OF THE AD8383 VERSUS ITS POWER SUPPLY FOR THE APPLICATION CIRCUIT –7.50 –8.75 5.7 (V2 – VCOM) = (VCOM – V1) 6.2 6.7 7.2 7.7 8.2 V+ – The circuit in Figure 8 ensures symmetry to within 1 mV with a minimum component count. Bypass capacitors are not shown for clarity. The transfer function and the input symmetry error of the AD8383 are shown in Figure 9 when the circuit of Figure 8 is used to generate VBIAS. Rev. 0 | Page 9 of 16 V– 8.7 9.2 9.7 10.2 10.7 (V) Figure 10. Accuracy for High Accuracy Reference Applications 04513-0-010 RESERVED CODE RANGE 04513-0-007 VFS = 5V V1 AD8383 PCB DESIGN FOR GOOD THERMAL PERFORMANCE THERMAL PAD DESIGN The total maximum power dissipation of the AD8383 is partly dependent on load. In a 6-channel 60 Hz XGA system running at a 65 MHz clock rate, the total maximum power dissipation is 1.08 W at an LCD panel input capacitance of 150 pF. Thermal performance of the AD8383 varies logarithmically with the contact area between the exposed thermal paddle and the thermal pad on the top layer of the PCB. See Figure 11. At the maximum specified clock rate of 100 Ms/s, the total maximum power dissipation can exceed 2 W for large capacitive loads, as shown in Table 4. The AD8383’s LFCSP package is designed to provide superior thermal characteristics, partly achieved by an exposed die paddle on the bottom surface of the package. In order to take full advantage of this feature, the exposed paddle must be in direct thermal contact with the PCB, which then serves as a heat sink. A thermally effective PCB must incorporate a thermal pad and a thermal via structure. The thermal pad provides a solderable contact surface on the top surface of the PCB. The thermal via structure provides a thermal path to the inner and bottom layers of the PCB to remove heat. In order to minimize thermal performance degradation of production PCBs, the contact area between the thermal pad and the PCB should be maximized. Therefore, the size of the thermal pad should match the exposed 5.25 mm × 5.25 mm paddle size. However, if the PCB design rules require a pad-topad clearance of more than 0.3 mm, the size of the thermal pad may be reduced to 5 mm × 5 mm. Additionally, a second thermal pad of the same size should be placed on the bottom side of the PCB. At least one thermal pad should be in direct thermal (and electrical) contact with the AVCC plane. 50 45 θJA (°C/W) Although the maximum safe operating junction temperature is higher, the AD8383 is 100% tested at a junction temperature of 125°C. Consequently, the maximum guaranteed operating junction temperature is 125°C. To limit the maximum junction temperature at or below the guaranteed maximum, the package, in conjunction with the PCB, must effectively conduct heat away from the junction. The θJA (of the AD8383 mounted on a standard JEDEC PCB) is reduced by approximately 40% as the contact area increases from 0% (no thermal pad) to 50%. It approaches its specified value as the contact area (on the JEDEC standard PCB) approaches 100%. 40 35 25 0 25 50 75 100 CONTACT AREA (%) Figure 11. Thermal Performance vs. Contact Area (on a JEDEC PCB) Table 4. Power Dissipation vs. Load Capacitance and VFS at 100 Ms/s Clock Rate CLOAD (pF) 150 200 250 300 PQUIESCENT (W) 0.7 0.7 0.7 0.7 PDYNAMIC (W) 0.72 0.96 1.20 1.44 VFS = 5 V PTOTAL (W) 1.42 1.66 1.90 2.14 Rev. 0 | Page 10 of 16 PDYNAMIC (W) 0.58 0.77 0.96 1.15 VFS = 4 V PTOTAL (W) 1.28 1.47 1.66 1.85 04513-0-011 30 AD8383 THERMAL VIA STRUCTURE DESIGN REFERENCE PCB DESIGN Effective heat transfer from the top to the inner and bottom layers of the PCB requires thermal vias incorporated into the thermal pad design. Thermal performance increases logarithmically with the number of vias, as shown in Figure 12. With the AD8383 on a standard JEDEC PCB, θJA reaches its specified value when a total of 16 vias are used. At a via count above 36, θJA approaches its optimum value as the slope of the curve approaches zero. The top copper layer is shown in Figure 13. 7 mm 7 mm 32 28 04513-0-013 θJA (°C/W) 30 26 Figure 13. Recommended PCB Landing 24 The bottom thermal pad forms AVCC plane. 0 10 20 30 04513-0-012 22 40 NUMBER OF VIAS Figure 12. Thermal Performance vs. Number of Vias (on a JEDEC PCB) Near optimum thermal performance of production PCBs is attained when the number of vias is at least 36. SOLDER MASKING To minimize the formation of solder voids due to solder flowing into the via holes (solder wicking), the via diameter should be small. Solder masking of the via holes on the top layer of the PCB plugs the via holes, inhibiting solder flow into the holes. To optimize the thermal pad coverage, the solder mask diameter should be no more than 0.1 mm larger than the via diameter. Thermal Pads Top PCB Layer: Bottom PCB Layer: 5.25 mm × 5.25 mm 5.25 mm × 5.25 mm Thermal via structure Diameter: 0.25 mm Number of vias: 41 Via Grid Pitch: 0.5 mm Miscellaneous Perimeter Pads: Solder Mask Swell: Rev. 0 | Page 11 of 16 0.5 mm × 0.25 mm 0.02 mm AD8383 θ θJB, ψJB θ, ψ θAIR-CASE θJC AD8383 TCASE θPCB θJC-BOTTOM P C TJ CAIR-CASE CJC-BOTTOM CPCB θAIR-PCB TPCB TA CAIR-PCB TAMBIENT 04513-0-014 CJC PCB Figure 14. Thermal Equivalent Circuit ESTIMATED JUNCTION TEMPERATURE Assuming no heat flows through the sides of the AD8383 package, heat flow from the AD8383 is through two paths. While part of the total heat generated dissipates through the top of the case, the remainder flows into the PCB to be dissipated. Assuming there is no other heat-generating component near the AD8383, the thermal equivalent circuit of a system that consists of one AD8383 mounted on a PCB is shown in Figure 14. Junction Temperature and Maximum Power Dissipation In a thermal steady state represented by the simplified schematic shown in Figure 15, heat flow from the die is partly through the top of the case, causing a temperature drop (TJ – TCASE), and partly through the PCB, causing a temperature drop (TJ – TPCB). The junction temperature is calculated as follows: P = PCASE + PPCB = The thermal resistance of the top of the case, θJC, is constant, independent of the system variables, and well defined. θJC depends on the thermal resistance of the molding compound. The thermal resistance of the system, θJA, is system dependent and therefore cannot be properly estimated. Although it is traditional to provide the thermal resistance of a JEDEC reference system in the data sheet, its value may not be appropriate for all systems and may result in large errors (>>25%). The thermal resistance of production PCBs, θJC, depends largely on the particular PCB design, and, to some extent, the environmental conditions specific to the particular system. Although θJB is traditionally not provided on data sheets, a thermal characterization parameter, ψJB, of a JEDEC reference system is gaining increasing acceptance. When the PCB thermal design near the AD8383 closely approximates the PCB of the JEDEC reference system, θJA approaches ψJB. For thermally enhanced packages, the thermal resistance of the exposed thermal paddle, θJC-BOTTOM, is very low and may therefore be ignored. TJ = (TJ − TCASE ) (TJ − TPCB) + θJC θPCB θJCθPCBP + θPCB TCASE + θJCTPCB θJC + θPCB where: TJ is the junction temperature TCASE is the temperature of the top of the case (near the output pins for the AD8383) TPCB is the PCB temperature on the solder side (directly under the AD8383) P is the total power dissipated by the AD8383 θJC is the thermal resistance of the top of the case θPCB is the thermal resistance of the PCB At a given maximum allowed junction temperature, the maximum allowed power dissipation is TCASE TPCB ⎤ ⎡ (θJC + θPCB ) − PMAX = ⎢ TJMAX − θJC θPCB ⎥⎦ ⎣ θJCθPCB For a thermally optimized PCB, θJC can be replaced with ψPCB and the equation can be rewritten as ⎡ (θJC + ψPCB ) TCASE TPCB ⎤ TJMAX − PMAX = ⎢ − ⎥ θJC ψPCB ⎦ ⎣ θJCψPCB Rev. 0 | Page 12 of 16 AD8383 P PPCB Power-Up and Power-Down Sequencing PC As indicated in the Absolute Maximum Ratings, the voltage at any input pin cannot exceed its supply voltage by more than 0.5 V. To ensure compliance with the Absolute Maximum Ratings, power-up and power-down sequencing may be required. TJ θPCB θJC TPCB TCASE θAIR-CASE TA P During power-down, the voltage at any input pin must reach zero during a period not exceeding the hold-up time of the power supply. 04513-0-015 θAIR-PCB During power-up, initial application of nonzero voltages to any of the input pins must be delayed until the supply voltage ramps up to at least the highest maximum operational input voltage. Failure to comply with the Absolute Maximum Ratings may result in functional failure or damage to the internal ESD diodes. Figure 15. Simplified Thermal Equivalent Circuit Verification of the Maximum Operating Junction Temperature In order to verify the system thermal design for compliance with the maximum operating junction temperature specification, temperature measurements TCASE and TPCB are required at the maximum possible total power dissipation in a complete, fully assembled LCD projection system. Maximum possible total power dissipation of the AD8383 occurs when the video input to the projector is a pattern with 1-pixel-wide white and black vertical lines. An alternative pattern that results in the maximum possible total power dissipation is a 1-pixel checkerboard pattern. The expected total power dissipation of the AD8383 in a 60 Hz, 6-channel XGA projector displaying the 1-pixel-wide vertical line or checkerboard pattern is 1.08 W (at AVCC = 15.5 V, VCOM = 7 V, and LCD capacitance = 150 pF). Although the case and PCB temperatures are highly dependent on the PCB design, their measured values are expected to be similar at approximately 40°C above the ambient (on a typical PCB with a minimal airflow whose thermal design follows the recommendations described in this note). The junction temperature then calculates to approximately 10°C above the case and PCB temperatures. At a 70°C ambient temperature, the junction temperature is expected to be at approximately 120°C. The AD8383 has a relatively small thermal mass. In order to minimize measurement errors due to the thermal mass of the measuring device, a small-gauge thermocouple or a thermal probe with a very small thermal mass is required for the measurement of TCASE and TPCB. Damaged ESD diodes may cause temporary parametric failures, which may result in image artifacts. Damaged ESD diodes cannot provide full ESD protection, thus reducing reliability. The recommended sequence is Power ON 1. Apply power to supplies. 2. Apply power to other I/Os. Power OFF 1. Remove power from I/Os. 2. Remove power from supplies. VBIAS Generation—V1, V2 Input Pin Functionality In order to avoid image flicker, a bias voltage of approximately 1 V minimum must be maintained across the pixels of HTPS LCDs. The AD8383 provides two methods of maintaining this bias voltage. Internal Bias Voltage Generation Standard systems that internally generate the bias voltage reserve the upper-most code range for the bias voltage and use the remaining code range to encode the video for gamma correction. Rev. 0 | Page 13 of 16 AD8383 OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR 6.75 BSC SQ TOP VIEW 0.30 0.23 0.18 PIN 1 INDICATOR 48 1 5.25 5.10 SQ 4.95 BOTTOM VIEW 0.50 0.40 0.30 25 24 12 13 0.25 MIN 1.00 0.85 0.80 5.50 REF 0.80 MAX 0.65 TYP 12° MAX 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 16. 48-Lead Frame Chip Scale Package [LFCSP] (CP-48) Dimensions shown in millimeters ORDERING GUIDE Model AD8383ACPZ9 9 Temperature Range 0°C to 85°C Package Description 48-Lead LFCSP Z = Pb-free part. Rev. 0 | Page 14 of 16 Package Option CP-48 AD8383 NOTES Rev. 0 | Page 15 of 16 AD8383 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03191–0–1/04(0) Rev. 0 | Page 16 of 16