8-Channel DAC with PLL, 192 kHz, 24 Bits AD1934 FEATURES GENERAL DESCRIPTION PLL generated or direct master clock Low EMI design 108 dB DAC dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz to 192 kHz sample rates Single-ended DAC output Log volume control with autoramp function SPI® controllable for flexibility Software-controllable clickless mute Software power-down Right-justified, left-justified, I2S and TDM modes Master and slave modes up to 16-channel in/out 48-lead LQFP The AD1934 is a high performance, single-chip that provides eight digital-to-analog converters (DACs) with single-ended output using the Analog Devices, Inc. patented multibit sigmadelta (Σ-Δ) architecture. An SPI port is included, allowing a microcontroller to adjust volume and many other parameters. The AD1934 operates from 3.3 V digital and analog supplies. The AD1934 is available in a 48-lead (single-ended output) LQFP. Other members of this family include a differential DAC output and I2C® control port version. The AD1934 is designed for low EMI. This consideration is apparent in both the system and circuit design architectures. By using the on-board PLL to derive the master clock from the LR clock or from an external crystal, the AD1934 eliminates the need for a separate high frequency master clock and can also be used with a suppressed bit clock. The digital-to-analog converters are designed using the latest ADI continuous time architectures to further minimize EMI. By using 3.3 V supplies, power consumption is minimized, further reducing emissions. APPLICATIONS Automotive audio systems Home theater systems Set-top boxes Digital audio effects processors FUNCTIONAL BLOCK DIAGRAM AD1934 DAC DAC DAC DIGITAL FILTER AND VOLUME CONTROL CLOCKS DIGITAL AUDIO INPUT/OUTPUT SERIAL DATA PORT SDATAIN DAC DAC ANALOG AUDIO OUTPUTS DAC TIMING MANAGEMENT AND CONTROL (CLOCK AND PLL) DAC DAC CONTROL PORT I2C/SPI CONTROL DATA INPUT/OUTPUT 6.144MHz 06106-001 PRECISION VOLTAGE REFERENCE Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. All rights reserved. AD1934 TABLE OF CONTENTS Features .............................................................................................. 1 Digital-to-Analog Converters (DACs) .................................... 12 Applications....................................................................................... 1 Clock Signals............................................................................... 12 General Description ......................................................................... 1 Reset and Power-Down ............................................................. 12 Functional Block Diagram .............................................................. 1 Serial Control Port ..................................................................... 13 Revision History ............................................................................... 2 Power Supply and Voltage Reference....................................... 14 Specifications..................................................................................... 3 Serial Data Ports—Data Format............................................... 14 Test Conditions............................................................................. 3 Time-Division Multiplexed (TDM) Modes............................ 14 Analog Performance Specifications ........................................... 3 Daisy-Chain Mode ..................................................................... 16 Crystal Oscillator Specifications................................................. 4 Control Registers ............................................................................ 20 Digital Input/Output Specifications........................................... 4 Definitions................................................................................... 20 Power Supply Specifications........................................................ 5 PLL and Clock Control Registers............................................. 20 Digital Filters................................................................................. 6 DAC Control Registers .............................................................. 21 Timing Specifications .................................................................. 6 Auxiliary TDM Port Control Registers ................................... 23 Absolute Maximum Ratings............................................................ 8 Additional Modes....................................................................... 23 Thermal Resistance ...................................................................... 8 Application Circuits ....................................................................... 25 ESD Caution.................................................................................. 8 Outline Dimensions ....................................................................... 26 Pin Configuration and Function Descriptions............................. 9 Ordering Guide .......................................................................... 26 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 12 REVISION HISTORY 6/07—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD1934 SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply Voltages (AVDD, DVDD) Temperature Range 1 Master Clock Input Sample Rate Measurement Bandwidth Word Width Load Capacitance (Digital Output) Load Current (Digital Output) Input Voltage HI Input Voltage LO 1 3.3 V As specified in Table 1 and Table 2 12.288 MHz (48 kHz fS, 256 × fS mode) 48 kHz 20 Hz to 20 kHz 24 bits 20 pF ±1 mA or 1.5 kΩ to ½ DVDD supply 2.0 V 0.8 V Functionally guaranteed at −40°C to +125°C case temperature. ANALOG PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). Table 1. Parameter DIGITAL-TO-ANALOG CONVERTERS Dynamic Range No Filter (RMS) With A-Weighted Filter (RMS) With A-Weighted Filter (Average) Total Harmonic Distortion + Noise Single-Ended Version Full-Scale Output Voltage Gain Error Interchannel Gain Mismatch Offset Error Gain Drift Interchannel Isolation Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output Conditions/Comments Min Typ 98 100 104 106 108 Max Unit 20 Hz to 20 kHz, −60 dB input 0 dBFS Two channels running Eight channels running −92 −86 0.88 (2.48) −10 −0.2 −16 −30 −4 dB dB dB −75 +10 +0.2 +16 +30 100 0 0.375 95 ±0.6 100 FILTR pin FILTR pin CM pin 1.32 Rev. 0 | Page 3 of 28 1.50 1.50 1.50 1.68 dB dB V rms (V p-p) % dB mV ppm/°C dB Degrees dB dB dB Ω V V V AD1934 Specifications measured at 130°C (case). Table 2. Parameter DIGITAL-TO-ANALOG CONVERTERS Dynamic Range No Filter (RMS) With A-Weighted Filter (RMS) With A-Weighted Filter (Average) Total Harmonic Distortion + Noise Single-Ended Version Full-Scale Output Voltage Gain Error Interchannel Gain Mismatch Offset Error Gain Drift REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output Conditions/Comments Min Typ 98 100 104 106 108 Max Unit 20 Hz to 20 kHz, −60 dB input 0 dBFS Two channels running Eight channels running −92 −86 0.8775 (2.482) −10 −0.2 −16 −30 FILTR pin FILTR pin CM pin 1.32 −4 1.50 1.50 1.50 dB dB dB −70 +10 +0.2 +16 +30 1.68 dB dB V rms (V p-p) % dB mV ppm/°C V V V CRYSTAL OSCILLATOR SPECIFICATIONS Table 3. Parameter Transconductance Min Typ 3.5 Max Unit Mmhos DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C < TA < +130°C, DVDD = 3.3 V ± 10%. Table 4. Parameter Input Voltage HI (VIH) Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage High Level Output Voltage (VOH) Low Level Output Voltage (VOL) Input Capacitance Conditions/Comments MCLKI pin IIH @ VIH = 2.4 V IIL @ VIL = 0.8 V IOH = 1 mA IOL = 1 mA Rev. 0 | Page 4 of 28 Min 2.0 2.2 Typ Max 0.8 10 10 DVDD − 0.60 0.4 5 Unit V V V μA μA V V pF AD1934 POWER SUPPLY SPECIFICATIONS Table 5. Parameter SUPPLIES Voltage Digital Current Normal Operation Power-Down Analog Current Normal Operation Power-Down DISSIPATION Operation All Supplies Digital Supply Analog Supply Power-Down, All Supplies POWER SUPPLY REJECTION RATIO Signal at Analog Supply Pins Conditions/Comments Min Typ Max Unit DVDD AVDD MCLK = 256 fS fS = 48 kHz fS = 96 kHz fS = 192 kHz fS = 48 kHz to 192 kHz 3.0 3.0 3.3 3.3 3.6 3.6 V V 56 65 95 2.0 mA mA mA mA 74 23 mA mA 429 185 244 83 mW mW mW mW 50 50 dB dB MCLK = 256 fS, 48 kHz 1 kHz, 200 mV p-p 20 kHz, 200 mV p-p Rev. 0 | Page 5 of 28 AD1934 DIGITAL FILTERS Table 6. Parameter DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay Mode Factor Min 48 kHz mode, typ @ 48 kHz 96 kHz mode, typ @ 96 kHz 192 kHz mode, typ @ 192 kHz 48 kHz mode, typ @ 48 kHz 96 kHz mode, typ @ 96 kHz 192 kHz mode, typ @ 192 kHz 48 kHz mode, typ @ 48 kHz 96 kHz mode, typ @ 96 kHz 192 kHz mode, typ @ 192 kHz 48 kHz mode, typ @ 48 kHz 96 kHz mode, typ @ 96 kHz 192 kHz mode, typ @ 192 kHz 48 kHz mode, typ @ 48 kHz 96 kHz mode, typ @ 96 kHz 192 kHz mode, typ @ 192 kHz 48 kHz mode, typ @ 48 kHz 96 kHz mode, typ @ 96 kHz 192 kHz mode, typ @ 192 kHz 0.4535 fS 0.3646 fS 0.3646 fS 35 Typ Max Unit 22 kHz kHz kHz dB dB dB kHz kHz kHz kHz kHz kHz dB dB dB μs μs μs 70 ±0.01 ±0.05 ±0.1 0.5 fS 0.5 fS 0.5 fS 0.5465 fS 0.6354 fS 0.6354 fS 24 48 96 26 61 122 70 70 70 25/fS 11/fS 8/fS 521 115 42 TIMING SPECIFICATIONS −40°C < TA < +130°C, DVDD = 3.3 V ± 10%. Table 7. Parameter INPUT MASTER CLOCK (MCLK) AND RESET tMH Condition Comments Min Max Unit MCLK duty cycle DAC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, 768 fS DAC clock source = direct MCLK @ 512 fS (bypass on-chip PLL) PLL mode, 256 fS reference Direct 512 fS mode 40 60 % 40 60 % 6.9 13.8 27.6 MHz MHz ns tMCLK 10 60 ms % tMH fMCLK fMCLK tPDR tPDRR PLL Lock Time 256 fS VCO Clock, Output Duty Cycle MCLKO Pin SPI PORT tCCH tCCL fCCLK tCDS tCDH tCLS tCLH tCLHIGH tCOE tCOD tCOH tCOTS MCLK frequency RST low RST recovery Reset to active output 15 4096 MCLK and LRCLK input 40 See Figure 9 CCLK high CCLK low CCLK frequency CDATA setup CDATA hold CLATCH setup CLATCH hold CLATCH high COUT enable COUT delay COUT hold COUT tri-state 35 35 fCCLK = 1/tCCP, only tCCP shown in Figure 9 To CCLK rising From CCLK rising To CCLK rising From CCLK falling Not shown in Figure 9 From CCLK falling From CCLK falling From CCLK falling, not shown in Figure 9 From CCLK falling Rev. 0 | Page 6 of 28 10 10 10 10 10 10 30 30 30 30 ns ns MHz ns ns ns ns ns ns ns ns ns AD1934 Parameter DAC SERIAL PORT tDBH tDBL tDLS tDLH tDLS tDDS tDDH AUXTDM SERIAL PORT tABH tABL tALS tALH tALS tDDS tDDH AUXILIARY INTERFACE tDXDD tXBH tXBL tDLS tDLH Condition DBCLK high DBCLK low DLRCLK setup DLRCLK hold DLRCLK skew DSDATA setup DSDATA hold AUXTDMBCLK high AUXTDMBCLK low AUXTDMLRCLK setup AUXTDMLRCLK hold AUXTDMLRCLK skew DSDATA setup DSDATA hold AUXDATA delay AUXBCLK high AUXBCLK low AUXLRCLK setup AUXLRCLK hold Comments See Figure 16 Slave mode Slave mode To DBCLK rising, slave mode From DBCLK rising, slave mode From DBCLK falling, master mode To DBCLK rising From DBCLK rising See Figure 17 Slave mode Slave mode To AUXTDMBCLK rising, slave mode From AUXTDMBCLK rising, slave mode From AUXTDMBCLK falling, master mode To AUXTDMBCLK, not shown in Figure 17 From AUXTDMBCLK rising, not shown in Figure 17 Min 10 10 10 5 −8 10 5 10 10 10 5 −8 10 5 From AUXBCLK falling To AUXBCLK rising From AUXBCLK rising Rev. 0 | Page 7 of 28 Max +8 +8 18 10 10 10 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns AD1934 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Rating −0.3 V to +3.6 V −0.3 V to +3.6 V ±20 mA –0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V −40°C to +125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. θJA represents thermal resistance, junction-to-ambient; θJC represents the thermal resistance, junction-to-case. All characteristics are for a 4-layer board. Table 9. Thermal Resistance Package Type 48-Lead LQFP ESD CAUTION Rev. 0 | Page 8 of 28 θJA 50.1 θJC 17 Unit °C/W AD1934 AVDD LF NC NC NC NC NC NC NC NC CM AVDD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 36 AGND 2 35 FILTR 3 34 AGND AGND 4 33 AVDD AVDD 5 AD1934 32 AGND OL3 6 31 OR2 OR3 7 TOP VIEW (Not to Scale) 30 OL2 OL4 8 29 OR1 OR4 9 28 OL1 PD/RST 10 27 CLATCH/ADR1 DSDATA4 11 26 CCLK/SCL DGND 12 25 DGND 18 19 20 21 22 23 24 NC AUXTDMBCLK AUXTDMLRCLK CIN/ADR0 COUT/SDA DSDATA2 17 AUXDATA1 DVDD 16 DLRCLK 15 DBCLK 14 DSDATA1 13 DSDATA3 NC = NO CONNECT SINGLE-ENDED OUTPUT 06106-020 MCLKI/XI MCLKO/XO Figure 2. Pin Configuration Table 10. Pin Function Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 In/Out I I O I I O O O O I I/O I I I/O I/O I I/O I/O O I/O I/O I I/O I Mnemonic AGND MCLKI/XI MCLKO/XO AGND AVDD OL3 OR3 OL4 OR4 PD/RST DSDATA4 DGND DVDD DSDATA3 DSDATA2 DSDATA1 DBCLK DLRCLK AUXDATA1 NC AUXTDMBCLK AUXTDMLRCLK CIN/ADR0 COUT/SDA DGND Description Analog Ground. Master Clock Input/Crystal Oscillator Input. Master Clock Output/Crystal Oscillator Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. DAC 3 Left Output. DAC 3 Right Output. DAC 4 Left Output. DAC 4 Right Output. Power-Down Reset (Active Low). DAC Input 4 (Input to DAC 4 L and R)/DAC TDM Data Out 2. Digital Ground. Digital Power Supply. Connect to digital 3.3 V supply. DAC Input 3 (Input to DAC 3 L and R)/DAC TDM Data In 2/Aux DAC 2 Data Output. DAC Input 2 (Input to DAC 2 L and R)/DAC TDM Data Out 1. DAC Input 1 (Input to DAC 1 L and R)/DAC TDM Data In 1. Bit Clock for DACs (Regular Stereo, TDM or Daisy-Chain TDM Mode). LR Clock for DACs (Regular Stereo, TDM or Daisy-Chain TDM Mode). Auxiliary Data Out 1 (to External DAC 1, Auxiliary Mode Only). No Connect. Auxiliary Mode Only DAC TDM Bit Clock. Auxiliary Mode Only DAC LR TDM Clock. Control Data Input (SPI). Control Data Output (SPI). Digital Ground. Rev. 0 | Page 9 of 28 AD1934 Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 to 46 47 48 In/Out I I O O O O I I I O I I O O I Mnemonic CCLK/SCL CLATCH/ADR1 OL1 OR1 OL2 OR2 AGND AVDD AGND FILTR AGND AVDD CM NC LF AVDD Description Control Clock Input (SPI). Latch Input for Control Data (SPI). DAC 1 Left Output. DAC 1 Right Output. DAC 2 Left Output. DAC 2 Right Output. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. Analog Ground. Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND. Analog Ground. Analog Power Supply. Connect to analog 3.3 V supply. Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND. Must Be Tied to Common Mode, Pin 38. Alternately, ac-coupled to ground. PLL Loop Filter. Return to AVDD. Analog Power Supply. Connect to analog 3.3 V supply. Rev. 0 | Page 10 of 28 AD1934 TYPICAL PERFORMANCE CHARACTERISTICS 0.06 0 MAGNITUDE (dB) MAGNITUDE (dB) 0.04 0.02 0 –0.02 –50 –100 –150 8 0 16 24 FREQUENCY (kHz) 06106-004 –0.06 0 24 48 72 96 FREQUENCY (kHz) 06106-007 –0.04 Figure 6. DAC Stop-Band Filter Response, 96 kHz Figure 3. DAC Pass-Band Filter Response, 48 kHz 0.5 0 0.4 0.2 MAGNITUDE (dB) MAGNITUDE (dB) 0.3 –50 –100 0.1 0 –0.1 –0.2 –0.3 12 24 36 48 FREQUENCY (kHz) –0.5 06106-005 0 0 8 16 32 06106-008 –0.4 –150 64 FREQUENCY (kHz) Figure 7. DAC Pass-Band Filter Response, 192 kHz Figure 4. DAC Stop-Band Filter Response, 48 kHz 0.10 0 –2 MAGNITUDE (dB) 0 –0.05 –6 0 24 48 72 FREQUENCY (kHz) 96 Figure 5. DAC Pass-Band Filter Response, 96 kHz –10 48 64 80 FREQUENCY (kHz) Figure 8. DAC Stop-Band Filter Response, 192 kHz Rev. 0 | Page 11 of 28 96 06106-009 –0.10 –4 –8 06106-006 MAGNITUDE (dB) 0.05 AD1934 THEORY OF OPERATION DIGITAL-TO-ANALOG CONVERTERS (DACs) The AD1934 DAC channels are arranged as single-ended, four stereo pairs giving eight analog outputs for minimum external components. The DACs include on-board digital reconstruction filters with 70 dB stop-band attenuation and linear phase response, operating at an oversampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz mode). Each channel has its own independently programmable attenuator, adjustable in 255 steps in increments of 0.375 dB. Digital inputs are supplied through four serial data input pins (one for each stereo pair) and a common frame (DLRCLK) and bit (DBCLK) clock. Alternatively, one of the TDM modes can be used to access up to 16 channels on a single TDM data line. Each output pin has a nominal common-mode dc level of 1.5 V and swings ±1.27 V for a 0 dBFS digital input signal. A single op amp, third-order, external, low-pass filter is recommended to remove high frequency noise present on the output pins. The use of op amps with low slew rate or low bandwidth can cause high frequency noise and tones to fold down into the audio band; therefore, exercise care in selecting these components. The voltage at CM, the common-mode reference pin, can be used to bias the external op amps that buffer the output signals (see the Power Supply and Voltage Reference section). CLOCK SIGNALS The on-chip phase locked loop (PLL) can be selected to reference the input sample rate from either of the LRCLK pins or 256, 384, 512, or 768 times the sample rate, referenced to the 48 kHz mode from the MCLKI pin. The default at power-up is 256 × fS from MCLKI pin. In 96 kHz mode, the master clock frequency stays at the same absolute frequency; therefore, the actual multiplication rate is divided by 2. In 192 kHz mode, the actual multiplication rate is divided by 4. For example, if a device in the AD1934 family is programmed in 256 × fS mode, the frequency of the master clock input is 256 × 48 kHz = 12.288 MHz. If the AD1934 is then switched to 96 kHz operation (by writing to the SPI or I2C port), the frequency of the master clock should remain at 12.288 MHz, which is now 128 × fS. In 192 kHz mode, this becomes 64 × fS. The PLL can be powered down in PLL and Clock Control 0 Register. To ensure reliable locking when changing PLL modes, or if the reference clock is unstable at power-on, power down the PLL and then power it back up when the reference clock has stabilized. The internal MCLK can be disabled in PLL and Clock Control 0 Register to reduce power dissipation when the AD1934 is idle. The clock should be stable before it is enabled. Unless a standalone mode is selected (see the Serial Control Port section), the clock is disabled by reset and must be enabled by writing to the SPI or I2C port for normal operation. To maintain the highest performance possible, it is recommended that the clock jitter of the internal master clock signal be limited to less than 300 ps rms time interval error (TIE). Even at these levels, extra noise or tones can appear in the DAC outputs if the jitter spectrum contains large spectral peaks. If the internal PLL is not being used, it is highly recommended that an independent crystal oscillator generate the master clock. In addition, it is especially important that the clock signal not be passed through an FPGA, CPLD, or other large digital chip (such as a DSP) before being applied to the AD1934. In most cases, this induces clock jitter due to the sharing of common power and ground connections with other unrelated digital output signals. When the PLL is used, jitter in the reference clock is attenuated above a certain frequency depending on the loop filter. RESET AND POWER-DOWN Reset sets all the control registers to their default settings. To avoid pops, reset does not power down the analog outputs. After reset is deasserted, and the PLL acquires lock condition, an initialization routine runs inside the AD1934. This initialization lasts for approximately 256 MCLKs. The power-down bits in the PLL and Clock Control 0 and DAC Control 1 registers power down the respective sections. All other register settings are retained. To guarantee proper startup, the reset pin should be pulled low by an external resistor. The internal clock for the DACs varies by mode: 512 × fS (48 kHz mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By default, the on-board PLL generates this internal master clock from an external clock. A direct 512 × fS (referenced to 48 kHz mode) master clock can be used for DACs if selected in PLL and Clock Control 1 Register. Rev. 0 | Page 12 of 28 AD1934 SERIAL CONTROL PORT The AD1934 has an SPI control port that permits programming and reading back of the internal control registers for the DACs and clock system. There is also a standalone mode available for operation without serial control that is configured at reset using the serial control pins. All registers are set to default, except the internal MCLK enable which is set to 1. Standalone mode only supports stereo mode with I2S data format and 256 fS master clock rate. Table 11 shows the SPI control port pins logic state when configured in standalone and SPI software control mode. All four SPI control port pins need to be set to logic low for standalone operation (see Table 11).It is recommended to use a weak pull-up resistor on CLATCH in applications that have a microcontroller. This pull-up resistor ensures that the AD1934 recognizes the presence of a microcontroller. The SPI control port of the AD1934 is a 4-wire serial control port. The format is similar to the Motorola SPI format except the input data-word is 24 bits wide. The serial bit clock and latch can be completely asynchronous to the sample rate of the DACs. Figure 9 shows the format of the SPI signal. The first byte is a global address with a read/write bit. For the AD1934, the address is 0x04, shifted left 1 bit due to the R/W bit. The second byte is the AD1934 register address and the third byte is the data. Table 11. SPI vs. Standalone Mode Configuration Codec Control COUT CIN CLATCH CCLK SPI Standalone OUT 0 IN 0 1 (Pull-Up) 0 IN 0 tCLS tCCH tCCL tCCP CLATCH tCLH tCOTS CCLK tCDS tCDH COUT D23 D22 D9 tCOE D9 D8 D0 D8 D0 06106-010 CIN tCOD Figure 9. Format of SPI Signal Rev. 0 | Page 13 of 28 AD1934 POWER SUPPLY AND VOLTAGE REFERENCE All digital inputs are compatible with TTL and CMOS levels. All outputs are driven from the 3.3 V DVDD supply and are compatible with TTL and 3.3 V CMOS levels. The DAC internal voltage reference (VREF) is brought out on FILTR and should be bypassed as close as possible to the chip, with a parallel combination of 10 μF and 100 nF. Any external current drawn should be limited to less than 50 μA. The internal reference can be disabled in PLL and Clock Control 1 Register and FILTR can be driven from an external source. This can be used to scale the DAC output to the clipping level of a power amplifier based on its power supply voltage. The CM pin is the internal common-mode reference. It should be bypassed as close as possible to the chip, with a parallel combination of 47 μF and 100 nF. This voltage can be used to bias external op amps to the common-mode voltage of the input and output signal pins. The output current should be limited to less than 0.5 mA source and 2 mA sink. SERIAL DATA PORTS—DATA FORMAT The eight DAC channels use a common serial bit clock (DBCLK) and a common left-right framing clock (DLRCLK) in the serial data port. The clock signals are all synchronous with the sample rate. The normal stereo serial modes are shown in Figure 15. The DAC serial data modes default to I2S. The ports can also be programmed for left-justified, right-justified, and TDM modes. The word width is 24 bits by default and can be programmed for 16 or 20 bits. The DAC serial formats are programmable according to DAC Control 0 Register. The polarity of the DBCLK and DLRCLK is programmable according to DAC Control 1 Register. The auxiliary TDM port is also provided for applications requiring more than eight DAC channels. In this mode, the AUXTDMLRCLK and AUXTDMBCLK pins are configured as TDM port clocks. In regular TDM mode, the DLRCLK and DBCLK pins are used as the TDM port clocks. The auxiliary TDM serial port’s format and its serial clock polarity is programmable according to the Auxiliary TDM Port Control 0 Register and Control 1 Register. Both DAC and auxiliary TDM serial ports are programmable to become the bus masters according to DAC Control 1 Register and auxiliary TDM Control 1 Register. By default, both auxiliary TDM and DAC serial ports are in the slave mode. TIME-DIVISION MULTIPLEXED (TDM) MODES The AD1934 serial ports also have several different TDM serial data modes. The most commonly used configuration is shown in Figure 10. In Figure 10, the eight on-chip DAC data slots are packed into one TDM stream. In this mode, DBCLK is 256 fS. The I/O pins of the serial ports are defined according to the serial mode selected. For a detailed description of the function of each pin in TDM and AUX Modes, see Table 12. The AD1934 allows systems with more than eight DAC channels to be easily configured by the use of an auxiliary serial data port. The DAC TDM-AUX mode is shown in Figure 11. In this mode, the AUX channels are the last four slots of the 16-channel TDM data stream. These slots are extracted and output to the AUX serial port. One major difference between the TDM mode and an auxiliary TDM mode is the assignment of the TDM port pins, as shown in Table 12. In auxiliary TDM mode, DBCLK and DLRCLK are assigned as the auxiliary port clocks, and AUXTDMBCLK and AUXTDMLRCLK are assigned as the TDM port clocks. In regular TDM or 16-channel, daisy-chain TDM mode, the DLRCLK and DBCLK pins are set as the TDM port clocks. It should be noted that due to the high AUXTDMBCLK frequency, 16-channel auxiliary TDM mode is available only in the 48 kHz/44.1 kHz/32 kHz sample rate. LRCLK 256 BCLKs BCLK DATA Rev. 0 | Page 14 of 28 32 BCLK SLOT 1 LEFT 1 SLOT 2 RIGHT 1 SLOT 3 LEFT 2 SLOT 4 RIGHT 2 SLOT 5 LEFT 3 SLOT 6 RIGHT 3 SLOT 7 LEFT 4 SLOT 8 RIGHT 4 LRCLK BCLK MSB MSB–1 MSB–2 DATA Figure 10. DAC TDM (8-Channel I2S Mode 06106-017 The AD1934 is designed for 3.3 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the pins as possible, to minimize noise pickup. A bulk aluminum electrolytic capacitor of at least 22 μF should also be provided on the same PC board as the codec. For critical applications, improved performance is obtained with separate supplies for the analog and digital sections. If this is not possible, it is recommended that the analog and digital supplies be isolated by means of a ferrite bead in series with each supply. It is important that the analog supply be as clean as possible. AD1934 Table 12. Pin Function Changes in TDM and AUX Modes Pin Name AUXDATA1 DSDATA1 DSDATA2 DSDATA3 DSDATA4 AUXTDMLRCLK AUXTDMBCLK DLRCLK DBCLK Stereo Modes Not Used (Float) DAC1 Data In DAC2 Data In DAC3 Data In DAC4 Data In Not Used (Ground) Not Used (Ground) DAC LRCLK In/Out DAC BCLK In/Out TDM Modes Not Used (Float) DAC TDM Data In DAC TDM Data Out DAC TDM Data In 2 (Dual-Line Mode) DAC TDM Data Out 2 (Dual-Line Mode) Not Used (Ground) Not Used (Ground) DAC TDM Frame Sync In/Out DAC TDM BCLK In/Out AUX Modes AUX Data Out 1 (to External DAC 1) TDM Data In Not Used (Ground) Not Used (Ground) AUX Data Out 2 (to External DAC 2) TDM Frame Sync In/Out TDM BCLK In/Out AUX LRCLK In/Out AUX BCLK In/Out AUXTDMLRCLK AUXTDMBCLK DSDATA1 (TDM_IN) UNUSED SLOTS EMPTY EMPTY EMPTY AUXILIARY DAC CHANNELS WILL APPEAR AT AUX DAC PORTS 8-ON-CHIP DAC CHANNELS EMPTY DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 AUX L1 AUX R1 AUX L2 AUX R2 32 BITS MSB DLRCLK (AUX PORT) LEFT RIGHT DBCLK (AUX PORT) MSB DSDATA4 (AUX2_OUT) MSB MSB MSB Figure 11. 16-Channel DAC TDM-AUX Mode Rev. 0 | Page 15 of 28 06106-051 AUXDATA1 (AUX1_OUT) AD1934 DAISY-CHAIN MODE The AD1934 also allows a daisy-chain configuration to expand the system 16 DACs (see Figure 12). In this mode, the DBCLK frequency is 512 fS. The first eight slots of the DAC TDM data stream belong to the first AD1934 in the chain and the last eight slots belong to the second AD1934. The second AD1934 is the device attached to the DSP TDM port. The dual-line, DAC TDM mode can also be used to send data at a 192 kHz sample rate into the AD1934, as shown in Figure 14. The I/O pins of the serial ports are defined according to the serial mode selected. See Table 13 for a detailed description of the function of each pin. See Figure 18 for a typical AD1934 configuration with two external stereo DACs. Figure 15 and Figure 16 show the serial mode formats. For maximum flexibility, the polarity of LRCLK and BCLK are programmable. In these figures, all of the clocks are shown with their normal polarity. The default mode is I2S. To accommodate 16 channels at a 96 kHz sample rate, the AD1934 can be configured into a dual-line, DAC TDM mode, as shown in Figure 13. This mode allows a slower DBCLK than normally required by the one-line TDM mode. Again, the first four channels of each TDM input belong to the first AD1934 in the chain and the last four channels belong to the second AD1934. DLRCLK DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN DSDATA1 (TDM_IN) OF THE SECOND AD1934 DAC L1 DAC R1 DAC L2 DSDATA2 (TDM_OUT) OF THE SECOND AD1934 THIS IS THE TDM TO THE FIRST AD1934 DAC R2 DAC L3 DAC R3 DAC L4 8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 8 UNUSED SLOTS FIRST AD1934 SECOND AD1934 DSP 06106-054 32 BITS MSB Figure 12. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain) DLRCLK DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN DSDATA1 (IN) DAC L1 DAC R1 DAC L2 DAC R2 DSDATA2 (OUT) DSDATA3 (IN) DAC L3 DAC R3 DSDATA4 (OUT) DAC L4 DAC R4 8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN DAC L1 DAC R1 DAC L2 DAC R2 DAC L1 DAC R1 DAC L2 DAC R2 DAC L3 DAC R3 DAC L4 DAC R4 DAC L3 DAC R3 DAC L4 DAC R4 32 BITS FIRST AD1934 SECOND AD1934 06106-055 MSB DSP Figure 13. Dual-Line, DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two AD1934 Daisy Chain); DSDATA3 and DSDATA4 Are the Daisy Chain Rev. 0 | Page 16 of 28 AD1934 DLRCLK DBCLK DSDATA1 DAC L1 DAC R1 DAC L2 DAC R2 DSDATA2 DAC L3 DAC R3 DAC L4 DAC R4 06106-058 32 BITS MSB Figure 14. Dual-Line, DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode) LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK SDATA LSB MSB LSB MSB LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK SDATA LSB MSB LSB MSB I2S MODE—16 BITS TO 24 BITS PER CHANNEL LEFT CHANNEL LRCLK RIGHT CHANNEL BCLK SDATA MSB LSB MSB LSB RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL LRCLK BCLK MSB MSB LSB LSB DSP MODE—16 BITS TO 24 BITS PER CHANNEL 1/fS NOTES 1. DSP MODE DOES NOT IDENTIFY CHANNEL. 2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 × fS. 3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE. Figure 15. Stereo Serial Modes Rev. 0 | Page 17 of 28 06106-013 SDATA AD1934 tDBH DBCLK tDBL tDLH tDLS DLRCLK tDDS DSDATA LEFT-JUSTIFIED MODE MSB MSB–1 tDDH tDDS DSDATA I2S-JUSTIFIED MODE MSB tDDH tDDS tDDS MSB LSB tDDH 06106-014 DSDATA RIGHT-JUSTIFIED MODE tDDH Figure 16. DAC Serial Timing tABH AUXTDMBCLK tABL tALH tALS AUXTDMLRCLK DSDATA1 I2S-JUSTIFIED MODE MSB MSB–1 MSB DSDATA1 RIGHT-JUSTIFIED MODE MSB Figure 17. AUXTDM Serial Timing Rev. 0 | Page 18 of 28 LSB 06106-015 DSDATA1 LEFT-JUSTIFIED MODE AD1934 Table 13. Pin Function Changes in TDM and AUX Modes (Replication of Table 12) Stereo Modes Not Used (Float) DAC1 Data In DAC2 Data In DAC3 Data In DAC4 Data In Not Used (Ground) Not Used (Ground) DAC LRCLK In/Out DAC BCLK In/Out TDM Modes Not Used (Float) DAC TDM Data In DAC TDM Data Out DAC TDM Data In 2 (Dual-Line Mode) DAC TDM Data Out 2 (Dual-Line Mode) Not Used (Ground) Not Used (Ground) DAC TDM Frame Sync In/Out DAC TDM BCLK In/Out TxDATA TxCLK TFS (NC) SHARC RxCLK 12.288MHz AUX Modes AUX Data Out 1 (to External DAC 1) TDM Data In Not Used (Ground) Not Used (Ground) AUX Data Out 2 (to External DAC 2) TDM Frame Sync In/Out TDM BCLK In/Out AUX LRCLK In/Out AUX BCLK In/Out SHARC IS RUNNING IN SLAVE MODE (INTERRUPT-DRIVEN) 30MHz FSYNC-TDM (RFS) LRCLK BCLK AUXTDMLRCLK AUXTDMBCLK DSDATA1 AUX DATA DAC 1 MCLK DBCLK DLRCLK DSDATA2 DSDATA3 AD1934 TDM MASTER AUX MASTER LRCLK AUXDATA1 DSDATA4 BCLK AUX DATA DAC 2 MCLK MCLK Figure 18. Example of AUX Mode Connection to SHARC® (AD1934 as TDM Master/AUX Master Shown) Rev. 0 | Page 19 of 28 06106-019 Pin Name AUXDATA1 DSDATA1 DSDATA2 DSDATA3 DSDATA4 AUXTDMLRCLK AUXTDMBCLK DLRCLK DBCLK AD1934 CONTROL REGISTERS DEFINITIONS The format is the same for I2C and SPI ports. The global address for the AD1934 is 0x04, shifted left 1 bit due to the R/W bit. However, in I2C, ADR0 and ADR1 are OR’ed into Bit 17 and Bit 8 to provide multiple chip addressing. All registers are reset to 0, except for the DAC volume registers that are set to full volume. Note that the first setting in each control register parameter is the default setting. Table 14. Register Format Bit Global Address R/W Register Address Data 23:17 16 15:8 7:0 Table 15. Register Addresses and Functions Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function PLL and Clock Control 0 PLL and Clock Control 1 DAC Control 0 DAC Control 1 DAC Control 2 DAC individual channel mutes DAC 1L volume control DAC 1R volume control DAC 2L volume control DAC 2R volume control DAC 3L volume control DAC 3R volume control DAC 4L volume control DAC 4R volume control Reserved Auxiliary TDM Port Control 0 Auxiliary TDM Port Control 1 PLL AND CLOCK CONTROL REGISTERS Table 16. PLL and Clock Control 0 Bit 0 2:1 4:3 6:5 7 Value 0 1 00 01 10 11 00 01 10 11 00 01 10 11 0 1 Function Normal operation Power-down INPUT 256 (×44.1 kHz or 48 kHz) INPUT 384 (×44.1 kHz or 48 kHz) INPUT 512 (×44.1 kHz or 48 kHz) INPUT 768 (×44.1 kHz or 48 kHz) XTAL oscillator enabled 256 × fS VCO output 512 × fS VCO output Off MCLK DLRCLK AUXTDMLRCLK Reserved Disable: DAC idle Enable: DAC active Description PLL power-down MCLK pin functionality (PLL active) MCLKO pin PLL input Internal MCLK enable Rev. 0 | Page 20 of 28 AD1934 Table 17. PLL and Clock Control 1 Bit 0 1 2 3 7:4 Value 0 1 0 1 0 1 0 1 0000 Function PLL clock MCLK PLL clock MCLK Enabled Disabled Not locked Locked Reserved Description DAC clock source select Clock source select On-chip voltage reference PLL lock indicator (read-only) DAC CONTROL REGISTERS Table 18. DAC Control 0 Bit 0 2:1 5:3 7:6 Value 0 1 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 Function Normal Power-down 32 kHz/44.1 kHz/48 kHz 64 kHz/88.2 kHz/96 kHz 128 kHz/176.4 kHz/192 kHz Reserved 1 0 8 12 16 Reserved Reserved Reserved Stereo (normal) TDM (daisy chain) DAC aux mode (DAC-, TDM-coupled) Dual-line TDM Description Power-down Sample rate SDATA delay (BCLK periods) Serial format Table 19. DAC Control 1 Bit 0 2:1 3 4 5 6 7 Value 0 1 00 01 10 11 0 1 0 1 0 1 0 1 0 1 Function Latch in midcycle (normal) Latch in at end of cycle (pipeline) 64 (2 channels) 128 (4 channels) 256 (8 channels) 512 (16 channels) Left low Left high Slave Master Slave Master DBCLK pin Internally generated Normal Inverted Description BCLK active edge (TDM in) BCLKs per frame LRCLK polarity LRCLK master/slave BCLK master/slave BCLK source BCLK polarity Rev. 0 | Page 21 of 28 AD1934 Table 20. DAC Control 2 Bit 0 2:1 4:3 5 7:6 Value 0 1 00 01 10 11 00 01 10 11 0 1 00 Function Unmute Mute Flat 48 kHz curve 44.1 kHz curve 32 kHz curve 24 20 Reserved 16 Noninverted Inverted Reserved Description Master mute De-emphasis (32 kHz/44.1 kHz/48 kHz mode only) Word width DAC output polarity Table 21. DAC Individual Channel Mutes Bit 0 1 2 3 4 5 6 7 Value 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Unmute Mute Description DAC 1 left mute DAC 1 right mute DAC 2 left mute DAC 2 right mute DAC 3 left mute DAC 3 right mute DAC 4 left mute DAC 4 right mute Table 22. DAC Volume Controls Bit 7:0 Value 0 1 to 254 255 Function No attenuation −3/8 dB per step Full attenuation Description DAC volume control Rev. 0 | Page 22 of 28 AD1934 AUXILIARY TDM PORT CONTROL REGISTERS Table 23. Auxiliary TDM Control 0 Bit 1:0 4:2 6:5 7 Value 00 01 10 11 000 001 010 011 100 101 110 111 00 01 10 11 0 1 Function 24 20 Reserved 16 1 0 8 12 16 Reserved Reserved Reserved Reserved Reserved DAC aux mode Reserved Latch in midcycle (normal) Latch in at end of cycle (pipeline) Description Word width SDATA delay (BCLK periods) Serial format BCLK active edge (TDM in) Table 24. Auxiliary TDM Control 1 Bit 0 1 2 3 5:4 6 7 Value 0 1 0 1 0 1 0 1 00 01 10 11 0 1 0 1 Function 50/50 (allows 32/24/20/16 BCLK/channel) Pulse (32 BCLK/channel) Drive out on falling edge (DEF) Drive out on rising edge Left low Left high Slave Master 64 128 256 512 Slave Master AUXTDMBCLK pin Internally generated ADDITIONAL MODES The AD1934 offers several additional modes for board level design enhancements. To reduce the EMI in board level design, serial data can be transmitted without an explicit BCLK. See Figure 19 for an example of a DAC TDM data transmission mode that does not require high speed DBCLK. This configuration is applicable when the AD1934 master clock is generated by the PLL with the DLRCLK as the PLL reference frequency. Description LRCLK format BCLK polarity LRCLK polarity LRCLK master/slave BCLKs per frame BCLK master/slave BCLK source To relax the requirement for the setup time of the AD1934 in cases of high speed TDM data transmission, the AD1934 can latch in the data using the falling edge of DBCLK. This effectively dedicates the entire BCLK period to the setup time. This mode is useful in cases where the source has a large delay time in the serial data driver. Figure 20 shows this pipeline mode of data transmission. Both the BLCK-less and pipeline modes are available. Rev. 0 | Page 23 of 28 AD1934 DLRCLK 32 BITS INTERNAL DBCLK DSDATA DLRCLK 06106-059 INTERNAL DBCLK TDM-DSDATA Figure 19. Serial DAC Data Transmission in TDM Format Without DBCLK (Applicable Only If PLL Locks to DLRCLK) DLRCLK DBCLK 06106-060 DATA MUST BE VALID AT THIS BCLK EDGE MSB DSDATA 2 Figure 20. I S Pipeline Mode in DAC Serial Data Transmission (Applicable in Stereo and TDM Useful for High Frequency TDM Transmission) Rev. 0 | Page 24 of 28 AD1934 APPLICATION CIRCUITS LRCLK 39nF 2 270pF NPO MCLK + 1 604Ω 4.7µF 4.99kΩ + 3.3nF NPO OP275 – AUDIO OUTPUT 49.9kΩ 4.99kΩ 5.6nF 2.2nF 390pF 3.32kΩ AVDD2 3 4.75kΩ 4.75kΩ 562Ω AVDD2 Figure 22. Typical DAC Output Filter Circuit (Single-Ended, Noninverting) 11kΩ Figure 21. Recommended Loop Filters for LRCLK or MCLK PLL Reference DAC OUT 68pF NPO 2 11kΩ 3.01kΩ CM 270pF NPO 0.1µF 3 – OP275 + 1 604Ω 4.7µF + 2.2nF NPO AUDIO OUTPUT 49.9kΩ Figure 23. Typical DAC Output Filter Circuit (Single-Ended, Inverting) Rev. 0 | Page 25 of 28 06106-025 + LF DAC OUT 06106-027 LF 240pF NPO 06106-024 Typical applications circuits are shown in Figure 21, Figure 22, and Figure 23. Recommended loop filters for LR clock and master clock as the PLL reference are shown in Figure 21. Output filters for the DAC outputs are shown in Figure 22 and Figure 23 for the noninverting and inverting cases, respectively. AD1934 OUTLINE DIMENSIONS 0.75 0.60 0.45 9.00 BSC SQ 1.60 MAX 37 48 36 1 PIN 1 0.15 0.05 7.00 BSC SQ TOP VIEW 1.45 1.40 1.35 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY VIEW A (PINS DOWN) 25 12 13 VIEW A 0.50 BSC LEAD PITCH 24 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 24. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters ORDERING GUIDE Model AD1934YSTZ 1 AD1934YSTZ-RL1 EVAL-AD1934EB 1 Temperature Range –40°C to +105°C –40°C to +105°C Package Description 48-Lead LQFP 48-Lead LQFP, 13” Reel Evaluation Board Z = Pb-free part. Rev. 0 | Page 26 of 28 Package Option ST-48 ST-48 AD1934 NOTES Rev. 0 | Page 27 of 28 AD1934 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06106-0-6/07(0) Rev. 0 | Page 28 of 28