ON ASM1832S Power supply monitor and reset circuit Datasheet

ASM1832
3.3 V mP Power Supply
Monitor and Reset Circuit
Description
The ASM1832 is a fully integrated microprocessor supervisor. It
can halt and restart a “hung−up” microprocessor, restart a
microprocessor after a power failure. It has a watchdog timer and
external reset override. RESET and RESET outputs are push−pull.
A precision temperature−compensated reference and comparator
circuits monitor the 3.3 V, VCC input voltage status. During power−up
or when the VCC power supply falls outside selectable tolerance
limits, both RESET and RESET become active. When VCC rises
above the threshold voltage, the reset signals remain active for an
additional 250 ms minimum, allowing the power supply and system
microprocessor to stabilize. The trip point tolerance signal, TOL,
selects the trip level tolerance to be either 10% or 20%.
A debounced manual reset input, PBRST, activates the reset outputs
for a minimum period of 250 ms. There is a watchdog timer to stop and
restart a microprocessor that is “hung−up”. The watchdog timeouts
periods are selectable: 150 ms, 610 ms, and 1200 ms. If the ST input is
not strobed LOW before the time−out period expires, a reset is
generated.
Devices are available in 8−pin PDIP, 8−pin SO and compact 8−pin
MicroSO packages.
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PDIP−8
NO SUFFIX
CASE 646AA
MICRO−8
U SUFFIX
CASE 846AA
SOIC−8
S SUFFIX
CASE 751BD
PIN CONFIGURATION
PBRST
TD
1
VCC
ASM1832
ST
TOL
RESET
GND
RESET
Features
•
•
•
•
•
•
•
•
•
•
•
3.3 V Supply Monitor
Push−pull Output
Selectable Watchdog Period
Debounce Manual Push−button Reset Input
Precision Temperature−compensated Voltage Reference and
Comparator
Power−up, Power−down and Brown Out Detection
250 ms Minimum Reset Time
Active LOW and HIGH Reset Signal
Selectable Trip Point Tolerance: 10% or 20%
Low−cost 8−pin DIP/SO and 8−pin Micro SO Packages
Wide Operating Temperature: −40°C to +85°C
Applications
•
•
•
•
•
Microprocessor Systems
Computers
Controllers
Portable Instruments
Automotive Systems
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
August, 2011 − Rev. 3
1
Publication Order Number:
ASM1832/D
ASM1832
Figure 1. Typical Operating Circuit
Figure 2. Block Diagram
Table 1. PIN DESCRIPTION
Pin #
8−Pin Package
Pin Name
1
PBRST
2
TD
Watchdog time delay selection.
(tTD = 150 ms for TD = GND, tTD = 610 ms for TD = Open, and tTD = 1200 ms for TD = VCC).
3
TOL
Selects 10% (TOL connected to GND) or 20% (TOL connected to VCC) trip point tolerance.
4
GND
Ground.
5
RESET
Active HIGH reset output. RESET is active:
1. If VCC falls below the reset voltage trip point.
2. If PBRST is LOW.
3. If ST is not strobed LOW before the timeout period set by TD expires.
4. During power−up.
6
RESET
Active LOW reset output. (See RESET).
7
ST
Strobe input.
8
VCC
3.3 V power.
Function
Debounced manual pushbutton reset input.
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Min
Max
Unit
Voltage on VCC (Note 1)
−0.5
7
V
Voltage on ST, TD (Note 1)
−0.5
VCC + 0.5
V
Voltage on PBRST, RESET, RESET (Note 1)
−0.5
VCC + 0.5
V
Operating Temperature Range
−40
+85
°C
+260
°C
+125
°C
HBM
2
KV
MM
200
V
Soldering Temperature (for 10 sec)
Storage Temperature
ESD rating
−55
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Voltages are measured with respect to ground.
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ASM1832
Table 3. DC ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VCC = 1.2 V to 5.5 V and specifications are over the
operating temperature range of −40°C to +85°C. All voltages are referenced to ground.)
Parameter
Symbol
Conditions
Min
Max
Unit
1.0
Typ
5.5
V
VCC ≥ 2.7 V
2
VCC+0.3
V
VCC < 2.7 V
VCC−0.4V
Supply Voltage
VCC
ST and PBRST Input High Level
VIH
ST and PBRST Input High Level
VIH
ST and PBRST Input Low Level
VIL
−0.3
VCC Trip Point (TOL = GND)
VCCTP
2.80
VCC Trip Point (TOL = VCC)
VCCTP
2.47
Watchdog Timeout Period
tTD
TD = GND
62.5
Watchdog Timeout Period
tTD
TD = VCC
500
Watchdog Timeout Period
tTD
TD Floating
250
610
Output Voltage
VOH
I = −500 mA, VCC < 2.7 V
(Note 2)
VCC−0.3V
VCC−0.1V
V
Output Current
IOH
Output = 2.4 V, VCC ≥ 2.7 V
350
mA
Output Current
IOL
Output = 0.4 V, VCC ≥ 2.7 V
Input Leakage
IIL
RESET Low Level
(Note 2)
Operating Current
ICC1
Outputs open, VCC ≤ 3.6 V
and all inputs at VCC or GND
Input Capacitance
CIN
Output Capacitance
2.97
V
2.55
2.64
V
150
250
mS
1200
2000
mS
1000
mS
mA
tRST
ST Pulse Width
tST
Must not exceed tRD
minimum. Watchdog cannot
be disabled.
tRPD
Pulses < 2 ms at VCCTP
minimum will not cause reset
PBRST = VIL
tPDLY
VCC Detect to RESET or
RESET inactive
tRPU
mA
0.4
V
40
kW
20
mA
5
pF
20
250
tF
PBRST Stable LOW to
RESET and RESET Active
1.0
7
Reset Active Time
VCC Slew Rate
2.88
COUT
tPB
VCC Slew Rate
V
10
PBRST pin
PBRST Manual Reset
Minimum Low Time
VCC Fail Detect to RESET or
RESET
0.5
−1.0
VOL
Internal Pull−up Resistor
V
610
1000
20
5
tR
250
0
ms
ns
8
20
trise = 5 ms
pF
ms
ms
ms
610
20
ms
1000
ms
ns
2. RESET remains within 0.5 V of VCC on power−down until VCC falls below 2 V. RESET remains within 0.5 V of ground on power−down until
VCC falls below 2.0 V.
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ASM1832
Detailed Description
pin (RESET) to Ground. This configuration will give a valid
value on the reset output with VCC approaching 0 V. During
both power up and down, the configuration will draw current
when the RESET is in the high state. The value of 100 KW
should be adequate to maintain a valid condition. The active
HIGH reset signal is valid down to a VCC level of 1.2 V also.
The ASM1832 monitors the microprocessor or
microcontroller power supply and issues reset signals, both
active HIGH and active LOW, that halt processor operation
whenever the power supply voltage levels are outside a
predetermined tolerance.
RESET and RESET Outputs
Table 4.
RESET and RESET signals are active for a minimum of
250 ms after the supply has returned to in−tolerance level.
This allows the power supply and monitored processor to
stabilize before instruction execution is allowed to begin.
Tolerance
Select
Trip Point Tolerance Selection
TRIP Point Voltage (V)
Tolerance
Min
Nom
Max
TOL = VCC
20%
2.47
2.55
2.64
TOL = GND
10%
2.80
2.88
2.97
The TOL input is used to determine the level VCC can vary
below 3.3 V without asserting a reset. With TOL connected
to VCC, RESET and RESET become active whenever VCC
falls below 2.64 V. RESET and RESET become active when
the VCC falls below 2.98 V if TOL is connected to ground.
After VCC has risen above the trip point set by TOL,
RESET and RESET remain active for a minimum time
period of 250 ms. On power−down, once VCC falls below
the reset threshold RESET stays LOW and is guaranteed to
be 0.4 V or less until VCC drops below 1.2 V. The reset
output on the ASM1832 uses a push−pull drive stage that can
maintain a valid output below 1.2 V. To sink current with
VCC below 1.2 V, a resistor can be connected from the reset
Figure 3.
Figure 4. Timing Diagram: Power Up
Figure 5. Timing Diagram: Power Down
Application Information
When PBRST is held LOW for the minimum time tPB,
both resets become active and remain active for a minimum
time period of 250 ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses
greater than 20 ms. No external pull−up resistor is required,
since PBRST is pulled HIGH by an internal 40 kW resistor.
The PBRST can be driven from a TTL or CMOS logic line
or shorted to ground with a mechanical switch.
Manual Reset Operation
Push−button switch input, PBRST, allows the user to
override the internal trip point detection circuits and issue
reset signals. The pushbutton input is debounced and is
pulled HIGH through an internal 40 kW resistor.
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ASM1832
Figure 6. Timing Diagram: Pushbutton Reset
Figure 7. Application Circuit: Pushbutton Reset
Watchdog Timer and ST Input
minimum timeout period, reset signals become active. On
power−up after the supply voltage returns to an in−tolerance
condition, the reset signal remains active for 250 ms
minimum, allowing the power supply and system
microprocessor to stabilize.
A watchdog timer stops and restarts a microprocessor that
is “hung−up”. The mP must toggle the ST input within a set
period (as selectable through TD input) to verify proper
software execution. If the ST is not toggled low within the
ST Pulses as short as 20 ns can be detected.
Table 5.
TD Voltage
Level
Watchdog Time−out Period (ms)
Min
Nom
Max
GND
62.5
150
250
Floating
250
610
1000
VCC
500
1200
2000
The watchdog timer can not be disabled. It must be
strobed with a high−to−low transition to avoid watchdog
timeout and reset.
Figure 8. Timing Diagram: Strobe Input
Timeouts periods of approximately 150 ms, 610 ms or
1,200 ms are selected through the TD pin.
Figure 9. Application Circuit: Watchdog Timer
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ASM1832
PACKAGE DIMENSIONS
Micro8t/TSSOP8 3x3
CASE 846AA−01
ISSUE O
D
HE
PIN 1 ID
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.
E
e
b 8 PL
0.08 (0.003)
T B
M
S
A
DIM
A
A1
b
c
D
E
e
L
HE
S
SEATING
−T− PLANE
0.038 (0.0015)
A
A1
MILLIMETERS
NOM
MAX
−−
1.10
0.08
0.15
0.33
0.40
0.18
0.23
3.00
3.10
3.00
3.10
0.65 BSC
0.40
0.55
0.70
4.75
4.90
5.05
MIN
−−
0.05
0.25
0.13
2.90
2.90
L
c
SOLDERING FOOTPRINT*
8X
1.04
0.041
0.38
0.015
3.20
0.126
6X
8X
4.24
0.167
0.65
0.0256
5.28
0.208
SCALE 8:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
INCHES
NOM
−−
0.003
0.013
0.007
0.118
0.118
0.026 BSC
0.016
0.021
0.187
0.193
MIN
−−
0.002
0.010
0.005
0.114
0.114
MAX
0.043
0.006
0.016
0.009
0.122
0.122
0.028
0.199
ASM1832
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
E1
6.10
6.35
7.11
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
eB
7.87
L
2.92
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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ASM1832
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
SYMBOL
E1
E
MIN
MAX
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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ASM1832
Table 6. ORDERING INFORMATION
Part Number
Package
Operating
Temperature Range
Maximum Supply
Current (mA)
Voltage Monitoring
Application
Package Marking
TIN − LEAD DEVICES
ASM1832
8−Pin PDIP
−40°C to +85°C
20
3.3 V
ASM1832
ASM1832S
8−SO
−40°C to +85°C
20
3.3 V
ASM1832S
ASM1832U
8−MicroSO
−40°C to +85°C
20
3.3 V
ASM1832U
LEAD FREE DEVICES
ASM1832F
8−Pin PDIP
−40°C to +85°C
20
3.3 V
ASM1832F
ASM1832SF
8−SO
−40°C to +85°C
20
3.3 V
ASM1832SF
ASM1832UF
8−MicroSO
−40°C to +85°C
20
3.3 V
ASM1832UF
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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ASM1832/D
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