AD AD9002AJ High speed 8-bit monolithic a/d converter Datasheet

a
FEATURES
150 MSPS Encode Rate
Low Input Capacitance: 17 pF
Low Power: 750 mW
–5.2 V Single Supply
MIL-STD-883 Compliant Versions Available
APPLICATIONS
Radar Systems
Digital Oscilloscopes/ATE Equipment
Laser/Radar Warning Receivers
Digital Radio
Electronic Warfare (ECM, ECCM, ESM)
Communication/Signal Intelligence
High Speed 8-Bit
Monolithic A/D Converter
AD9002
FUNCTIONAL BLOCK DIAGRAM
OVERFLOW
INHIBIT
AD9002
ANALOG IN
R
256
R
BIT 8 (MSB)
255
R
128
R/2
REFMID
R/2
127
R
GENERAL DESCRIPTION
The AD9002 is an 8-bit, high speed, analog-to-digital converter.
The AD9002 is fabricated in an advanced bipolar process that
allows operation at sampling rates in excess of 150 megasamples/
second. Functionally, the AD9002 is comprised of 256 parallel
comparator stages whose outputs are decoded to drive the ECL
compatible output latches.
An exceptionally wide large signal analog input bandwidth of
160 MHz is due to an innovative comparator design and very
close attention to device layout considerations. The wide input
bandwidth of the AD9002 allows very accurate acquisition of
high speed pulse inputs, without an external track-and-hold.
The comparator output decoding scheme minimizes false codes,
which is critical to high speed linearity.
The AD9002 provides an external hysteresis control pin that
can be used to optimize comparator sensitivity to further improve performance. Additionally, the AD9002’s low power
dissipation of 750 mW makes it usable over the full extended
temperature range. The AD9002 also incorporates an overflow
OVERFLOW
+VREF
D
E
C
O
D
I
N
G
L
O
G
I
C
BIT 7
L
A
T
C
H
BIT 6
BIT 5
BIT 4
BIT 3
2
BIT 2
R
BIT 1 (LSB)
1
–VREF
ENCODE
ENCODE
GND
HYSTERESIS
–VS
bit to indicate overrange inputs. This overflow output can be
disabled with the overflow inhibit pin.
The AD9002 is available in two grades, one with 0.5 LSB linearity and one with 0.75 LSB linearity. Both versions are offered
in an industrial grade, –25°C to +85°C, packaged in a 28-lead
DIP and a 28-leaded JLCC. The military temperature range
devices, –55°C to +125°C, are available in ceramic DIP and
LCC packages and comply with MIL-STD-883 Class B.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD9002–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Temp
RESOLUTION
DC ACCURACY
Differential Linearity
Integral Linearity
No Missing Codes
INITIAL OFFSET ERROR
Top of Reference Ladder
Bottom of Reference Ladder
Offset Drift Coefficient
ANALOG INPUT
Input Bias Current1
Input Resistance
Input Capacitance
Large Signal Bandwidth2
Input Slew Rate3
+25°C
Full
+25°C
Full
Full
(–VS = –5.2 V; Differential Reference Voltage = 2.0 V; unless otherwise noted)
AD9002AD/AJ
Min
Typ
Max
AD9002BD/BJ
Min
Typ
Max
AD9002SD/SE
Min
Typ
Max
AD9002TD/TE
Min
Typ
Max
Units
8
8
8
8
Bits
0.6
0.75
1.0
0.6
1.0
1.2
GUARANTEED
+25°C
Full
+25°C
Full
Full
8
+25°C
Full
+25°C
+25°C
+25°C
+25°C
60
4
25
200
17
160
440
+25°C
DYNAMIC PERFORMANCE
Conversion Rate
Aperture Delay
Aperture Uncertainty (Jitter)
Output Delay (tPD)4, 5
Transient Response6
Overvoltage Recovery Time7
Output Rise Time4
Output Fall Time4
Output Time Skew4, 8
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
ENCODE INPUT
Logic “1” Voltage4
Logic “0” Voltage4
Logic “1” Current
Logic “0” Current
Input Capacitance
Encode Pulsewidth (Low)9
Encode Pulsewidth (High)9
Full
Full
Full
Full
+25°C
+25°C
+25°C
OVERFLOW INHIBIT INPUT
0 V Input Current
Full
144
+25°C
7.6
AC LINEARITY10
Effective Bits11
In-Band Harmonics
dc to 1.23 MHz
dc to 9.3 MHz
dc to 19.3 MHz
Signal-to-Noise Ratio12
Two Tone Intermod Rejection13
DIGITAL OUTPUTS4
Logic “1” Voltage
Logic “0” Voltage
POWER SUPPLY14
Supply Current (–5.2 V)
Nominal Power Dissipation
Reference Ladder Dissipation
Power Supply Rejection Ratio15
40
80
0.25
10
125
150
1.3
15
3.7
6
6
2.5
14
17
10
12
8
4
200
200
60
25
200
17
160
440
22
110
5.5
40
80
0.25
10
125
150
1.3
15
3.7
6
6
2.5
200
200
25
110
5.5
200
17
160
440
40
80
0.25
10
125
150
1.3
15
3.7
6
6
2.5
25
22
110
5.5
46
1.5
200
200
µA
µA
kΩ
pF
MHz
V/µs
80
0.25
10
125
150
1.3
15
3.7
6
6
2.5
22
110
5.5
3.0
2.5
–1.5
150
120
3
1.5
1.5
144
48
mV
mV
mV
mV
µV/°C
0.6
300
55
50
44
47.6
60
144
48
46
–1.1
750
50
0.8
40
7.6
175
200
200
17
160
440
300
750
50
0.8
1.5
MSPS
ns
ps
ns
ns
ns
ns
ns
ns
V
V
µA
µA
pF
ns
ns
µA
Bits
55
50
44
47.6
60
dB
dB
dB
dB
dB
–1.1
175
200
Ω
Ω/°C
MHz
7.6
–1.5
145
LSB
LSB
LSB
LSB
14
17
10
12
–1.1
–1.5
145
60
–1.5
150
120
300
–1.1
–1.5
1.5
200
200
3
55
50
44
47.6
60
46
4
0.6
7.6
48
8
20
–1.1
144
175
200
14
17
10
12
1.5
1.5
300
0.5
0.75
0.4
0.5
1.2
GUARANTEED
3.0
2.5
3
55
50
44
47.6
60
750
50
0.8
60
22
1.5
1.5
145
4
–1.5
150
120
3
1.5
1.5
–1.1
8
0.4
20
–1.1
–1.5
150
120
Full
Full
14
17
10
12
0.6
–1.1
46
0.75
1.0
0.6
1.0
1.2
GUARANTEED
3.0
2.5
0.6
48
0.6
20
3.0
2.5
+25°C
+25°C
+25°C
+25°C
+25°C
+25°C
Full
+25°C
+25°C
+25°C
0.5
0.75
0.4
0.5
1.2
GUARANTEED
20
REFERENCE INPUT
Reference Ladder Resistance
Ladder Temperature Coefficient
Reference Input Bandwidth
+25°C
0.4
–1.5
145
750
50
0.8
175
200
1.5
V
V
mA
mA
mW
mW
mV/V
bit-to-bit time skew differences.
9
ENCODE signal rise/fall times should be less than 10 ns for normal operation.
10
Measured at 125 MSPS encode rate.
11
Analog input frequency = 1.23 MHz.
12
RMS signal to rms noise, with 1.23 MHz analog input signal.
13
Input signals 1 V p-p @ 1.23 MHz and 1 V p-p @ 2.30 MHz.
14
Supplies should remain stable within ± 5% for normal operation.
15
Measured at –5.2 V ± 5%.
Specifications subject to change without notice.
NOTES
1
Measured with AIN = 0 V.
2
Measured by FFT analysis where fundamental is –3 dBc.
3
Input slew rate derived from rise time (10 to 90%) of full scale input.
4
0utputs terminated through 100 Ω to –2 V.
5
Measured from ENCODE in to data out for LSB only.
6
For full-scale step input, 8-bit accuracy is attained in specified time.
7
Recovers to 8-bit accuracy in specified time after 150% full-scale input overvoltage.
8
Output time skew includes high-to-low and low-to-high transitions as well as
–2–
REV. D
AD9002
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . –6 V
Analog-to-Digital Supply Voltage Differential . . . . . . . . . 0.5 V
Analog Input Voltage . . . . . . . . . . . . . . . . . . . . . –VS to +0.5 V
Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . –VS to 0 V
Reference Input Voltage (+VREF – V REF)2 . . . . –3.5 V to 0.1 V
Differential Reference Voltage . . . . . . . . . . . . . . . . . . . . .2.1 V
Reference Midpoint Current . . . . . . . . . . . . . . . . . . . . ± 4 mA
ENCODE to ENCODE Differential Voltage . . . . . . . . . . . 4 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature Range
AD9002AD/BD/AJ/BJ . . . . . . . . . . . . . . . . –25°C to +85°C
AD9002SE/SD/TD/TE . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature3 . . . . . . . . . . . . . . . . . . . . . . . .+175°C
Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300°C
NOTES
1
Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect device
reliability.
2
+V REF ≥ –VREF under all circumstances.
3
Maximum junction temperature (t J max) should not exceed +175°C for ceramic
packages, and +150°C for plastic packages:
tJ = PD (θ JA) + tA
PD (θ JC) + t C
where
PD = power dissipation
θJA = thermal impedance from junction to ambient (°C/W)
θJC = thermal impedance from junction to case ( °C/W)
tA = ambient temperature (°C)
tC = case temperature (°C)
Typical thermal impedances are:
Ceramic DIP θ JA = 56°C/W; θJC = 20°C/W
Ceramic LCC θJA = 69°C/W; θJC = 23°C/W
PLCC θJA = 60°C/W; θ JC = 19°C/W.
Recommended Operating Conditions
Input Voltage
Parameter
Min
Nominal
Max
–VS
+VREF
–VREF
Analog Input
–5.46
–VREF
–2.1
–VREF
–5.20
0.0 V
–2.0
–4.94
+0.1
+VREF
+VREF
EXPLANATION OF TEST LEVELS
Test Level I
Test Level II
– 100% production tested.
– 100% production tested at +25°C, and
sample tested at specified temperatures.
Test Level III – Sample tested only.
Test Level IV – Parameter is guaranteed by design and
characterization testing.
Test Level V – Parameter is a typical value only.
Test Level VI – All devices are 100% production tested at
+25°C. 100% production tested at temperature extremes for extended temperature
devices; sample tested at temperature extremes for commercial/industrial devices.
ORDERING GUIDE
Model
Package
Linearity Temperature Range Option*
AD9002AD
AD9002BD
AD9002AJ
AD9002BJ
AD9002SD/883B
AD9002SE/883B
AD9002TD/883B
AD9002TE/883B
0.75 LSB
0.50 LSB
0.75 LSB
0.50 LSB
0.75 LSB
0.75 LSB
0.50 LSB
0.50 LSB
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–25°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
D-28
D-28
J-28
J-28
D-28
E-28A
D-28
E-28A
*D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; J = Ceramic Chip
Carrier, J-Formed Leads.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9002 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. D
–3–
WARNING!
ESD SENSITIVE DEVICE
AD9002
FUNCTIONAL DESCRIPTION
Pin #
Name
Description
1
2
DIGITAL GROUND
OVERFLOW INH
One of four digital ground pins. All digital ground pins should be connected together.
OVERFLOW INHIBIT controls the data output polarity for overvoltage inputs.
3
HYSTERESIS
4
5
6
7
+VREF
ANALOG INPUT
ANALOG GROUND
ENCODE
8
9
10
11
12
13
14
ENCODE
ANALOG GROUND
ANALOG INPUT
–VREF
REFMID
DIGITAL GROUND
DIGITAL –VS
15
16–19
20
21, 22
D1 (LSB)
D2–D5
DIGITAL GROUND
ANALOG –VS
23
24, 25
26
27
DIGITAL GROUND
D6, D7
D8 (MSB)
OVERFLOW
28
DIGITAL –VS
Analog Input
Overflow Enabled
(Floating or –5.2 V)
of D1–D8
Overflow Inhibited (GND)
of D1–D8
VIN > +VREF
1 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1
VIN ≤ +VREF
0 X X X X X X X X
0 X X X X X X X X
The Hysteresis control voltage varies the comparator hysteresis from 0 mV to 10 mV, for a change
from –5.2 V to –2.2 V at the Hysteresis control pin. Normally converted to –5.2 V.
The most positive reference voltage for the internal resistor ladder.
One of two analog input pins. Both analog input pins should be connected together.
One of two analog ground pins. Both analog ground pins should be connected together.
Noninverted input of the differential encode input. This pin is driven in conjunction with
ENCODE. Data is latched on the rising edge of the ENCODE signal.
Inverted input of the differential encode input. This pin is driven in conjunction with ENCODE.
One of two analog ground pins. Both analog ground pins should be connected together.
One of two analog input pins. Both analog inputs should be connected together.
The most negative reference voltage for the internal resistor ladder.
The midpoint tap on the internal resistor ladder.
One of four digital ground pins. All digital ground pins should be connected together.
One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be connected together.
Digital data output.
Digital data output.
One of four digital ground pins. All digital ground pins should be connected together.
One of two negative analog supply pins (nominally –5.2 V). Both analog supply pins should be connected together.
One of four digital ground pins. All digital ground pins should be connected together.
Digital data output.
Digital data output.
Overflow data output. Logic high indicates an input overvoltage (V IN > +V REF) if OVERFLOW
INHIBIT is enabled (overflow enabled, –5.2 V). See OVERFLOW INHIBIT.
One of two negative digital supply pins (nominally –5.2 V). Both digital supply pins should be
connected together.
1 28 27 26
15
D1(LSB)
21 ANALOG
20 DIGITAL
GROUND
–VREF 11
19 D 5
12 13 14 15 16 17 18
–4–
–VS
D5
ANALOG –VS
DIGITAL GROUND
DIGITAL GROUND
D3
AD9002
16
D2
TOP
TOP VIEW
VIEW
15
D1(LSB)
(Not
(Notto
to Scale)
Scale)
14
DIGITAL –VS 28
DIGITAL
GROUND 1
OVERFLOW INH 2
DIGITAL –VS
DIGITAL
GROUND
12 REF
MID
13
HYSTERESIS 3
+VREF 4
5
6
7
8
9
10
11
–VREF
D2
TOP VIEW
(Not to Scale)
D4
17
ANALOG INPUT
16
AD9002
18
OVERFLOW 27
ANALOG GROUND
D3
DIGITAL
GROUND
22 ANALOG –VS
23
D4
D4
17
24 D6
D3
18
ENCODE 8
ANALOG 9
GROUND
ANALOG INPUT 10
25 D7
D2
–VREF 11
REFMID 12
ANALOG INPUT 5
ANALOG 6
GROUND
ENCODE 7
ANALOG –VS
25 24 23 22 21 20 19
D8(MSB) 26
ENCODE
2
ENCODE
3
D1(LSB)
TOP VIEW
(Not to Scale) 21
ANALOG –VS
ENCODE 8
DIGITAL
ANALOG 9
20
GROUND
GROUND
ANALOG INPUT 10
19 D5
DIGITAL 13
GROUND
DIGITAL –VS 14
4
DIGITAL –VS
AD9002
DIGITAL
GROUND
22 ANALOG –VS
23
REFMID
DIGITAL GROUND
ANALOG 6
GROUND
ENCODE 7
D7
D6
D6
24
ANALOG INPUT
D7
ANALOG INPUT 5
ANALOG GROUND
D8(MSB)
25
JLCC
D8(MSB)
26
+VREF 4
DIGITAL –VS
HYSTERESIS 3
OVERFLOW
OVERFLOW
OVERFLOW INH
DIGITAL –VS
27
+VREF
HYSTERESIS
28
DIGITAL GROUND
PIN DESIGNATIONS
LCC
DIP
DIGITAL 1
GROUND
OVERFLOW INH 2
1 1
REV. D
AD9002
N+1
ANALOG
INPUT
N
N+2
APERTURE
DELAY
ENCODE
t PD
OUTPUT
DATA
N–1
N+1
N
Figure 1. Timing Diagram
AD9002
+VREF
AD9002
R
AD9002
R/2
ENCODE
ANALOG
INPUT
REFMID
R/2
ENCODE
DIGITAL
OUTPUT
–5.2V
–5.2V
R
–5.2V
–VREF
–5.2V
–5.2V
COMPARATOR CELLS
Figure 2. Input/Output Circuits
OVERFLOW
INHIBIT
HYSTERESIS
DIGITAL
GROUND
DIGITAL –VS
OVERFLOW
0.1mF
+VREF
–5.2V
–VS
HYSTERESIS
OVERFLOW
D8
OVERFLOW INH
AD1
100V
1kV
AD2
AD3
1kV
–2V
ANALOG IN
D7
ENCODE
D6
ENCODE
D5
–VREF
D4
0.1mF
AD9002
D3
D2
+VREF
GROUND
1kV
1kV
1kV
D8 (MSB)
D7
ANALOG
INPUT
D6
1kV
ANALOG
GROUND
1kV
ENCODE
ANALOG –VS
1kV
ENCODE
DIGITAL
GROUND
1kV
1kV
1kV
D1
DIGITAL
GROUND
ANALOG
GROUND
D5
ANALOG
INPUT
D4
STATIC BURN IN
AD1 = 0V
AD2 = ECL HIGH
DYNAMIC BURN IN
AD1
AD3 = ECL LOW
D1 (LSB)
DIGITAL
GROUND DIGITAL
REFMID
–VS
–VREF
0V
–2V
D2
D3
ECL HIGH
AD2
Figure 4. Die Layout and Mechanical Information
ECL LOW
ECL HIGH
AD3
ECL LOW
ALL RESISTORS 6 5%, V
ALL CAPACITORS 6 20%, mF
ALL SUPPLIES 6 5%
Figure 3. Burn-in Diagram
REV. D
Die Dimensions . . . . . . . . . . . . . . . . . 106 × 114 × 15 (± 2) mils
Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils
Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold
Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None
Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS
Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride
Die Attach . . . . . . . . . . . . . . . . . . . . . Gold Eutectic (Ceramic)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Epoxy (Plastic)
Bond Wire . . . . . . . . . . . . . 1-1.3 mil Gold; Gold Ball Bonding
–5–
AD9002
APPLICATION INFORMATION
LAYOUT SUGGESTIONS
The AD9002 is compatible with all standard ECL logic families,
including 10K and 10KH. 100K ECL’s logic levels are temperature compensated, and are therefore compatible with the
AD9002 (and most other ECL device families) only over a
limited temperature range. To operate at the highest encode
rates, the supporting logic around the AD9002 will need to be
equally fast. Whichever of the ECL logic families is used, special
care must be exercised to keep digital switching noise away from
the analog circuits around the AD9002. The two most critical
items are digital supply lines and digital ground return.
Designs using the AD9002, like all high speed devices, must
follow a few basic layout rules to insure optimum performance.
Essentially, these guidelines are meant to avoid many of the
problems associated with high speed designs. The first requirement is for a substantial ground plane around and under the
AD9002. Separate ground plane areas for the digital and analog
components may be useful, but these separate grounds should
be connected together at the AD9002 to avoid the effects of
“ground loop” currents.
The second area that requires an extra degree of attention involves the three reference inputs, +VREF, REFMID, and –VREF.
The +VREF input and the –VREF input should both be driven
from a low impedance source (note that the +VREF input is
typically tied to analog ground). A low drift amplifier should
provide satisfactory results, even over an extended temperature
range. Adjustments at the REFMID input may be useful in improving the integral linearity by correcting any reference ladder
skews. The application circuit shown below demonstrates a
simple and effective means of driving the reference circuit.
The input capacitance of the AD9002 is an exceptionally low
17 pF. This allows the use of a wide range of input amplifiers,
both hybrid and monolithic. To take full advantage of the wide
input bandwidth of the AD9002, a hybrid amplifier such as the
AD9610 will be required. For those applications that do not
require the full input bandwidth of the AD9002, more traditional monolithic amplifiers, such as the AD846, will work very
well. Overall performance with any amplifier can be improved
by inserting a 10 Ω resistor in series with the amplifier output.
The reference inputs should be adequately decoupled to ground
through 0.1 µF chip capacitors to limit the effects of system
noise on conversion accuracy. The power supply pins must also
be decoupled to ground to improve noise immunity; 0.1 µF and
0.01 µF chip capacitors are recommended.
The output data is buffered through the ECL compatible output
latches. All data is delayed by one clock cycle, in addition to the
latch propagation delay (tPD), before becoming available at the
outputs. Both the analog-to-digital conversion cycle and the
data transfer to the output latches are triggered on the rising
edge of the differential, ECL compactible ENCODE signal (see
timing diagram). In applications where only a single-ended
signal is available, the AD96685, a high speed, ECL voltage
comparator, can be employed to generate the differential signals. All ECL signals (including the overflow bit) should be
terminated properly to avoid ringing and reflection.
The analog input signal is brought into the AD9002 through
two separate input pins. It is very important that the two input
pins be driven symmetrically with equal length electrical connections. Otherwise, aperture delay errors may degrade converter performance at high frequencies.
–15V
The AD9002 also incorporates a HYSTERESIS control pin
which provides from 0 mV to 10 mV of additional hysteresis in
the comparator input stages. Adjustments in the HYSTERESIS
control voltage may help improve noise immunity and overall
performance in harsh environments.
1kV
4kV
100V
ANALOG
INPUT
(0V TO +2V)
0.1mF
2N3906
AD741
The OVERFLOW INHIBIT pin of the AD9002 determines
how the converter handles overrange inputs (AIN ≥ +VREF). In
the “enabled” state (floating at –5.2 V), the OVERFLOW output will be at logic HIGH and all other outputs will be at logic
LOW for overrange inputs (return-to-zero operation). In the
“inhibited” state (tied to ground), the OVERFLOW output will
be at logic LOW, and all other outputs will be at logic HIGH
for overrange inputs (nonreturn-to-zero operation).
NYQUEST
FILTER
0.1mF
1.5kV
AIN
40V
50V
The AD9002 provides outstanding error rate performance. This
is due to tight control of comparator offset matching and a fault
tolerant decoding stage. Additional improvements in error rate
are possible through the addition of hysteresis (see HYSTERESIS control pin). This level of performance is extremely important in fault-sensitive applications such as digital radio
(QAM).
–VREF +VREF
EQUAL
DISTANCE
AD9611
ENCODE
INPUT
(GROUND
THRESHOLD)
10V
AIN
AD9002
ENCODE
50V
ENCODE
AD96685
0.01mF
OVERFLOW
D8 (MSB)
D7
D6
D5
D4
D3
D2
–5.2A –5.2D
0.1mF
0.1mF
D1 (LSB)
0.01mF
Figure 5. Typical Application
Dramatic improvements in comparator design and construction
give the AD9002 excellent dynamic characteristics, especially
SNR (signal-to-noise ratio). The 160 MHz input bandwidth
and low error rate performance give the AD9002 an SNR of
48 dB with a 1.23 MHz input. High SNR performance is particularly important in wide bandwidth applications, such as
pulse signature analysis, commonly performed in advanced
radar receivers.
–6–
REV. D
AD9002
LINEARITY OUTPUT
(ERROR WAVEFORM)
HOS100
RECONSTRUCTED
OUTPUT
HOS100
50V
1kV
–15V
1kV 4.3kV
3.75V
150V
0.1mF
2N3906
AD741 90V 20V 90V
0.01mF
AD9768
DAC
0.1mF
50V
ANALOG
INPUT
AIN
75V
10mF
–VREF REF
+VREF
MID
OVERFLOW
EQUAL
DISTANCE
50V
HOS200
2kV
D8(MSB)
D7
AIN
AD96687
D6
ENCODE
3.9kV
1kV
1kV
ENCODE INPUT
(GROUND
THRESHOLD)
–5.2V
D2
D1(LSB)
0.1mF
–5.2A
–5.2D
625V
0.1mF
0.1mF
0.01mF
AD96687
0.01mF
AD96687
AD96687
50V
510V
–5.2V
1kV
DELAY
510V
0.1mF
1kV
–5.2V
*CONTACT FACTORY ABOUT
EVALUATION BOARD AVAILABILITY
13kV
880V
13kV
–15V
DELAY
880V
–15V
Figure 6. AD9002 Evaluation Circuit
RMS SIGNAL-TO-NOISE RATIO (dB)
AND HARMONIC LEVELS (–dBc)
65
60
55
2ND HARMONIC
3RD HARMONIC
50
SNR
45
40
35
30
10MHz
100MHz
1MHz
ANALOG INPUT FREQUENCY (0.1dB BELOW FULL SCALE)
125 MSPS ENCODE RATE
Figure 7. Dynamic Performance
REV. D
37 PIN
D
CONNECTOR
D3
HYSTERESIS
–15V
LINE
DRIVER
100114
D4
OVERFLOW
INH
0.1mF
REGISTER
100151
D5
AD9002*
ENCODE
–7–
NOTE:
100114 LINE DRIVER OUTPUTS
REQUIRE 510V PULL-DOWN
RESISTORS TO –5.2V. ALL OTHER
ECL OUTPUTS SHOULD BE
TERMINATED TO –2V WITH
100V RESISTERS, UNLESS
OTHERWISE SPECIFIED.
RESISTORS ARE IN V.
CAPACITORS ARE IN mF.
AD9002
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Ceramic Side-Brazed DIP
(D-28)
28
15
1
C1043d–0–11/99
0.098 (2.49) MAX
0.005 (0.13) MIN
0.310 (7.87)
0.220 (5.59)
14
PIN 1
1.490 (37.85) MAX
0.606 (15.4)
0.58 (14.74)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.023 (0.58)
0.014 (0.36)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.070 (1.78)
0.030 (0.76)
28-Lead Ceramic Leadless Chip Carrier
(E-28A)
0.300 (7.62)
BSC
0.150
(3.51)
BSC
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.458 (11.63)
0.442 (11.23)
SQ
0.095 (2.41)
0.075 (1.90)
0.015 (0.38)
MIN
4
26
25
28
5
1
TOP
VIEW
0.458
(11.63)
MAX
SQ
0.011 (0.28)
0.007 (0.18)
R TYP
0.075
(1.91)
REF
0.088 (2.24)
0.054 (1.37)
BOTTOM
VIEW
12
11
19
18
0.200
(5.08)
BSC
0.055 (1.40)
0.045 (1.14)
0.028 (0.71)
0.022 (0.56)
0.050
(1.27)
BSC
458 TYP
28-Leaded JLCC
(J-28)
25
0.450 60.006
SQ
(11.43 60.152)
0.171 (4.34)
MAX
26
18
0.050
(1.27)
BSC
PIN 1
0.300
(7.62)
TYP
TOP VIEW
(PINS DOWN)
0.028 60.002
(0.711 60.051)
PRINTED IN U.S.A.
BOTTOM VIEW
0.039 60.005
(0.991 60.127)
19
0.420 60.010
(10.668 60.254)
0.019 60.002
(0.483 60.051)
12
4
5
0.022 60.003
(0.559 60.076)
0.488 60.010 SQ
(11.43 60.254)
–8–
11
0.102 60.010
(1.448 60.254)
0.006 60.0006
(0.152 60.015)
REV. D