TI1 AWR1642ABISABLQ1 Single-chip 77- and 79-ghz fmcw radar sensor Datasheet

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AWR1642
SWRS203A – MAY 2017 – REVISED APRIL 2018
AWR1642 Single-Chip 77- and 79-GHz FMCW Radar Sensor
1 Device Overview
1.1
Features
1
• FMCW Transceiver
– Integrated PLL, Transmitter, Receiver,
Baseband, and A2D
– 76- to 81-GHz Coverage With 4 GHz Available
Bandwidth
– Four Receive Channels
– Two Transmit Channels
– Ultra-Accurate Chirp (Timing) Engine Based on
Fractional-N PLL
– TX Power: 12.5 dBm
– RX Noise Figure:
– 14 dB (76 to 77 GHz)
– 15 dB (77 to 81 GHz)
– Phase Noise at 1 MHz:
– –95 dBc/Hz (76 to 77 GHz)
– –93 dBc/Hz (77 to 81 GHz)
• Built-in Calibration and Self-Test (Monitoring)
– ARM® Cortex®-R4F-Based Radio Control
System
– Built-in Firmware (ROM)
– Self-calibrating System Across Frequency and
Temperature
• C674x DSP for FMCW Signal Processing
• On-Chip Memory: 1.5MB
• Cortex-R4F Microcontroller for Object Tracking and
Classification, AUTOSAR, and Interface Control
– Supports Autonomous Mode (Loading User
Application from QSPI Flash Memory)
• Integrated Peripherals
– Internal Memories With ECC
• Host Interface
– CAN (Two Instances, One Being CAN-FD)
1.2
•
•
•
•
• Other Interfaces Available to User Application
– Up to 6 ADC Channels
– Up to 2 SPI Channels
– Up to 2 UARTs
– I2C
– GPIOs
– 2-Lane LVDS Interface for Raw ADC Data and
Debug Instrumentation
• ASIL B Targeted
• AECQ100 Qualified
• AWR1642 Advanced Features
– Embedded Self-monitoring With No Host
Processor Involvement
– Complex Baseband Architecture
– Embedded Interference Detection Capability
• Power Management
– Built-in LDO Network for Enhanced PSRR
– I/Os Support Dual Voltage 3.3 V/1.8 V
• Clock Source
– Supports External Oscillator at 40 MHz
– Supports Externally Driven Clock (Square/Sine)
at 40 MHz
– Supports 40 MHz Crystal Connection with Load
Capacitors
• Easy Hardware Design
– 0.65-mm Pitch, 161-Pin 10.4 mm × 10.4 mm
Flip Chip BGA Package for Easy Assembly and
Low-Cost PCB Design
– Small Solution Size
• Supports Automotive Temperature Operating
Range
Applications
Blind Spot Detection
Lane Change Assistance
Cross Traffic Alert
Parking Assistance
•
•
•
Occupancy Detection
Simple Gesture Recognition
Car Door Opener Applications
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AWR1642
SWRS203A – MAY 2017 – REVISED APRIL 2018
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40-MHz
Crystal
Serial
Flash
Power Management
QSPI
Integrated MCU
ARM Cortex-R4F
Antenna
Structure
RX1
RX2
RX3
RX4
CAN
DCAN
PHY
Automotive
Network
CAN FD
MCAN
PHY
Automotive
Network
Radar
Front End
TX1
TX2
Integrated DSP
TI C674x
AWR1642
Figure 1-1. Autonomous Radar Sensor For Automotive Applications
1.3
Description
The AWR1642 device is an integrated single-chip FMCW radar sensor capable of operation in the 76- to
81-GHz band. The device is built with TI’s low-power 45-nm RFCMOS process and enables
unprecedented levels of integration in an extremely small form factor. The AWR1642 is an ideal solution
for low-power, self-monitored, ultra-accurate radar systems in the automotive space.
The AWR1642 device is a self-contained FMCW radar sensor single-chip solution that simplifies the
implementation of Automotive Radar sensors in the band of 76 to 81 GHz. It is built on TI’s low-power 45nm RFCMOS process, which enables a monolithic implementation of a 2TX, 4RX system with built-in PLL
and A2D converters. It integrates the DSP subsystem, which contains TI's high-performance C674x DSP
for the Radar Signal processing. The device includes an ARM R4F-based processor subsystem, which is
responsible for radio configuration, control, and calibration. Simple programming model changes can
enable a wide variety of sensor implementation (Short, Mid, Long) with the possibility of dynamic
reconfiguration for implementing a multimode sensor. Additionally, the device is provided as a complete
platform solution including reference hardware design, software drivers, sample configurations, API guide,
and user documentation.
Device Information (1)
PART NUMBER
AWR1642ABIGABLQ1 (Tray)
AWR1642ABIGABLRQ1 (Reel)
(1)
2
PACKAGE
BODY SIZE
FCBGA (161)
10.4 mm × 10.4 mm
For more information, see Section 10, Mechanical Packaging and Orderable Information.
Device Overview
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1.4
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Functional Block Diagram
QSPI
RX1
LNA
IF
Cortex R4F
@ 200 MHz
ADC
SPI
Optional
External MCU
interface
SPI / I2C
PMIC control
(User programmable)
RX2
LNA
IF
Serial Flash
interface
ADC
Digital Front
End
RX3
LNA
IF
ADC
RX4
LNA
IF
ADC
Prog
RAM
(256kB*)
(Decimation
filter chain)
Data
RAM
(192kB*)
Boot
ROM
DCAN
Primary
communication
interfaces (automotive)
TX1
Bus Matrix
CAN-FD
PA
DMA
Master subsystem
(Customer programmed)
Debug
UARTs
Test/
Debug
JTAG for debug/
development
Mailbox
LVDS
TX2
For debug
PA
x4
Synth
(20 GHz)
Ramp
Generator
HIL
C674x DSP
@600 MHz
High-speed ADC
output interface
(for recording)
High-speed input for
hardware-in-loop
verification
ADC
Buffer
6
GPADC
Osc.
RF Control/
BIST
VMON
Temp
L1P
(32KB)
DMA
L1D
(32KB)
CRC
DSP subsystem
(Customer programmed)
RF/Analog subsystem
L2
(256KB)
Radar Data Memory
(L3)
768 KB*
* Up to 512 KB of Data Memory can be switched to the Master R4F if required
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Device Overview
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Table of Contents
1
2
3
Device Overview ......................................... 1
6.1
Overview
1.2
Applications ........................................... 1
6.2
Functional Block Diagram ........................... 58
1.3
Description ............................................ 2
6.3
Subsystems
1.4
Functional Block Diagram ............................ 3
6.4
Other Subsystems................................... 65
4
............................................
.........................................
58
58
Revision History ......................................... 5
Device Comparison ..................................... 7
7
Monitoring and Diagnostics.......................... 67
Related Products ..................................... 8
8
Applications, Implementation, and Layout........ 72
7.1
Monitoring and Diagnostic Mechanisms
............
Terminal Configuration and Functions .............. 9
8.1
.......................................... 9
4.2
Pin Attributes ........................................ 13
4.3
Signal Descriptions .................................. 24
Specifications ........................................... 29
5.1
Absolute Maximum Ratings ......................... 29
5.2
ESD Ratings ........................................ 29
5.3
Power-On Hours (POH) ............................. 29
5.4
Recommended Operating Conditions ............... 30
5.5
Power Supply Specifications ........................ 30
5.6
Power Consumption Summary...................... 31
5.7
RF Specification ..................................... 32
5.8
CPU Specifications .................................. 33
.................................
8.3
Reference Schematic ...............................
8.4
Layout ...............................................
Device and Documentation Support ...............
9.1
Device Nomenclature ...............................
9.2
Tools and Software .................................
9.3
Documentation Support .............................
9.4
Community Resources ..............................
9.5
Trademarks..........................................
9.6
Electrostatic Discharge Caution .....................
9.7
Export Control Notice ...............................
9.8
Glossary .............................................
4.1
5
Detailed Description ................................... 58
Features .............................................. 1
3.1
4
6
1.1
Pin Diagram
5.9
Thermal Resistance Characteristics for FCBGA
Package [ABL0161] ................................. 33
5.10
Timing and Switching Characteristics ............... 34
8.2
9
67
Application Information .............................. 72
Short-Range Radar
72
72
75
79
79
80
80
81
81
81
81
81
10 Mechanical, Packaging, and Orderable
Information .............................................. 82
10.1
Packaging Information
Table of Contents
..............................
82
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2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from May 1, 2017 to April 30, 2018 (from * Revision (May 2017) to A Revision)
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Updated/Changed document from ADVANCE INFORMATION to PRODUCTION DATA .................................. 1
Updated/Changed TX Power from "12 dBm" to "12.5 dBm" .................................................................... 1
Updated/Changed RX Noise Figure from "15 dB (76 to 77 GHz)" to "14 dB (76 to 77 GHz)" ............................. 1
Updated/Changed RX Noise Figure from "16 dB (77 to 81 GHz)" to "15 dB (77 to 81 GHz)" ............................. 1
Updated/Changed Phase Noise at 1 MHz from " –94 dBc/Hz (76 to 77 GHz)" to " –95 dBc/Hz (76 to 77 GHz)" ....... 1
Updated/Changed Phase Noise at 1 MHz from "–91 dBc/Hz (77 to 81 GHz)" to "–93 dBc/Hz (77 to 81 GHz)" ........ 1
Updated/Changed Features from "ASIL B Capable" to "ASIL B Targeted" ................................................... 1
Removed "40.0 MHz Crystal With Internal Oscillator" bullet .................................................................... 1
Updated/Changed Features from "External Oscillator at 40 and 50 MHz" to "External Oscillator at 40 MHz" ........... 1
Updated/Changed Features from "...Driven Clock (Square/Sine) at 40 and 50 MHz" to "...Driven Clock
(Square/Sine) at 40 MHz" ........................................................................................................... 1
Added "Supports 40 MHz Crystal Connection..." ................................................................................. 1
Updated RX and TX connections in Functional Block Diagram ................................................................ 3
Added GPADC block to Functional Block Diagram .............................................................................. 3
Updated/Changed Functional Block Diagram footnote text from "576 KB to 512 KB" ...................................... 3
Added AWR1243P to Device Features Comparison ............................................................................. 7
Updated/Changed Device Features Comparison ASIL for AWR1243P, AWR1243, and AWR1642 from "BCapable" to "B-Targeted" ............................................................................................................ 7
Added "Max complex sampling rate (Msps)" to Device Features Comparison ............................................... 7
Corrected A10 pin to "VOUT_14APLL"........................................................................................... 10
Updated Top Right Quadrant image to match complete Pin Diagram ....................................................... 12
Updated/Changed N14 from GPIO48 to DMM_SYNC ......................................................................... 16
Added two register tables after Pin Attributes ................................................................................... 21
Updated/Changed PAD IO Control Registers ................................................................................... 21
Updated/Changed CLKP and CLKM descriptions in Signal Descriptions ................................................... 27
Removed R14 from Power supply VIOIN ........................................................................................ 27
Added pin R15 to Power supply VSS ............................................................................................ 28
Added footnote to V(ESD) ............................................................................................................ 29
Updated/Changed VIL in Recommended Operating Conditions............................................................... 30
Updated/Changed VOH MIN from "85% VIOIN" to "VIOIN – 450"............................................................. 30
Deleted CLKP and CLKM row in Recommended Operating Conditions ..................................................... 30
Updated/Changed VOL MAX from "350" to "450" ............................................................................... 30
Added NRESET row to Recommended Operating Conditions ................................................................ 30
Completely updated Ripple Specifications table ................................................................................ 31
Updated/Changed Current consumption from "Total current drawn by all nodes driven by 1.3V rail" to "Total
current drawn by all nodes driven by 1.3V or 1.0V raisl" ...................................................................... 31
Updated Average Power Consumption at Power Terminals .................................................................. 31
Added footnote to RF Specification .............................................................................................. 32
Updated/Changed RF Specification Receiver from "...(Out of Band)..." to "...(Out of Band / Specified at 10 kHz)..." . 32
Updated/Changed RF Specification Receiver 1-dB compression Point from "–5 dBm" to "–8 dBm" .................... 32
Updated/Changed RF Specification Receiver from "IQ gain mismatch" to "Image Rejection Ratio (IMRR)" ........... 32
Removed IQ phase mismatch from RF Specification .......................................................................... 32
Updated/Changed RF Specification Receiver from "A2D sampling rate (complex)" to "A2D sampling rate
(complex 1x)" ........................................................................................................................ 32
Added multiple row to RF Specification Receiver ............................................................................... 32
Updated/Changed Power Supply Sequencing and Reset Timing image .................................................... 34
Updated/Changed Crystal Implementation image from "40 and 50 MHz" to "40 MHz" .................................... 35
Updated/Changed Crystal Implementation text from "XTALP" and "XTALM" to "CLKP" and "CLKM" .................. 35
Updated Frequency tolerance from ±50 to ±200 ................................................................................ 35
Added External Clock Electrical Characteristics ................................................................................ 36
Added External Clock Mode Specifications ...................................................................................... 36
Updated SPI Slave Mode Switching Parameters ............................................................................... 42
Updated SPI Slave Mode Timing Requirements ................................................................................ 42
Updated/Changed QSPI Timing Requirements tsu(D-SCLK) MIN value from "6.3" to "7.3" ................................... 52
Revision History
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Updated/Changed QSPI Timing Requirements th(SCLK-D) MIN value from "1" to "1.5" ......................................
Updated/Changed QSPI Timing Requirements tsu(D-SCLK) MIN value from "6.2 – P" to "7.3 – P" .........................
Updated/Changed QSPI Timing Requirements th(SCLK-D) MIN value from "1 + P" to "1.5 + P" ............................
Added Q12, Q13, Q14, and Q15 to QSPI Switching Characteristics ........................................................
Updated/Changed Clock Subsystem diagram ...................................................................................
Updated/Changed Recieve Subsystem text from "...cutoff frequencies above 350 kHz..." to "...cutoff frequencies
above 175 kHz..." ...................................................................................................................
Removed "...and ENOB of ~9 bits" from ADC Channels (Service) for User Application ..................................
Updated/Changed text from "ADC channel mapped to B12" to "GPADC channel 6" ......................................
Updated/Changed GP-ADC Parameter table ...................................................................................
Updated/Changed S No 1 in Monitoring and Diagnostic Mechanisms .......................................................
Deleted S No 6 from Monitoring and Diagnostic Mechanisms ................................................................
Updated/Changed Device Nomenclature ........................................................................................
Revision History
52
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59
60
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66
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67
80
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3 Device Comparison
Table 3-1. Device Features Comparison
FUNCTION
Number of receivers
Number of transmitters
On-chip memory
ASIL
Max I/F (Intermediate Frequency) (MHz)
Max real sampling rate (Msps)
AWR1243P
AWR1243
AWR1443
AWR1642
4
4
4
4
3 (1)
3
3
2
—
—
576KB
1.5MB
B-Targeted
B-Targeted
—
B-Targeted
15
15
5
5
37.5
Max complex sampling rate (Msps)
37.5
12.5
12.5
18.75
6.25
6.25
Processor
MCU (R4F)
—
—
Yes
Yes
DSP (C674x)
—
—
—
Yes
Serial Peripheral Interface (SPI) ports
1
1
1
2
Quad Serial Peripheral Interface (QSPI)
—
—
Yes
Yes
Inter-Integrated Circuit (I2C) interface
—
—
1
1
Controller Area Network (DCAN) interface
—
—
Yes
Yes
CAN FD
—
—
—
Yes
Trace
—
—
—
Yes
PWM
—
—
—
Yes
Hardware In Loop (HIL/DMM)
—
—
—
Yes
Peripherals
GPADC
—
—
Yes
Yes
LVDS/Debug
Yes
Yes
Yes
Yes
CSI2
Yes
Yes
—
—
Hardware accelerator
—
—
Yes
—
1-V bypass mode
Yes
Yes
Yes
Yes
Cascade (20-GHz sync)
Yes
Yes
—
—
JTAG
—
—
Yes
Yes
Number of Tx that can be simultaneously used
3
2
2
2
Yes
—
—
—
AI
AI
AI
PD
Per chirp configurable Tx phase shifter
Product
status (2)
(1)
(2)
PRODUCT PREVIEW (PP),
ADVANCE INFORMATION (AI),
or PRODUCTION DATA (PD)
3 Tx Simultaneous operation is supported only in AWR1243P with 1V (RF Supply) mode.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Device Comparison
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3.1
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Related Products
For information about other devices in this family of products or related products see the links that follow.
mmWave Sensors TI’s mmWave sensors rapidly and accurately sense range, angle and velocity with
less power using the smallest footprint mmWave sensor portfolio for automotive applications.
Automotive mmWave Sensors TI’s automotive mmWave sensor portfolio offers high-performance radar
front end to ultra-high resolution, small and low-power single-chip radar solutions. TI’s
scalable sensor portfolio enables design and development of ADAS system solution for
every performance, application and sensor configuration ranging from comfort functions to
safety functions in all vehicles.
Companion Products for AWR1642 Review products that are frequently purchased or used in
conjunction with this product.
Reference Designs for AWR1642 TI Designs Reference Design Library is a robust reference design
library spanning analog, embedded processor and connectivity. Created by TI experts to
help you jump-start your system design, all TI Designs include schematic or block diagrams,
BOMs and design files to speed your time to market. Search and download designs at
ti.com/tidesigns.
8
Device Comparison
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4 Terminal Configuration and Functions
4.1
Pin Diagram
Figure 4-1 shows the pin locations for the 161-pin FCBGA package. Figure 4-2, Figure 4-3, Figure 4-4,
and Figure 4-5 show the same pins, but split into four quadrants.
1
2
3
A
VSSA
VOUT_PA
VSSA
B
VSSA
VOUT_PA
VSSA
TX1
VSSA
TX2
VSSA
C
VSSA
VIN
_13RF2
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
F
G
VSSA
H
J
VSSA
K
L
5
6
7
VSSA
8
9
10
GPIO_46
VOUT_
14APLL
GPIO_45
GPIO_44
VBGAP
GPIO_43
GPIO_42
VSSA
11
13
14
15
VOUT
_14SYNTH
OSC
_CLKOUT
VSSA
GPADC5
GPIO_40
GPIO_41
SPIA_cs_n
GPADC6
CLKP
SPIA_mosi
GPIO_39
CLKM
VSS
SPIA_clk
SPIA_miso
VIOIN
_18DIFF
VSS
SPIB_mosi
SPIB_clk
VIOIN
SYNC_OUT
SPIB_miso
VIN_SRAM
GPIO_0
SPIB_cs_n
VDDIN
GPIO_1
LVDS_TXP0
LVDS_TXM0
GPIO_2
LVDS_TXP1
LVDS_TXM1
VPP
LVDS_CLKP
LVDS_CLKM
LVDS
_FRCLKP
LVDS
_FRCLKM
VIN
_18CLK
12
VIN
_18VCO
VIN
_13RF2
D
E
4
VSSA
M
VSSA
VSSA
VSS
RX4
VSSA
VIN_18BB
VSSA
VSSA
VIN
_13RF1
RX3
VSSA
VIN
_13RF1
VSSA
VSSA
VIN
_13RF1
RX2
VSSA
VIN_18BB
VSSA
VSSA
VSS
RX1
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N
VSSA
VSSA
VSSA
rs232_rx
rs232_tx
P
GPADC1
GPADC2
GPADC3
SYNC_in
GPIO_32
GPIO_34
R
VSSA
GPADC4
NRESET
GPIO_31
GPIO_33
VDDIN
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MCU
_CLKOUT
Warm
_Reset
TMS
VDDIN
QSPI[1]
TDO
DMM_SYNC
GPIO_47
GPIO_36
GPIO_38
PMIC
_CLKOUT
TCK
QSPI_cs_n
QSPI[3]
SPI_HOST_INTR
VNWA
VDDIN
GPIO_35
GPIO_37
VIOIN_18
VIOIN
TDI
QSPI_clk
QSPI[0]
QSPI[2]
VSS
nERROR_OUT nERROR_IN
Not to scale
Figure 4-1. Pin Diagram
Terminal Configuration and Functions
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1
2
3
4
5
6
A
VSSA
VOUT_PA
VSSA
B
VSSA
VOUT_PA
VSSA
TX1
VSSA
TX2
VSSA
GPIO_45
C
VSSA
VIN
_13RF2
VSSA
VSSA
VSSA
VSSA
VSSA
GPIO_43
VSS
VSSA
7
8
VSSA
VIN
_13RF2
D
E
VSSA
F
G
VSSA
VSSA
VSSA
VSS
RX4
VSSA
VIN_18BB
VSSA
VSSA
VIN
_13RF1
VSS
VSS
VSS
VSS
Not to scale
1
2
3
4
Figure 4-2. Top Left Quadrant
10
Terminal Configuration and Functions
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9
10
A
GPIO_46
VOUT
_14APLL
B
GPIO_44
VBGAP
C
GPIO_42
11
VSS
F
VSS
VSS
G
1
2
3
4
13
14
15
VOUT
_14SYNTH
OSC
_CLKOUT
VSSA
GPADC5
GPIO_40
GPIO_41
SPIA_cs_n
GPADC6
CLKP
SPIA_mosi
GPIO_39
CLKM
VSS
SPIA_clk
SPIA_miso
VIOIN
_18DIFF
VSS
SPIB_mosi
SPIB_clk
VIOIN
SYNC_OUT
SPIB_miso
VIN_SRAM
VIN
_18CLK
D
E
12
VIN
_18VCO
Not to scale
Figure 4-3. Top Right Quadrant
Terminal Configuration and Functions
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1
H
J
VSSA
K
L
VSSA
M
2
3
4
5
RX3
VSSA
VIN
_13RF1
VSSA
VSSA
VIN
_13RF1
RX2
VSSA
VIN_18BB
VSSA
VSSA
VSS
RX1
VSSA
6
7
8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
nERROR_OUT nERROR_IN
MCU
_CLKOUT
N
VSSA
VSSA
VSSA
rs232_rx
rs232_tx
P
GPADC1
GPADC2
GPADC3
SYNC_in
GPIO_32
GPIO_34
GPIO_36
GPIO_38
R
VSSA
GPADC4
NRESET
GPIO_31
GPIO_33
VDDIN
GPIO_35
GPIO_37
Not to scale
1
2
3
4
Figure 4-4. Bottom Left Quadrant
12
Terminal Configuration and Functions
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9
H
10
11
VSS
12
VSS
J
VSS
K
VSS
VSS
L
VSS
VSS
13
14
15
GPIO_0
SPIB_cs_n
VDDIN
GPIO_1
LVDS_TXP0
LVDS_TXM0
GPIO_2
LVDS_TXP1
LVDS_TXM1
VPP
LVDS_CLKP
LVDS_CLKM
LVDS
_FRCLKP
LVDS
_FRCLKM
M
N
Warm
_Reset
TMS
VDDIN
QSPI[1]
TDO
DMM_SYNC
GPIO_47
P
PMIC
_CLKOUT
TCK
QSPI_cs_n
QSPI[3]
SPI_HOST_INTR
VNWA
VDDIN
R
VIOIN_18
VIOIN
TDI
QSPI_clk
QSPI[0]
QSPI[2]
VSS
Not to scale
1
2
3
4
Figure 4-5. Bottom Right Quadrant
4.2
Pin Attributes
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (ABL0161 Package)
BALL NUMBER [1]
H13
J13
K13
R4
P5
BALL NAME [2]
GPIO_0
GPIO_1
GPIO_2
GPIO_31
GPIO_32
SIGNAL NAME [3]
GPIO_13
PINCNTL
ADDRESS [4]
0xFFFFEA04
0
IO
1
IO
PMIC_CLKOUT
2
O
ePWM1b
10
O
ePWM2a
11
O
0
IO
GPIO_1
1
IO
SYNC_OUT
2
O
DMM_MUX_IN
12
I
SPIB_cs_n_1
13
IO
SPIB_cs_n_2
14
IO
ePWM1SYNCI
15
I
0
IO
GPIO_2
1
IO
OSC_CLKOUT
2
O
MSS_uartb_tx
7
O
BSS_uart_tx
8
O
SYNC_OUT
9
O
PMIC_CLKOUT
10
O
0
O
GPIO_31
1
IO
DMM0
2
I
MSS_uarta_tx
4
IO
0
O
1
IO
2
I
0
O
1
IO
2
I
0
O
GPIO_34
1
IO
DMM3
2
I
ePWM3SYNCO
4
O
0
O
GPIO_35
1
IO
DMM4
2
I
ePWM2SYNCO
4
O
GPIO_16
0xFFFFEA08
GPIO_26
0xFFFFEA64
TRACE_DATA_0
0xFFFFEA7C
TRACE_DATA_1
0xFFFFEA80
DMM1
GPIO_33
TRACE_DATA_2
0xFFFFEA84
GPIO_33
DMM2
P6
R7
14
GPIO_34
GPIO_35
TYPE [6]
GPIO_0
GPIO_32
R5
MODE [5]
TRACE_DATA_3
0xFFFFEA88
TRACE_DATA_4
0xFFFFEA8C
Terminal Configuration and Functions
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
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Table 4-1. Pin Attributes (ABL0161 Package) (continued)
BALL NUMBER [1]
P7
R8
P8
D14
B14
B15
C9
C8
BALL NAME [2]
GPIO_36
GPIO_37
GPIO_38
GPIO_39
GPIO_40
GPIO_41
GPIO_42
GPIO_43
SIGNAL NAME [3]
TRACE_DATA_5
PINCNTL
ADDRESS [4]
0xFFFFEA90
MODE [5]
TYPE [6]
0
O
GPIO_36
1
IO
DMM5
2
I
MSS_uartb_tx
5
O
0
O
GPIO_37
1
IO
DMM6
2
I
BSS_uart_tx
5
O
0
O
GPIO_38
1
IO
DMM7
2
I
DSS_uart_tx
5
O
0
O
GPIO_39
1
IO
DMM8
2
I
CAN_FD_tx
4
IO
ePWM1SYNCI
5
I
0
O
GPIO_40
1
IO
DMM9
2
I
CAN_FD_rx
4
IO
ePWM1SYNCO
5
O
0
O
GPIO_41
1
IO
DMM10
2
I
ePWM3a
4
O
0
O
GPIO_42
1
IO
DMM11
2
I
ePWM3b
4
O
0
O
GPIO_43
1
IO
DMM12
2
I
ePWM1a
4
O
CAN_tx
5
IO
TRACE_DATA_6
0xFFFFEA94
TRACE_DATA_7
0xFFFFEA98
TRACE_DATA_8
0xFFFFEA9C
TRACE_DATA_9
0xFFFFEAA0
TRACE_DATA_10
TRACE_DATA_11
TRACE_DATA_12
0xFFFFEAA4
0xFFFFEAA8
0xFFFFEAAC
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (ABL0161 Package) (continued)
BALL NUMBER [1]
B9
B8
A9
N15
BALL NAME [2]
GPIO_44
GPIO_45
GPIO_46
GPIO_47
SIGNAL NAME [3]
TRACE_DATA_13
PINCNTL
ADDRESS [4]
0
O
1
IO
DMM13
2
I
ePWM1b
4
O
CAN_rx
5
I
0
O
GPIO_45
1
IO
DMM14
2
I
ePWM2a
4
O
0
O
GPIO_46
1
IO
DMM15
2
I
ePWM2b
4
O
0
O
1
IO
2
I
0
O
1
IO
2
I
0
IO
1
O
TRACE_DATA_15
TRACE_CLK
0xFFFFEAB4
0xFFFFEAB8
0xFFFFEABC
GPIO_47
DMM_CLK
N14
DMM_SYNC
TRACE_CTL
0xFFFFEAC0
RESERVED
DMM_SYNC
N8
MCU_CLKOUT
TYPE [6]
GPIO_44
TRACE_DATA_14
0xFFFFEAB0
MODE [5]
GPIO_25
0xFFFFEA60
MCU_CLKOUT
ePWM1a
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Down
12
O
N7
nERROR_IN
nERROR_IN
0xFFFFEA44
0
I
Input
N6
nERROR_OUT
nERROR_OUT
0xFFFFEA4C
0
O
Hi-Z (Open Drain)
P9
PMIC_CLKOUT
SOP[2]
0xFFFFEA68
During Power Up
I
Output Disabled
Pull Down
GPIO_27
0
IO
PMIC_CLKOUT
1
O
ePWM1b
11
O
ePWM2a
12
O
0
IO
Output Disabled
Pull Down
1
IO
2
IO
0
IO
Output Disabled
Pull Down
QSPI[1]
1
IO
SPIB_mosi
2
IO
SPIB_cs_n_2
8
IO
0
IO
Output Disabled
Pull Down
QSPI[2]
1
I
CAN_FD_tx
8
O
R13
QSPI[0]
GPIO_8
0xFFFFEA2C
QSPI[0]
SPIB_miso
N12
R14
16
QSPI[1]
QSPI[2]
GPIO_9
0xFFFFEA30
GPIO_10
0xFFFFEA34
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (ABL0161 Package) (continued)
BALL NUMBER [1]
P12
BALL NAME [2]
QSPI[3]
SIGNAL NAME [3]
GPIO_11
PINCNTL
ADDRESS [4]
0xFFFFEA38
IO
1
IO
8
I
0
IO
QSPI_clk
1
IO
SPIB_clk
2
IO
DSS_uart_tx
6
O
0
IO
1
IO
2
IO
0
IO
rs232_rx
1
I
MSS_uarta_rx
2
I
BSS_uart_tx
6
IO
MSS_uartb_rx
7
IO
CAN_FD_rx
8
I
I2C_scl
9
IO
ePWM2a
10
O
ePWM2b
11
O
ePWM3a
12
O
0
IO
rs232_tx
1
O
MSS_uarta_tx
5
IO
MSS_uartb_tx
6
IO
BSS_uart_tx
7
IO
CAN_FD_tx
10
O
I2C_sda
11
IO
ePWM1a
12
O
ePWM1b
13
O
NDMM_EN
14
I
ePWM2a
15
O
0
IO
SPIA_clk
1
IO
CAN_rx
6
I
DSS_uart_tx
7
O
0
IO
SPIA_cs_n
1
IO
CAN_tx
6
O
CAN_FD_rx
P11
QSPI_clk
QSPI_cs_n
GPIO_7
0xFFFFEA3C
GPIO_6
0xFFFFEA40
QSPI_cs_n
SPIB_cs_n
N4
N5
E13
C13
rs232_rx
rs232_tx
SPIA_clk
SPIA_cs_n
TYPE [6]
0
QSPI[3]
R12
MODE [5]
GPIO_15
0xFFFFEA74
GPIO_14
0xFFFFEA78
GPIO_3
0xFFFFEA14
GPIO_30
0xFFFFEA18
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
Output Disabled
Pull Down
Output Disabled
Pull Down
Output Disabled
Pull Up
Input Enabled
Pull Up
Output Enabled
Output Disabled
Pull Up
Output Disabled
Pull Up
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (ABL0161 Package) (continued)
BALL NUMBER [1]
E14
BALL NAME [2]
SPIA_miso
SIGNAL NAME [3]
GPIO_20
PINCNTL
ADDRESS [4]
0xFFFFEA10
IO
1
IO
2
O
0
IO
SPIA_mosi
1
IO
CAN_FD_rx
2
I
DSS_uart_tx
8
O
0
IO
SPIB_clk1
1
IO
MSS_uarta_rx
2
I
MSS_uartb_tx
6
O
BSS_uart_tx
7
O
CAN_FD_rx
8
I
0
IO
SPIB_cs_n
1
IO
MSS_uarta_tx
2
O
MSS_uartb_tx
6
O
BSS_uart_tx
7
IO
QSPI_clk_ext
8
I
CAN_FD_tx
9
O
0
IO
SPIB_miso
1
IO
I2C_scl
2
IO
DSS_uart_tx
6
O
0
IO
1
IO
2
IO
0
IO
1
O
6
IO
0
IO
SYNC_IN
1
I
MSS_uartb_rx
6
IO
DMM_MUX_IN
7
I
SYNC_OUT
9
O
CAN_FD_tx
F14
H14
G14
F13
SPIA_mosi
SPIB_clk
SPIB_cs_n
SPIB_miso
SPIB_mosi
GPIO_19
0xFFFFEA0C
GPIO_5
0xFFFFEA24
GPIO_4
0xFFFFEA28
GPIO_22
0xFFFFEA20
GPIO_21
0xFFFFEA1C
SPIB_mosi
I2C_sda
P13
SPI_HOST_INTR
GPIO_12
0xFFFFEA00
SPI_HOST_INTR
SPIB_cs_n_1
P4
18
SYNC_in
TYPE [6]
0
SPIA_miso
D13
MODE [5]
GPIO_28
0xFFFFEA6C
Terminal Configuration and Functions
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
Output Disabled
Pull Up
Output Disabled
Pull Up
Output Disabled
Pull Up
Output Disabled
Pull Up
Output Disabled
Pull Up
Output Disabled
Pull Up
Output Disabled
Pull Down
Output Disabled
Pull Down
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Table 4-1. Pin Attributes (ABL0161 Package) (continued)
BALL NUMBER [1]
G13
P10
R11
BALL NAME [2]
SYNC_OUT
TCK
TDI
SIGNAL NAME [3]
SOP[1]
PINCNTL
ADDRESS [4]
0xFFFFEA70
During Power Up
I
0
IO
SYNC_OUT
1
O
DMM_MUX_IN
9
I
SPIB_cs_n_1
10
IO
SPIB_cs_n_2
11
IO
0
IO
TCK
1
I
MSS_uartb_tx
2
O
CAN_FD_tx
8
O
0
IO
1
I
2
I
During Power Up
I
GPIO_24
0
IO
TDO
1
O
MSS_uarta_tx
2
O
MSS_uartb_tx
6
O
BSS_uart_tx
7
O
NDMM_EN
9
I
0
IO
TMS
1
I
BSS_uart_tx
2
O
CAN_FD_rx
6
I
0
IO
GPIO_17
0xFFFFEA50
GPIO_23
0xFFFFEA58
MSS_uarta_rx
N10
N9
TDO
TMS
Warm_Reset
TYPE [6]
GPIO_29
TDI
N13
MODE [5]
SOP[0]
0xFFFFEA5C
GPIO_18
0xFFFFEA54
Warm_Reset
0xFFFFEA48
BALL RESET
STATE [7]
PULL UP/DOWN
TYPE [8]
Output Disabled
Pull Down
Input Enabled
Pull Down
Input Enabled
Pull Up
Output Enabled
Input Enabled
Pull Down
Hi-Z Input (Open
Drain)
The following list describes the table column headers:
1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).
4. PINCNTL ADDRESS: MSS Address for PinMux Control
5. MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has
bit range value.
6. TYPE: Signal type and direction:
– I = Input
– O = Output
Terminal Configuration and Functions
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– IO = Input or Output
7. BALL RESET STATE: The state of the terminal at power-on reset
8. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or
disabled via software.
– Pull Up: Internal pullup
– Pull Down: Internal pulldown
– An empty box means No pull.
9. Pin Mux Control Value maps to lower 4 bits of register.
20
Terminal Configuration and Functions
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IO MUX registers are available in the MSS memory map and the respective mapping to device pins is as follows:
Table 4-2. PAD IO Control Registers
Default Pin/Ball Name
Package Ball /Pin (Address)
Pin Mux Config Register
SPI_HOST_INTR
P13
0xFFFFEA00
GPIO_0
H13
0xFFFFEA04
GPIO_1
J13
0xFFFFEA08
SPIA_mosi
D13
0xFFFFEA0C
SPIA_miso
E14
0xFFFFEA10
0xFFFFEA14
SPIA_clk
E13
SPIA_cs_n
C13
0xFFFFEA18
SPIB_mosi
F13
0xFFFFEA1C
SPIB_miso
G14
0xFFFFEA20
SPIB_clk
F14
0xFFFFEA24
SPIB_cs_n
H14
0xFFFFEA28
QSPI[0]
R13
0xFFFFEA2C
QSPI[1]
N12
0xFFFFEA30
QSPI[2]
R14
0xFFFFEA34
QSPI[3]
P12
0xFFFFEA38
QSPI_clk
R12
0xFFFFEA3C
QSPI_csn_n
P11
0xFFFFEA40
nERROR_IN
N7
0xFFFFEA44
Warm_Reset
N9
0xFFFFEA48
nERROR_OUT
N6
0xFFFFEA4C
TCK
P10
0xFFFFEA50
TMS
N10
0xFFFFEA54
TDI
R11
0xFFFFEA58
TDO
N13
0xFFFFEA5C
MCU_CLKOUT
N8
0xFFFFEA60
0xFFFFEA64
GPIO_2
K13
PMIC_CLKOUT
P9
0xFFFFEA68
SYNC_in
P4
0xFFFFEA6C
SYNC_OUT
G13
0xFFFFEA70
rs232_rx
N4
0xFFFFEA74
rs232_tx
N5
0xFFFFEA78
Terminal Configuration and Functions
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Table 4-2. PAD IO Control Registers (continued)
22
Default Pin/Ball Name
Package Ball /Pin (Address)
Pin Mux Config Register
GPIO_31
R4
0xFFFFEA7C
GPIO_32
P5
0xFFFFEA80
GPIO_33
R5
0xFFFFEA84
GPIO_34
P6
0xFFFFEA88
GPIO_35
R7
0xFFFFEA8C
GPIO_36
P7
0xFFFFEA90
GPIO_37
R8
0xFFFFEA94
GPIO_38
P8
0xFFFFEA98
GPIO_39
D14
0xFFFFEA9C
GPIO_40
B14
0xFFFFEAA0
GPIO_41
B15
0xFFFFEAA4
GPIO_42
C9
0xFFFFEAA8
GPIO_43
C8
0xFFFFEAAC
GPIO_44
B9
0xFFFFEAB0
GPIO_45
B8
0xFFFFEAB4
GPIO_46
A9
0xFFFFEAB8
GPIO_47
N15
0xFFFFEABC
DMM_SYNC
N14
0xFFFFEAC0
Terminal Configuration and Functions
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The register layout is as follows:
Table 4-3. PAD IO Register Bit Descriptions
BIT
FIELD
31-11 NU
TYPE
RESET
(POWER ON
DEFAULT)
DESCRIPTION
RW
0
Reserved
10
SC
RW
0
IO slew rate control:
0 = Higher slew rate
1 = Lower slew rate
9
PUPDSEL
RW
0
Pullup/PullDown Selection
0 = Pull Down
1 = Pull Up (This field is valid only if Pull Inhibit is set as '0')
8
PI
RW
0
Pull Inhibit/Pull Disable
0 = Enable
1 = Disable
7
OE_OVERRIDE
RW
1
Output Override
6
OE_OVERRIDE_CTR RW
L
1
Output Override Control:
(A '1' here overrides any o/p manipulation of this IO by any of the peripheral
block hardware it is associated with for example a SPI Chip select)
5
IE_OVERRIDE
RW
0
Input Override
4
IE_OVERRIDE_CTR
L
RW
0
Input Override Control:
(A '1' here overrides any i/p value on this IO with a desired value)
FUNC_SEL
RW
1
Function select for Pin Multiplexing (Refer to the Pin Mux Sheet)
3-0
Terminal Configuration and Functions
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Signal Descriptions
Table 4-4. Signal Descriptions - Digital
SIGNAL NAME
PIN TYPE
DESCRIPTION
BALL NO.
BSS_UART_TX
O
Debug UART Transmit [Radar Block]
F14, H14, K13, N10, N13,
N4, N5, R8
CAN_FD_RX
I
CAN FD (MCAN) Receive Signal
B14, D13, F14, N10, N4,
P12
CAN_FD_TX
O
CAN FD (MCAN) Transmit Signal
D14, E14, H14, N5, P10,
R14
CAN_RX
I
CAN (DCAN) Receive Signal
B9, E13
CAN_TX
IO
CAN (DCAN) Transmit Signal
C13, C8
DMM0
I
Debug Interface (Hardware In Loop) - Data Line
R4
DMM1
I
Debug Interface (Hardware In Loop) - Data Line
P5
DMM2
I
Debug Interface (Hardware In Loop) - Data Line
R5
DMM3
I
Debug Interface (Hardware In Loop) - Data Line
P6
DMM4
I
Debug Interface (Hardware In Loop) - Data Line
R7
DMM5
I
Debug Interface (Hardware In Loop) - Data Line
P7
DMM6
I
Debug Interface (Hardware In Loop) - Data Line
R8
DMM7
I
Debug Interface (Hardware In Loop) - Data Line
P8
DMM8
I
Debug Interface (Hardware In Loop) - Data Line
D14
DMM9
I
Debug Interface (Hardware In Loop) - Data Line
B14
DMM10
I
Debug Interface (Hardware In Loop) - Data Line
B15
DMM11
I
Debug Interface (Hardware In Loop) - Data Line
C9
DMM12
I
Debug Interface (Hardware In Loop) - Data Line
C8
DMM13
I
Debug Interface (Hardware In Loop) - Data Line
B9
DMM14
I
Debug Interface (Hardware In Loop) - Data Line
B8
DMM15
I
Debug Interface (Hardware In Loop) - Data Line
DMM_CLK
I
Debug Interface (Hardware In Loop) - Clock
DMM_MUX_IN
I
Debug Interface (Hardware In Loop) Mux Select between DMM1 and
DMM2 (Two Instances)
DMM_SYNC
I
Debug Interface (Hardware In Loop) - Sync
DSS_UART_TX
O
Debug UART Transmit [DSP]
EPWM1A
O
PWM Module 1 - OutPut A
C8, N5, N8
EPWM1B
O
PWM Module 1 - OutPut B
B9, H13, N5, P9
EPWM1SYNCI
I
D14, J13
EPWM1SYNCO
O
B14
EPWM2A
O
PWM Module 2- OutPut A
B8, H13, N4, N5, P9
EPWM2B
O
PWM Module 2 - OutPut B
A9, N4
EPWM2SYNCO
O
EPWM3A
O
PWM Module 3 - OutPut A
B15, N4
EPWM3B
O
PWM Module 3 - OutPut B
C9
EPWM3SYNCO
O
GPIO_0
IO
General-purpose I/O
H13
GPIO_1
IO
General-purpose I/O
J13
GPIO_2
IO
General-purpose I/O
K13
GPIO_3
IO
General-purpose I/O
E13
GPIO_4
IO
General-purpose I/O
H14
GPIO_5
IO
General-purpose I/O
F14
GPIO_6
IO
General-purpose I/O
P11
GPIO_7
IO
General-purpose I/O
R12
24
A9
N15
G13, J13, P4
N14
D13, E13, G14, P8, R12
R7
P6
Terminal Configuration and Functions
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Table 4-4. Signal Descriptions - Digital (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
BALL NO.
GPIO_8
IO
General-purpose I/O
R13
GPIO_9
IO
General-purpose I/O
N12
GPIO_10
IO
General-purpose I/O
R14
GPIO_11
IO
General-purpose I/O
P12
GPIO_12
IO
General-purpose I/O
P13
GPIO_13
IO
General-purpose I/O
H13
GPIO_14
IO
General-purpose I/O
N5
GPIO_15
IO
General-purpose I/O
N4
GPIO_16
IO
General-purpose I/O
J13
GPIO_17
IO
General-purpose I/O
P10
GPIO_18
IO
General-purpose I/O
N10
GPIO_19
IO
General-purpose I/O
D13
GPIO_20
IO
General-purpose I/O
E14
GPIO_21
IO
General-purpose I/O
F13
GPIO_22
IO
General-purpose I/O
G14
GPIO_23
IO
General-purpose I/O
R11
GPIO_24
IO
General-purpose I/O
N13
GPIO_25
IO
General-purpose I/O
N8
GPIO_26
IO
General-purpose I/O
K13
GPIO_27
IO
General-purpose I/O
P9
GPIO_28
IO
General-purpose I/O
P4
GPIO_29
IO
General-purpose I/O
G13
GPIO_30
IO
General-purpose I/O
C13
GPIO_31
IO
General-purpose I/O
R4
GPIO_32
IO
General-purpose I/O
P5
GPIO_33
IO
General-purpose I/O
R5
GPIO_34
IO
General-purpose I/O
P6
GPIO_35
IO
General-purpose I/O
R7
GPIO_36
IO
General-purpose I/O
P7
GPIO_37
IO
General-purpose I/O
R8
GPIO_38
IO
General-purpose I/O
P8
GPIO_39
IO
General-purpose I/O
D14
GPIO_40
IO
General-purpose I/O
B14
GPIO_41
IO
General-purpose I/O
B15
GPIO_42
IO
General-purpose I/O
C9
GPIO_43
IO
General-purpose I/O
C8
GPIO_44
IO
General-purpose I/O
B9
GPIO_45
IO
General-purpose I/O
B8
GPIO_46
IO
General-purpose I/O
A9
GPIO_47
IO
General-purpose I/O
N15
I2C_SCL
IO
I2C Clock
G14, N4
I2C_SDA
IO
I2C Data
F13, N5
LVDS_TXP[0]
O
LVDS_TXM[0]
O
LVDS_TXP[1]
O
LVDS_TXM[1]
O
Differential data Out – Lane 0
Differential data Out – Lane 1
J14
J15
K14
K15
Terminal Configuration and Functions
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Table 4-4. Signal Descriptions - Digital (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
BALL NO.
LVDS_CLKP
O
L14
LVDS_CLKM
O
LVDS_FRCLKP
O
LVDS_FRCLKM
O
MCU_CLKOUT
O
Programmable clock given out to external MCU or the processor
MSS_UARTA_RX
I
Master Subsystem - UART A Receive
F14, N4, R11
MSS_UARTA_TX
O
Master Subsystem - UART A Transmit
H14, N13, N5, R4
MSS_UARTB_RX
IO
Master Subsystem - UART B Receive
N4, P4
F14, H14, K13, N13, N5,
P10, P7
Differential clock Out
L15
M14
Differential Frame Clock
M15
N8
MSS_UARTB_TX
O
Master Subsystem - UART B Transmit
NDMM_EN
I
Debug Interface (Hardware In Loop) Enable - Active Low Signal
nERROR_IN
I
Failsafe input to the device. Nerror output from any other device can
be concentrated in the error signaling monitor module inside the
device and appropriate action can be taken by Firmware
N7
nERROR_OUT
O
Open drain fail safe output signal. Connected to
PMIC/Processor/MCU to indicate that some severe criticality fault
has happened. Recovery would be through reset.
N6
PMIC_CLKOUT
O
Output Clock from AWR1642 device for PMIC
QSPI[0]
IO
QSPI Data Line #0 (Used with Serial Data Flash)
R13
QSPI[1]
IO
QSPI Data Line #1 (Used with Serial Data Flash)
N12
QSPI[2]
I
QSPI Data Line #2 (Used with Serial Data Flash)
R14
QSPI[3]
IO
QSPI Data Line #3 (Used with Serial Data Flash)
P12
QSPI_CLK
IO
QSPI Clock (Used with Serial Data Flash)
R12
I
QSPI Clock (Used with Serial Data Flash)
H14
QSPI Chip Select (Used with Serial Data Flash)
P11
N4
QSPI_CLK_EXT
QSPI_CS_N
IO
N13, N5
H13, K13, P9
RS232_RX
I
Debug UART (Operates as Bus Master) - Receive Signal
RS232_TX
O
Debug UART (Operates as Bus Master) - Transmit Signal
N5
SOP[0]
I
Sense On Power - Line#0
N13
SOP[1]
I
Sense On Power - Line#1
G13
SOP[2]
I
Sense On Power - Line#2
P9
SPIA_CLK
IO
SPI Channel A - Clock
E13
SPIA_CS_N
IO
SPI Channel A - Chip Select
C13
SPIA_MISO
IO
SPI Channel A - Master In Slave Out
E14
SPIA_MOSI
IO
SPI Channel A - Master Out Slave In
D13
SPIB_CLK
IO
SPI Channel B - Clock
SPIB_CS_N
IO
SPI Channel B Chip Select (Instance ID 0)
H14, P11
SPIB_CS_N_1
IO
SPI Channel B Chip Select (Instance ID 1)
G13, J13, P13
SPIB_CS_N_2
IO
SPI Channel B Chip Select (Instance ID 2)
G13, J13, N12
SPIB_MISO
IO
SPI Channel B - Master In Slave Out
G14, R13
SPIB_MOSI
IO
SPI Channel B - Master Out Slave In
F13, N12
SPI_HOST_INTR
O
Out of Band Interrupt to an external host communicating over SPI
P13
SYNC_IN
I
Low frequency Synchronization signal input
P4
SYNC_OUT
O
Low Frequency Synchronization Signal output
TCK
I
JTAG Test Clock
P10
TDI
I
JTAG Test Data Input
R11
TDO
O
JTAG Test Data Output
N13
TMS
I
JTAG Test Mode Signal
N10
TRACE_CLK
O
Debug Trace Output - Clock
N15
TRACE_CTL
O
Debug Trace Output - Control
N14
26
Terminal Configuration and Functions
F14, R12
G13, J13, K13, P4
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Table 4-4. Signal Descriptions - Digital (continued)
SIGNAL NAME
PIN TYPE
DESCRIPTION
BALL NO.
TRACE_DATA_0
O
Debug Trace Output - Data Line
TRACE_DATA_1
O
Debug Trace Output - Data Line
P5
TRACE_DATA_2
O
Debug Trace Output - Data Line
R5
TRACE_DATA_3
O
Debug Trace Output - Data Line
P6
TRACE_DATA_4
O
Debug Trace Output - Data Line
R7
TRACE_DATA_5
O
Debug Trace Output - Data Line
P7
TRACE_DATA_6
O
Debug Trace Output - Data Line
R8
TRACE_DATA_7
O
Debug Trace Output - Data Line
P8
TRACE_DATA_8
O
Debug Trace Output - Data Line
D14
TRACE_DATA_9
O
Debug Trace Output - Data Line
B14
TRACE_DATA_10
O
Debug Trace Output - Data Line
B15
TRACE_DATA_11
O
Debug Trace Output - Data Line
C9
TRACE_DATA_12
O
Debug Trace Output - Data Line
C8
TRACE_DATA_13
O
Debug Trace Output - Data Line
B9
TRACE_DATA_14
O
Debug Trace Output - Data Line
B8
TRACE_DATA_15
O
Debug Trace Output - Data Line
A9
IO
Open drain fail safe warm reset signal. Can be driven from PMIC for
diagnostic or can be used as status signal that the device is going
through reset.
N9
WARM_RESET
R4
Table 4-5. Signal Descriptions - Analog
INTERFACE
SIGNAL NAME
PIN
TYPE
DESCRIPTION
BALL NO.
TX1
O
Single ended transmitter1 o/p
TX2
O
Single ended transmitter2 o/p
B6
RX1
I
Single ended receiver1 i/p
M2
RX2
I
Single ended receiver2 i/p
K2
RX3
I
Single ended receiver3 i/p
H2
RX4
I
Single ended receiver4 i/p
F2
NRESET
I
Power on reset for chip. Active low
R3
CLKP
I
In XTAL mode: Differential port for reference crystal
In External clock mode: Single ended input
reference clock port
C15
CLKM
I
In XTAL mode: Differential port for reference crystal
In External clock mode: Connect this port to ground
D15
Reference clock
OSC_CLKOUT
O
Reference clock output from clocking sub system
after cleanup PLL (1.8V output voltage swing).
A14
Bandgap voltage
VBGAP
O
VDDIN
Power
1.2V digital power supply
VIN_SRAM
Power
1.2V power rail for internal SRAM
G15
VNWA
Power
1.2V power rail for SRAM array back bias
P14
VIOIN
Power
I/O Supply (3.3V or 1.8V): All CMOS I/Os would
operate on this supply
VIOIN_18
Power
1.8V supply for CMOS IO
R9
VIN_18CLK
Power
1.8V supply for clock module
B11
VIOIN_18DIFF
Power
1.8V supply for LVDS port
E15
VPP
Power
Voltage supply for fuse chain
L13
Transmitters
Receivers
Reset
Reference
Oscillator
Power supply
B4
B10
H15, N11, P15, R6
R10, F15
Terminal Configuration and Functions
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Table 4-5. Signal Descriptions - Analog (continued)
INTERFACE
PIN
TYPE
SIGNAL NAME
DESCRIPTION
VIN_13RF1
Power
1.3V Analog and RF supply,VIN_13RF1 and
VIN_13RF2 could be shorted on the board
VIN_13RF2
Power
1.3V Analog and RF supply
C2,D2
VIN_18BB
Power
1.8V Analog base band power supply
K5, F5
VIN_18VCO
Power
1.8V RF VCO supply
VSS
Ground
VSSA
Test and Debug
output for preproduction phase.
Can be pinned out
on production
hardware for field
debug
(1)
28
Ground
G5, H5, J5
B12
Digital ground
L5, L6, L8, L10,
K7, K8, K9, K10,
K11, J6, J7, J8,
J10, H7, H9, H11,
G6, G7, G8, G10,
F9, F11, E5, E6,
E8, E10, E11, R15
Analog ground
A1, A3, A5, A7,
A15, B1, B3, B5,
B7, C1, C3, C4,
C5, C6, C7, E1,
E2, E3, F3, G1,
G2, G3, H3, J1, J2,
J3, K3, L1, L2, L3,
M3, N1, N2, N3,
R1
Power supply
Internal LDO
output/inputs
BALL NO.
VOUT_14APLL
O
A10
VOUT_14SYNTH
O
A13
VOUT_PA
O
Analog Test1 / ADC1
IO
ADC Channel 1 (1)
P1
Analog Test2 / ADC2
IO
ADC Channel 2 (1)
P2
Analog Test3 / ADC3
IO
ADC Channel 3
(1)
P3
Analog Test4 / ADC4
IO
ADC Channel 4 (1)
R2
ANAMUX / ADC5
IO
ADC Channel 5 (1)
B13
IO
(1)
C14
VSENSE / ADC6
A2, B2
ADC Channel 6
For details, see Section 6.4.1.
Specifications
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5 Specifications
Absolute Maximum Ratings (1) (2)
5.1
MIN
MAX
VDDIN
1.2 V digital power supply
PARAMETERS
–0.5
1.4
V
VIN_SRAM
1.2 V power rail for internal SRAM
–0.5
1.4
V
VNWA
1.2 V power rail for SRAM array back bias
–0.5
1.4
V
VIOIN
I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this
supply.
–0.5
3.8
V
VIOIN_18
1.8 V supply for CMOS IO
–0.5
2
V
VIN_18CLK
1.8 V supply for clock module
–0.5
2
V
VIOIN_18DIFF
1.8 V supply for port
VIOIN_18DIFF
1.8 V supply for LVDS port
–0.5
2
V
VIN_13RF1
1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could
be shorted on the board.
–0.5
1.45
V
1-V Internal LDO bypass mode. Device supports mode where
external Power Management block can supply 1 V on
VIN_13RF1 and VIN_13RF2 rails. In this configuration, the
internal LDO of the device would be kept bypassed.
–0.5
1.4
V
VIN_18BB
1.8-V Analog baseband power supply
–0.5
2
V
VIN_18VCO supply
1.8-V RF VCO supply
–0.5
2
V
–0.3V
VIOIN + 0.3
VIN_13RF2
VIN_13RF1
VIN_13RF2
Input and output
voltage range
Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)
Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V
(Transient Overshoot/Undershoot) or external oscillator input
UNIT
V
VIOIN + 20% up to
20% of signal period
CLKP, CLKM
Input ports for reference crystal
–0.5
2
V
Clamp current
Input or Output Voltages 0.3 V above or below their respective
power rails. Limit clamp current that flows through the internal
diode protection cells of the I/O.
–20
20
mA
TJ
Operating junction temperature range
–40
125
ºC
TSTG
Storage temperature range after soldered onto PC board
–55
150
ºC
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS, unless otherwise noted.
5.2
ESD Ratings
VALUE
V(ESD)
(1)
(2)
5.3
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
Charged-device model (CDM), per AEC Q100-011 (2)
UNIT
±1000
±250
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Corner pins are rated as ±750 V
Power-On Hours (POH) (1)
JUNCTION
TEMPERATURE (Tj)
OPERATING
CONDITION
NOMINAL CVDD VOLTAGE (V)
POWER-ON HOURS [POH] (HOURS)
–40°C
600 (6%)
75°C
2000 (20%)
95°C
100% duty cycle
1.2
125°C
(1)
(1)
6500 (65%)
900 (9%)
This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms
and conditions for TI semiconductor products.
Specifications
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Recommended Operating Conditions
MIN
NOM
MAX
UNIT
VDDIN
1.2 V digital power supply
1.14
1.2
1.32
V
VIN_SRAM
1.2 V power rail for internal SRAM
1.14
1.2
1.32
V
VNWA
1.2 V power rail for SRAM array back bias
1.14
1.2
1.32
V
VIOIN
I/O supply (3.3 V or 1.8 V):
All CMOS I/Os would operate on this supply.
3.15
3.3
3.45
1.71
1.8
1.89
VIOIN_18
1.8 V supply for CMOS IO
1.71
1.8
1.9
V
VIN_18CLK
1.8 V supply for clock module
1.71
1.8
1.9
V
VIOIN_18DIFF
1.8 V supply for LVDS port
1.71
1.8
1.9
V
VIN_13RF1
1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2
could be shorted on the board
1.23
1.3
1.36
V
1.23
1.3
1.36
V
0.95
1
1.05
V
0.95
1
1.05
V
VIN_13RF2
VIN_13RF1
(1-V Internal LDO
bypass mode)
Device supports mode where external Power Management
block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In
this configuration, the internal LDO of the device would be
kept bypassed.
VIN_13RF2
(1-V Internal LDO
bypass mode)
V
VIN18BB
1.8-V Analog baseband power supply
1.71
1.8
1.9
V
VIN_18VCO
1.8V RF VCO supply
1.71
1.8
1.9
V
Voltage Input High (1.8 V mode)
1.17
Voltage Input High (3.3 V mode)
2.25
VIH
VIL
V
Voltage Input Low (1.8 V mode)
0.3*VIOIN
Voltage Input Low (3.3 V mode)
0.62
VOH
High-level output threshold (IOH = 6 mA)
VOL
Low-level output threshold (IOL = 6 mA)
450
VIL (1.8V Mode)
0.2
NRESET
SOP[2:0]
VIOIN – 450
VIH (1.8V Mode)
0.3
VIH (3.3V Mode)
5.5
mV
0.96
VIL (3.3V Mode)
V
mV
V
1.57
Power Supply Specifications
Table 5-1 describes the four rails from an external power supply block of the AWR1642 device.
Table 5-1. Power Supply Rails Characteristics
SUPPLY
DEVICE BLOCKS POWERED FROM THE SUPPLY
RELEVANT IOS IN THE DEVICE
1.8 V
Synthesizer and APLL VCOs, crystal oscillator, IF
Amplifier stages, ADC, LVDS
Input: VIN_18VCO, VIN18CLK, VIN_18BB,
VIOIN_18DIFF, VIOIN_18IO
LDO Output: VOUT_14SYNTH, VOUT_14APLL
1.3 V (or 1 V in internal
LDO bypass mode)
Power Amplifier, Low Noise Amplifier, Mixers and LO
Distribution
Input: VIN_13RF2, VIN_13RF1
LDO Output: VOUT_PA
3.3 V (or 1.8 V for 1.8 V
I/O mode)
Digital I/Os
Input VIOIN
1.2 V
Core Digital and SRAMs
Input: VDDIN, VIN_SRAM
30
Specifications
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lists tolerable ripple specifications for 1.3-V (1.0-V) and 1.8-V supply rails.
Table 5-2. Ripple Specifications
RF RAIL
5.6
VCO/IF RAIL
FREQUENCY (kHz)
1.0 V (INTERNAL LDO BYPASS)
(µVRMS)
1.3 V (µVRMS)
1.8 V (µVRMS)
137.5
7
648
83
275
5
76
21
550
3
22
11
1100
2
4
6
2200
11
82
13
4400
13
93
19
6600
22
117
29
Power Consumption Summary
Table 5-3 and summarize the power consumption at the power terminals.
Table 5-3. Maximum Current Ratings at Power Terminals
PARAMETER
Current consumption
SUPPLY NAME
DESCRIPTION
MIN
TYP
MAX
VDDIN, VIN_SRAM, VNWA
Total current drawn by
all nodes driven by
1.2V rail
1000
VIN_13RF1, VIN_13RF2
Total current drawn by
all nodes driven by
1.3V or 1.0V rail
2000
VIOIN_18, VIN_18CLK,
VIOIN_18DIFF, VIN_18BB,
VIN_18VCO
Total current drawn by
all nodes driven by
1.8V rail
850
VIOIN
Total current drawn by
all nodes driven by
3.3V rail
50
UNIT
mA
Table 5-4. Average Power Consumption at Power Terminals
PARAMETER
CONDITION
DESCRIPTION
1TX, 4RX
25% Duty
Cycle
1.0-V internal
LDO bypass
mode
2TX, 4RX
1TX, 4RX
50% Duty
Cycle
Average power
consumption
2TX, 4RX
1TX, 4RX
25% Duty
Cycle
1.3-V internal
LDO enabled
mode
2TX, 4RX
1TX, 4RX
50% Duty
Cycle
2TX, 4RX
Use Case: Low power mode,
3.2 MSps complex transceiver,
25-ms frame time, 128 chirps,
128 samples/chirp, 8-µs
interchirp time (25% duty
cycle), DSP active
MIN
TYP
1.38
1.77
Use Case: Low power mode,
3.2 MSps complex transceiver,
25-ms frame time, 128 chirps,
128 samples/chirp, 8-µs
interchirp time (25% duty
cycle), DSP active
1.4
1.92
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W
1.48
1.94
2.14
Specifications
Copyright © 2017–2018, Texas Instruments Incorporated
UNIT
1.3
Use Case: Low power mode,
3.2 MSps complex transceiver,
25-ms frame time, 256 chirps,
128 samples/chirp, 8-µs
interchirp time (50% duty
cycle), DSP active
Use Case: Low power mode,
3.2 MSps complex transceiver,
25-ms frame time, 256 chirps,
128 samples/chirp, 8-µs
interchirp time (50% duty
cycle), DSP active
MAX
31
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RF Specification
over recommended operating conditions (unless otherwise noted)
PARAMETER
MIN
Noise figure (1)
76 to 77 GHz
14
77 to 81 GHz
15
dBm
48
dB
Gain range
24
dB
2
dB
21
dB
(2)
5
MHz
A2D sampling rate (real)
12.5
Msps
A2D sampling rate (complex 1x)
6.25
Msps
A2D resolution
Return loss (S11)
Gain mismatch variation (over temperature)
Phase mismatch variation (over temperature)
12
Bits
<–10
dB
±0.5
dB
±3
°
In-band IIP2
RX gain = 30dB
IF = 1.5, 2 MHz at
–12 dBFS
20
dBm
Out-of-band IIP2
RX gain = 24dB
IF = 10 kHz at -10dBm,
1.9 MHz at -30 dBm
35
dBm
–90
dBFS
Idle Channel Spurs
Output power
12.5
dBm
Amplitude noise
–145
dBc/Hz
Frequency range
76
81
Ramp rate
Phase noise at 1-MHz offset
(1)
(2)
dB
–8
IF bandwidth
Clock
subsystem
UNIT
Maximum gain
Image Rejection Ratio (IMRR)
Transmitter
MAX
1-dB compression Point (Out Of Band / Specified at 10 kHz)
Gain step size
Receiver
TYP
GHz
100 MHz/µs
76 to 77 GHz
–95
77 to 81 GHz
–93
dBc/Hz
Specification is quoted for complex 1x mode.
The analog IF stages include high-pass filtering, with two independently configurable first-order high-pass corner frequencies. The set of
available HPF corners is summarized as follows:
Available HPF Corner Frequencies (kHz)
HPF1
175, 235, 350, 700
HPF2
350, 700, 1400, 2800
The filtering performed by the baseband chain is targeted to provide:
• Less than ±0.5 dB pass-band ripple/droop, and
• Better than 60 dB anti-aliasing attenuation for any frequency that can alias back into the pass-band.
32
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NF (dB)
15.6
15.3
-20
NF (db)
IB P1db (dBm) -24
15
-28
14.7
-32
14.4
-36
14.1
-40
13.8
-44
13.5
24
26
28
30
32
34 36 38
RX Gain (dB)
40
42
44
46
IB P1dB (dBm)
Figure 5-1 shows variations of noise figure and in-band P1dB parameters with respect to receiver gain
programmed.
-48
48
Figure 5-1. Noise Figure, In-band P1dB vs Receiver Gain
5.8
CPU Specifications
over recommended operating conditions (unless otherwise noted)
PARAMETER
DSP
Subsystem
(C674
Family)
Master
Controller
Subsystem
(R4F Family)
Shared
Memory
MIN
Clock Speed
TYP
MAX
MHz
L1 Code Memory
32
KB
L1 Data Memory
32
KB
L2 Memory
256
KB
Clock Speed
200
MHz
Tightly Coupled Memory - A (Program)
256
KB
Tightly Coupled Memory - B (Data)
192
KB
Shared L3 Memory
768
KB
Thermal Resistance Characteristics for FCBGA Package [ABL0161] (1)
5.9
THERMAL METRICS (2)
°C/W (3)
RΘJC
Junction-to-case
4.92
RΘJB
Junction-to-board
6.57
RΘJA
Junction-to-free air
22.3
RΘJMA
Junction-to-moving air
PsiJT
Junction-to-package top
4.92
PsiJB
Junction-to-board
6.4
(1)
(2)
(3)
(4)
UNIT
600
(4)
N/A (1)
N/A = not applicable
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
°C/W = degrees Celsius per watt.
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
A junction temperature of 125ºC is assumed.
Specifications
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5.10 Timing and Switching Characteristics
5.10.1 Power Supply Sequencing and Reset Timing
The AWR1642 device expects all external voltage rails to be stable before reset is deasserted. Figure 5-2
describes the device wake-up sequence.
PMIC_CLKOUT
(SOP[2]),
SYNC_OUT(SOP
[1]), TDO
(SOP[0])
Power down
sequence
001 (Functional)
CAN BE CHANGED
(VIOIN)
Includes ramping of VIOIN_18
(VIOIN_18DIFF)
(VDDIN)
Includes ramping of all other supplies VIN_18BB, VIN_18CLK, VIN_13RF*, VION_18DIFF
(VIN_*)
3mS
3mS
(NRESET)
MCU_CLK_OUT(1)
External
Signals
(1)
MCU_CLK_OUT in autonomous mode, where AWR1642 application is booted from the serial flash, MCU_CLK_OUT is not enabled
by default by the device bootloader.
PORZ_1P8V
PORZ_TOP/ GEN_TOP
FUSE_SHIFT_EN
Controls HHV of IO
Reset Control to Top Digital and Analog
~400 cycles
EFC_READY
XTAL_DET_STAT
XTAL_EN/ SLICER_EN
XTAL STATUS 1 if XTAL FOUND/ ‘0’ if EXTERNAL CLK is FORCED
Reference Clock Stabilization time
~5mS
SLICER_REF_CLK
(CLKP+CLKM thru’ SLICER)
CPU_CLK
CPU CLK is REF CLK if STATUS is 1
ELSE INT_RCOSC_CLK if STATUS is 0
1 IF REF CLK is NOT PRESENT
LIMP_MODE_STATUS
PORZ_CPU/
PORZ_DIG/
GEN_ANA
Reset Control to Digital Processor and Analog/RF
Internal Signals
Mentioned for reference only
*Names are representative
Wake Up Done
Figure 5-2. Device Wake-up Sequence
34
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5.10.2 Input Clocks and Oscillators
5.10.2.1 Clock Specifications
The AWR1642 requires external clock source (that is, a 40-MHz crystal) for initial boot and as a reference
for an internal APLL hosted in the device. An external crystal is connected to the device pins. Figure 5-3
shows the crystal implementation.
Cf1
CLKP
Cp
40 MHz
CLKM
Cf2
Figure 5-3. Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 5-3, should be chosen such that Equation 1 is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to
the associated oscillator CLKP and CLKM pins.
C L = C f1 ´
C f2
C f1 + C f 2
+CP
(1)
Table 5-5 lists the electrical characteristics of the clock crystal.
Table 5-5. Crystal Electrical Characteristics (Oscillator Mode)
NAME
DESCRIPTION
fP
Parallel resonance crystal frequency
CL
Crystal load capacitance
ESR
Crystal ESR
Crystal frequency tolerance
(1) (2)
Drive level
(1)
(2)
TYP
MAX
40
5
Temperature range Expected temperature range of operation
Frequency
tolerance
MIN
8
UNIT
MHz
12
pF
50
Ω
–40
150
ºC
–200
200
ppm
200
µW
50
The crystal manufacturer's specification must satisfy this requirement.
Includes initial tolerance of the crystal, drift over temperature, aging and frequency pulling due to incorrect load capacitance.
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In the case where an external clock is used as the clock resource, the signal is fed to the CLKP pin only;
CLKM is grounded. The phase noise requirement is very important when a 40-MHz clock is fed externally.
Table 5-6 lists the electrical characteristics of the external clock signal.
Table 5-6. External Clock Mode Specifications
SPECIFICATION
PARAMETER
MIN
Frequency
MAX
40
UNIT
MHz
AC-Amplitude
700
1200
mV (pp)
DC-Vil
0.00
0.20
V
DC-Vih
1.6
1.95
V
–132
dBc/Hz
–143
dBc/Hz
–152
dBc/Hz
–153
dBc/Hz
Input Clock:
External AC-coupled sine wave or DC- Phase Noise at 1 kHz
coupled square wave
Phase Noise at 10 kHz
Phase Noise referred to 40MHz
Phase Noise at 100 kHz
Phase Noise at 1 MHz
36
TYP
Duty Cycle
35
65
%
Freq Tolerance
–50
50
ppm
Specifications
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5.10.3 Multibuffered / Standard Serial Peripheral Interface (MibSPI)
5.10.3.1 Peripheral Description
The MibSPI/SPI is a high-speed synchronous serial input/output port that allows a serial bit stream of
programmed length (2 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate.
The MibSPI/SPI is normally used for communication between the microcontroller and external peripherals
or another microcontroller.
Standard and MibSPI modules have the following features:
• 16-bit shift register
• Receive buffer register
• 8-bit baud clock generator
• SPICLK can be internally-generated (master mode) or received from an external clock source
(slave mode)
• Each word transferred can have a unique format.
• SPI I/Os not used in the communication can be used as digital input/output signals
5.10.3.2 MibSPI Transmit and Receive RAM Organization
The Multibuffer RAM is comprised of 256 buffers. Each entry in the Multibuffer RAM consists of 4 parts: a
16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. The Multibuffer
RAM can be partitioned into multiple transfer group with variable number of buffers each.
Table 5-8 to Table 5-11 assume the operating conditions stated in Table 5-7.
Table 5-7. SPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
Input rise time
1
3
ns
tF
Input fall time
1
3
ns
2
15
pF
Output Conditions
CLOAD
Output load capacitance
Specifications
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Table 5-8. SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input) (1) (2) (3)
NO.
1
2 (4)
3 (4)
4 (4)
5 (4)
PARAMETER
tc(SPC)M
Cycle time, SPICLK (4)
tw(SPCH)M
6
(1)
(2)
(3)
(4)
(5)
38
MAX
256tc(VCLK)
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
td(SPCH-SIMO)M
Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)
0.5tc(SPC)M – 3
td(SPCL-SIMO)M
Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)
0.5tc(SPC)M – 3
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)
0.5tc(SPC)M – 10.5
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)
0.5tc(SPC)M – 10.5
(C2TDELAY+2) *
tc(VCLK) + 7
CSHOLD = 1
(C2TDELAY +3) *
tc(VCLK) – 7.5
(C2TDELAY+3) *
tc(VCLK) + 7
CSHOLD = 0
(C2TDELAY+2)*tc(VCLK
) – 7.5
(C2TDELAY+2) *
tc(VCLK) + 7
CSHOLD = 1
(C2TDELAY +3) *
tc(VCLK) – 7.5
(C2TDELAY+3) *
tc(VCLK) + 7
Hold time, SPICLK low until CS inactive (clock polarity = 0)
0.5*tc(SPC)M +
(T2CDELAY + 1)
*tc(VCLK) – 7
0.5*tc(SPC)M +
(T2CDELAY + 1) *
tc(VCLK) + 7.5
Hold time, SPICLK high until CS inactive (clock polarity = 1)
0.5*tc(SPC)M +
(T2CDELAY + 1)
*tc(VCLK) – 7
0.5*tc(SPC)M +
(T2CDELAY + 1) *
tc(VCLK) + 7.5
tT2CDELAY
ns
ns
ns
ns
(C2TDELAY+2)*tc(VCLK
) – 7.5
tC2TDELAY
UNIT
ns
CSHOLD = 0
Setup time CS active until SPICLK low
(clock polarity = 1)
7 (5)
TYP
25
Setup time CS active until SPICLK high
(clock polarity = 0)
(5)
MIN
ns
ns
The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared (where x= 0 or 1).
tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25ns, where PS is the prescale value set in the SPIFMTx.[15:8]
register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25ns.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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Table 5-9. SPI Master Mode Input Timing Requirements (CLOCK PHASE = 0, SPICLK = output,
SPISIMO = output, and SPISOMI = input) (1)
NO.
8
9
(1)
(2)
MIN
tsu(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
5
tsu(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
5
th(SPCL-SOMI)M
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
3
th(SPCH-SOMI)M
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
3
(2)
(2)
TYP
MAX
UNIT
ns
ns
The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
1
SPICLK
(clock polarity = 0)
2
1
3
SPICLK
(clock polarity = 1
5
4
Master Out Data Is Valid
SPISIMO
1
8
9
Master In Data
Must Be Valid
SPISOMI
Figure 5-4. SPI Master Mode External Timing (CLOCK PHASE = 0)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
Master Out Data Is Valid
6
7
SPICSn
Figure 5-5. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0)
Specifications
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Table 5-10. SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input) (1) (2) (3)
NO.
1
2 (4)
3 (4)
4 (4)
5 (4)
PARAMETER
tc(SPC)M
Cycle time, SPICLK (4)
tw(SPCH)M
MIN
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)M – 4
0.5tc(SPC)M + 4
td(SPCH-SIMO)M
Delay time, SPISIMO valid before SPICLK low, (clock polarity = 0)
0.5tc(SPC)M – 3
td(SPCL-SIMO)M
Delay time, SPISIMO valid before SPICLK high, (clock polarity = 1)
0.5tc(SPC)M – 3
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after SPICLK low, (clock polarity = 0)
0.5tc(SPC)M – 10.5
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after SPICLK high, (clock polarity = 1)
0.5tc(SPC)M – 10.5
7
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
CSHOLD = 1
0.5*tc(SPC)M +
(C2TDELAY +
2)*tc(VCLK) – 7
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
CSHOLD = 0
0.5*tc(SPC)M +
(C2TDELAY+2)*tc(
VCLK) – 7
0.5*tc(SPC)M +
(C2TDELAY+2) *
tc(VCLK) + 7.5
CSHOLD = 1
0.5*tc(SPC)M +
(C2TDELAY+3)*tc(
VCLK) – 7
0.5*tc(SPC)M +
(C2TDELAY+3) *
tc(VCLK) + 7.5
Hold time, SPICLK low until CS inactive (clock polarity = 0)
(T2CDELAY + 1)
*tc(VCLK) – 7.5
(T2CDELAY + 1)
*tc(VCLK) + 7
Hold time, SPICLK high until CS inactive (clock polarity = 1)
(T2CDELAY + 1)
*tc(VCLK) – 7.5
(T2CDELAY + 1)
*tc(VCLK) + 7
(1)
(2)
(3)
(4)
(5)
40
tT2CDELAY
ns
ns
ns
ns
0.5*tc(SPC)M +
(C2TDELAY +
2)*tc(VCLK) – 7
tC2TDELAY
UNIT
ns
CSHOLD = 0
Setup time CS active until SPICLK low
(clock polarity = 1)
(5)
MAX
256tc(VCLK)
Setup time CS active until SPICLK high
(clock polarity = 0)
6 (5)
TYP
25
ns
ns
The MASTER bit (SPIGCRx.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set ( where x = 0 or 1 ).
tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
When the SPI is in Master mode, the following must be true: For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where PS is the prescale value set in the SPIFMTx.[15:8]
register bits. For PS values of 0: tc(SPC)M = 2tc(MSS_VCLK) ≥ 25 ns.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
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Table 5-11. SPI Master Mode Input Requirements (CLOCK PHASE = 1, SPICLK = output,
SPISIMO = output, and SPISOMI = input) (1)
NO.
8
9
(1)
(2)
MIN
tsu(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
5
tsu(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
5
th(SPCL-SOMI)M
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
3
th(SPCH-SOMI)M
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
3
(2)
(2)
TYP
MAX
UNIT
ns
ns
The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
Master Out Data Is Valid
SPISIMO
8
Data Valid
9
Master In Data
Must Be Valid
SPISOMI
Figure 5-6. SPI Master Mode External Timing (CLOCK PHASE = 1)
Write to buffer
SPICLK
(clock polarity=0)
SPICLK
(clock polarity=1)
SPISIMO
Master Out Data Is Valid
6
7
SPICSn
Figure 5-7. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1)
Specifications
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5.10.3.3 SPI Slave Mode I/O Timings
Table 5-12. SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input,
and SPISOMI = output) (1) (2) (3)
NO.
1
2 (5)
3 (5)
4
5
4
5
(1)
(2)
(3)
(4)
(5)
PARAMETER
MIN
TYP
MAX
tc(SPC)S
Cycle time, SPICLK (4)
25
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
10
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
10
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
10
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
10
td(SPCH-SOMI)S
Delay time, SPISOMI valid after SPICLK high (clock
polarity = 0)
10
td(SPCL-SOMI)S
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1)
10
th(SPCH-SOMI)S
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
2
th(SPCL-SOMI)S
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
2
td(SPCH-SOMI)S
Delay time, SPISOMI valid after SPICLK high (clock
polarity = 0; clock phase = 0) OR (clock polarity = 1;
clock phase = 1)
10
td(SPCL-SOMI)S
Delay time, SPISOMI valid after SPICLK low (clock
polarity = 1; clock phase = 0) OR (clock polarity = 0;
clock phase = 1)
10
th(SPCH-SOMI)S
Hold time, SPISOMI data valid after SPICLK high
(clock polarity = 0; clock phase = 0) OR (clock
polarity = 1; clock phase = 1)
2
th(SPCL-SOMI)S
Hold time, SPISOMI data valid after SPICLK low
(clock polarity = 1; clock phase = 0) OR (clock
polarity = 0; clock phase = 1)
2
(5)
(5)
(5)
(5)
UNIT
ns
ns
ns
ns
ns
ns
ns
The MASTER bit (SPIGCRx.0) is cleared ( where x = 0 or 1 ).
The CLOCK PHASE bit (SPIFMTx.16) is either cleared or set for CLOCK PHASE = 0 or CLOCK PHASE = 1 respectively.
tc(MSS_VCLK) = master subsystem clock time = 1 / f(MSS_VCLK). For more details, see the Technical Reference Manual.
When the SPI is in Slave mode, the following must be true: For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(MSS_VCLK) ≥ 25 ns, where
PS is the prescale value set in the SPIFMTx.[15:8] register bits.For PS values of 0: tc(SPC)S = 2tc(MSS_VCLK) ≥ 25 ns.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
Table 5-13. SPI Slave Mode Timing Requirements (SPICLK = input, SPISIMO = input,
and SPISOMI = output)
NO.
6 (1)
7 (1)
6
7
(1)
42
MIN
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0)
3
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 1)
3
th(SPCL-SIMO)S
Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0)
0
th(SPCL-SIMO)S
Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0)
0
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 0; clock phase = 0)
OR (clock polarity = 1; clock phase = 1)
3
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 1; clock phase =
0) OR (clock polarity = 0; clock phase = 1)
3
th(SPCL-SIMO)S
Hold time, SPISIMO data valid after SPICLK low (clock polarity = 0; clock
phase = 0) OR (clock polarity = 1; clock phase = 1)
1
th(SPCL-SIMO)S
Hold time, SPISIMO data valid after SPICLK high (clock polarity = 1; clock
phase = 0) OR (clock polarity = 0; clock phase = 1)
1
(1)
(1)
TYP
MAX
UNIT
ns
ns
ns
ns
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
Specifications
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1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO Data
Must Be Valid
SPISIMO
Figure 5-8. SPI Slave Mode External Timing (CLOCK PHASE = 0)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISOMI
SPISOMI Data Is Valid
6
7
SPISIMO
SPISIMO Data
Must Be Valid
Figure 5-9. SPI Slave Mode External Timing (CLOCK PHASE = 1)
Specifications
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5.10.3.4 Typical Interface Protocol Diagram (Slave Mode)
1. Host should ensure that there is a delay of two SPI clocks between CS going low and start of SPI
clock.
2. Host should ensure that CS is toggled for every 16 bits of transfer through SPI.
Figure 5-10 shows the SPI communication timing of the typical interface protocol.
2 SPI clocks
CS
CLK
0x1234
0x4321
CRC
0x5678
0x8765
MOSI
0xDCBA
16 bytes
0xABCD
CRC
MISO
IRQ
Figure 5-10. SPI Communication
44
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5.10.4 LVDS Interface Configuration
The AWR1642 supports four differential LVDS IOs/Lanes. The lane configuration supported is two Data
lanes (LVDS_TXP/M), one Bit Clock lane (LVDS_CLKP/M) and one Frame clock lane
(LVDS_FRCLKP/M). The LVDS interface supports the following data rates:
• 900 Mbps (450 MHz DDR Clock)
• 600 Mbps (300 MHz DDR Clock)
• 450 Mbps (225 MHz DDR Clock)
• 400 Mbps (200 MHz DDR Clock)
• 300 Mbps (150 MHz DDR Clock)
• 225 Mbps (112.5 MHz DDR Clock)
• 150 Mbps (75 MHz DDR Clock)
Note that the bit clock is in DDR format and hence the numbers of toggles in the clock is equivalent to
data.
LVDS_TXP/M
LVDS_FRCLKP/M
Data bitwidth
LVDS_CLKP/M
Figure 5-11. LVDS Interface Lane Configuration And Relative Timings
5.10.4.1 LVDS Interface Timings
LVDS_CLK
twH1
twL1
twH2
twL2
Calculation showing tw parameters:
Freq = 900MHz, Period = 1.11ns
At 50% twH1/twL1 = 1.11ns/2 = 0.55ns
Rise time = Fall time = 200ps (as per LVDS IO spec @1pF load)
twH2/twL2 = (1.11ns-2*200ps)/2 = 0.35ns
200ps
LVDS_CLK
LVDS_TXP/M
LVDS_FRCLKP/M
Clock Jitter = 6sigma = 60ps
200ps
200ps
1100ps
Figure 5-12. Timing Parameters
Specifications
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Table 5-14. LVDS Electrical Characteristics
PARAMETER
TEST CONDITIONS
MIN
0.55
twH2 / twL2
0.35
Duty Cycle Requirements
max 1 pF lumped capacitive load on
LVDS lanes
48%
VOH
Output Differential Voltage
MAX
ns
52%
925
peak-to-peak single-ended with 100
Ω resistive load between differential
pairs
Output Offset Voltage
Specifications
UNIT
ns
1475
VOL
46
TYP
twH1 / twL1
mV
mV
250
450
mV
1125
1275
mV
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5.10.5 General-Purpose Input/Output
Table 5-15 lists the switching characteristics of output timing relative to load capacitance.
Table 5-15. Switching Characteristics for Output Timing versus Load Capacitance (CL) (1) (2)
PARAMETER
tr
TEST CONDITIONS
Max rise time
Slew control = 0
tf
tr
Max fall time
Max rise time
Slew control = 1
tf
(1)
(2)
Max fall time
VIOIN = 1.8V
VIOIN = 3.3V
CL = 20 pF
2.878
3.013
CL = 50 pF
6.446
6.947
CL = 75 pF
9.43
10.249
CL = 20 pF
2.827
2.883
CL = 50 pF
6.442
6.687
CL = 75 pF
9.439
9.873
CL = 20 pF
3.307
3.389
CL = 50 pF
6.77
7.277
CL = 75 pF
9.695
10.57
CL = 20 pF
3.128
3.128
CL = 50 pF
6.656
6.656
CL = 75 pF
9.605
9.605
UNIT
ns
ns
ns
ns
Slew control, which is configured by PADxx_CFG_REG, changes behavior of the output driver (faster or slower output slew rate).
The rise/fall time is measured as the time taken by the signal to transition from 10% and 90% of VIOIN voltage.
Specifications
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5.10.6 Controller Area Network Interface (DCAN)
The DCAN supports the CAN 2.0B protocol standard and uses a serial, multimaster communication
protocol that efficiently supports distributed real-time control with robust communication rates of up to 1
Mbps. The DCAN is ideal for applications operating in noisy and harsh environments that require reliable
serial communication or multiplexed wiring.
The DCAN has the following features:
• Supports CAN protocol version 2.0 part A, B
• Bit rates up to 1 Mbps
• Configurable Message objects
• Individual identifier masks for each message object
• Programmable FIFO mode for message objects
• Suspend mode for debug support
• Programmable loop-back modes for self-test operation
• Direct access to Message RAM in test mode
• Supports two interrupt lines - Level 0 and Level 1
• Automatic Message RAM initialization
Table 5-16. Dynamic Characteristics for the DCANx TX and RX Pins
PARAMETER
MIN
TYP
MAX
UNIT
td(CAN_tx)
Delay time, transmit shift register to CAN_tx pin (1)
15
ns
td(CAN_rx)
Delay time, CAN_rx pin to receive shift register (1)
10
ns
(1)
48
These values do not include rise/fall times of the output buffer.
Specifications
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5.10.7 Controller Area Network - Flexible Data-rate (CAN-FD)
The CAN-FD module supports both classic CAN and CAN FD (CAN with Flexible Data-Rate)
specifications. CAN FD feature allows high throughput and increased payload per data frame. The classic
CAN and CAN FD devices can coexist on the same network without any conflict.
The CAN-FD has the following features:
• Conforms with CAN Protocol 2.0 A, B and ISO 11898-1
• Full CAN FD support (up to 64 data bytes per frame)
• AUTOSAR and SAE J1939 support
• Up to 32 dedicated Transmit Buffers
• Configurable Transmit FIFO, up to 32 elements
• Configurable Transmit Queue, up to 32 elements
• Configurable Transmit Event FIFO, up to 32 elements
• Up to 64 dedicated Receive Buffers
• Two configurable Receive FIFOs, up to 64 elements each
• Up to 128 11-bit filter elements
• Internal Loopback mode for self-test
• Mask-able interrupts, two interrupt lines
• Two clock domains (CAN clock / Host clock)
• Parity / ECC support - Message RAM single error correction and double error detection (SECDED)
mechanism
• Full Message Memory capacity (4352 words).
Table 5-17. Dynamic Characteristics for the DCANx TX and RX Pins
PARAMETER
MIN
TYP
MAX
UNIT
td(CAN_FD_tx)
Delay time, transmit shift register to
CAN_FD_tx pin (1)
15
ns
td(CAN_FD_rx)
Delay time, CAN_FD_rx pin to receive shift
register (1)
10
ns
MAX
UNIT
(1)
These values do not include rise/fall times of the output buffer.
5.10.8 Serial Communication Interface (SCI)
The SCI has the following features:
• Standard universal asynchronous receiver-transmitter (UART) communication
• Standard non-return to zero (NRZ) format
• Double-buffered receive and transmit functions
• Asynchronous or iso-synchronous communication modes with no CLK pin
• Capability to use Direct Memory Access (DMA) for transmit and receive data
• Two external pins: RS232_RX and RS232_TX
Table 5-18. SCI Timing Requirements
MIN
f(baud)
Supported baud rate at 20 pF
TYP
921.6
kHz
Specifications
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5.10.9 Inter-Integrated Circuit Interface (I2C)
The inter-integrated circuit (I2C) module is a multimaster communication module providing an interface
between devices compliant with Philips Semiconductor I2C-bus specification version 2.1 and connected by
an I2C-bus™. This module will support any slave or master I2C compatible device.
The I2C has the following features:
• Compliance to the Philips I2C bus specification, v2.1 (The I2C Specification, Philips document number
9398 393 40011)
– Bit/Byte format transfer
– 7-bit and 10-bit device addressing modes
– General call
– START byte
– Multi-master transmitter/ slave receiver mode
– Multi-master receiver/ slave transmitter mode
– Combined master transmit/receive and receive/transmit mode
– Transfer rates of 100 kbps up to 400 kbps (Phillips fast-mode rate)
• Free data format
• Two DMA events (transmit and receive)
• DMA event enable/disable capability
• Module enable/disable capability
• The SDA and SCL are optionally configurable as general purpose I/O
• Slew rate control of the outputs
• Open drain control of the outputs
• Programmable pullup/pulldown capability on the inputs
• Supports Ignore NACK mode
NOTE
This I2C module does not support:
• High-speed (HS) mode
• C-bus compatibility mode
• The combined format in 10-bit address mode (the I2C sends the slave address second
byte every time it sends the slave address first byte)
50
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Table 5-19. I2C Timing Requirements (1)
STANDARD MODE
MIN
FAST MODE
MAX
MIN
MAX
UNIT
tc(SCL)
Cycle time, SCL
10
2.5
μs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low
(for a repeated START condition)
4.7
0.6
μs
th(SCLL-SDAL)
Hold time, SCL low after SDA low
(for a START and a repeated START condition)
4
0.6
μs
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
μs
tw(SCLH)
Pulse duration, SCL high
4
0.6
μs
tsu(SDA-SCLH)
Setup time, SDA valid before SCL high
th(SCLL-SDA)
Hold time, SDA valid after SCL low
tw(SDAH)
Pulse duration, SDA high between STOP and START
conditions
tsu(SCLH-SDAH)
Setup time, SCL high before SDA high
(for STOP condition)
tw(SP)
Pulse duration, spike (must be suppressed)
Cb
(1)
(2)
(3)
(2) (3)
250
0
100
3.45 (1)
μs
0
0.9
μs
4.7
1.3
μs
4
0.6
μs
0
Capacitive load for each bus line
400
50
ns
400
pF
The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
The maximum th(SDA-SCLL) for I2C bus devices has only to be met if the device does not stretch the low period (tw(SCLL)) of the SCL
signal.
Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.
SDA
tw(SDAH)
tsu(SDA-SCLH)
tw(SCLL)
tw(SP)
tsu(SCLH-SDAH)
tw(SCLH)
tr(SCL)
SCL
tc(SCL)
tf(SCL)
th(SCLL-SDAL)
th(SDA-SCLL)
tsu(SCLH-SDAL)
th(SCLL-SDAL)
Stop
Start
Repeated Start
Stop
Figure 5-13. I2C Timing Diagram
NOTE
•
•
A device must internally provide a hold time of at least 300 ns for the SDA signal
(referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling
edge of SCL.
The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW
period (tw(SCLL)) of the SCL signal. E.A Fast-mode I2C-bus device can be used in a
Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of
the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + tsu(SDA-SCLH).
Specifications
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5.10.10 Quad Serial Peripheral Interface (QSPI)
The quad serial peripheral interface (QSPI™) module is a kind of SPI module that allows single, dual, or
quad read access to external SPI devices. This module has a memory mapped register interface, which
provides a direct interface for accessing data from external SPI devices and thus simplifying software
requirements. The QSPI works as a master only. The QSPI in the device is primarily intended for fast
booting from quad-SPI flash memories.
The QSPI supports the following features:
• Programmable clock divider
• Six-pin interface
• Programmable length (from 1 to 128 bits) of the words transferred
• Programmable number (from 1 to 4096) of the words transferred
• Support for 3-, 4-, or 6-pin SPI interface
• Optional interrupt generation on word or frame (number of words) completion
• Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles
Table 5-21 and Table 5-22 assume the operating conditions stated in Table 5-20.
Table 5-20. QSPI Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
Input rise time
1
3
ns
tF
Input fall time
1
3
ns
2
15
pF
Output Conditions
CLOAD
Output load capacitance
Table 5-21. Timing Requirements for QSPI Input (Read) Timings (1) (2)
MIN
TYP
MAX
UNIT
tsu(D-SCLK)
Setup time, d[3:0] valid before falling sclk edge
th(SCLK-D)
Hold time, d[3:0] valid after falling sclk edge
tsu(D-SCLK)
Setup time, final d[3:0] bit valid before final falling sclk edge
th(SCLK-D)
Hold time, final d[3:0] bit valid after final falling sclk edge
1.5 + P (3)
ns
(1)
(2)
(3)
52
7.3
ns
1.5
ns
7.3 – P (3)
ns
Clock Mode 0 (clk polarity = 0 ; clk phase = 0 ) is the mode of operation.
The Device captures data on the falling clock edge in Clock Mode 0, as opposed to the traditional rising clock edge. Although nonstandard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI sevices that
launch data on the falling edge in Clock Mode 0.
P = SCLK period in ns.
Specifications
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Table 5-22. QSPI Switching Characteristics
NO.
Q1
(1)
(2)
(3)
PARAMETER
tc(SCLK)
MIN
Cycle time, sclk
ns
tw(SCLKL)
Pulse duration, sclk low
Y*P – 3
tw(SCLKH)
Pulse duration, sclk high
Y*P – 3 (1) (1)
Delay time, sclk falling edge to cs active edge
Q5
td(SCLK-CS)
Delay time, sclk falling edge to cs inactive edge
Q6
td(SCLK-D1)
Delay time, sclk falling edge to d[1] transition
UNIT
ns
Q3
td(CS-SCLK)
MAX
(1) (2)
Q2
Q4
TYP
25
ns
(1) (3)
–M*P +
2.5 (1) (3)
ns
N*P – 1 (1) (3)
N*P +
2.5 (1) (3)
ns
–3.5
7
ns
(3)
(3)
ns
–M*P – 1
Q7
tena(CS-D1LZ)
Enable time, cs active edge to d[1] driven (lo-z)
–P – 4
Q8
tdis(CS-D1Z)
Disable time, cs active edge to d[1] tri-stated (hi-z)
–P – 4 (3)
–P +1 (3)
ns
Q9
td(SCLK-D1)
Delay time, sclk first falling edge to first d[1] transition
(for PHA = 0 only)
(3)
(3)
ns
Q12
tsu(D-SCLK)
Setup time, d[3:0] valid before falling sclk edge
7.3
ns
Q13
th(SCLK-D)
Hold time, d[3:0] valid after falling sclk edge
1.5
ns
Q14
tsu(D-SCLK)
Setup time, final d[3:0] bit valid before final falling sclk
edge
7.3 — P (3)
ns
Q15
th(SCLK-D)
Hold time, final d[3:0] bit valid after final falling sclk
edge
1.5 + P (3)
ns
–3.5 – P
–P +1
7–P
The Y parameter is defined as follows: If DCLK_DIV is 0 or ODD then, Y equals 0.5. If DCLK_DIV is EVEN then, Y equals
(DCLK_DIV/2) / (DCLK_DIV+1). For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle
distortion. The HSDIVIDER on CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All
required details about clock division factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
P = SCLK period in ns.
M = QSPI_SPI_DC_REG.DDx + 1, N = 2
PHA=0
cs
Q5
Q4
Q1
Q2
POL=0
Q3
sclk
Q7
d[0]
Q6
Q9
Command Command
Bit n-1
Bit n-2
Q12 Q13
Read Data
Bit 1
Q12 Q13
Read Data
Bit 1
d[3:1]
Q12 Q13
Read Data
Bit 0
Q12 Q13
Read Data
Bit 0
SPRS85v_TIMING_OSPI1_02
Figure 5-14. QSPI Read (Clock Mode 0)
Specifications
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PHA=0
cs
Q5
Q4
POL=0
Q1
Q2
Q3
sclk
Q7
d[0]
Q9
Q6
Command Command
Bit n-1
Bit n-2
Q6
Q8
Q6
Write Data
Bit 1
Write Data
Bit 0
d[3:1]
SPRS85v_TIMING_OSPI1_04
Figure 5-15. QSPI Write (Clock Mode 0)
54
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5.10.11 ETM Trace Interface
Table 5-24 and assume the recommended operating conditions stated in Table 5-23.
Table 5-23. ETMTRACE Timing Conditions
MIN
TYP
MAX
UNIT
Output Conditions
CLOAD
Output load capacitance
2
20
pF
MAX
UNIT
Table 5-24. ETM TRACE Switching Characteristics
NO.
PARAMETER
1
tcyc(ETM)
Cycle time, TRACECLK period
2
th(ETM)
3
tl(ETM)
4
tr(ETM)
Clock and data rise time
5
tf(ETM)
Clock and data fall time
MIN
ns
Pulse Duration, TRACECLK High
9
ns
Pulse Duration, TRACECLK Low
9
td(ETMTRAC
6
ECLKHETMDATAV)
ECLKlETMDATAV)
ns
3.3
ns
3.3
ns
1
7
ns
1
7
ns
Delay time, ETM trace clock high to ETM data valid
td(ETMTRAC
7
TYP
20
Delay time, ETM trace clock low to ETM data valid
tl(ETM)
th(ETM)
tr(ETM)
tf(ETM)
tcyc(ETM)
Figure 5-16. ETMTRACECLKOUT Timing
Figure 5-17. ETMDATA Timing
Specifications
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5.10.12 Data Modification Module (DMM)
A Data Modification Module (DMM) gives the ability to write external data into the device memory.
The DMM has the following features:
• Acts as a bus master, thus enabling direct writes to the 4GB address space without CPU intervention
• Writes to memory locations specified in the received packet (leverages packets defined by trace mode
of the RAM trace port [RTP] module)
• Writes received data to consecutive addresses, which are specified by the DMM (leverages packets
defined by direct data mode of RTP module)
• Configurable port width (1, 2, 4, 8, 16 pins)
• Up to 65 Mbit/s pin data rate
Table 5-25. DMM Timing Requirements
MIN
TYP
MAX
15.4
UNIT
tcyc(DMM)
Clock period
tR
Clock rise time
1
3
ns
ns
tF
Clock fall time
1
3
ns
th(DMM)
High pulse width
6
ns
tl(DMM)
Low pulse width
6
ns
tssu(DMM)
SYNC active to clk falling edge setup time
2
ns
tsh(DMM)
DMM clk falling edge to SYNC deactive hold time
3
ns
tdsu(DMM)
DATA to DMM clk falling edge setup time
2
ns
tdh(DMM)
DMM clk falling edge to DATA hold time
3
ns
tl(DMM)
tr
th(DMM)
tf
tcyc(DMM)
Figure 5-18. DMMCLK Timing
tssu(DMM)
tsh(DMM)
DMMSYNC
DMMCLK
DMMDATA
tdsu(DMM)
tdh(DMM)
Figure 5-19. DMMDATA Timing
56
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5.10.13 JTAG Interface
Table 5-27 and Table 5-28 assume the operating conditions stated in Table 5-26.
Table 5-26. JTAG Timing Conditions
MIN
TYP
MAX
UNIT
Input Conditions
tR
Input rise time
1
3
ns
tF
Input fall time
1
3
ns
2
15
pF
MAX
UNIT
Output Conditions
CLOAD
Output load capacitance
Table 5-27. Timing Requirements for IEEE 1149.1 JTAG
NO.
MIN
TYP
1
tc(TCK)
Cycle time TCK
66.66
ns
1a
tw(TCKH)
Pulse duration TCK high (40% of tc)
26.67
ns
1b
tw(TCKL)
Pulse duration TCK low(40% of tc)
26.67
ns
tsu(TDI-TCK)
Input setup time TDI valid to TCK high
2.5
ns
tsu(TMS-TCK)
Input setup time TMS valid to TCK high
2.5
ns
th(TCK-TDI)
Input hold time TDI valid from TCK high
18
ns
th(TCK-TMS)
Input hold time TMS valid from TCK high
18
ns
3
4
Table 5-28. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
2
PARAMETER
td(TCKL-TDOV)
MIN
Delay time, TCK low to TDO valid
0
TYP
MAX
UNIT
25
ns
1
1a
1b
TCK
2
TDO
3
4
TDI/TMS
SPRS91v_JTAG_01
Figure 5-20. JTAG Timing
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6 Detailed Description
6.1
Overview
The AWR1642 device includes the entire Millimeter Wave blocks and analog baseband signal chain for
two transmitters and four receivers, as well as a customer-programmable MCU. This device is applicable
as a radar-on-a-chip in use-cases with modest requirements for memory, processing capacity and
application code size. These could be cost-sensitive automotive applications that are evolving from 24
GHz narrowband implementation and some emerging simple ultra-short-range radar applications. Typical
application examples for this device include basic Blind Spot Detect, Parking Assist, and so forth.
In terms of scalability, the AWR1642 device could be paired with a low-end external MCU, to address
more complex applications that might require additional memory for larger application software footprint
and faster interfaces. Because the AWR1642 device also provides high speed data interfaces like SerialLVDS, it is suitable for interfacing with more capable external processing blocks. Here system designers
can choose the AWR1642 to provide raw ADC data.
6.2
Functional Block Diagram
QSPI
RX1
LNA
IF
Cortex R4F
@ 200 MHz
ADC
SPI
Optional
External MCU
interface
SPI / I2C
PMIC control
(User programmable)
RX2
LNA
IF
Serial Flash
interface
ADC
Digital Front
End
RX3
LNA
IF
ADC
RX4
LNA
IF
ADC
Prog
RAM
(256kB*)
(Decimation
filter chain)
Data
RAM
(192kB*)
Boot
ROM
DCAN
Primary
communication
interfaces (automotive)
TX1
Bus Matrix
CAN-FD
PA
DMA
Master subsystem
(Customer programmed)
Debug
UARTs
Test/
Debug
JTAG for debug/
development
Mailbox
LVDS
TX2
For debug
PA
x4
Synth
(20 GHz)
Ramp
Generator
HIL
C674x DSP
@600 MHz
High-speed ADC
output interface
(for recording)
High-speed input for
hardware-in-loop
verification
ADC
Buffer
6
GPADC
Osc.
RF Control/
BIST
VMON
Temp
L1P
(32KB)
DMA
L1D
(32KB)
CRC
DSP subsystem
(Customer programmed)
RF/Analog subsystem
L2
(256KB)
Radar Data Memory
(L3)
768 KB*
* Up to 512 KB of Data Memory can be switched to the Master R4F if required
Copyright © 2018, Texas Instruments Incorporated
6.3
6.3.1
Subsystems
RF and Analog Subsystem
The RF and analog subsystem includes the RF and analog circuitry – namely, the synthesizer, PA, LNA,
mixer, IF, and ADC. This subsystem also includes the crystal oscillator and temperature sensors. The
three transmit channels can be operated up to a maximum of two at a time (simultaneously) for transmit
beamforming purpose as required; whereas the four receive channels can all be operated simultaneously.
58
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6.3.1.1
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Clock Subsystem
The AWR1642 clock subsystem generates 76 to 81 GHz from an input reference of 40-MHz crystal. It has
a built-in oscillator circuit followed by a clean-up PLL and a RF synthesizer circuit. The output of the RF
synthesizer is then processed by an X4 multiplier to create the required frequency in the 76- to 81-GHz
spectrum. The RF synthesizer output is modulated by the timing engine block to create the required
waveforms for effective sensor operation.
The clean-up PLL also provides a reference clock for the host processor after system wakeup.
The clock subsystem also has built-in mechanisms for detecting the presence of a crystal and monitoring
the quality of the generated clock.
RF SYNTH
Self Test
ADCs
TX Phase Mod.
PA Envelope
Lock Detect
Figure 6-1 describes the clock subsystem.
Timing
Engine
CleanUp PLL
OSC_CLKOUT
XO/
Slicer
SYNCIN
TX LO
RX LO
x4
MULT
SYNC_OUT
Lock Detect
SoC Clock
CLK Detect
40 MHz
Figure 6-1. Clock Subsystem
Detailed Description
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6.3.1.2
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Transmit Subsystem
The AWR1642 transmit subsystem consists of two parallel transmit chains, each with independent binary
phase and amplitude control. The device supports binary phase modulation for MIMO radar and
interference mitigation.
Each transmit chain can deliver a maximum of 12 dBm at the antenna port on the PCB. The transmit
chains also support programmable backoff for system optimization.
Figure 6-2 describes the transmit subsystem.
Loopback
Path
Chip
PCB
Package
Self Test
12 dBm
at 50 W
DF
LO
0 or 180°
(from Timing
Engine)
Figure 6-2. Transmit Subsystem (Per Channel)
6.3.1.3
Receive Subsystem
The AWR1642 receive subsystem consists of four parallel channels. A single receive channel consists of
an LNA, mixer, IF filtering, A2D conversion, and decimation. All four receive channels can be operational
at the same time an individual power-down option is also available for system optimization.
Unlike conventional real-only receivers, the AWR1642 device supports a complex baseband architecture,
which uses quadrature mixer and dual IF and ADC chains to provide complex I and Q outputs for each
receiver channel. The AWR1642 is targeted for fast chirp systems. The band-pass IF chain has
configurable lower cutoff frequencies above 175 kHz and can support bandwidths up to 5 MHz.
Self Test
LO
Q
DSM
RSSI
ADC Buffer
I
50 W
GSG
I/Q Correction
Decimation
DSM
Image Rejection
Loopback
Path
Chip
PCB
Package
DAC
Saturation
Detect
Figure 6-3 describes the receive subsystem.
DAC
Figure 6-3. Receive Subsystem (Per Channel)
60
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Processor Subsystem
Unified
128KB x 2
L2
ROM
Cache/
RAM
L1P
32KB
L1d
32KB
EDMA
Master
R4F
DSP
HIL
JTAG
CRC
HIL
DSP Interconnect ± 128 bit @ 200 MHz
Data
Handshake
Memory
ADC Buffer
L3
TCM A
256KB
TCM B
192KB
Master Interconnect
BSS Interconnect
CRC
Mail
Box
MSS
DMA
32KB
32KB Ping-Pong
768KB
(static sharing
with R4F Space)
Interconnect
LVDS
SPI
UART
I2C
QSPI
CAN
FD
CAN
PWM,
PMIC
CLK
Figure 6-4. Processor Subsystem
Figure 6-4 shows the block diagram for customer programmable processor subsystems in the AWR1642
device. At a high level there are two customer programmable subsystems, as shown separated by a
dotted line in the diagram. Left hand side shows the DSP Subsystem which contains TI's highperformance C674x DSP, a high-bandwidth interconnect for high performance (128-bit, 200MHz) and
associated peripherals – four DMAs for data transfer, LVDS interface for Measurement data output, L3
Radar data cube memory, ADC buffers, CRC engine, and data handshake memory (additional memory
provided on interconnect).
The right side of the diagram shows the Master subsystem. Master subsystem as name suggests is the
master of the device and controls all the device peripherals and house-keeping activities of the device.
Master subsystem contains Cortex-R4F (Master R4F) processor and associated peripherals and housekeeping components such as DMAs, CRC and Peripherals (I2C, UART, SPIs, CAN, PMIC clocking
module, PWM, and others) connected to Master Interconnect through Peripheral Central Resource (PCR
interconnect).
Details of the DSP CPU core can be found at http://www.ti.com/product/TMS320C6748.
HIL module is shown in both the subsystems and can be used to perform the radar operations feeding the
captured data from outside into the device without involving the RF subsystem. HIL on master SS is for
controlling the configuration and HIL on DSPSS for high speed ADC data input to the device. Both HIL
modules uses the same IOs on the device, one additional IO (DMM_MUX_IN) allows selecting either of
the two.
6.3.3
Automotive Interface
The AWR1642 communicates with the automotive network over the following main interfaces:
• CAN (2 interfaces available, one of them being CAN-FD)
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6.3.4
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Master Subsystem Cortex-R4F Memory Map
Table 6-1 shows the master subsystem, Cortex-R4F memory map.
NOTE
There are separate Cortex-R4F addresses and DMA MSS addresses for the master
subsystem. See the Technical Reference Manual for a complete list.
Table 6-1. Master Subsystem, Cortex-R4F Memory Map
FRAME ADDRESS (HEX)
NAME
START
END
SIZE
DESCRIPTION
CPU Tightly-Coupled Memories
TCMA ROM
0x0000_0000
0x0001_FFFF
128 KiB
Program ROM
TCM RAM-A
0x0020_0000
0x0023_FFFF (or
0x0027_FFFF)
512 KiB
256/512KB based on variant
TCM RAM-B
0x0800_0000
0x0802_FFFF
192 KB
Data RAM
0x0C20_0000
0x0C20_1FFF
8 KB
S/W Scratchpad memory
0xF060_1000
0xF060_17FF
2 KB
RADARSS to MSS mailbox memory space
0xF060_2000
0xF060_27FF
0xF060_8000
0xF060_80FF
0xF060_8060
0xF060_86FF
0xF060_4000
0xF060_47FF
0xF060_5000
0xF060_57FF
0xF060_8400
0xF060_84FF
0xF060_8300
0xF060_83FF
0xF060_6000
0xF060_67FF
0xF060_7000
0xF060_7FFF
0xF060_8200
0xF060_82FF
0xF060_8100
0xF060_81FF
0xFFFF_E100
0xFFFF_E2FF
756 B
TOP Level Reset, Clock management registers
0xFFFF_FF00
0xFFFF_FFFF
256 B
MSS Reset, Clock management registers
0xFFFF_EA00
0xFFFF_EBFF
512 KB
IO Mux module registers
0xFFFF_F800
0xFFFF_FBFF
352 B
General-purpose control registers
GIO
0xFFF7_BC00
0xFFF7_BDFF
180 B
GIO module configuration registers
DMA-1
0xFFFF_F000
0xFFFF_F3FF
1 KB
DMA-1 module configuration registers
DMA-2
0xFCFF_F800
0xFCFF_FBFF
1 KB
DMA-2 module configuration registers
DMM-1
0xFCFF_F700
0xFCFF_F7FF
472 B
DMM-1 module configuration registers
DMM-2
0xFCFF_F600
0xFCFF_F6FF
472 B
DMM-2 module configuration registers
VIM
0xFFFF_FD00
0xFFFF_FEFF
512 B
VIM module configuration registers
RTI-A/WD
0xFFFF_FC00
0xFFFF_FCFF
192 B
RTI-A module configuration registers
RTI-B
0xFFFF_EE00
0xFFFF_EEFF
192 B
RTI-B module configuration registers
0xC000_0000
0xC07F_FFFF
8 MB
QSPI –flash memory space
0xC080_0000
0xC0FF_FFFF
116 B
QSPI module configuration registers
0xFFF7_F400
0xFFF7_F5FF
512 B
MIBSPI-A module configuration registers
S/W Scratch Pad Memory
SW_ Buffer
System Peripherals
Mail Box
MSS<->RADARSS
Mail Box
MSS<->DSPSS
Mail Box
RADARSS<>DSPSS
PRCM and Control
Module
MSS to RADARSS mailbox memory space
188 B
MSS to RADARSS mailbox Configuration
registers
RADARSS to MSS mailbox Configuration
registers
2 KB
DSPSS to MSS mailbox memory space
MSS to DSPSS mailbox memory space
188 B
MSS to DSPSS mailbox Configuration registers
DSPSS to MSS mailbox Configuration registers
2 KB
RADARSS to DSPSS mailbox memory space
DSPSS to RADARSS mailbox memory space
188 B
RADARSS to DSPSS mailbox Configuration
registers
DSPSS to RADARSS mailbox Configuration
registers
Serial Interfaces and Connectivity
QSPI
MIBSPI-A
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Table 6-1. Master Subsystem, Cortex-R4F Memory Map (continued)
NAME
FRAME ADDRESS (HEX)
START
END
SIZE
DESCRIPTION
MIBSPI-B
0xFFF7_F600
0xFFF7_F7FF
512 B
MIBSPI-B module configuration registers
SCI-A
0xFFF7_E500
0xFFF7_E5FF
148 B
SCI-A module configuration registers
SCI-B
0xFFF7_E700
0xFFF7_E7FF
148 B
SCI-B module configuration registers
CAN
0xFFF7_DC00
0xFFF7_DDFF
512 B
CAN module configuration registers
CAN_FD(MCAN)
0xFFF7_C800
0xFFF7_CFFF
768 B
CAN-FD module configuration registers
0xFFF7_A000
0xFFF7_A1FF
452 B
MCAN ECC module registers
0xFFF7_D400
0xFFF7_D4FF
112 B
I2C module configuration registers
PCR-1
0xFFF7_8000
0xFFF7_87FF
1 KiB
PCR-1 interconnect configuration port
PCR-2
0xFCFF_1000
0xFCFF_17FF
1 KiB
PCR-2 interconnect configuration port
CRC
0xFE00_0000
0xFEFF_FFFF
16 KiB
CRC module configuration registers
PBIST
0xFFFF_E400
0xFFFF_E5FF
464 B
PBIST module configuration registers
STC
0xFFFF_E600
0xFFFF_E7FF
284 B
STC module configuration registers
DCC-A
0xFFFF_EC00
0xFFFF_ECFF
44 B
DCC-A module configuration registers
DCC-B
0xFFFF_F400
0xFFFF_F4FF
44 B
DCC-B module configuration registers
ESM
0xFFFF_F500
0xFFFF_F5FF
156 B
ESM module configuration registers
CCMR4
0xFFFF_F600
0xFFFF_F6FF
136 B
CCMR4 module configuration registers
0xFD00_0000
0XFDFF_FFFF
3 KiB
Crypto module configuration registers
DSS_TPTC0
0x5000 0000
0x5000 0317
792 B
TPTC0 module configuration space
DSS_REG
0x5000 0400
0x5000 075F
864 B
DSPSS control module registers
DSS_TPTC1
0x5000 0800
0x5000 0B17
792 B
TPTC1 module configuration space
DSS_REG2
0x5000 0C00
0x5000 0EA3
676 B
DSPSS control module registers
DSS_TPCC0
0x5001 0000
0x5001 3FFF
16 KB
TPCC0 module configuration space
DSS_RTIA/WDT
0x5002 0000
0x5002 00BF
192 B
DSS_RTIA/WDT configuration space
DSS_SCI
0x5003 0000
0x5003 0093
148 B
SCI memory space
DSS_STC
0x5004 0000
0x5004 011B
284 B
STC module configuration space
DSS_CBUFF
0x5007 0000
0x5007 0233
564 B
Common Buffer module configuration registers
DSS_TPTC2
0x5009 0000
0x5009 0317
792 B
TPTC2 module configuration space
DSS_TPTC3
0x5009 0400
0x5009 0717
792 B
TPTC3 module configuration space
DSS_TPCC1
0x500A 0000
0x500A 3FFF
16 KB
TPCC1 module configuration space
DSS_ESM
0x500D 0000
0x500D 005B
92 B
ESM module configuration registers
DSS_RTIB
0x500F 0000
0x500F 00BF
192 B
RTI-B module configuration registers
DSS_L3RAM
Shared memory
0x5100 0000
0x511F FFFF
2 MB (1)
L3 shared memory space
DSS_ADCBUF
Buffer
0x5200 0000
0x5200 7FFF
32 KB
ADC buffer memory space
DSS_CBUFF_FIFO
0x5202 0000
0x5202 3FFF
16 KB
Common buffer FIFO space
DSS_HSRAM1
I2C
Interconnects
Safety Modules
Security Modules
Crypto
Other Subsystems
0x5208 0000
0x5208 7FFF
32 KB
Handshake memory space
DSS_DSP_L2_UMA 0x577E 0000
P1
0x577F FFFF
128 KB
L2 RAM space
DSS_DSP_L2_UMA 0x5780 0000
P0
0x5781 FFFF
128 KB
L2 RAM space
DSS_DSP_L1P
0x57E0 0000
0x57E0 7FFF
32 KB
L1 program memory space
DSS_DSP_L1D
0x57F0 0000
0x57F0 7FFF
32 KB
L1 data memory space
(1)
768 KB memory within 2 MB memory space
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Table 6-1. Master Subsystem, Cortex-R4F Memory Map (continued)
FRAME ADDRESS (HEX)
NAME
START
END
SIZE
DESCRIPTION
Peripheral Memories (System and Nonsystem)
CAN RAM
0xFF1E_0000
0xFF1F_FFFF
128 KB
CAN RAM memory space
CAN-FD RAM
0xFF50_0000
0xFF51_FFFF
68 KB
CAN-FD RAM memory space
DMA1 RAM
0xFFF8_0000
0xFFF8_0FFF
4 KB
DMA1 RAM memory space
DMA2 RAM
0xFCF8 1000
0xFCF8_0FFF
4 KB
DMA2 RAM memory space
VIM RAM
0xFFF8_2000
0xFFF8_2FFF
2 KB
VIM RAM memory space
MIBSPIB-TX RAM
0xFF0C_0000
0xFF0C_01FF
0.5 KB
MIBSPIB-TX RAM memory space
MIBSPIB-RX RAM
0xFF0C_0200
0xFF0C_03FF
0.5 KB
MIBSPIB-RX RAM memory space
MIBSPIA-TX RAM
0xFF0E_0000
0xFF0E_01FF
0.5 KB
MIBSPIA-TX RAM memory space
MIBSPIA- RX RAM
0xFF0E_0200
0xFF0E_03FF
0.5 KB
MIBSPIA- RX RAM memory space
0xFFA0_0000
0xFFAF_FFFF
244 KB
Debug subsystem memory space and registers
Debug Modules
Debug subsystem
6.3.5
DSP Subsystem Memory Map
Table 6-2 shows the DSP C674x memory map.
Table 6-2. DSP C674x Memory Map
Name
Frame Address (Hex)
Size
Description
0x00F0_7FFF
32 KiB
L1 data memory space
0x00E0_7FFF
32 KiB
L1 program memory
space
0x0080_0000
0x0081_FFFF
128 KiB
L2 RAM space
0x007E_0000
0x007F_FFFF
128 KiB
L2 RAM space
TPCC0
0x0201_0000
0x0201_3FFF
16 KiB
TPCC0 module
configuration space
TPCC1
0x020A_0000
0x020A_3FFF
16 KiB
TPCC1 module
configuration space
TPTC0
0x0200 0000
0x0200 03FF
1 KiB
TPTC0 module
configuration space
TPTC1
0x0200 0800
0x0200 0BFF
1 KiB
TPTC1 module
configuration space
TPTC2
0x0209_0000
0x0209_03FF
1 KiB
TPTC2 module
configuration space
TPTC3
0x0209_0400
0x0209_07FF
1 KiB
TPTC3 module
configuration space
DSS_REG
0x0200_0400
0x0200_07FF
864 B
DSPSS control module
registers
DSS_REG2
0x0200_0C00
0x0200_0FFF
624 B
DSPSS control module
registers
ADC Buffer
0x2100_0000
0x2100_7FFC
32 KiB
ADC buffer memory space
CBUFF-FIFO
0x2102_0000
0x2102_3FFC
16 KiB
Common buffer FIFO
space
L3-Shared memory
0x2000_0000
0x201F_FFFF
2 MB
L3 shared memory space
Start
End
DSP_L1D
0x00F0_0000
DSP_L1P
0x00E0_0000
DSP_L2_UMAP0
DSP_L2_UMAP1
DSP Memories
EDMA
Control Registers
System Memories
64
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Table 6-2. DSP C674x Memory Map (continued)
Name
Frame Address (Hex)
Size
Description
0x2108_7FFC
32 KiB
Handshake memory
space
0x0202_0000
0x0202_00FF
192 B
RTI-A module
configuration registers
RTI-B
0x020F_0000
0x020F_00FF
192 B
RTI-B module
configuration registers
CBUFF
0x0207_0000
0x0207_03FF
564 B
Common Buffer module
Configuration registers
Mail Box
MSS<->RADARSS
0x5060_1000
0x5060_17FF
2 KiB
RADARSS to MSS
mailbox memory space
0x5060_2000
0x5060_27FF
0x0460_8000
0x0460_80FF
0x0460_8060
0x0460_86FF
0x5060_4000
0x5060_47FF
0x5060_5000
0x5060_57FF
0x0460_8400
0x0460_84FF
0x0460_8300
0x0460_83FF
0x5060_6000
0x5060_67FF
0x5060_7000
0x5060_7FFF
0x0460_8200
0x0460_82FF
0x0460_8100
0x0460_81FF
Start
End
0x2108_0000
RTI-A/WD
HS-RAM
System Peripherals
Mail Box
MSS<->DSPSS
Mail Box
RADARSS<->DSPSS
MSS to RADARSS
mailbox memory space
188 B
MSS to RADARSS
mailbox Configuration
registers
RADARSS to MSS
mailbox Configuration
registers
2 KiB
DSPSS to MSS mailbox
memory space
MSS to DSPSS mailbox
memory space
188 B
MSS to DSPSS mailbox
Configuration registers
DSPSS to MSS mailbox
Configuration registers
2 KiB
RADARSS to DSPSS
mailbox memory space
DSPSS to RADARSS
mailbox memory space
188 B
RADARSS to DSPSS
mailbox Configuration
registers
DSPSS to RADARSS
mailbox Configuration
registers
Safety Modules
ESM
0x020D_0000
92 B
ESM module
Configuration registers
CRC
0x2200_0000
0x2200_03FF
1 KiB
CRC module
Configuration registers
STC
0x0204_0000
0x0204_01FF
284 B
STC module Configuration
registers
0x0203_0000
0x0203_00FF
148 B
SCI module Configuration
registers
Nonsystem Peripherals
SCI
6.4
6.4.1
Other Subsystems
ADC Channels (Service) for User Application
The AWR1642 device includes provision for an ADC service for user application, where the
GPADC engine present inside the device can be used to measure up to six external voltages. The ADC1,
ADC2, ADC3, ADC4, ADC5, and ADC6 pins are used for this purpose.
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•
•
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ADC itself is controlled by TI firmware running inside the BIST subsystem and access to it for
customer’s external voltage monitoring purpose is via ‘monitoring API’ calls routed to the BIST
subsystem. This API could be linked with the user application running on the Master R4.
BIST subsystem firmware will internally schedule these measurements along with other (1) RF and
Analog monitoring operations. The API allows configuring the settling time (number of ADC samples to
skip) and number of consecutive samples to take. At the end of a frame, the minimum, maximum and
average of the readings will be reported for each of the monitored voltages.
GPADC Specifications:
• 625 Ksps SAR ADC
• 0 to 1.8V input range
• 10-bit resolution
• For 5 out of the 6 inputs, an optional internal buffer is available. Without the buffer, the ADC has a
switched capacitor input load modeled with 5pF of sampling capacitance and 12pF parasitic
capacitance (GPADC channel 6, the internal buffer is not available).
ANALOG TEST 1-4,
ANAMUX
5
GPADC
5
VSENSE
Figure 6-5. ADC Path
(1)
GPADC structures are used for measuring the output of internal temperature sensors. The accuracy of these measurements is ±10ºC
Table 6-3. GP-ADC Parameter
PARAMETER
TYP
UNIT
1.8
V
ADC unbuffered input voltage range
0 – 1.8
V
ADC buffered input voltage range (1)
0.4 – 1.3
V
ADC resolution
10
bits
ADC offset error
±5
LSB
ADC gain error
±5
LSB
ADC DNL
–1/+2.5
LSB
ADC INL
±2.5
LSB
ADC sample rate (2)
625
Ksps
ADC sampling time (2)
400
ns
ADC internal cap
10
pF
ADC buffer input capacitance
2
pF
ADC input leakage current
3
uA
ADC supply
(1)
(2)
66
Outside of given range, the buffer output will become nonlinear.
ADC itself is controlled by TI firmware running inside the BIST subsystem. For more details please refer to the API calls.
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7 Monitoring and Diagnostics
7.1
Monitoring and Diagnostic Mechanisms
Below is the list given for the main monitoring and diagnostic mechanisms available in the AWR1642.
Table 7-1. Monitoring and Diagnostic Mechanisms for AWR1642
S No
1
2
3
4
5
7
Feature
Description
Boot time LBIST For Master
R4F Core and associated
VIM
AWR1642 architecture supports hardware logic BIST (LBIST) engine self-test Controller
(STC). This logic is used to provide a very high diagnostic coverage (>90%) on the Master
R4F CPU core and Vectored Interrupt Module (VIM) at a transistor level.
LBIST for the CPU and VIM need to be triggered by application code before starting the
functional safety application. CPU stays there in while loop and does not proceed further if a
fault is identified.
Boot time PBIST for Master
R4F TCM Memories
Master R4F has three Tightly coupled Memories (TCM) memories TCMA, TCMB0 and
TCMB1. AWR1642 architecture supports a hardware programmable memory BIST (PBIST)
engine. This logic is used to provide a very high diagnostic coverage (March-13n) on the
implemented Master R4F TCMs at a transistor level.
PBIST for TCM memories is triggered by Bootloader at the boot time before starting
download of application from Flash or peripheral interface. CPU stays there in while loop and
does not proceed further if a fault is identified.
End to End ECC for Master
R4F TCM Memories
TCMs diagnostic is supported by Single error correction double error detection (SECDED)
ECC diagnostic. An 8-bit code word is used to store the ECC data as calculated over the 64bit data bus. ECC evaluation is done by the ECC control logic inside the CPU. This scheme
provides end-to-end diagnostics on the transmissions between CPU and TCM. CPU can be
configured to have predetermined response (Ignore or Abort generation) to single and double
bit error conditions.
Master R4F TCM bit
multiplexing
Logical TCM word and its associated ECC code is split and stored in two physical SRAM
banks. This scheme provides an inherent diagnostic mechanism for address decode failures
in the physical SRAM banks. Faults in the bank addressing are detected by the CPU as an
ECC fault.
Further, bit multiplexing scheme implemented such that the bits accessed to generate a
logical (CPU) word are not physically adjacent. This scheme helps to reduce the probability
of physical multi-bit faults resulting in logical multi-bit faults; rather they manifest as multiple
single bit faults. As the SECDED TCM ECC can correct a single bit fault in a logical word,
this scheme improves the usefulness of the TCM ECC diagnostic.
Both these features are hardware features and cannot be enabled or disabled by application
software.
Clock Monitor
AWR1642 architecture supports Three Digital Clock Comparators (DCCs) and an internal
RCOSC. Dual functionality is provided by these modules – Clock detection and Clock
Monitoring.
DCCint is used to check the availability/range of Reference clock at boot otherwise the
device is moved into limp mode (Device still boots but on 10MHz RCOSC clock source. This
provides debug capability). DCCint is only used by boot loader during boot time. It is disabled
once the APLL is enabled and locked.
DCC1 is dedicated for APLL lock detection monitoring, comparing the APLL output divided
version with the Reference input clock of the device. Initially (before configuring APLL),
DCC1 is used by bootloader to identify the precise frequency of reference input clock against
the internal RCOSC clock source. Failure detection for DCC1 would cause the device to go
into limp mode.
DCC2 module is one which is available for user software . From the list of clock options
given in detailed spec, any two clocks can be compared. One example usage is to compare
the CPU clock with the Reference or internal RCOSC clock source. Failure detection is
indicated to the Master R4F CPU via Error Signaling Module (ESM).
RTI/WD for Master R4F
AWR1642 architecture supports the use of an internal watchdog that is implemented in the
real-time interrupt (RTI) module. The internal watchdog has two modes of operation: digital
watchdog (DWD) and digital windowed watchdog (DWWD). The modes of operation are
mutually exclusive; the designer can elect to use one mode or the other but not both at the
same time.
Watchdog can issue either an internal (warm) system reset or a CPU non-mask able
interrupt upon detection of a failure.
The Watchdog is enabled by the bootloader in DWD mode at boot time to track the boot
process. Once the application code takes up the control, Watchdog can be configured again
for mode and timings based on specific customer requirements.
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AWR1642
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Table 7-1. Monitoring and Diagnostic Mechanisms for AWR1642 (continued)
S No
Description
MPU for Master R4F
Cortex-R4F CPU includes an MPU. The MPU logic can be used to provide spatial separation
of software tasks in the device memory. Cortex-R4F MPU supports 12 regions. It is expected
that the operating system controls the MPU and changes the MPU settings based on the
needs of each task. A violation of a configured memory protection policy results in a CPU
abort.
PBIST for Peripheral
interface SRAMs - SPIs,
CANs
AWR1642 architecture supports a hardware programmable memory BIST (PBIST) engine for
Peripheral SRAMs as well.
PBIST for peripheral SRAM memories can be triggered by the application. User can elect to
run the PBIST on one SRAM or on groups of SRAMs based on the execution time, which
can be allocated to the PBIST diagnostic. The PBIST tests are destructive to memory
contents, and as such are typically run only at boot time. However, the user has the freedom
to initiate the tests at any time if peripheral communication can be hindered.
Any fault detected by the PBIST results in an error indicated in PBIST status registers.
ECC for Peripheral interface
SRAMs – SPIs, CANs
Peripheral interface SRAMs diagnostic is supported by Single error correction double error
detection (SECDED) ECC diagnostic. When a single or double bit error is detected the
Master R4F is notified via ESM (Error Signaling Module). This feature is disabled after reset.
Software must configure and enable this feature in the peripheral and ESM module. ECC
failure (both single bit corrected and double bit uncorrectable error conditions) is reported to
the Master R4F as an interrupt via ESM module.
Configuration registers
protection for Master SS
peripherals
All the Master SS peripherals (SPIs, CANs, I2C, DMAs, RTI/WD, DCCs, IOMUX etc.) are
connected to interconnect via Peripheral Central resource (PCR). This provides two
diagnostic mechanisms that can limit access to peripherals. Peripherals can be clock gated
per peripheral chip select in the PCR. This can be utilized to disable unused features such
that they cannot interfere. In addition, each peripheral chip select can be programmed to limit
access based on privilege level of transaction. This feature can be used to limit access to
entire peripherals to privileged operating system code only.
These diagnostic mechanisms are disabled after reset. Software must configure and enable
these mechanisms. Protection violation also generates an ‘aerror’ that result in abort to
Master R4F or error response to other masters such as DMAs.
Cyclic Redundancy Check
–Master SS
AWR1642 architecture supports hardware CRC engine on Master SS implementing the
below polynomials.
•
CRC16 CCITT – 0x10
•
CRC32 Ethernet – 0x04C11DB7
•
CRC64
•
CRC 32C – CASTAGNOLI – 0x1EDC6F4
•
CRC32P4 – E2E Profile4 – 0xF4ACFB1
•
CRC-8 – H2F Autosar – 0x2F
•
CRC-8 – VDA CAN – 0x1D
The read operation of the SRAM contents to the CRC can be done by CPU or by DMA. The
comparison of results, indication of fault, and fault response are the responsibility of the
software managing the test.
13
MPU for DMAs
AWR1642 architecture supports MPUs on Master SS DMAs. Failure detection by MPU is
reported to the Master R4F CPU core as an interrupt via ESM.
DSPSS’s high performance EDMAs also includes MPUs on both read and writes master
ports. EDMA MPUs supports 8 regions. Failure detection by MPU is reported to the DSP
core as an interrupt via local ESM.
14
Boot time LBIST For BIST
R4F Core and associated
VIM
AWR1642 architecture supports hardware logic BIST (LBIST) even for BIST R4F core and
associated VIM module. This logic provides very high diagnostic coverage (>90%) on the
BIST R4F CPU core and VIM.
This is triggered by Master R4F boot loader at boot time and it does not proceed further if
the fault is detected.
15
Boot time PBIST for BIST
R4F TCM Memories
AWR1642 architecture supports a hardware programmable memory BIST (PBIST) engine for
BIST R4F TCMs which provide a very high diagnostic coverage (March-13n) on the BIST
R4F TCMs.
PBIST is triggered by Master R4F Bootloader at the boot time and it does not proceed
further if the fault is detected.
16
End to End ECC for BIST
R4F TCM Memories
BIST R4F TCMs diagnostic is supported by Single error correction double error detection
(SECDED) ECC diagnostic. Single bit error is communicated to the BIST R4FCPU while
double bit error is communicated to Master R4F as an interrupt so that application code
becomes aware of this and takes appropriate action.
8
9
10
11
12
68
Feature
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Table 7-1. Monitoring and Diagnostic Mechanisms for AWR1642 (continued)
S No
(2)
Description
17
BIST R4F TCM bit
multiplexing
Logical TCM word and its associated ECC code is split and stored in two physical SRAM
banks. This scheme provides an inherent diagnostic mechanism for address decode failures
in the physical SRAM banks and helps to reduce the probability of physical multi-bit faults
resulting in logical multi-bit faults.
18
RTI/WD for BIST R4F
AWR1642 architecture supports an internal watchdog for BIST R4F. Timeout condition is
reported via an interrupt to Master R4F and rest is left to application code to either go for SW
reset for BIST SS or warm reset for the AWR1642 device to come out of faulty condition.
19
Boot time PBIST for L1P,
L1D, L2 and L3 Memories
AWR1642 architecture supports a hardware programmable memory BIST (PBIST) engine for
DSPSS’s L1P, L1D, L2 and L3 memories which provide a very high diagnostic coverage
(March-13n).
PBIST is triggered by Master R4F Bootloader at the boot time and it does not proceed
further if the fault is detected.
20
Parity on L1P
AWR1642 architecture supports Parity diagnostic on DSP’s L1P memory. Parity error is
reported to the CPU as an interrupt.
Note:- L1D memory is not covered by parity or ECC and need to be covered by application
level diagnostics.
21
ECC on DSP’s L2 Memory
AWR1642 architecture supports both Parity Single error correction double error detection
(SECDED) ECC diagnostic on DSP’s L2 memory. L2 Memory is a unified 256KB of memory
used to store program and Data sections for the DSP. A 12-bit code word is used to store
the ECC data as calculated over the 256-bit data bus (logical instruction fetch size). The
ECC logic for the L2 access is located in the DSP and evaluation is done by the ECC control
logic inside the DSP. This scheme provides end-to-end diagnostics on the transmissions
between DSP and L2. Byte aligned Parity mechanism is also available on L2 to take care of
data section.
22
ECC on Radar Data Cube
(L3) Memory
L3 memory is used as Radar data section in AWR1642. AWR1642 architecture supports
Single error correction double error detection (SECDED) ECC diagnostic on L3 memory. An
8-bit code word is used to store the ECC data as calculated over the 64-bit data bus.
Failure detection by ECC logic is reported to the Master R4F CPU core as an interrupt via
ESM.
RTI/WD for DSP Core
AWR1642 architecture supports the use of an internal watchdog for BIST R4F that is
implemented in the real-time interrupt (RTI) module – replication of same module as used in
Master SS. This module supports same features as that of RTI/WD for Master/BIST R4F.
This watchdog is enabled by customer application code and Timeout condition is reported
via an interrupt to Master R4F and rest is left to application code in Master R4F to either go
for SW reset for DSP SS or warm reset for the AWR1642 device to come out of faulty
condition.
24
CRC for DSP Sub-System
AWR1642 architecture supports dedicated hardware CRC on DSPSS implementing the
below polynomials.
•
CRC16 CCITT - 0x10
•
CRC32 Ethernet - 0x04C11DB7
•
CRC64
The read of SRAM contents to the CRC can be done by DSP CPU or by DMA. The
comparison of results, indication of fault, and fault response are the responsibility of the
software managing the test.
25
MPU for DSP
AWR1642 architecture supports MPUs for DSP memory accesses (L1D, L1P, and L2). L2
memory supports 64 regions and 16 regions for L1P and L1D each. Failure detection by
MPU is reported to the DSP core as an abort.
26
Temperature Sensors
AWR1642 architecture supports various temperature sensors all across the device (next to
power hungry modules such as PAs, DSP etc) which is monitored during the inter-frame
period. (1)
27
Tx Power Monitors
AWR1642 architecture supports power detectors at the Tx output. (2)
23
(1)
Feature
Monitoring is done by the TI's code running on BIST R4F. There are two modes in which it could be configured to report the temperature
sensed via API by customer application.
• Report the temperature sensed after every N frames
• Report the condition once the temperature crosses programmed threshold.
It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4Fvia Mailbox.
Monitoring is done by the TI's code running on BIST R4F.
There are two modes in which it could be configured to report the detected output power via API by customer application.
• Report the power detected after every N frames
• Report the condition once the output power degrades by more than configured threshold from the configured.
It is completely up to customer SW to decide on the appropriate action based on the message from BIST R4F.
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Table 7-1. Monitoring and Diagnostic Mechanisms for AWR1642 (continued)
S No
70
Feature
Description
28
Error Signaling
Error Output
When a diagnostic detects a fault, the error must be indicated. The AWR1642 architecture
provides aggregation of fault indication from internal monitoring/diagnostic mechanisms using
a peripheral logic known as the Error Signaling Module (ESM). The ESM provides
mechanisms to classify errors by severity and to provide programmable error response.
ESM module is configured by customer application code and specific error signals can be
enabled or masked to generate an interrupt (Low/High priority) for the Master R4F CPU.
AWR1642 supports Nerror output signal (IO) which can be monitored externally to identify
any kind of high severity faults in the design which could not be handled by the R4F.
29
Synthesizer (Chirp)
frequency monitor
Monitors Synthesizer’s frequency ramp by counting (divided-down) clock cycles and
comparing to ideal frequency ramp. Excess frequency errors above a certain threshold, if
any, are detected and reported.
30
AWR1642 architecture supports a ball break detection mechanism based on Impedance
measurement at the TX output(s) to detect and report any large deviations that can indicate
a ball break.
Ball break detection for TX
Monitoring is done by TIs code running on BIST R4F and failure is reported to the Master
ports (TX Ball break monitor)
R4F via Mailbox.
It is completely up to customer SW to decide on the appropriate action based on the
message from BIST R4F.
31
RX loopback test
Built-in TX to RX loopback to enable detection of failures in the RX path(s), including
Gain/Noise figure, inter-RX balance, etc.
32
IF loopback test
Built-in IF (square wave) test tone input to monitor IF filter’s frequency response and detect
failure.
33
RX saturation detect
Provision to detect ADC saturation due to excessive incoming signal level and/or
interference.
34
Boot time LBIST for DSP
core
AWR1642 device supports boot time LBIST for the DSP Core. LBIST can be triggered by the
Master R4F application code during boot time.
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7.1.1
SWRS203A – MAY 2017 – REVISED APRIL 2018
Error Signaling Module
From Hardware Diagnostics
When a diagnostic detects a fault, the error must be indicated. AWR1642 architecture provides
aggregation of fault indication from internal diagnostic mechanisms using a peripheral logic known as the
error signaling module (ESM). The ESM provides mechanisms to classify faults by severity and allows
programmable error response. Below is the high level block diagram for ESM module.
Low Priority
Interrupt
Handing
Low Priority
Interrupy
High Priority
Interrupt
Handing
High Priority
Interrupy
Error Signal
Handling
Device Output
Pin
Error Group 1
Interrupt Enable
Interrupt Priority
Error Group 2
Nerror Enable
Error Group 3
Figure 7-1. ESM Module Diagram
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8 Applications, Implementation, and Layout
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
8.1
Application Information
Key device features driving the following applications are:
• Integration of Radar Front End and Programmable MCU
• Flexible boot modes: Autonomous Application boot using a serial flash or external boot over SPI.
8.2
Short-Range Radar
40-MHz
Crystal
Serial
Flash
Power Management
QSPI
Integrated MCU
ARM Cortex-R4F
Antenna
Structure
RX1
RX2
RX3
RX4
CAN
DCAN
PHY
Automotive
Network
CAN FD
MCAN
PHY
Automotive
Network
Radar
Front End
TX1
TX2
Integrated DSP
TI C674x
AWR1642
Figure 8-1. Short-Range Radar
8.3
Reference Schematic
Figure 8-2 and Figure 8-3 show the reference schematic and low-noise LDO circuitry for the AWR1642
device.
72
Applications, Implementation, and Layout
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SWRS203A – MAY 2017 – REVISED APRIL 2018
+3.3VD
AR_1V8
AR_1V8
AR_1P3_RF2
PMIC_1V2
AR_1V4_APLL
AR_1V4_SYNTH
AR_1V8
PMIC_1V2
1V8 SUPPLY
AR_VBGAP
AR_VOUT_PA
BB SUPPLY
AR_1V8
AR_1P3_RF1
0.22UF
B4
B6
A14
AR_OSC_CLKOUT
AR_XTALP
AR_XTALM
AR_PMIC_CLKOUT_SOP2
AR_MCUCLKOUT
C15
D15
P9
N8
P1
AR_ANATEST1
AR_ANATEST2
AR_ANATEST3
AR_ANATEST4
AR_ANAMUX
AR_VSENSE
P2
P3
R2
B13
C14
N15
AR_DMM_CLK
AR_DMM_SYNC
AR_DP0
AR_DP1
AR_DP2
AR_DP3
AR_DP4
AR_DP5
AR_DP6
AR_DP7
AR_DP8
AR_DP9
AR_DP10
AR_DP11
AR_DP12
AR_DP13
AR_DP14
AR_DP15
N14
R4
P5
R5
P6
R7
P7
R8
P8
D14
B14
B15
C9
C8
B9
B8
A9
AR_SYNC_IN
P4
G13
AR_SYNC_OUT_SOP1
B10
B2
VBGAP
VOUT_PA
VOUT_PA
OSC_CLKOUT
CLKP
CLKM
PMIC_CLKOUT
MCU_CLKOUT
GPADC_1
GPADC_2
GPADC_3
GPADC_4
GPADC_5
GPADC_6
AWR1642
DMM_CLK
DMM_SYNC
DP0
DP1
DP2
DP3
DP4
DP5
DP6
DP7
DP8
DP9
DP10
DP11
DP12
DP13
DP14
DP15
AWR1642_PRELIMINARY
SYNC_IN
SYNC_OUT
XTAL
R15
AR_XTALM
K11
Y1
H11
F11
E11
40MHZ
L10
AR_LVDS_0P
AR_LVDS_0M
AR_LVDS_1P
AR_LVDS_1M
AR_LVDS_CLKP
AR_LVDS_CLKM
AR_LVDS_FRCLKP
AR_LVDS_FRCLKM
LVDS_TXP_0
LVDS_TXM_0
LVDS_TXP_1
LVDS_TXM_1
LVDS_CLKP
LVDS_CLKM
LVDS_FRCLKP
LVDS_FRCLKM
J14
NRESET
WARM_RESET
NERROR_IN
NERROR_OUT
R3
RS232_RX
RS232_TX
N4
AR_RS232RX
N5
AR_RS232TX
QSPI_CLK
QSPI_CS
QSPI_0
QSPI_1
QSPI_2
QSPI_3
R12
TCK
TMS
TDO
TDI
P10
SPI_HOST_INTR_1
SPI_CLK_1
SPI_CS_1
MISO_1
MOSI_1
P13
SPI_CLK_2
SPI_CS_2
MISO_2
MOSI_2
F14
GPIO_0
GPIO_1
GPIO_2
H13
VSSA
VSSA
VSSA
VSSA
VSSA
VCLK SUPPLY
AR_1V8
10UF
C6
C10
0.22UF
0.22UF
0.22UF
0.22UF
10UF
C14
C20
C28
C33
C35
J15
K14
K15
L14
L15
M14
M15
AR_NRST
AR_WARMRST
AR_NERRIN
AR_NERR_OUT
N9
N7
N6
P11
R13
N12
R14
P12
R11
E14
D13
H14
G14
F13
RF1 SUPPLY
RF2 SUPPLY
+3.3VD
AR_1P3_RF2
AR_1P3_RF1
OPENDRAIN SIGNALS
PLACE ONBOARD
PULLUPS
0.22UF
10UF
0.22UF
10UF
C5
C7
C13
C17
AR_TCK
AR_TMS
AR_TDO_SOP0
AR_TDI
N13
C13
3V3 IO SUPPLY
1V3 SUPPLY
TRACES
0.22UF
0.22UF
C29
C32
2.2UF
C87
AR_QSPI_SCLK
AR_QSPI_CS
AR_QSPI_D0
AR_QSPI_D1
AR_QSPI_D2
AR_QSPI_D3
N10
E13
100 OHMS
DIFFERENTIAL
OUTPUT DECAPS
AR_VBGAP
AR_HOSTINTR1
AR_SPICLK1
AR_CS1
AR_MISO1
AR_MOSI1
0.22UF
AR_MSS_LOGGER
AR_BSS_LOGGER
C4
AR_VOUT_PA
0.22UF
C11
AR_1V4_APLL
AR_1V4_SYNTH
10UF
C12
1UF
1UF
C30
C24
AR_SCL
AR_SDA
J13
AR_GPIO_0
AR_GPIO_1
K13
AR_GPIO_2
A1
B1
1V2 SUPPLY
C1
E1
VNWA SUPPLY
G1
SRAM SUPPLY
DIG SUPPLY
J1
L1
N1
J2
R1
L2
E2
G2
B3
A3
C3
N2
E3
J3
F3
H3
G3
L3
K3
N3
M3
B5
A5
C5
C4
B7
A7
C7
C6
E5
A15
J6
L5
E6
G6
J7
L6
H7
G7
J8
E8
K7
G8
L8
F9
K8
K9
H9
K10
J10
4.7PF
E10
Y1 Y1
4.7PF
VCOLDO SUPPLY
AR_1V8
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
C9
C15
VSS
VSS
VSS
VSS
VSS
VSS
G10
AR_XTALP
1P8V IO SUPPLY
AR_1V8
A2
A13
A10
F5
K5
VIN_18BB
VIN_18BB
VOUT_14APLL
B11
B12
VIN_18CLK
VIN_18VCO
D2
C2
VIN_13RF2
VIN_13RF2
H5
G5
G15
J5
VIN_SRAM
VIN_13RF1
VIN_13RF1
VIN_13RF1
R6
P14
VNWA
R10
H15
N11
P15
E15
F15
R9
L13
RX1
RX2
RX3
RX4
TX1
TX2
VOUT_14SYNTH
F2
VIOIN
VIOIN
VDDIN
VDDIN
VDDIN
VDDIN
H2
TO ANTENNA
VIOIN_18DIFF
50 OHMS RF TRACES
VPP
VIOIN_18
U2
0.22UF
C3
0.1UF
C8
K2
AR_1V8
AR_1V8
PMIC_1V2
VPP_1P7
M2
DIFF SUPPLY
AR_1V8
+3.3VD
AR_TDO_SOP0
10K
R10
SOP0
R11
SOP1
0.1UF
0.1UF
2.2UF
0.22UF
C16
C26
C27
C31
0.22UF
C34
SOP LINES TO BE SET
R5
+3.3VD
AR_SYNC_OUT_SOP1
10K
DURING BOOTUP TO DECIDE
0
THE POWERUP MODE.
+3.3VD
+3.3VD
AR_PMIC_CLKOUT_SOP2
R3
R1
1UF
47.5K
10K
C1
S25FL132K0XNFB01
10K
R12
SOP2
10K
0.1UF
R9
C2
U1
S25FL132K0XN
AR_QSPI_CS
AR_QSPI_D1
1
33.2
R4
2
3
33.2
R2
4
8
7
6
5
R6
R8
R7
33.2
33.2
33.2
AR_QSPI_D3
AR_QSPI_SCLK
AR_QSPI_D0
EP
AR_QSPI_D2
CS_N
VCC
SO/IO1 HOLD_N/IO3
WP_N/IO2
SCK
VSS
SI/IO0
EP
Copyright © 2017, Texas Instruments Incorporated
Figure 8-2. AWR1642 Reference Schematic
Applications, Implementation, and Layout
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LDO_01 (1.8V OUTPUT)
PMIC_2V3
AR_1V8
U4
PMIC_2V3
8
7
6
5
R84
10K
0.1UF
R83
C21
10K
22UF
C25
10UF
0.47UF
C23
OUT
OUT
FB/SNS
GND
EPAD
1
2
3
4
EP
LDO_EN
LDO_EN
TPS7A8101
IN
IN
NR
EN
0.47UF
12.7K
R82
10UF
C18
C19
C22
DNI=TRUE
10K
R81
LDO_02 (1.3V LDO)
AR_1P3_RF1
C42
R15
C44
0.01UF
1.96K
1UF
C48
C46
SS_CTRL
C40
0.01UF
C36
C37
C38
C39
5
LDO_EN
0.01UF
17
16
20
19
18
EN1
NR/SS1
SS_CTRL1
PG1
FB1
TPS7A8801
9
4
IN1
IN1
GND
IN2
IN2
OUT1
OUT1
GND
OUT2
OUT2
GND
14
AR_1P3_RF2
13
12
11
EP
0
C41
3K
15
10
3
TPS7A8801RTJ
1.96K
R14
0.01UF
C43
1UF
10UF
10UF
C45
C47
C49
SS_CTRL
10UF
EN2
NR/SS2
SS_CTRL2
PG2
FB2
22UF
6
2
10UF
7
1
22UF
8
PMIC_1V8
10UF
R132
LDO_EN
U3
10UF
R13
3K
R121
Copyright © 2017, Texas Instruments Incorporated
Figure 8-3. AWR1642 Low-Noise LDO Circuitry
74
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8.4
SWRS203A – MAY 2017 – REVISED APRIL 2018
Layout
The top layer routing, top layer closeup, and bottom layer routing are shown in Figure 8-4, Figure 8-5, and
Figure 8-6, respectively.
8.4.1
Layout Guidelines
Figure 8-4. Top Layer Routing
Applications, Implementation, and Layout
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Figure 8-5. Top Layer Routing Closeup
76
Applications, Implementation, and Layout
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Figure 8-6. Bottom Layer Routing
Applications, Implementation, and Layout
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8.4.2
www.ti.com
Stackup Details
1
Rogers 4835 4mil coreH/1 Low Pro
Rogers 4835
0.689
4.000
1.260
2.067
4.000
1.260
3.480
Iteq IT180A Prepreg 1080
Dielectric
4.195
2.830
3.700
Iteq IT180A Prepreg 1080
Dielectric
4.195
2.830
3.700
Iteq IT180A 28 mil core 1/1
FR4
1.260
28.000
1.260
1.260
28.000
1.260
4.280
Iteq IT180A Prepreg 1080
Dielectric
4.195
2.691
3.700
Iteq IT180A Prepreg 1080
Dielectric
4.195
2.691
3.700
FR4
1.260
4.000
0.689
1.260
4.000
2.067
3.790
3
4
56.21
2
5
Iteq IT180A 4 mil core 1/H
6
78
Applications, Implementation, and Layout
100.000
73.000
69.000
48.000
72.000
100.000
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9 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the
device, generate code, and develop solutions follow.
9.1
Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, AWR1642). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ABL0161), the temperature range (for example, blank is the default
commercial temperature range). Figure 9-1 provides a legend for reading the complete device name for
any AWR1642 device.
For orderable part numbers of AWR1642 devices in the ABL0161 package types, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the AWR1642 Device
Errata.
Device and Documentation Support
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AWR
1
www.ti.com
6
42
B
I
G
ABL
Q1
Qualification
Q1 = Q100
Blank = no special Qual
Prefix
AWR = Production
Tray or Tape & Reel
Generation
1 = 76 ± 81 GHz
R = Big Reel
Blank = Tray
Variant
2 = FE
4 = FE + FFT + MCU
6 = FE + MCU + DSP + 1.5 MB
Package
ABL = BGA
Security
Num RX/TX Channels
RX = 1,2,3,4
TX = 1,2,3
G = General
S = Secure
D = Development Secure
Silicon PG Revision
Blank = Rev 1.0
A = Rev 2.0
Temperature (Tj)
C = 0°C to 70°C
K = ±40°C to 85°C
A = ±40°C to 105°C
I = ±40°C to 125°C
Features
Blank = Baseline
P = High Performance
Safety Level
A = ASIL A Targeted
B = ASIL B Targeted
Figure 9-1. Device Nomenclature
9.2
Tools and Software
Models
AWR1642 BSDL Model Boundary scan database of testable input and output pins for IEEE 1149.1 of the
specific device.
AWR1642 IBIS Model IO buffer information model for the IO buffers of the device. For simulation on a
circuit board, see IBIS Open Forum.
AWR1642 Checklist for Schematic Review, Layout Review, Bringup/Wakeup A set of steps in
spreadsheet form to select system functions and pinmux options. Specific EVM schematic
and layout notes to apply to customer engineering. A bringup checklist is suggested for
customers.
9.3
Documentation Support
To receive notification of documentation updates—including silicon errata—go to the product folder for
your device on ti.com (AWR1642). In the upper right corner, click the "Alert me" button. This registers you
to receive a weekly digest of product information that has changed (if any). For change details, check the
revision history of any revised document.
The current documentation that describes the DSP, related peripherals, and other technical collateral
follows.
Errata
AWR1642 Device Errata Describes known advisories, limitations, and cautions on silicon and provides
workarounds.
80
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9.4
SWRS203A – MAY 2017 – REVISED APRIL 2018
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
TI Embedded Processors Wiki Established to help developers get started with Embedded Processors
from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
9.5
Trademarks
E2E is a trademark of Texas Instruments.
ARM, Cortex are registered trademarks of ARM Limited.
All other trademarks are the property of their respective owners.
9.6
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.7
Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data
(as defined by the U.S., EU, and other Export Administration Regulations) including software, or any
controlled product restricted by other applicable national regulations, received from disclosing party under
nondisclosure obligations (if any), or any direct product of such technology, to any destination to which
such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior
authorization from U.S. Department of Commerce and other competent Government authorities to the
extent required by those laws.
9.8
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
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10 Mechanical, Packaging, and Orderable Information
10.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
CAUTION
The following package information is subject to change without notice.
82
Mechanical, Packaging, and Orderable Information
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AWR1642
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SWRS203A – MAY 2017 – REVISED APRIL 2018
PACKAGE OUTLINE
ABL0161B
FCBGA - 1.17 mm max height
SCALE 1.400
PLASTIC BALL GRID ARRAY
10.5
10.3
A
B
BALL A1 CORNER
10.5
10.3
1.17 MAX
C
SEATING PLANE
BALL TYP
0.37
TYP
0.27
0.1 C
9.1 TYP
PKG
(0.65) TYP
R
P
(0.65) TYP
N
M
L
K
J
9.1
TYP
PKG
H
G
F
E
D
161X
C
B
0.45
0.35
0.15
0.08
C A B
C
A
0.65 TYP
1 2
BALL A1 CORNER
3
4 5
6 7 8
9 10 11 12 13 14 15
0.65 TYP
4223365/A 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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www.ti.com
EXAMPLE BOARD LAYOUT
ABL0161B
FCBGA - 1.17 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
161X (
0.32)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
(0.65) TYP
B
C
D
E
F
G
PKG
H
J
K
L
M
N
P
R
PKG
LAND PATTERN EXAMPLE
SCALE:10X
0.05 MAX
0.05 MIN
( 0.32)
METAL
METAL UNDER
SOLDER MASK
( 0.32)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223365/A 10/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
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SWRS203A – MAY 2017 – REVISED APRIL 2018
EXAMPLE STENCIL DESIGN
ABL0161B
FCBGA - 1.17 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
161X ( 0.32)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
A
B
(0.65) TYP
C
D
E
F
G
PKG
H
J
K
L
M
N
P
R
PKG
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4223365/A 10/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OPTION ADDENDUM
www.ti.com
5-Jun-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
AWR1642ABIGABLQ1
ACTIVE
FC/CSP
ABL
161
1
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 125
AWR1642
IG
502A
AWR1642ABIGABLRQ1
ACTIVE
FC/CSP
ABL
161
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 125
AWR1642
IG
AWR1642ABISABLQ1
ACTIVE
FC/CSP
ABL
161
1
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 125
AWR1642
IS
502AC
AWR1642ABISABLRQ1
ACTIVE
FC/CSP
ABL
161
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 125
AWR1642
IS
X1642BIGABL
ACTIVE
FC/CSP
ABL
161
1
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Jun-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
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solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
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Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
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TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
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INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
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Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
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medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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