TI1 ADS112C04 16-bit, 4-channel, 2-ksps, delta-sigma adc with i2c interface Datasheet

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ADS112C04
SBAS894 – APRIL 2018
ADS112C04 16-Bit, 4-Channel, 2-kSPS, Delta-Sigma ADC With I2C Interface
1 Features
3 Description
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The ADS112C04 is a precision, 16-bit, analog-todigital converter (ADC) that offers many integrated
features to reduce system cost and component count
in applications measuring small sensor signals. The
device features two differential or four single-ended
inputs through a flexible input multiplexer (MUX), a
low-noise, programmable gain amplifier (PGA), two
programmable excitation current sources, a voltage
reference, an oscillator, and a precision temperature
sensor.
1
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•
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•
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Current Consumption as Low as 315 µA (typ)
Wide Supply Range: 2.3 V to 5.5 V
Programmable Gain: 1 to 128
Programmable Data Rates: Up to 2 kSPS
16-Bit, Noise-Free Resolution at 20 SPS
Simultaneous 50-Hz and 60-Hz Rejection at
20 SPS With Single-Cycle Settling Digital Filter
Two Differential or Four Single-Ended Inputs
Dual-Matched Programmable Current Sources:
10 µA to 1.5 mA
Internal 2.048-V Reference: 5 ppm/°C (typ) Drift
Internal 2% Accurate Oscillator
Internal Temperature Sensor:
0.5°C (typ) Accuracy
I2C-Compatible Interface
Supported I2C Bus Speed Modes:
Standard-Mode, Fast-Mode, Fast-Mode Plus
16 Pin-Configurable I2C Addresses
Package: 3.0-mm × 3.0-mm × 0.75-mm WQFN
The device can perform conversions at data rates up
to 2000 samples-per-second (SPS) with single-cycle
settling. At 20 SPS, the digital filter offers
simultaneous 50-Hz and 60-Hz rejection for noisy
industrial applications. The internal PGA offers gains
up to 128. This PGA makes the ADS112C04 ideally
suited for applications measuring small sensor
signals, such as resistance temperature detectors
(RTDs), thermocouples, thermistors, and resistive
bridge sensors.
The ADS112C04 features a 2-wire, I2C-compatible
interface that supports I2C bus speeds up to 1 Mbps.
Two address pins allow selection of 16 different I2C
addresses for the device.
2 Applications
•
•
•
•
•
The ADS112C04 is offered in a leadless 16-pin
WQFN or a 16-pin TSSOP package and is specified
over a temperature range of –40°C to +125°C.
Field Transmitters:
Temperature, Pressure, Strain, Flow
PLC and DCS Analog Input Modules
Temperature Controllers
Heat Meters
Patient Monitoring Systems:
Body Temperature, Blood Pressure
Device Information(1)
PART NUMBER
ADS112C04
PACKAGE
BODY SIZE (NOM)
WQFN (16)
3.00 mm × 3.00 mm
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
K-Type Thermocouple Measurement
3.3 V
3.3 V
0.1 F
3.3 V
0.1 F
REFP
10 A to
1.5 mA
Isothermal Block
REFN
DVDD
AVDD
2.048-V
Reference
AIN0
Reference
Mux
ADS112C04
SCL
AIN1
SDA
Thermocouple
PGA
MUX
3.3 V
16-Bit
û ADC
Digital Filter
and
I2C Interface
AIN2
A0
A1
DRDY
VDD
RESET
LM94022
GS1
AIN3
Precision
Temperature
Sensor
OUT
GS0
GND
AVSS
Low Drift
Oscillator
DGND
Cold-Junction
Compensation
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
ADS112C04
SBAS894 – APRIL 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
8.5 Programming........................................................... 35
8.6 Register Map........................................................... 41
1
1
1
2
3
4
9
9.1 Application Information............................................ 46
9.2 Typical Applications ................................................ 51
10 Power Supply Recommendations ..................... 61
10.1 Power-Supply Sequencing.................................... 61
10.2 Power-Supply Decoupling..................................... 61
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
I2C Timing Requirements.......................................... 8
I2C Switching Characteristics.................................... 9
Typical Characteristics ............................................ 11
7
Parameter Measurement Information ................ 18
8
Detailed Description ............................................ 21
11 Layout................................................................... 62
11.1 Layout Guidelines ................................................. 62
11.2 Layout Example .................................................... 63
12 Device and Documentation Support ................. 64
12.1
12.2
12.3
12.4
12.5
12.6
12.7
7.1 Noise Performance ................................................. 18
8.1
8.2
8.3
8.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Application and Implementation ........................ 46
21
21
22
32
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
64
64
64
64
64
64
64
13 Mechanical, Packaging, and Orderable
Information ........................................................... 64
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
April 2018
*
Initial release.
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5 Pin Configuration and Functions
4
AIN2
SDA
A0
SCL
14
A0
1
16
SCL
A1
2
15
SDA
RESET
3
14
DRDY
DGND
4
13
DVDD
AVSS
5
12
AVDD
AIN3
6
11
AIN0
AIN2
7
10
AIN1
REFN
8
9
REFP
13
12
DRDY
11
DVDD
10
AVDD
9
AIN0
8
AIN3
Pad
AIN1
3
7
AVSS
PW Package
16-Pin TSSOP
Top View
Thermal
REFP
2
6
DGND
REFN
1
5
RESET
15
16
A1
RTE Package
16-Pin WQFN
Top View
Not to scale
Not to scale
Pin Functions
PIN
NO.
NAME
RTE
PW
ANALOG OR DIGITAL
INPUT/OUTPUT
DESCRIPTION (1)
Digital input
I C slave address select pin 0. See the I2C Address section for details.
2
Digital input
I2C slave address select pin 1. See the I2C Address section for details.
11
Analog input
Analog input 0
10
Analog input
Analog input 1
7
Analog input
Analog input 2
4
6
Analog input
Analog input 3
AVDD
10
12
Analog supply
Positive analog power supply. Connect a 100-nF (or larger) capacitor to AVSS.
AVSS
3
5
Analog supply
Negative analog power supply
DGND
2
4
Digital supply
Digital ground
DRDY
12
14
Digital output
Data ready, active low. Connect to DVDD using a pullup resistor.
DVDD
11
13
Digital supply
Positive digital power supply. Connect a 100-nF (or larger) capacitor to DGND.
REFN
6
8
Analog input
Negative reference input
REFP
7
9
Analog input
Positive reference input
RESET
1
3
Digital input
Reset, active low
SCL
14
16
Digital input
Serial clock input. Connect to DVDD using a pullup resistor.
SDA
13
15
Digital input/output
Pad
—
—
A0
15
A1
16
AIN0
9
AIN1
8
AIN2
5
AIN3
Thermal pad
(1)
1
2
Serial data input and output. Connect to DVDD using a pullup resistor.
Thermal power pad. Connect to AVSS.
See the Unused Inputs and Outputs section for details on how to connect unused pins.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
Power-supply voltage
MIN
MAX
AVDD to AVSS
–0.3
7
DVDD to DGND
–0.3
7
AVSS to DGND
–2.8
0.3
UNIT
V
Analog input voltage
AIN0, AIN1, AIN2, AIN3, REFP, REFN
AVSS – 0.3
AVDD + 0.3
Digital input voltage
SCL, SDA, A0, A1, DRDY, RESET
DGND – 0.3
7
V
Input current
Continuous, any pin except power-supply pins
–10
10
mA
Temperature
(1)
Junction, TJ
V
150
Storage, Tstg
–60
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±750
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
POWER SUPPLY
Unipolar analog power supply
Bipolar analog power supply
Digital power supply
AVDD to AVSS
2.3
AVSS to DGND
–0.1
5.5
0
0.1
V
AVDD to DGND
2.3
2.5
2.75
AVSS to DGND
–2.75
–2.5
–2.3
DVDD to DGND
2.3
5.5
PGA disabled, gain = 1 to 4
AVSS – 0.1
AVDD + 0.1
PGA enabled, gain = 1 to 4
AVSS + 0.2
AVDD – 0.2
AVSS + 0.2 +
|VINMAX|·(Gain – 4) / 8
AVDD – 0.2 –
|VINMAX|·(Gain – 4) / 8
–VREF / Gain
VREF / Gain
V
V
V
ANALOG INPUTS (1)
V(AINx)
Absolute input voltage (2)
PGA enabled, gain = 8 to 128
VIN
Differential input voltage
VIN = VAINP – VAINN (3)
V
VOLTAGE REFERENCE INPUTS
VREF
Differential reference input voltage
V(REFN)
Absolute negative reference voltage
V(REFP)
Absolute positive reference voltage
VREF = V(REFP) – V(REFN)
AVDD – AVSS
V
AVSS – 0.1
0.75
2.5
V(REFP) – 0.75
V
V(REFN) + 0.75
AVDD + 0.1
V
SCL, SDA, A0, A1, DRDY,
2.3 V ≤ DVDD < 3.0 V
DGND
DVDD + 0.5
SCL, SDA, A0, A1, DRDY,
3.0 V ≤ DVDD ≤ 5.5 V
DGND
5.5
RESET
DGND
DVDD
–40
125
DIGITAL INPUTS
Input voltage
V
TEMPERATURE RANGE
TA
(1)
(2)
(3)
4
Operating ambient temperature
°C
AINP and AINN denote the positive and negative inputs of the PGA. AINx denotes one of the four available analog inputs.
PGA disabled means the low-noise PGA is powered down and bypassed. Gains of 1, 2, and 4 are still possible in this case.
See the Low-Noise Programmable Gain Stage section for more information.
VINMAX denotes the maximum differential input voltage, VIN, that is expected in the application. |VINMAX| can be smaller than VREF / Gain.
Excluding the effects of offset and gain error.
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6.4 Thermal Information
ADS112C04
THERMAL METRIC (1)
WQFN (RTE)
TSSOP (PW)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
57.7
90.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
29.0
31.7
°C/W
RθJB
Junction-to-board thermal resistance
19.9
41.8
°C/W
ψJT
Junction-to-top characterization parameter
0.3
1.8
°C/W
ψJB
Junction-to-board characterization parameter
19.8
41.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
11.8
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.3 V to 5.5 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, all data rates, and internal
reference enabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS
PGA disabled, gain = 1 to 4, normal mode, VIN = 0 V
Absolute input current
Absolute input current drift
Differential input current
Differential input current drift
±5
PGA disabled, gain = 1 to 4, turbo mode, VIN = 0 V
±10
Gain = 1 to 128, VIN = 0 V
±1
PGA disabled, gain = 1 to 4, VIN = 0 V
10
Gain = 1 to 128, VIN = 0 V
nA
pA/°C
5
PGA disabled, gain = 1 to 4, normal mode,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
±5
PGA disabled, gain = 1 to 4, turbo mode,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
±10
Gain = 1 to 128,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
±1
PGA disabled, gain = 1 to 4,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
10
Gain = 1 to 128,
VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain
2
nA
pA/°C
SYSTEM PERFORMANCE
Resolution (no missing codes)
DR
Data rate
Noise (input-referred)
INL
Integral nonlinearity
VIO
Input offset voltage
16
Normal mode
Turbo mode
(1)
Normal mode, gain = 128, DR = 20 SPS
AVDD = 3.3 V, gain = 1 to 128, VCM = AVDD / 2,
external VREF, normal mode, best fit
490
–15
Gain = 1, differential inputs, TA = 25°C
PGA disabled, gain = 1 to 4
150
µV
µV/°C
0.6
±0.01%
–0.05%
±0.01%
0.05%
–0.1%
±0.015%
0.1%
PGA disabled, gain = 1 to 4
0.5
Gain = 1 to 32
0.5
2
1
4
Gain = 64 to 128
(1)
(2)
±5
0.1
Gain = 64 to 128, TA = 25°C
ppmFSR
0.02
Gain = 1 to 128
Gain = 1 to 32, TA = 25°C
15
±4
PGA disabled, gain = 1 to 4
Gain drift vs temperature (2)
±6
nVRMS
±4
–150
Gain = 2 to 128, differential inputs
Gain error (2)
SPS
40, 90, 180, 350, 660, 1200, 2000
PGA disabled, gain = 1 to 4, differential inputs
Offset drift vs temperature
Bits
20, 45, 90, 175, 330, 600, 1000
ppm/°C
See the Noise Performance section for more information.
Excluding error of voltage reference.
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Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.3 V to 5.5 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, all data rates, and internal
reference enabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
50 Hz ±1 Hz, DR = 20 SPS
78
88
60 Hz ±1 Hz, DR = 20 SPS
80
88
MAX
UNIT
SYSTEM PERFORMANCE (continued)
NMRR
Normal-mode rejection ratio
CMRR
Common-mode rejection ratio
At dc, gain = 1, AVDD = 3.3 V
PSRR
Power-supply rejection ratio
dB
90
105
fCM = 50 Hz or 60 Hz, DR = 20 SPS, AVDD = 3.3 V
105
115
fCM = 50 Hz or 60 Hz, DR = 2 kSPS, AVDD = 3.3 V
95
110
AVDD at dc, VCM = AVDD / 2
85
105
DVDD at dc, VCM = AVDD / 2
95
115
–0.15%
±0.01%
0.15%
5
30
dB
dB
INTERNAL VOLTAGE REFERENCE
VREF
Reference voltage
Accuracy
2.048
TA = 25°C
Temperature drift
Long-term drift
V
ppm/°C
1000 hours
110
ppm
REFP = VREF, REFN = AVSS, AVDD = 3.3 V
±10
nA
VOLTAGE REFERENCE INPUTS
Reference input current
INTERNAL OSCILLATOR
fCLK
Frequency
Accuracy
Normal mode
1.024
Turbo mode
2.048
MHz
Normal mode
–2%
±1%
2%
Turbo mode
–4%
±2%
4%
EXCITATION CURRENT SOURCES (IDACs) (AVDD = 3.3 V to 5.5 V)
Current settings
10, 50, 100, 250, 500, 1000, 1500
Compliance voltage
All IDAC settings
Accuracy (each IDAC)
IDAC = 50 µA to 1.5 mA
Current matching between
IDACs
IDAC = 50 µA to 1.5 mA, TA = 25°C
–6%
Temperature drift (each IDAC) IDAC = 50 µA to 1.5 mA
Temperature drift matching
between IDACs
µA
AVDD – 0.9
±1%
6%
0.3%
2%
50
IDAC = 50 µA to 1.5 mA
8
V
ppm/°C
40
ppm/°C
BURN-OUT CURRENT SOURCES (BOCS)
Magnitude
Sink and source
10
Accuracy
µA
±5%
TEMPERATURE SENSOR
Conversion resolution
14
Temperature resolution
Accuracy
TA = 0°C to +85°C
TA = –40°C to +125°C
Accuracy vs analog supply
voltage
6
Bits
0.03125
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°C
–1
±0.25
1
–1.5
±0.5
1.5
0.0625
0.25
°C
°C/V
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Electrical Characteristics (continued)
minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;
all specifications are at AVDD = 2.3 V to 5.5 V, AVSS = 0 V, DVDD = 3.3 V, PGA enabled, all data rates, and internal
reference enabled (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS/OUTPUTS
VIL
Logic input level, low
DGND
0.3 DVDD
2.3 V ≤ DVDD < 3.0 V,
SCL, SDA, A0, A1, DRDY
0.7 DVDD
DVDD + 0.5
3.0 V ≤ DVDD ≤ 5.5 V,
SCL, SDA, A0, A1, DRDY
0.7 DVDD
5.5
RESET
0.7 DVDD
DVDD
VIH
Logic input level, high
Vhys
Hysteresis of Schmitt-trigger
inputs
Fast-mode, fast-mode plus
VOL
Logic output level, low
IOL = 3 mA
DGND
VOL = 0.4 V, standard-mode, fast-mode
IOL
Low-level output current
0.05 DVDD
VOL = 0.4 V, fast-mode plus
VOL = 0.6 V, fast-mode
Ii
Input current
DGND + 0.1 V < VDigital Input < DVDD – 0.1 V
Ci
Capacitance
Each pin
V
V
V
0.15
0.4
V
3
20
mA
6
–10
10
µA
10
pF
ANALOG SUPPLY CURRENT (AVDD = 3.3 V, VIN = 0 V, IDACs Turned Off)
IAVDD
Analog supply current
Power-down mode
0.1
Normal mode, PGA disabled, gain = 1 to 4
250
Normal mode, gain = 1 to 16
360
Normal mode, gain = 32
455
Normal mode, gain = 64, 128
550
Turbo mode, PGA disabled, gain = 1 to 4
370
Turbo mode, gain = 1 to 16
580
Turbo mode, gain = 32
765
Turbo mode, gain = 64, 128
955
3
510
µA
ADDITIONAL ANALOG SUPPLY CURRENTS PER FUNCTION (AVDD = 3.3 V)
IAVDD
Analog supply current
External reference selected
IDAC overhead (excludes the actual IDAC current)
60
µA
195
DIGITAL SUPPLY CURRENT (DVDD = 3.3 V, All Data Rates, I2C Not Active)
IDVDD
Digital supply current
Power-down mode
0.3
5
Normal mode
65
100
Turbo mode
µA
100
POWER DISSIPATION (AVDD = DVDD = 3.3 V, All Data Rates, VIN = 0 V, I2C Not Active)
PD
Power dissipation
Normal mode, gain = 1 to 16
1.4
Turbo mode, gain = 1 to 16
2.2
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6.6 I2C Timing Requirements
over operating ambient temperature range and DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullup
resistor = 1 kΩ (unless otherwise noted)
MIN
MAX
UNIT
100
kHz
STANDARD-MODE
fSCL
SCL clock frequency
0
tHD;STA
Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.
4
µs
tLOW
Pulse duration, SCL low
4.7
µs
tHIGH
Pulse duration, SCL high
4.0
µs
tSU;STA
Setup time, repeated START condition
4.7
µs
tHD;DAT
Hold time, data
0
µs
tSU;DAT
Setup time, data
tr
Rise time, SCL, SDA
1000
ns
tf
Fall time, SCL, SDA
250
ns
tSU;STO
Setup time, STOP condition
4.0
tBUF
Bus free time, between STOP and START condition
4.7
tVD;DAT
Valid time, data
3.45
µs
tVD;ACK
Valid time, acknowledge
3.45
µs
400
kHz
250
ns
µs
µs
FAST-MODE
fSCL
SCL clock frequency
tHD;STA
Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.
0
0.6
µs
tLOW
Pulse duration, SCL low
1.3
µs
tHIGH
Pulse duration, SCL high
0.6
µs
tSU;STA
Setup time, repeated START condition
0.6
µs
tHD;DAT
Hold time, data
0
µs
tSU;DAT
Setup time, data
tr
Rise time, SCL, SDA
tf
Fall time, SCL, SDA
tSU;STO
Setup time, STOP condition
0.6
tBUF
Bus free time, between STOP and START condition
1.3
tVD;DAT
Valid time, data
0.9
µs
tVD;ACK
Valid time, acknowledge
0.9
µs
tSP
Pulse width of spikes that must be suppressed by the input filter
0
50
ns
0
1000
100
ns
20
300
ns
20 · (DVDD / 5.5 V)
250
ns
µs
µs
FAST-MODE PLUS
fSCL
SCL clock frequency
tHD;STA
Hold time, (repeated) START condition.
After this period, the first clock pulse is generated.
tLOW
tHIGH
kHz
0.26
µs
Pulse duration, SCL low
0.5
µs
Pulse duration, SCL high
0.26
µs
tSU;STA
Setup time, repeated START condition
0.26
µs
tHD;DAT
Hold time, data
0
µs
tSU;DAT
Setup time, data
50
tr
Rise time, SCL, SDA
tf
Fall time, SCL, SDA
tSU;STO
Setup time, STOP condition
tBUF
Bus free time, between STOP and START condition
tVD;DAT
Valid time, data
0.45
µs
tVD;ACK
Valid time, acknowledge
0.45
µs
tSP
Pulse duration of spikes that must be suppressed by the input filter
50
ns
8
Pullup resistor = 350 Ω
20 · (DVDD / 5.5 V)
ns
120
ns
120
ns
0.26
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0.5
0
µs
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I2C Timing Requirements (continued)
over operating ambient temperature range and DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullup
resistor = 1 kΩ (unless otherwise noted)
MIN
MAX
UNIT
RESET PIN
tw(RSL)
Pulse duration, RESET low
250
ns
td(RSSTA)
Delay time, START condition after RESET rising edge (1)
100
ns
0
ns
DRDY PIN
td(DRSTA)
Delay time, START condition after DRDY falling edge
TIMEOUT
Timeout (2)
(1)
(2)
Normal mode
14000
Turbo mode
28000
tMOD
No delay time is required when using the RESET command as long as all I2C timing requirements for the (repeated) START and STOP
conditions are met.
See the Timeout section for more information.
tMOD = 1 / fMOD. Modulator frequency fMOD = 256 kHz (normal mode) and 512 kHz (turbo mode).
6.7 I2C Switching Characteristics
over operating ambient temperature range, DVDD = 2.3 V to 5.5 V, bus capacitance = 10 pF to 400 pF, and pullup resistor =
1 kΩ (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tw(DRH)
Pulse duration, DRDY high (1)
tp(RDDR)
Propagation delay time, RDATA command latched to
DRDY rising edge
(1)
MIN
TYP
MAX
2
UNIT
tMOD
2
tMOD
tMOD = 1 / fMOD. Modulator frequency fMOD = 256 kHz (normal mode) and 512 kHz (turbo mode).
tf
SDA
tSU;DAT
tr
70%
30%
...
cont.
tHD;DAT
tf
tVD;DAT
tHIGH
tr
70%
30%
70%
30%
SCL
tLOW
tHD;STA
S
...
cont.
9th clock
1 / fSCL
1st clock cycle
tBUF
SDA
tSU;STA
tHD;STA
tVD;ACK
tSP
tSU;STO
70%
30%
SCL
Sr
9th clock
P
S
Figure 1. I2C Timing Requirements
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tw(RSL)
RESET
ttd(RSSTA)t
SDA
ADDRESS
SCL
S
START
Condition
Figure 2. RESET Pin Timing Requirements
tw(DRH)
DRDY
td(DRSTA)
SDA
ttp(RDDR)t
ADDRESS
W
ACK
RDATA
Command
ACK
SCL
S
P
START
Condition
STOP
Condition
Figure 3. DRDY Pin Timing Requirements and Switching Characteristics
10
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6.8 Typical Characteristics
15
15
10
10
Absolute Input Current (nA)
Absolute Input Current (nA)
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
5
0
-5
-10
-40qC
25qC
85qC
5
0
-5
-10
-40qC
125qC
0
0.5
1
1.5
2
V(AINx) (V)
2.5
3
0
3.5
Normal mode, PGA disabled, VIN = 0 V
125qC
15
10
10
5
0
-5
-10
-40qC
25qC
0.5
1
1.5
2
V(AINx) (V)
2.5
3
3.5
Figure 5. Absolute Input Current vs Absolute Input Voltage
15
Absolute Input Current (nA)
Absolute Input Current (nA)
85qC
Normal mode, PGA enabled, VIN = 0 V
Figure 4. Absolute Input current vs Absolute Input Voltage
85qC
5
0
-5
-10
125qC
-40qC
-15
25qC
85qC
125qC
-15
0
0.5
1
1.5
2
V(AINx) (V)
2.5
3
3.5
0
Turbo mode, PGA disabled, VIN = 0 V
1
1.5
2
V(AINx) (V)
2.5
3
3.5
Figure 7. Absolute Input Current vs Absolute Input Voltage
20
15
15
Differential Input Current (nA)
20
10
5
0
-5
-10
-15
10
5
0
-5
-10
-15
-40qC
-20
-2.5
0.5
Turbo mode, PGA enabled, VIN = 0 V
Figure 6. Absolute Input Current vs Absolute Input Voltage
Differential Input Current (nA)
25qC
-15
-15
-2
-1.5
-1
-0.5
25qC
0
0.5
VIN (V)
85qC
1
125qC
1.5
Normal mode, PGA disabled, VCM = 1.65 V
2
2.5
-40qC
-20
-2.5
-2
-1.5
-1
-0.5
25qC
0
0.5
VIN (V)
85qC
1
125qC
1.5
2
2.5
Normal mode, PGA enabled, VCM = 1.65 V
Figure 8. Differential Input Current vs
Differential Input Voltage
Figure 9. Differential Input Current vs
Differential Input Voltage
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Typical Characteristics (continued)
20
20
15
15
Differential Input Current (nA)
Differential Input Current (nA)
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
10
5
0
-5
-10
-15
10
5
0
-5
-10
-15
-40qC
-20
-2.5
-2
-1.5
-1
25qC
-0.5
85qC
0
0.5
VIN (V)
1
125qC
1.5
2
-40qC
-20
-2.5
2.5
Turbo mode, PGA disabled, VCM = 1.65 V
-2
0
0.5
VIN (V)
1
1.5
2
2.5
60
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Gain = 32
Gain = 64
Gain = 128
5
0
-5
Gain = 1
Gain = 2
Gain = 4
40
INL (ppm of FSR)
10
INL (ppm of FSR)
-0.5
125qC
Figure 11. Differential Input Current vs
Differential Input Voltage
15
-10
Gain = 8
Gain = 16
Gain = 32
Gain =64
Gain = 128
20
0
-20
-40
-15
-100 -80
-60
-40
-20
0
20
VIN (% of FS)
40
60
80
-60
-100 -80
100
PGA enabled, external reference, best fit
Figure 12. INL vs Differential Input Voltage
-40
-20
0
20
VIN (% of FS)
40
60
80
100
Figure 13. INL vs Differential Input Voltage
10
250
Gain = 1
Gain = 2
Gain = 4
Offset Voltage (PV)
8
200
150
100
6
4
2
100
75
50
25
0
-25
-50
-75
-100
50
0
-60
PGA enabled, internal reference, best fit
300
Number of Occurrences
-1
85qC
Turbo mode, PGA enabled, VCM = 1.65 V
Figure 10. Differential Input Current vs
Differential Input Voltage
0
-50
-25
Offset Voltage ( V)
PGA enabled, gain = 1, 620 samples
Figure 14. Offset Voltage Histogram
12
-1.5
25qC
0
25
50
Temperature (qC)
75
100
125
PGA disabled
Figure 15. Input Offset Voltage vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
20
300
Gain = 1
Gain = 128
250
Number of Occurrences
Offset Voltage (PV)
16
12
8
200
150
100
4
0.04
0.05
0.05
PGA enabled
0.04
0
125
0.03
100
0.02
75
0.01
25
50
Temperature (qC)
0
0
-0.01
-25
-0.03
0
-50
-0.02
50
Gain Error (%)
PGA disabled, gain = 1, 620 samples
Figure 17. Gain Error Histogram
250
250
Gain Error (%)
PGA enabled, gain = 128, 620 samples
Figure 19. Gain Error Histogram
0
-0.005
-0.005
-0.01
-0.01
Gain error (%)
Gain error (%)
Figure 18. Gain Error Histogram
0
-0.015
-0.02
-0.03
-50
Gain = 1
Gain = 2
Gain = 4
-25
-0.015
-0.02
-0.025
0
25
50
Temperature (qC)
0.03
Gain Error (%)
PGA enabled, gain = 1, 620 samples
-0.025
0.02
0.05
0.04
0.03
0.02
0.01
0
0
0
-0.01
50
-0.02
50
0.01
100
0
100
150
-0.01
150
200
-0.02
200
-0.03
Number of Occurrences
300
-0.03
Number of Occurrences
Figure 16. Input Offset Voltage vs Temperature
300
75
100
125
-0.03
-50
PGA disabled
Gain = 1
Gain = 2
Gain = 4
Gain = 8
-25
Gain = 16
Gain = 32
Gain = 64
Gain = 128
0
25
50
Temperature (qC)
75
100
125
PGA enabled
Figure 20. Gain Error vs Temperature
Figure 21. Gain Error vs Temperature
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Typical Characteristics (continued)
125
125
120
120
CMRR (dB)
CMRR (dB)
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
115
110
105
115
110
105
DR = 20 SPS
100
-50
-25
0
DR = 2000 SPS
25
50
Temperature (qC)
75
100
100
-50
125
Gain = 1, DR = 20 SPS
Gain = 1, DR = 2000 SPS
Gain = 128, DR = 20 SPS
Gain = 128, DR = 2000 SPS
-25
0
PGA disabled
75
100
125
PGA enabled
Figure 22. DC CMRR vs Temperature
Figure 23. DC CMRR vs Temperature
2000
2.051
1000
2.049
2.048
2.047
2.046
2.045
-50
2.0486
2.0484
2.0482
2.048
2.0478
2.0476
2.047
0
2.0474
500
AVDD = 3.3 V
AVDD = 5.0V
2.05
Internal Reference Voltage (V)
1500
2.0472
Number of Occurrences
25
50
Temperature (qC)
-25
0
25
50
Temperature (qC)
75
100
125
Internal Reference Voltage (V)
5940 samples
Figure 25. Internal Reference Voltage vs Temperature
Figure 24. Internal Reference Voltage Histogram
0
VREF = 1 V
VREF = 1.5 V
Reference Input Current (nA)
Internal Reference Voltage (V)
2.0486
2.0484
2.0482
2.048
2.0478
2
2.5
3
3.5
4
AVDD (V)
4.5
5
Figure 26. Internal Reference Voltage vs AVDD
14
5.5
VREF = 2 V
VREF = 2.5 V
-5
-10
-15
-20
-50
-25
0
25
50
Temperature (qC)
75
100
125
Figure 27. External Reference Input Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
300
Internal Oscillator Frequency (MHz)
1.026
Number of Occurrences
250
200
150
100
1.024
1.023
1.022
1.021
1.02
-50
1.032
1.03
1.028
1.026
1.024
1.022
1.02
1.016
0
1.018
50
1.025
-25
0
Internal Oscillator Frequency (MHz)
25
50
Temperature (qC)
75
100
125
Normal mode
Normal mode
Figure 29. Internal Oscillator Frequency vs Temperature
6
1.025
4
1.024
2
IDAC = 1000 µA
IDAC = 500 µA
IDAC = 100 µA
IDAC Error (%)
Internal Oscillator Frequency (MHz)
Figure 28. Internal Oscillator Frequency Histogram
1.026
1.023
1.022
0
±2
±4
1.021
±6
1.02
2
2.5
3
3.5
4
DVDD (V)
4.5
5
0.5
5.5
0.6
0.7
0.8
0.9
Compliance Voltage (V)
1.0
C006
Normal mode
Figure 31. IDAC Accuracy vs Compliance Voltage
Figure 30. Internal Oscillator Frequency vs DVDD
1
6
IDAC Matching Error (%)
Absolute IDAC Error (%)
2
0
-2
-4
-6
-50
IDAC = 1000 PA
IDAC = 500 PA
IDAC = 100 PA
0.75
4
0.5
0.25
0
-0.25
-0.5
-0.75
-25
0
25
50
Temperature (qC)
75
100
Figure 32. IDAC Accuracy vs Temperature
125
-1
-50
-25
0
25
50
Temperature (qC)
75
100
125
Figure 33. IDAC Matching vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
1.25
Digital Pin Output Voltage (V)
Temperature Error (qC)
1
0.5
Mean
Mean + 6V
Mean - 6V
0.75
0.5
0.25
0
-0.25
40°C
25°C
125°C
0.4
0.3
0.2
0.1
-0.5
-0.75
-50
0
-25
0
25
50
Temperature (qC)
75
100
125
0
2
4
6
8
10
12
14
Sinking Current (mA)
16
18
20
DVDD = 3.3 V
Figure 34. Internal Temperature Sensor Accuracy vs
Temperature
Figure 35. Digital Pin Output Voltage vs Sinking Current
1
700
600
AVDD Current (PA)
AVDD Current (PA)
0.8
0.6
0.4
500
400
300
200
0.2
100
0
-50
-25
0
25
50
Temperature (qC)
75
100
PGA disabled
Gain = 1
0
-50
125
-25
0
Power-down mode
25
50
Temperature (qC)
Gain = 32
Gain = 128
75
100
125
Normal mode
Figure 36. Analog Supply Current vs Temperature
Figure 37. Analog Supply Current vs Temperature
700
2
500
DVDD Current (PA)
AVDD Current (PA)
600
400
300
200
1.5
1
0.5
100
PGA disabled
Gain = 1
Gain = 32
Gain = 128
0
2
2.5
3
3.5
4
AVDD (V)
4.5
5
5.5
0
-50
Normal mode
0
25
50
Temperature (qC)
75
100
125
Power-down mode
Figure 38. Analog Supply Current vs AVDD
16
-25
Figure 39. Digital Supply Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, AVDD = 3.3 V, and AVSS = 0 V using internal VREF = 2.048 V (unless otherwise noted)
100
90
90
DVDD Current (PA)
DVDD Current (PA)
85
80
75
70
80
70
60
65
60
-50
50
-25
0
25
50
Temperature (qC)
75
100
125
2
2.5
Normal mode
3
3.5
4
DVDD (V)
4.5
5
5.5
Normal mode
Figure 40. Digital Supply Current vs Temperature
Figure 41. Digital Supply Current vs DVDD
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7 Parameter Measurement Information
7.1 Noise Performance
Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) are based on the principle of oversampling. The input
signal of a ΔΣ ADC is sampled at a high frequency (modulator frequency) and subsequently filtered and
decimated in the digital domain to yield a conversion result at the respective output data rate. The ratio between
modulator frequency and output data rate is called oversampling ratio (OSR). By increasing the OSR, and thus
reducing the output data rate, the noise performance of the ADC can be optimized. In other words, the inputreferred noise drops when reducing the output data rate because more samples of the internal modulator are
averaged to yield one conversion result. Increasing the gain also reduces the input-referred noise, which is
particularly useful when measuring low-level signals.
Table 1 to Table 8 summarize the device noise performance. Data are representative of typical noise
performance at TA = 25°C using the internal 2.048-V reference. Data shown are the result of averaging readings
from a single device over a time period of approximately 0.75 seconds and are measured with the inputs
internally shorted together. Table 1, Table 3, Table 5, and Table 7 list the input-referred noise in units of μVRMS
for the conditions shown. Values in µVPP are shown in parenthesis. Table 2, Table 4, Table 6, and Table 8 list
the corresponding data in effective resolution calculated from μVRMS values using Equation 1. Noise-free
resolution calculated from peak-to-peak noise values using Equation 2 are shown in parenthesis.
The input-referred noise (Table 1, Table 3, Table 5, and Table 7) only changes marginally when using an
external low-noise reference, such as the REF5020. Use Equation 1 and Equation 2 to calculate effective
resolution numbers and noise-free resolution when using a reference voltage other than 2.048 V:
Effective Resolution = ln [2 · VREF / (Gain · VRMS-Noise)] / ln(2)
Noise-Free Resolution = ln [2 · VREF / (Gain · VPP-Noise)] / ln(2)
(1)
(2)
Table 1. Noise in μVRMS (μVPP)
at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, PGA Enabled, and Internal VREF = 2.048 V
DATA
RATE
(SPS)
GAIN (PGA Enabled)
1
2
4
8
16
32
64
128
20
62.50 (62.50)
31.25 (31.25)
15.63 (15.63)
7.81 (7.81)
3.91 (3.91)
1.95 (1.95)
0.98 (0.98)
0.49 (0.49)
45
62.50 (62.50)
31.25 (31.25)
15.63 (15.63)
7.81 (7.81)
3.91 (3.91)
1.95 (1.95)
0.98 (0.98)
0.49 (0.57)
90
62.50 (62.50)
31.25 (31.25)
15.63 (15.63)
7.81 (7.81)
3.91 (3.91)
1.95 (2.06)
0.98 (1.20)
0.49 (0.91)
175
62.50 (63.79)
31.25 (37.30)
15.63 (17.00)
7.81 (9.81)
3.91 (5.27)
1.95 (3.32)
0.98 (1.93)
0.49 (1.49)
330
62.50 (107.88)
31.25 (48.95)
15.63 (28.25)
7.81 (14.47)
3.91 (8.06)
1.95 (4.64)
0.98 (2.93)
0.49 (1.91)
600
62.50 (153.77)
31.25 (76.01)
15.63 (38.94)
7.81 (22.30)
3.91 (12.07)
1.95 (6.69)
0.98 (4.49)
0.51 (3.14)
1000
62.50 (228.90)
31.25 (108.90)
15.63 (58.24)
7.81 (31.55)
3.91 (17.41)
1.95 (10.23)
1.04 (6.21)
0.73 (4.69)
Table 2. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, PGA Enabled, and Internal VREF = 2.048 V
18
DATA
RATE
(SPS)
GAIN (PGA Enabled)
1
2
4
8
16
32
64
128
20
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
45
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (15.78)
90
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (15.92)
16 (15.70)
16 (15.10)
175
16 (15.97)
16 (15.74)
16 (15.88)
16 (15.48)
16 (15.57)
16 (15.23)
16 (15.02)
16 (14.39)
330
16 (15.21)
16 (15.35)
16 (15.12)
16 (15.15)
16 (14.96)
16 (14.75)
16 (14.41)
16 (14.03)
600
16 (14.70)
16 (14.72)
16 (14.68)
16 (14.70)
16 (14.37)
16 (14.22)
16 (13.80)
15.83 (13.32)
1000
16 (14.13)
16 (14.20)
16 (14.10)
16 (13.99)
16 (13.99)
16 (13.61)
15.91 (13.33)
15.49 (12.74)
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Table 3. Noise in μVRMS (μVPP)
at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, PGA Disabled, and Internal VREF = 2.048 V
GAIN (PGA Disabled)
DATA RATE
(SPS)
1
2
4
20
62.50 (62.50)
31.25 (31.25)
15.63 (15.63)
45
62.50 (62.50)
31.25 (31.25)
15.63 (15.63)
90
62.50 (62.50)
31.25 (31.25)
15.63 (15.63)
175
62.50 (65.71)
31.25 (35.00)
15.63 (16.83)
330
62.50 (106.06)
31.25 (52.59)
15.63 (26.30)
600
62.50 (150.81)
31.25 (79.15)
15.63 (36.87)
1000
62.50 (221.61)
31.25 (111.61)
15.63 (55.07)
Table 4. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V, AVSS = 0 V, Normal Mode, PGA Disabled, and Internal VREF = 2.048 V
GAIN (PGA Disabled)
DATA RATE
(SPS)
1
2
4
20
16 (16)
16 (16)
16 (16)
45
16 (16)
16 (16)
16 (16)
90
16 (16)
16 (16)
16 (16)
175
16 (15.93)
16 (15.84)
16 (15.89)
330
16 (15.24)
16 (15.25)
16 (15.25)
600
16 (14.73)
16 (14.66)
16 (14.76)
1000
16 (14.17)
16 (14.16)
16 (14.18)
Table 5. Noise in μVRMS (μVPP)
at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, PGA Enabled, and Internal VREF = 2.048 V
DATA
RATE
(SPS)
GAIN (PGA Enabled)
1
2
4
8
16
32
64
128
40
62.50 (62.50)
31.25 (31.25)
15.63 (15.63)
7.81 (7.81)
3.91 (3.91)
1.95 (1.95)
0.98 (0.98)
0.49 (0.51)
90
62.50 (62.50)
31.25 (31.25)
15.63 (15.63)
7.81 (7.81)
3.91 (3.91)
1.95 (1.95)
0.98 (0.98)
0.49 (0.76)
180
62.50 (62.50)
31.25 (31.25)
15.63 (15.63)
7.81 (7.81)
3.91 (4.11)
1.95 (2.49)
0.98 (1.51)
0.49 (1.05)
350
62.50 (71.04)
31.25 (37.00)
15.63 (19.17)
7.81 (10.76)
3.91 (5.91)
1.95 (3.54)
0.98 (2.13)
0.49 (1.64)
660
62.50 (105.64)
31.25 (54.97)
15.63 (27.74)
7.81 (16.98)
3.91 (8.45)
1.95 (5.07)
0.98 (3.32)
0.49 (2.38)
1200
62.50 (153.74)
31.25 (78.75)
15.63 (39.68)
7.81 (23.84)
3.91 (13.19)
1.95 (7.46)
0.98 (5.17)
0.58 (3.50)
2000
62.50 (226.39)
31.25 (112.98)
15.63 (59.37)
7.81 (32.97)
3.91 (18.73)
1.95 (11.12)
1.12 (7.06)
0.83 (5.41)
Table 6. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, PGA Enabled, and Internal VREF = 2.048 V
DATA
RATE
(SPS)
GAIN (PGA Enabled)
1
2
4
8
16
32
64
128
40
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (15.94)
90
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (16)
16 (15.36)
180
16 (16)
16 (16)
16 (16)
16 (16)
16 (15.93)
16 (15.65)
16 (15.37)
16 (14.90)
350
16 (15.82)
16 (15.76)
16 (15.71)
16 (15.55)
16 (15.40)
16 (15.14)
16 (14.87)
16 (14.25)
660
16 (15.24)
16 (15.19)
16 (15.17)
16 (14.88)
16 (14.89)
16 (14.62)
16 (14.23)
16 (13.71)
1200
16 (14.70)
16 (14.67)
16 (14.66)
16 (14.39)
16 (14.24)
16 (14.07)
16 (13.60)
15.75 (13.16)
2000
16 (14.14)
16 (14.15)
16 (14.07)
16 (13.92)
16 (13.74)
16 (13.49)
15.80 (13.15)
15.23 (12.53)
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Table 7. Noise in μVRMS (μVPP)
at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, PGA Disabled, and Internal V REF = 2.048 V
GAIN (PGA Disabled)
DATA RATE
(SPS)
1
2
4
40
62.50 (62.50)
31.25 (31.25)
15.63 (15.63)
90
62.50 (62.50)
31.25 (31.25)
15.63 (15.63)
180
62.50 (62.50)
31.25 (31.25)
15.63 (15.63)
350
62.50 (72.79)
31.25 (33.34)
15.63 (18.31)
660
62.50 (103.97)
31.25 (51.15)
15.63 (24.69)
1200
62.50 (149.07)
31.25 (76.35)
15.63 (37.48)
2000
62.50 (224.19)
31.25 (113.98)
15.63 (56.87)
Table 8. Effective Resolution From RMS Noise (Noise-Free Resolution From Peak-to-Peak Noise)
at AVDD = 3.3 V, AVSS = 0 V, Turbo Mode, PGA Disabled, and Internal V REF = 2.048 V
20
GAIN (PGA Disabled)
DATA RATE
(SPS)
1
2
4
40
16 (16)
16 (16)
16 (16)
90
16 (16)
16 (16)
16 (16)
180
16 (16)
16 (16)
16 (16)
350
16 (15.78)
16 (15.91)
16 (15.77)
660
16 (15.27)
16 (15.29)
16 (15.34)
1200
16 (14.75)
16 (14.71)
16 (14.74)
2000
16 (14.16)
16 (14.13)
16 (14.14)
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8 Detailed Description
8.1 Overview
The ADS112C04 is a small, low-power, 16-bit, ΔΣ ADC that offers many integrated features to reduce system
cost and component count in applications measuring small sensor signals.
In addition to the ΔΣ ADC core and single-cycle settling digital filter, the device offers a low-noise, high input
impedance, programmable gain amplifier (PGA), an internal 2.048-V voltage reference, and a clock oscillator.
The device also integrates a highly linear and accurate temperature sensor as well as two matched
programmable current sources (IDACs) for sensor excitation. All of these features are intended to reduce the
required external circuitry in typical sensor applications and improve overall system performance. The device is
fully configured through four registers and controlled by six commands through an I2C-compatible interface. The
Functional Block Diagram section shows the device functional block diagram.
The ADS112C04 ADC measures a differential signal, VIN, which is the difference in voltage between nodes AINP
and AINN. The converter core consists of a differential, switched-capacitor, ΔΣ modulator followed by a digital
filter. The digital filter receives a high-speed bitstream from the modulator and outputs a code proportional to the
input voltage. This architecture results in a very strong attenuation of any common-mode signal.
The device has two available conversion modes: single-shot conversion and continuous conversion mode. In
single-shot conversion mode, the ADC performs one conversion of the input signal upon request and stores the
value in an internal data buffer. The device then enters a low-power state to save power. Single-shot conversion
mode is intended to provide significant power savings in systems that require only periodic conversions, or when
there are long idle periods between conversions. In continuous conversion mode, the ADC automatically begins
a conversion of the input signal as soon as the previous conversion is completed. New data are available at the
programmed data rate. Data can be read at any time without concern of data corruption and always reflect the
most recently completed conversion.
8.2 Functional Block Diagram
REFP
10 A to
1.5 mA
REFN
AVDD
DVDD
2.048-V
Reference
AIN0
Reference
Mux
ADS112C04
SCL
AIN1
SDA
MUX
PGA
16-bit
û ADC
Digital Filter
and
I2C Interface
AIN2
A0
A1
DRDY
RESET
Precision
Temperature
Sensor
AIN3
Low Drift
Oscillator
AVSS
DGND
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8.3 Feature Description
8.3.1 Multiplexer
Figure 42 shows the flexible input multiplexer of the device. Either four single-ended signals, two differential
signals, or a combination of two single-ended signals and one differential signal can be measured. The
multiplexer is configured by four bits (MUX[3:0]) in the configuration register. When single-ended signals are
measured, the negative ADC input (AINN) is internally connected to AVSS by a switch within the multiplexer. For
system-monitoring purposes, the analog supply [(AVDD – AVSS) / 4] or the currently selected external reference
voltage [(VREFP – VREFN) / 4] can be selected as inputs to the ADC. The multiplexer also offers the possibility to
route any of the two programmable current sources to any analog input (AINx) or to the dedicated reference pins
(REFP, REFN).
System Monitors
(VREFP ± VREFN) / 4
(AVDD ± AVSS) / 4
AVDD
AVDD
IDAC1
AVDD
AVSS
AVDD
AVSS
IDAC2
(AVDD + AVSS) / 2
AIN0
AVDD
AIN1
Burnout Current Source (10 µA)
AVDD
AVSS
AVDD
AVSS
AIN2
AINP
PGA
To ADC
AINN
AIN3
AVDD
AVSS
Burnout Current Source (10 µA)
REFP
AVDD
AVSS
AVSS
AVSS
REFN
Figure 42. Analog Input Multiplexer
Electrostatic discharge (ESD) diodes to AVDD and AVSS protect the inputs. The absolute voltage on any input
must stay within the range provided by Equation 3 to prevent the ESD diodes from turning on:
AVSS – 0.3 V < V(AINx) < AVDD + 0.3 V
(3)
If the voltages on the input pins have any potential to violate these conditions, external Schottky clamp diodes or
series resistors may be required to limit the input current to safe values (see the Absolute Maximum Ratings
table). Overdriving an unused input on the device can affect conversions taking place on other input pins.
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Feature Description (continued)
8.3.2 Low-Noise Programmable Gain Stage
The device features programmable gains of 1, 2, 4, 8, 16, 32, 64, and 128. Three bits (GAIN[2:0]) in the
configuration register are used to configure the gain. Gains are achieved in two stages. The first stage is a lownoise, low-drift, high input impedance, programmable gain amplifier (PGA). The second gain stage is
implemented by a switched-capacitor circuit at the input to the ΔΣ modulator. Table 9 shows how each gain is
implemented.
Table 9. Gain Implementation
GAIN SETTING
PGA GAIN
SWITCHED-CAPACITOR GAIN
1
1
1
2
1
2
4
1
4
8
2
4
16
4
4
32
8
4
64
16
4
128
32
4
The PGA consists of two chopper-stabilized amplifiers (A1 and A2) and a resistor feedback network that sets the
PGA gain. The input is equipped with an electromagnetic interference (EMI) filter. Figure 43 shows a simplified
diagram of the PGA.
200
AINP
+
A1
25 pF
-
RF
OUTP
VOUT = PGA Gain·VIN
RG
VIN
RF
OUTN
A2
200
AINN
+
25 pF
Figure 43. Simplified PGA Diagram
VIN denotes the differential input voltage VIN = VAINP – VAINN. Use Equation 4 to calculate the gain of the PGA.
Gain is changed inside the device using a variable resistor, RG.
PGA Gain = 1 + 2 · RF / RG
(4)
The switched-capacitor gain is changed using variable capacitors at the input to the ΔΣ modulator. Gains 1, 2,
and 4 are implemented by using only the switched-capacitor circuit, which allows these gains to be used even
when the PGA is bypassed; see the Bypassing the PGA section for more information about bypassing the PGA.
Equation 5 shows that the differential full-scale input voltage range (FSR) of the device is defined by the gain
setting and the reference voltage used:
FSR = ±VREF / Gain
(5)
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Table 10 shows the corresponding full-scale ranges when using the internal 2.048-V reference.
Table 10. Full-Scale Range
GAIN SETTING
FSR
1
±2.048 V
2
±1.024 V
4
±0.512 V
8
±0.256 V
16
±0.128 V
32
±0.064 V
64
±0.032 V
128
±0.016 V
8.3.2.1 PGA Input Voltage Requirements
As with many amplifiers, the PGA has an absolute input voltage range requirement that cannot be exceeded.
The maximum and minimum absolute input voltages are limited by the voltage swing capability of the PGA
output. The specified minimum and maximum absolute input voltages (VAINP and VAINN) depend on the PGA gain,
the maximum differential input voltage (VINMAX), and the tolerance of the analog power-supply voltages (AVDD
and AVSS). Because gain on the ADS112C04 is implemented by both the PGA and a switched-capacitor gain
circuit, there are two formulas that define the absolute input voltages. Use Equation 6 when the device gain is
configured to less than or equal to 4. Use Equation 7 when the device gain is greater than 4. Use the maximum
differential input voltage expected in the application for VINMAX.
AVSS + 0.2 V ≤ VAINP, VAINN ≤ AVDD – 0.2 V
AVSS + 0.2 V + |VINMAX| · (Gain – 4) / 8 ≤ VAINP, VAINN ≤ AVDD – 0.2 V – |VINMAX| · (Gain – 4) / 8
(6)
(7)
Figure 44 graphically shows the relationship between the PGA input voltages to the PGA output voltages for
gains larger than 4. The PGA output voltages (VOUTP, VOUTN) depend on the PGA gain and the differential input
voltage magnitudes. For linear operation, the PGA output voltages must not exceed AVDD – 0.2 V or AVSS +
0.2 V. Figure 44 depicts an example of a positive differential input voltage that results in a positive differential
output voltage.
PGA Input
PGA Output
AVDD
AVDD ± 0.2 V
VOUTP = VAINP + VIN Â (Gain ± 4) / 8
VAINP
VIN = VAINP ± VAINN
VAINN
VOUTN = VAINN ± VIN Â (Gain ± 4) / 8
AVSS + 0.2 V
AVSS
Figure 44. PGA Input/Output Voltage Relationship
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8.3.2.2 Bypassing the PGA
At gains of 1, 2, and 4, the device can be configured to disable and bypass the low-noise PGA by setting the
PGA_BYPASS bit in the configuration register. Disabling the PGA lowers the overall power consumption and
also removes the restrictions of Equation 6 and Equation 7 for the absolute input voltage range. The usable
absolute input voltage range is (AVSS – 0.1 V ≤ VAINP, VAINN ≤ AVDD + 0.1 V) when the PGA is disabled.
In order to measure single-ended signals that are referenced to AVSS (AINP = VIN, AINN = AVSS), the PGA must
be bypassed. Configure the device for single-ended measurements by either connecting one of the analog inputs
to AVSS externally or by using the internal AVSS connection of the multiplexer (MUX[3:0] settings 1000 through
1011). When configuring the internal multiplexer for settings where AINN = AVSS (MUX[3:0] = 1000 through
1011), the PGA is automatically bypassed and disabled irrespective of the PGA_BYPASS setting and gain is
limited to 1, 2, and 4. In case gain is set to greater than 4, the device limits gain to 4.
When the PGA is disabled, the device uses a buffered switched-capacitor stage to obtain gains 1, 2, and 4. An
internal buffer in front of the switched-capacitor stage ensures that the effect on the input loading resulting from
the capacitor charging and discharging is minimal. See the Electrical Characteristics section for the typical values
of absolute input currents (current flowing into or out of each input) and differential input currents (difference in
absolute current between the positive and negative input) when the PGA is disabled.
For signal sources with high output impedance, external buffering may still be necessary. Active buffers can
introduce noise as well as offset and gain errors. Consider all of these factors in high-accuracy applications.
8.3.3 Voltage Reference
The device offers an integrated, low-drift, 2.048-V reference. For applications that require a different reference
voltage value or a ratiometric measurement approach, the device offers a differential reference input pair (REFP
and REFN). In addition, the analog supply (AVDD – AVSS) can be used as a reference.
The reference source is selected by two bits (VREF[1:0]) in the configuration register. By default, the internal
reference is selected. The internal voltage reference requires less than 25 µs to fully settle after power-up, when
coming out of power-down mode, or when switching from an external reference source to the internal reference.
The differential reference input allows freedom in the reference common-mode voltage. The reference inputs are
internally buffered to increase input impedance. Therefore, additional reference buffers are usually not required
when using an external reference. When used in ratiometric applications, the reference inputs do not load the
external circuitry; however, the analog supply current increases when using an external reference because the
reference buffers are enabled.
In most cases the conversion result is directly proportional to the stability of the reference source. Any noise and
drift of the voltage reference is reflected in the conversion result.
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8.3.4 Modulator and Internal Oscillator
A ΔΣ modulator is used in the ADS112C04 to convert the analog input voltage into a pulse code modulated
(PCM) data stream. The modulator runs at a modulator clock frequency of fMOD = fCLK / 4, where fCLK is provided
by the internal oscillator. The oscillator frequency, and therefore also the modulator frequency, depend on the
selected operating mode. Table 11 shows the oscillator and modulator frequencies for the different operating
modes.
Table 11. Oscillator and Modulator Clock Frequencies for Different Operating Modes
OPERATING MODE
fCLK
fMOD
Normal mode
1.024 MHz
256 kHz
Turbo mode
2.048 MHz
512 kHz
8.3.5 Digital Filter
0
0
-20
-20
-40
-40
Magnitude (dB)
Magnitude (dB)
The device uses a linear-phase finite impulse response (FIR) digital filter that performs both filtering and
decimation of the digital data stream coming from the modulator. The digital filter is automatically adjusted for the
different data rates and always settles within a single cycle. The frequency responses of the digital filter are
illustrated in Figure 45 to Figure 53 for different output data rates. The filter notches and output data rate scale
proportionally with the clock frequency. The internal oscillator can vary over temperature as specified in the
Electrical Characteristics table. The data rate or conversion time, respectively, and consequently also the filter
notches vary proportionally.
-60
-80
-100
-60
-80
-100
-120
0
20
40
60
80 100 120
Frequency (Hz)
140
160
180
-120
46
200
Figure 45. Filter Response
(Normal Mode, DR = 20 SPS)
0
0
-10
-10
-20
-20
-30
-40
52
54
56
58
Frequency (Hz)
60
62
64
D001
-30
-40
-50
-50
-60
-60
0
20
40
60
80 100 120
Frequency (Hz)
140
160
180
200
0
100
filt
Figure 47. Filter Response
(Normal Mode, DR = 45 SPS)
26
50
Figure 46. Detailed View of the Filter Response
(Normal Mode, DR = 20 SPS)
Magnitude (dB)
Magnitude (dB)
48
D002
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200
300
400 500 600
Frequency (Hz)
700
800
900 1000
D004
Figure 48. Filter Response
(Normal Mode, DR = 90 SPS)
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0
0
-10
-10
-20
-20
Magnitude (dB)
Magnitude (dB)
www.ti.com
-30
-40
-50
-30
-40
-50
-60
-60
0
100
200
300
400 500 600
Frequency (Hz)
700
800
900 1000
0
200
400
Figure 49. Filter Response
(Normal Mode, DR = 175 SPS)
800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
D006
Figure 50. Filter Response
(Normal Mode, DR = 330 SPS)
0
0
-20
-20
Magnitude (dB)
Magnitude (dB)
600
D005
-40
-40
-60
-60
-80
-80
0
500
1000
1500 2000 2500
Frequency (Hz)
3000
3500
4000
0
1
2
3
4
5
6
Frequency (kHz)
D007
Figure 51. Filter Response
(Normal Mode, DR = 600 SPS)
7
8
9
10
D008
Figure 52. Filter Response
(Normal Mode, DR = 1 kSPS)
0
Magnitude (dB)
-20
-40
-60
-80
0
1
2
3
4
5
6
Frequency (kHz)
7
8
9
10
D009
Figure 53. Filter Response
(Turbo Mode, DR = 2 kSPS)
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8.3.6 Conversion Times
Table 12 shows the actual conversion times for each data rate setting. The values provided are in terms of tCLK
cycles and in milliseconds.
Continuous conversion mode data rates are timed from one DRDY falling edge to the next DRDY falling edge.
The first conversion starts 28.5 · tCLK (normal mode) or 105 · tCLK (turbo mode) after the START/SYNC command
is latched.
Single-shot conversion mode data rates are timed from when the START/SYNC command is latched to the
DRDY falling edge and rounded to the next tCLK.
Commands are latched on the eighth falling edge of SCL in the command byte.
Table 12. Conversion Times
NOMINAL
DATA RATE
(SPS)
–3-dB
BANDWIDTH
(Hz)
CONTINUOUS CONVERSION MODE (1)
SINGLE-SHOT CONVERSION MODE
ACTUAL
CONVERSION TIME
(tCLK) (2)
ACTUAL
CONVERSION TIME
(ms)
ACTUAL
CONVERSION TIME
(tCLK) (2)
ACTUAL
CONVERSION TIME
(ms)
NORMAL MODE
20
13.1
51192
49.99
51213
50.01
45
20.0
22780
22.5
22805
22.27
90
39.6
11532
11.26
11557
11.29
175
77.8
5916
5.78
5941
5.80
330
150.1
3116
3.04
3141
3.07
600
279.0
1724
1.68
1749
1.71
1000
483.8
1036
1.01
1061
1.04
40
17.1
51192
25.00
51217
25.01
90
39.9
22780
11.12
22809
11.14
180
79.2
11532
5.63
11561
5.65
350
155.6
5916
2.89
5945
2.90
660
300.3
3116
1.52
3145
1.54
1200
558.1
1724
0.84
1753
0.86
2000
967.6
1036
0.51
1065
0.52
TURBO MODE
(1)
(2)
The first conversion starts 28.5 · tCLK (normal mode) or 105 · tCLK (turbo mode) after the START/SYNC command is latched. The times
listed in this table do not include that time.
tCLK = 1 / fCLK. fCLK = 1.024 MHz in normal mode and 2.048 MHz in turbo mode.
Although the conversion time at the 20-SPS setting is not exactly 1 / 20 Hz = 50 ms, this discrepancy does not
affect the 50-Hz or 60-Hz rejection. The conversion time and filter notches vary by the amount specified in the
Electrical Characteristics table for oscillator accuracy.
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8.3.7 Excitation Current Sources
The device provides two matched programmable excitation current sources (IDACs) for resistance temperature
detector (RTD) applications. The output current of the current sources can be programmed to 10 µA, 50 µA,
100 µA, 250 µA, 500 µA, 1000 µA, or 1500 µA using the respective bits (IDAC[2:0]) in the configuration register.
Each current source can be connected to any of the analog inputs (AINx) as well as to the dedicated reference
inputs (REFP and REFN). Both current sources can also be connected to the same pin. Routing of the IDACs is
configured by bits (I1MUX[2:0], I2MUX[2:0]) in the configuration register. Care must be taken not to exceed the
compliance voltage of the IDACs. In other words, limit the voltage on the pin where the IDAC is routed to
≤ (AVDD – 0.9 V), otherwise the specified accuracy of the IDAC current is not met. For three-wire RTD
applications, the matched current sources can be used to cancel errors caused by sensor lead resistance (see
the 3-Wire RTD Measurement section for more details).
The IDACs require up to 200 µs to start up after the IDAC current is programmed to the respective value using
the IDAC[2:0] bits. Set the IDAC current to the respective value using the IDAC[2:0] bits and then select the
routing for each IDAC (I1MUX[2:0], I2MUX[2:0]) thereafter.
In single-shot conversion mode, the IDACs remain active between any two conversions if the IDAC[2:0] bits are
set to a value other than 000. However, the IDACs are powered down whenever the POWERDOWN command is
issued.
Keep in mind that the analog supply current increases when enabling the IDACs (that is, when the IDAC[2:0] bits
are set to a value other than 000). The IDAC circuit needs this bias current to operate even when the IDACs are
not routed to any pin (I1MUX[2:0] = I2MUX[2:0] = 000). In addition, the selected output current is drawn from the
analog supply when I1MUX[2:0] or I2MUX[2:0] are set to a value other than 000.
8.3.8 Sensor Detection
To help detect a possible sensor malfunction, the device provides internal 10-µA, burn-out current sources.
When enabled by setting the respective bit (BCS) in the configuration register, one current source provides
current to the positive analog input (AINP) currently selected and the other current source sinks current from the
selected negative analog input (AINN).
In case of an open circuit in the sensor, these burn-out current sources pull the positive input towards AVDD and
the negative input towards AVSS, resulting in a full-scale reading. A full-scale reading can also indicate that the
sensor is overloaded or that the reference voltage is absent. A near-zero reading can indicate a shorted sensor.
The absolute value of the burn-out current sources typically varies by ±5% and the internal multiplexer adds a
small series resistance. Therefore, distinguishing a shorted sensor condition from a normal reading can be
difficult, especially if an RC filter is used at the inputs. In other words, even if the sensor is shorted, the voltage
drop across the external filter resistance and the residual resistance of the multiplexer causes the output to read
a value higher than zero.
Keep in mind that ADC readings of a functional sensor may be corrupted when the burn-out current sources are
enabled. Disable the burn-out current sources when preforming the precision measurement, and only enable
these sources to test for sensor fault conditions.
8.3.9 System Monitor
The device provides some means for monitoring the analog power supply and the external voltage reference. To
select a monitoring voltage, the internal multiplexer (MUX[3:0]) must be configured accordingly in the
configuration register. The device automatically bypasses the PGA and sets the gain to 1, irrespective of the
configuration register settings when the monitoring feature is used. The system monitor function only provides a
coarse result and is not meant to be a precision measurement.
When measuring the analog power supply (MUX[3:0] = 1101), the resulting conversion is approximately (AVDD –
AVSS) / 4. The device uses the internal 2.048-V reference for the measurement regardless of what reference
source is selected in the configuration register (VREF[1:0]).
When monitoring the external reference voltage source (MUX[3:0] = 1100), the result is approximately (V(REFP) –
V(REFN)) / 4. The device automatically uses the internal reference for the measurement.
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8.3.10 Temperature Sensor
The ADS112C04 offers an integrated precision temperature sensor. The temperature sensor mode is enabled by
setting the TS bit = 1 in the configuration register. When in temperature sensor mode, the settings of
configuration register 0 have no effect and the device uses the internal reference for measurement, regardless of
the selected voltage reference source. Temperature readings follow the same process as the analog inputs for
starting and reading conversion results. Temperature data are represented as a 14-bit effective result that is leftjustified within the 16-bit conversion result. When reading the two data bytes, the first 14 bits (MSBs) are used to
indicate the temperature measurement result. The LSBs of the data output do not indicate temperature. Only the
14 MSBs are relevant. One 14-bit LSB equals 0.03125°C. Negative numbers are represented in binary two's
complement format. Table 13 shows the mapping between temperature and digital codes.
Table 13. 14-Bit Temperature Data Format
DIGITAL OUTPUT
TEMPERATURE (°C)
BINARY
HEX
128
01 0000 0000 0000
1000
127.96875
00 1111 1111 1111
0FFF
100
00 1100 1000 0000
0C80
75
00 1001 0110 0000
0960
50
00 0110 0100 0000
0640
25
00 0011 0010 0000
0320
0.25
00 0000 0000 1000
0008
0.03125
00 0000 0000 0001
0001
0
00 0000 0000 0000
0000
–0.25
11 1111 1111 1000
3FF8
–25
11 1100 1110 0000
3CE0
–40
11 1011 0000 0000
3B00
8.3.10.1 Converting From Temperature to Digital Codes
8.3.10.1.1 For Positive Temperatures (For Example, 50°C):
Two's complement is not performed on positive numbers. Therefore, simply convert the number to binary code in
a 14-bit, left-justified format with the MSB = 0 to denote the positive sign.
Example: 50°C / (0.03125°C per count) = 1600 = 0640h = 00 0110 0100 0000
8.3.10.1.2 For Negative Temperatures (For Example, –25°C):
Generate the two's complement of a negative number by complementing the absolute binary number and adding
1. Then, denote the negative sign with the MSB = 1.
Example: |–25°C| / (0.03125°C per count) = 800 = 0320h = 00 0011 0010 0000
Two's complement format: 11 1100 1101 1111 + 1 = 11 1100 1110 0000
8.3.10.2 Converting From Digital Codes to Temperature
To convert from digital codes to temperature, first check whether the MSB is a 0 or a 1. If the MSB is a 0, simply
multiply the decimal code by 0.03125°C to obtain the result. If the MSB is a 1, subtract 1 from the result and
complement all bits. Then, multiply the result by –0.03125°C.
Example: The device reads back 0960h: 0960h has an MSB = 0.
0960h · 0.03125°C = 2400 · 0.03125°C = 75°C
Example: The device reads back 3CE0h: 3CE0h has an MSB = 1.
Subtract 1 and complement the result: 3CE0h → 0320h
0320h · (–0.03125°C) = 800 · (–0.03125°C) = –25°C
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8.3.11 Offset Calibration
The internal multiplexer offers the option to short both PGA inputs (AINP and AINN) to mid-supply (AVDD +
AVSS) / 2. This option can be used to measure and calibrate the device offset voltage by storing the result of the
shorted input voltage reading in a microcontroller and consequently subtracting the result from each following
reading. Take multiple readings with the inputs shorted and average the result to reduce the effect of noise.
8.3.12 Conversion Data Counter
The ADS112C04 offers an optional data counter word to help the host determine if the conversion data are new.
The DCNT bit in the configuration register enables the conversion data counter. The data counter appears as an
8-bit word that precedes the conversion data each time a conversion result is read. The reset value of the
counter is 00h. The word increments each time the ADC completes a conversion. The counter rolls over to 00h
after reaching FFh.
When the host reads a conversion result, the host can determine if the data being read are new by comparing
the counter value with the counter value obtained with the last data read. If the counter values are the same,
then this result indicates that no new conversion data are available from the ADC. The counter can also help the
host determine if a conversion result was missed.
Reset the conversion data counter by clearing the DCNT bit to 0 and then setting DCNT back to 1. A device
reset also resets the conversion data counter.
8.3.13 Data Integrity Features
There are two methods for ensuring data integrity for data output on the ADS112C04. Output data can be
register contents or conversion results. The optional data counter word that precedes conversion data is covered
by both data integrity options. The data integrity modes are configured using the CRC[1:0] bits in the
configuration register. When CRC[1:0] = 01, a bitwise-inverted version of the data is output immediately following
the most significant byte (MSB) of the data.
When CRC[1:0] = 10, a 16-bit CRC word is output immediately following the MSB of the data. In CRC mode, the
checksum bytes are the 16-bit remainder of the bitwise exclusive-OR (XOR) of the data bytes with a CRC
polynomial. The CRC is based on the CRC-16-CCITT polynomial: x16 + x12 + x5 + 1 with an initial value of
FFFFh.
The 17 binary coefficients of the polynomial are: 1 0001 0000 0010 0001. To calculate the CRC, divide (XOR
operation) the data bytes (excluding the CRC) with the polynomial and compare the calculated CRC values to
the ADC CRC value. If the values do not match, a data transmission error has occurred. In the event of a data
transmission error, read the data again.
The following list shows a general procedure to compute the CRC value:
1. Left-shift the initial data value by 16 bits, with zeros padded to the right.
2. Align the MSB of the CRC polynomial to the left-most, logic-one value of the data.
3. Perform an XOR operation on the data value with the aligned CRC polynomial. The XOR operation creates a
new, shorter-length value. The bits of the data values that are not in alignment with the CRC polynomial drop
down and append to the right of the new XOR result.
4. When the XOR result is less than 1 0000 0000 0000 0000, the procedure ends, yielding the 16-bit CRC
value. Otherwise, continue with the XOR operation shown in step 2 using the current data value. The number
of loop iterations depends on the value of the initial data.
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8.4 Device Functional Modes
Figure 54 shows a flow chart of the different operating modes and how the device transitions from one mode to
another.
Power-On Reset or
RESET pin high or
RESET command(1)
Reset device to
default settings
Low-power state
No
No
START/SYNC
Command?
POWERDOWN
Command?
Yes
Yes
Conversion
Mode
Power-down Mode(3)
Yes
Start new
conversion
START/SYNC
Command?
No
No
0 = Single-Shot
conversion mode
Conversion
mode selection(2)
1 = Continuous
conversion mode
POWERDOWN
Command?
Yes
(1)
Any reset (power-on, command, or pin) immediately resets the device.
(2)
The conversion mode is selected with the CM bit in the configuration register.
(3)
The POWERDOWN command allows any ongoing conversion to complete before placing the device in power-down
mode.
Figure 54. Operating Flow Chart
8.4.1 Power-Up and Reset
The ADS112C04 is reset in one of three ways: either by a power-on reset, by the RESET pin, or by a RESET
command.
When a reset occurs, the configuration registers reset to the default values and the device enters a low-power
state. The device then waits for the START/SYNC command to enter conversion mode; see the I2C Timing
Requirements table for reset timing information.
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Device Functional Modes (continued)
8.4.1.1 Power-On Reset
During power up, the device is held in reset. The power-on reset releases approximately 500 µs after both
supplies have exceeded their respective power-up reset thresholds. After this time all internal circuitry (including
the voltage reference) are stable and communication with the device is possible. As part of the power-on reset
process, the device sets all bits in the configuration registers to the respective default settings. After power-up,
the device enters a low-power state. This power-up behavior is intended to prevent systems with tight powersupply requirements from encountering a current surge during power-up.
8.4.1.2 RESET Pin
Reset the ADC by taking the RESET pin low for a minimum of tw(RSL) and then returning the pin high. After the
rising edge of the RESET pin, a delay time of td(RSSTA) is required before communicating with the device; see the
I2C Timing Requirements section for reset timing information.
8.4.1.3 Reset by Command
Reset the ADC by using the RESET command (06h or 07h). No delay time is required after the RESET
command is latched before starting to communicate with the device as long as the timing requirements (see the
I2C Timing Requirements table) for the (repeated) START and STOP conditions are met. Alternatively, the device
also responds to the I2C general-call software reset.
8.4.2 Conversion Modes
The device operates in one of two conversion modes that are selected by the CM bit in the configuration register.
These conversion modes are single-shot conversion and continuous conversion mode. A START/SYNC
command must be issued each time the CM bit is changed.
8.4.2.1 Single-Shot Conversion Mode
In single-shot conversion mode, the device only performs a conversion when a START/SYNC command is
issued. The device consequently performs one single conversion and returns to a low-power state afterwards.
The internal oscillator and all analog circuitry (except for the excitation current sources) are turned off while the
device waits in this low-power state until the next conversion is started. Writing to any configuration register when
a conversion is ongoing functions as a new START/SYNC command that stops the current conversion and
restarts a single new conversion. Each conversion is fully settled (assuming the analog input signal settles to the
final value before the conversion starts) because the device digital filter settles within a single cycle.
8.4.2.2 Continuous Conversion Mode
In continuous conversion mode, the device continuously performs conversions. When a conversion completes,
the device places the result in the output buffer and immediately begins another conversion.
In order to start continuous conversion mode, the CM bit must be set to 1 followed by a START/SYNC command.
The first conversion starts 28.5 · tCLK (normal mode) or 105 · tCLK (turbo mode) after the START/SYNC command
is latched. Writing to any configuration register during an ongoing conversion restarts the current conversion.
Send a START/SYNC command immediately after the CM bit is set to 1.
Stop continuous conversions by sending the POWERDOWN command.
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Device Functional Modes (continued)
8.4.3 Operating Modes
In addition to the different conversion modes, the device can also be operated in different operating modes that
can be selected to trade-off power consumption, noise performance, and output data rate. These modes are:
normal mode, turbo mode, and power-down mode.
8.4.3.1 Normal Mode
Normal mode is the default mode of operation after power-up. In this mode, the internal modulator of the ΔΣ ADC
runs at a modulator clock frequency of fMOD = fCLK / 4 = 256 kHz, where the system clock (fCLK) is provided by the
internal oscillator. Normal mode offers output data rate options ranging from 20 SPS to 1 kSPS. The data rate is
selected by the DR[2:0] bits in the configuration register.
8.4.3.2 Turbo Mode
Applications that require higher data rates up to 2 kSPS can operate the device in turbo mode. In this mode, the
internal modulator runs at a higher frequency of fMOD = fCLK / 4 = 512 kHz. Compared to normal mode, the device
power consumption increases because the modulator runs at a higher frequency. Running the ADS112C04 in
turbo mode at a comparable output data rate as in normal mode yields better noise performance. For example,
the input-referred noise at 90 SPS in turbo mode is lower than the input-referred noise at 90 SPS in normal
mode.
8.4.3.3 Power-Down Mode
When the POWERDOWN command is issued, the device enters power-down mode after completing the current
conversion. In this mode, all analog circuitry (including the voltage reference and both IDACs) are powered down
and the device typically only uses 400 nA of current. When in power-down mode, the device holds the
configuration register settings and responds to commands, but does not perform any data conversions.
Issuing a START/SYNC command wakes up the device and either starts a single conversion or starts continuous
conversion mode, depending on the conversion mode selected by the CM bit.
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8.5 Programming
8.5.1 I2C Interface
The ADS112C04 uses an I2C-compatible (inter-integrated circuit) interface for serial communication. I2C is a 2wire communication interface that allows communication of a master device with multiple slave devices on the
same bus through the use of device addressing. Each slave device on an I2C bus must have a unique address.
Communication on the I2C bus always takes place between two devices: one acting as the master and the other
as the slave. Both the master and slave can receive and transmit data, but the slave can only read or write under
the direction of the master. The ADS112C04 always acts as an I2C slave device.
An I2C bus consists of two lines: SDA and SCL. SDA carries data and SCL provides the clock. Devices on the
I2C bus drive the bus lines low by connecting the lines to ground; the devices never drive the bus lines high.
Instead, the bus wires are pulled high by pullup resistors; thus, the bus wires are always high when a device is
not driving the lines low. As a result of this configuration, two devices do not conflict. If two devices drive the bus
simultaneously, there is no driver contention.
See the I2C-Bus Specification and User Manual from NXP Semiconductors™ for more details.
8.5.1.1 I2C Address
The ADS112C04 has two address pins: A0 and A1. Each address pin can be tied to either DGND, DVDD, SDA,
or SCL, providing 16 possible unique addresses. This configuration allows up to 16 different ADS112C04 devices
to be present on the same I2C bus. Table 14 shows the truth table for the I2C addresses for the possible address
pin connections.
At the start of every transaction, that is between the START condition (first falling edge of SDA) and the first
falling SCL edge of the address byte, the ADS112C04 decodes its address configuration again.
Table 14. I2C Address Truth Table
A1
A0
I2C ADDRESS
DGND
DGND
100 0000
DGND
DVDD
100 0001
DGND
SDA
100 0010
DGND
SCL
100 0011
DVDD
DGND
100 0100
DVDD
DVDD
100 0101
DVDD
SDA
100 0110
DVDD
SCL
100 0111
SDA
DGND
100 1000
SDA
DVDD
100 1001
SDA
SDA
100 1010
SDA
SCL
100 1011
SCL
DGND
100 1100
SCL
DVDD
100 1101
SCL
SDA
100 1110
SCL
SCL
100 1111
8.5.1.2 Serial Clock (SCL) and Serial Data (SDA)
The serial clock (SCL) line is used to clock data in and out of the device. The master always drives the clock line.
The ADS112C04 cannot act as a master and as a result can never drive SCL.
The serial data (SDA) line allows for bidirectional communication between the host (the master) and the
ADS112C04 (the slave). When the master reads from a ADS112C04, the ADS112C04 drives the data line; when
the master writes to a ADS112C04, the master drives the data line.
Data on the SDA line must be stable during the high period of the clock. The high or low state of the data line
can only change when the SCL line is low. One clock pulse is generated for each data bit transferred. When in
an idle state, the master should hold SCL high.
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8.5.1.3 Data Ready (DRDY)
DRDY is an open-drain output pin that indicates when a new conversion result is ready for retrieval. When DRDY
falls low, new conversion data are ready. DRDY transitions back high when the conversion result is latched for
output transmission. In case a conversion result in continuous conversion mode is not read, DRDY releases high
for tw(DRH) before the next conversion completes. See the I2C Timing Requirements table for more details.
8.5.1.4 Interface Speed
The ADS112C04 supports I2C interface speeds up to 1 Mbps. Standard-mode (Sm) with bit rates up to 100 kbps,
fast-mode (Fm) with bit rates up to 400 kbps, and fast-mode plus (Fm+) with bit rates up to 1 Mbps are
supported. High-speed mode (Hs-mode) is not supported.
8.5.1.5 Data Transfer Protocol
Figure 55 shows the format of the data transfer. The master initiates all transactions with the ADS112C04 by
generating a START (S) condition. A high-to-low transition on the SDA line while SCL is high defines a START
condition. The bus is considered to be busy after the START condition.
Following the START condition, the master sends the 7-bit slave address corresponding to the address of the
ADS112C04 that the master wants to communicate with. The master then sends an eighth bit that is a data
direction bit (R/W). An R/W bit of 0 indicates a write operation, and an R/W bit of 1 indicates a read operation.
After the R/W bit, the master generates a ninth SCLK pulse and releases the SDA line to allow the ADS112C04
to acknowledge (ACK) the reception of the slave address by pulling SDA low. In case the device does not
recognize the slave address, the ADS112C04 holds SDA high to indicate a not acknowledge (NACK) signal.
Next follows the data transmission. If the transaction is a read (R/W = 1), the ADS112C04 outputs data on SDA.
If the transaction is a write (R/W = 0), the host outputs data on SDA. Data are transferred byte-wise, most
significant bit (MSB) first. The number of bytes that can be transmitted per transfer is unrestricted. Each byte
must be acknowledged (via the ACK bit) by the receiver. If the transaction is a read, the master issues the ACK.
If the transaction is a write, the ADS112C04 issues the ACK.
The master terminates all transactions by generating a STOP (P) condition. A low-to-high transition on the SDA
line while SCL is high defines a STOP condition. The bus is considered free again tBUF (bus-free time) after the
STOP condition.
SDA
A6 ± A0
D7 ± D0
D7 ± D0
SCL
1-7
8
9
1-8
9
1-8
9
ADDRESS
R/W
ACK
from slave
DATA
ACK
from receiver
DATA
ACK
from receiver
S
START
Condition
P
STOP
Condition
Figure 55. I2C Data Transfer Format
8.5.1.6 I2C General Call (Software Reset)
The ADS112C04 responds to the I2C general-call address (0000 000) if the R/W bit is 0. The device
acknowledges the general-call address and, if the next byte is 06h, performs a reset. The general-call software
reset has the same effect as the RESET command.
8.5.1.7 Timeout
The ADS112C04 offers a I2C timeout feature that can be used to recover communication when a serial interface
transmission is interrupted. If the host initiates contact with the ADS112C04 but subsequently remains idle for
14000 · tMOD in normal mode and 28000 · tMOD in turbo mode before completing a command, the ADS112C04
interface is reset. If the ADS112C04 interface resets because of a timeout condition, the host must abort the
transaction and restart the communication again by issuing a new START condition.
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8.5.2 Data Format
The device provides 16 bits of data in binary two's complement format. Use Equation 8 to calculate the size of
one code (LSB).
1 LSB = (2 · VREF / Gain) / 216 = +FS / 215
(8)
A positive full-scale input [VIN ≥ (+FS – 1 LSB) = (VREF / Gain – 1 LSB)] produces an output code of 7FFFh and a
negative full scale input (VIN ≤ –FS = –VREF / Gain) produces an output code of 8000h. The output clips at these
codes for signals that exceed full-scale.
Table 15 summarizes the ideal output codes for different input signals.
Table 15. Ideal Output Code versus Input Signal
INPUT SIGNAL,
VIN = VAINP – VAINN
15
≥ FS (2
IDEAL OUTPUT CODE (1)
15
– 1) / 2
7FFFh
FS / 215
(1)
0001h
0
0000h
–FS / 215
FFFFh
≤ –FS
8000h
Excludes the effects of noise, INL, offset, and gain errors.
Figure 56 shows the mapping of the analog input signal to the output codes.
7FFFh
0001h
0000h
FFFFh
...
Output Code
...
7FFEh
8001h
8000h
...
-FS
2
15
-FS
2
0
...
+FS
Input Voltage VIN
2
-1
15
15
+FS
2
-1
15
Figure 56. Code Transition Diagram
NOTE
Single-ended signal measurements, where VAINN = 0 V and VAINP = 0 V to +FS, only use
the positive code range from 0000h to 7FFFh. However, because of device offset, the
ADS112C04 can still output negative codes when VAINP is close to 0 V.
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8.5.3 Commands
As Table 16 shows, the device offers six different commands to control device operation. Four commands are
stand-alone instructions (RESET, START/SYNC, POWERDOWN, and RDATA). The commands to read (RREG)
and write (WREG) configuration register data from and to the device require additional information as part of the
instruction.
Table 16. Command Definitions
COMMAND
DESCRIPTION
COMMAND BYTE (1)
RESET
Reset the device
0000 011x
START/SYNC
Start or restart conversions
0000 100x
POWERDOWN
Enter power-down mode
0000 001x
RDATA
Read data by command
0001 xxxx
RREG
Read register at address rr
0010 rrxx
WREG
Write register at address rr
0100 rrxx
(1)
Operands: rr = register address (00 to 11), x = don't care.
8.5.3.1 Command Latching
Commands are not processed until latched by the ADS112C04. Commands are latched on the eighth falling
edge of SCL in the command byte.
NOTE
The legend for Figure 57 to Figure 63:
From master to slave
S = START condition
Sr = Repeated START condition
P = STOP condition
From slave to master
A = acknowledge (SDA low)
A = not acknowledge (SDA high)
8.5.3.2 RESET (0000 011x)
This command resets the device to the default states. No delay time is required after the RESET command is
latched before starting to communicate with the device as long as the timing requirements (see the I2C Timing
Requirements table) for the (repeated) START and STOP conditions are met.
8.5.3.3 START/SYNC (0000 100x)
In single-shot conversion mode, the START/SYNC command is used to start a single conversion, or (when sent
during an ongoing conversion) to reset the digital filter and then restart a single new conversion. When the
device is set to continuous conversion mode, the START/SYNC command must be issued one time to start
converting continuously. Sending the START/SYNC command when converting in continuous conversion mode
resets the digital filter and restarts continuous conversions.
8.5.3.4 POWERDOWN (0000 001x)
The POWERDOWN command places the device into power-down mode. This command shuts down all internal
analog components and turns off both IDACs, but holds all register values. In case the POWERDOWN command
is issued when a conversion is ongoing, the conversion completes before the ADS112C04 enters power-down
mode. As soon as a START/SYNC command is issued, all analog components return to their previous states.
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8.5.3.5 RDATA (0001 xxxx)
The RDATA command loads the output shift register with the most recent conversion result. Reading conversion
data must be performed as shown in Figure 57 by using two I2C communication frames. The first frame is an I2C
write operation where the R/W bit at the end of the address byte is 0 to indicate a write. In this frame, the host
sends the RDATA command to the ADS112C04. The second frame is an I2C read operation where the R/W bit
at the end of the address byte is 1 to indicate a read. The ADS112C04 reports the latest ADC conversion data in
this second I2C frame. If a conversion finishes in the middle of the RDATA command byte, the state of the DRDY
pin at the end of the read operation signals whether the old or the new result is loaded. If the old result is loaded,
DRDY stays low, indicating that the new result is not read out. The new conversion result loads when DRDY is
high.
S
SLAVE ADDRESS
‡‡‡
W
CONVERSION DATA (MSB)
A
RDATA
A
Sr
A
CONVERSION DATA (LSB)
A
P
SLAVE ADDRESS
R
A
‡‡‡
Figure 57. Read Conversion Data Sequence
8.5.3.6 RREG (0010 rrxx)
The RREG command reads the value of the register at address rr. Reading a register must be performed as
shown in Figure 58 by using two I2C communication frames. The first frame is an I2C write operation where the
R/W bit at the end of the address byte is 0 to indicate a write. In this frame, the host sends the RREG command
including the register address to the ADS112C04. The second frame is an I2C read operation where the R/W bit
at the end of the address byte is 1 to indicate a read. The ADS112C04 reports the contents of the requested
register in this second I2C frame.
‡‡‡
S
SLAVE ADDRESS
W
A
RREG
A
‡‡‡
Sr
SLAVE ADDRESS
R
A
REGISTER DATA
A
P
Figure 58. Read Register Sequence
8.5.3.7 WREG (0100 rrxx dddd dddd)
The WREG command writes dddd dddd to the register at address rr. Multiple registers can be written within the
same I2C frame by simply issuing another WREG command without providing a STOP condition following the
previous register write. Figure 59 shows the sequence for writing an arbitrary number of registers. The R/W bit at
the end of the address byte is 0 to indicate a write. The WREG command forces the digital filter to reset and any
ongoing ADC conversion to restart.
S
SLAVE ADDRESS
W
A
WREG
A
REGISTER DATA
A
‡‡‡
‡‡‡
WREG
A
REGISTER DATA
A
P
Figure 59. Write Register Sequence
8.5.4 Reading Data and Monitoring for New Conversion Results
Conversion data are read by issuing the RDATA command. The ADS112C04 responds to the RDATA command
with the latest conversion result. There are three ways to monitor for new conversion data.
One way is to monitor for the falling edge of the DRDY signal. When DRDY falls low, a new conversion result is
available for retrieval using the RDATA command. Figure 60 illustrates the timing diagram for collecting data
using the DRDY signal to indicate new data.
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DRDY
‡‡‡
S
‡‡‡
SLAVE ADDRESS
W
CONVERSION DATA (MSB)
A
RDATA
A
Sr
A
CONVERSION DATA (LSB)
A
P
SLAVE ADDRESS
R
A
‡‡‡
Figure 60. Using the DRDY Pin to Check for New Conversion Data
Another way to monitor for a new conversion result is to periodically read the DRDY bit in the configuration
register. If set, the DRDY bit indicates that a new conversion result is ready for retrieval. The host can
subsequently issue an RDATA command to retrieve the data. The rate at which the host polls the ADS112C04
for new data must be at least as fast as the data rate in continuous conversion mode to prevent the host from
missing a conversion result.
If a new conversion result becomes ready during an I2C transmission, the transmission is not corrupted. The new
data are loaded into the output shift register upon the following RDATA command.
Figure 61 shows the timing diagram for collecting data using the DRDY bit in the configuration register to indicate
new data.
S
SLAVE ADDRESS
‡‡‡
REGISTER DATA (02h)
A
Sr
SLAVE ADDRESS
R
A
‡‡‡
Sr
W
A
RREG (02h)
A
Sr
SLAVE ADDRESS
W
A
A
CONVERSION DATA (MSB)
SLAVE ADDRESS
R
A
‡‡‡
RDATA
A
‡‡‡
CONVERSION DATA (LSB)
A
P
Figure 61. Using the DRDY Bit to Check for New Conversion Data
The last way to detect if new conversion data are available is through the use of the conversion data counter
word. In this mode, the host periodically requests data from the device using the RDATA command and checks
the conversion data counter word against the conversion data counter word read for the previous data received.
If the counter values are the same, the host can disregard the data because that data has already been
gathered. If the counter has incremented, the host records the data. The rate at which the host polls the
ADS112C04 for new data must be at least as fast as the data rate in continuous conversion mode to prevent the
host from missing a conversion result.
If a new conversion result becomes ready during an I2C transmission, the transmission is not corrupted. The new
data are loaded into the output shift register after the following RDATA command.
Figure 62 shows the timing diagram for collecting data using the conversion data counter word to indicate new
data.
S
‡‡‡
SLAVE ADDRESS
CONVERSION COUNTER
W
A
RDATA
A
A
CONVERSION DATA (MSB)
A
Sr
SLAVE ADDRESS
CONVERSION DATA (LSB)
R
A
A
P
‡‡‡
Figure 62. Using the Conversion Counter to Check for New Conversion Data
The conversion data counter can be used in conjunction with the previously discussed methods of detecting new
data to ensure that the host did not miss a conversion result.
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8.5.5 Data Integrity
The optional data integrity checks can be configured using the CRC[1:0] bits in the configuration register. When
one of the data integrity options is enabled, the data integrity check is output on the SDA pin immediately
following the conversion or register data; see the Data Integrity Features section for a detailed description of the
data integrity functionality. Additional words are always two bytes when CRC16 is enabled. The number of
additional words in the inverted data mode when reading conversion data varies from two to three, depending on
whether the conversion data counter is enabled. Figure 63 shows data retrieval when either inverted data output
or CRC are enabled.
S
SLAVE ADDRESS
W
A
RDATA
A
Sr
‡‡‡
CONVERSION DATA (MSB)
A
CONVERSION DATA (LSB)
A
‡‡‡
‡‡‡
CRC / CONVERSION DATA (MSB)
A
CRC / CONVERSION DATA (LSB)
A
P
SLAVE ADDRESS
R
A
‡‡‡
Figure 63. Conversion Data Output With CRC or Inverted Data Output Enabled
8.6 Register Map
8.6.1 Configuration Registers
The device has four 8-bit configuration registers that are accessible through the I2C interface using the RREG
and WREG commands. After power-up or reset, all registers are set to the default values (which are all 0). All
register values are retained during power-down mode. Table 17 shows the register map of the configuration
registers.
Table 17. Configuration Register Map
REGISTER
(Hex)
BIT 7
BIT 6
00h
BIT 5
BIT 4
BIT 3
MODE
CM
MUX[3:0]
01h
DRDY
03h
DCNT
BIT 1
GAIN[2:0]
DR[2:0]
02h
BIT 2
CRC[1:0]
I1MUX[2:0]
BIT 0
PGA_BYPASS
VREF[1:0]
TS
BCS
IDAC[2:0]
I2MUX[2:0]
0
0
8.6.2 Register Descriptions
Table 18 lists the access codes for the ADS112C04 registers.
Table 18. Register Access Type Codes
Access Type
Code
Description
R
R
Read
R/W
R/W
Read-Write
W
W
Write
-n
Value after reset or the default value
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8.6.2.1 Configuration Register 0 (address = 00h) [reset = 00h]
Figure 64. Configuration Register 0
7
6
5
4
3
MUX[3:0]
R/W-0h
2
GAIN[2:0]
R/W-0h
1
0
PGA_BYPASS
R/W-0h
Table 19. Configuration Register 0 Field Descriptions
Bit
Field
Type
Reset
Description
7:4
MUX[3:0]
R/W
0h
Input multiplexer configuration.
These bits configure the input multiplexer.
For settings where AINN = AVSS, the PGA must be disabled (PGA_BYPASS = 1)
and only gains 1, 2, and 4 can be used.
0000 :
0001 :
0010 :
0011 :
0100 :
0101 :
0110 :
0111 :
1000 :
1001 :
1010 :
1011 :
1100 :
1101 :
1110 :
1111 :
3:1
GAIN[2:0]
R/W
0h
Gain configuration.
These bits configure the device gain.
Gains 1, 2, and 4 can be used without the PGA. In this case, gain is obtained by
a switched-capacitor structure.
000 :
001 :
010 :
011 :
100 :
101 :
110 :
111 :
0
PGA_BYPASS
R/W
0h
AINP = AIN0, AINN = AIN1 (default)
AINP = AIN0, AINN = AIN2
AINP = AIN0, AINN = AIN3
AINP = AIN1, AINN = AIN0
AINP = AIN1, AINN = AIN2
AINP = AIN1, AINN = AIN3
AINP = AIN2, AINN = AIN3
AINP = AIN3, AINN = AIN2
AINP = AIN0, AINN = AVSS
AINP = AIN1, AINN = AVSS
AINP = AIN2, AINN = AVSS
AINP = AIN3, AINN = AVSS
(V(REFP) – V(REFN)) / 4 monitor (PGA bypassed)
(AVDD – AVSS) / 4 monitor (PGA bypassed)
AINP and AINN shorted to (AVDD + AVSS) / 2
Reserved
Gain
Gain
Gain
Gain
Gain
Gain
Gain
Gain
= 1 (default)
=2
=4
=8
= 16
= 32
= 64
= 128
Disables and bypasses the internal low-noise PGA.
Disabling the PGA reduces overall power consumption and allows the absolute
input voltage range to span from AVSS – 0.1 V to AVDD + 0.1 V.
The PGA can only be disabled for gains 1, 2, and 4.
The PGA is always enabled for gain settings 8 to 128, regardless of the
PGA_BYPASS setting.
0 : PGA enabled (default)
1 : PGA disabled and bypassed
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8.6.2.2 Configuration Register 1 (address = 01h) [reset = 00h]
Figure 65. Configuration Register 1
7
6
DR[2:0]
R/W-0h
5
4
MODE
R/W-0h
3
CM
R/W-0h
2
1
VREF[1:0]
R/W-0h
0
TS
R/W-0h
Table 20. Configuration Register 1 Field Descriptions
Bit
Field
Type
Reset
Description
7:5
DR[2:0]
R/W
0h
Data rate.
These bits control the data rate setting depending on the selected operating
mode. Table 21 lists the bit settings for normal and turbo mode.
4
MODE
R/W
0h
Operating mode.
These bits control the operating mode that the device operates in.
0 : Normal mode (256-kHz modulator clock, default)
1 : Turbo mode (512-kHz modulator clock)
3
CM
R/W
0h
Conversion mode.
This bit sets the conversion mode for the device.
0 : Single-shot conversion mode (default)
1 : Continuous conversion mode
2:1
VREF[1:0]
R/W
0h
Voltage reference selection.
These bits select the voltage reference source that is used for the conversion.
00
01
10
11
0
TS
R/W
0h
:
:
:
:
Internal 2.048-V reference selected (default)
External reference selected using the REFP and REFN inputs
Analog supply (AVDD – AVSS) used as reference
Analog supply (AVDD – AVSS) used as reference
Temperature sensor mode.
This bit enables the internal temperature sensor and puts the device in
temperature sensor mode.
The settings of configuration register 0 have no effect and the device uses the
internal reference for measurement when temperature sensor mode is enabled.
0 : Temperature sensor mode disabled (default)
1 : Temperature sensor mode enabled
Table 21. DR Bit Settings
NORMAL MODE
TURBO MODE
000 = 20 SPS
000 = 40 SPS
001 = 45 SPS
001 = 90 SPS
010 = 90 SPS
010 = 180 SPS
011 = 175 SPS
011 = 350 SPS
100 = 330 SPS
100 = 660 SPS
101 = 600 SPS
101 = 1200 SPS
110 = 1000 SPS
110 = 2000 SPS
111 = Reserved
111 = Reserved
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8.6.2.3 Configuration Register 2 (address = 02h) [reset = 00h]
Figure 66. Configuration Register 2
7
DRDY
R-0h
6
DCNT
R/W-0h
5
4
3
BCS
R/W-0h
CRC[1:0]
R/W-0h
2
1
IDAC[2:0]
R/W-0h
0
Table 22. Configuration Register 2 Field Descriptions
Bit
Field
Type
Reset
Description
7
DRDY
R
0h
Conversion result ready flag.
This bit flags if a new conversion result is ready. This bit is reset when conversion
data are read.
0 : No new conversion result available (default)
1 : New conversion result ready
6
DCNT
R/W
0h
Data counter enable.
The bit enables the conversion data counter.
0 : Conversion counter disabled (default)
1 : Conversion counter enabled
5:4
CRC[1:0]
R/W
0h
Data integrity check enable.
These bits enable and select the data integrity checks.
00
01
10
11
3
BCS
R/W
0h
:
:
:
:
Disabled (default)
Inverted data output enabled
CRC16 enabled
Reserved
Burn-out current sources.
This bit controls the 10-µA, burn-out current sources. The burn-out current
sources can be used to detect sensor faults such as wire breaks and shorted
sensors.
0 : Current sources off (default)
1 : Current sources on
2:0
IDAC[2:0]
R/W
0h
IDAC current setting.
These bits set the current for both IDAC1 and IDAC2 excitation current sources.
000 :
001 :
010 :
011 :
100 :
101 :
110 :
111 :
44
Off (default)
10 µA
50 µA
100 µA
250 µA
500 µA
1000 µA
1500 µA
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8.6.2.4 Configuration Register 3 (address = 03h) [reset = 00h]
Figure 67. Configuration Register 3
7
6
I1MUX[2:0]
R/W-0h
5
4
3
I2MUX[2:0]
R/W-0h
2
1
0
R-0h
0
0
R-0h
Table 23. Configuration Register 3 Field Descriptions
Bit
Field
Type
Reset
Description
7:5
I1MUX[2:0]
R/W
0h
IDAC1 routing configuration.
These bits select the channel that IDAC1 is routed to.
000 :
001 :
010 :
011 :
100 :
101 :
110 :
111 :
4:2
I2MUX[2:0]
R/W
0h
IDAC2 routing configuration.
These bits select the channel that IDAC2 is routed to.
000 :
001 :
010 :
011 :
100 :
101 :
110 :
111 :
1:0
RESERVED
R
0h
IDAC1 disabled (default)
IDAC1 connected to AIN0
IDAC1 connected to AIN1
IDAC1 connected to AIN2
IDAC1 connected to AIN3
IDAC1 connected to REFP
IDAC1 connected to REFN
Reserved
IDAC2 disabled (default)
IDAC2 connected to AIN0
IDAC2 connected to AIN1
IDAC2 connected to AIN2
IDAC2 connected to AIN3
IDAC2 connected to REFP
IDAC2 connected to REFN
Reserved
Reserved.
Always write 0
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The ADS112C04 is a precision, 16-bit, delta-sigma (ΔΣ), analog-to-digital converter (ADC) that offers many
integrated features to ease the measurement of the most common sensor types, including various types of
temperature and bridge sensors. Primary considerations when designing an application with the ADS112C04
include analog input filtering, establishing an appropriate external reference for ratiometric measurements, and
setting the absolute input voltage range for the internal PGA. Connecting and configuring the interface
appropriately is another concern. These considerations are discussed in the following sections.
9.1.1 Interface Connections
Figure 68 shows the principle interface connections for the ADS112C04.
GPIO/IRQ
DVSS
DVDD
SDA
SCL
Microcontroller with I2C Interface
0.1 PF
3.3 V
Rp
3.3 V
3.3 V
3.3 V
2 A1
SDA 15
3 RESET
Rp
SCL 16
Rp
3.3 V
1 A0
DRDY 14
4 DGND
DVDD 13
3.3 V
Device
5 AVSS
AVDD 12
6 AIN3
AIN0 11
7 AIN2
AIN1 10
8 REFN
3.3 V
0.1 PF
0.1 PF
REFP 9
Figure 68. Interface Connections
The ADS112C04 interfaces directly to standard-mode, fast-mode, or fast-mode plus I2C controllers. Any
microcontroller I2C peripheral, including master-only and single-master I2C peripherals, operates with the
ADS112C04. Details of the I2C communication protocol of the device can be found in the Programming section.
The ADS112C04 does not perform clock-stretching (that is, the device never pulls the clock line low), so this
function does not need to be provided for unless other clock-stretching devices are present on the same I2C bus.
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Application Information (continued)
Pullup resistors are required on both the SDA and SCL lines, as well as on the open-drain DRDY output. The
size of these resistors depends on the bus operating speed and capacitance of the bus lines. Higher-value
resistors yield lower power consumption when the bus lines are pulled low, but increase the transition times on
the bus, which limits the bus speed. Lower-value resistors allow higher interface speeds, but at the expense of
higher power consumption when the bus lines are pulled low. Long bus lines have higher capacitance and
require smaller pullup resistors to compensate. Do not use resistors that are too small because the bus drivers
may be unable to pull the bus lines low. See the I2C-Bus Specification and User Manual for details on pullup
resistor sizing.
9.1.2 Connecting Multiple Devices on the Same I2C Bus
Up to 16 ADS112C04 devices can be connected to a single I2C bus by using different address pin configurations
for each device. Use the address pins, A0 and A1, to set the ADS112C04 to one of 16 different I2C addresses.
Figure 69 shows an example with three ADS112C04 devices on the same I2C bus. One set of pullup resistors is
required per bus line. If needed, decrease the pullup resistor values to compensate for the additional bus
capacitance presented by multiple devices and increased line length.
GPIO/IRQ
DVDD
Rp
DVDD
1 A0
SCL 16
2 A1
SDA 15
3 RESET
DVDD
1 A0
SCL 16
2 A1
SDA 15
DRDY 14
3 RESET
DVDD
Rp
DVSS
DVDD
SDA
SCL
Microcontroller with I2C Interface
1 A0
SCL 16
2 A1
SDA 15
DRDY 14
3 RESET
DRDY 14
DVDD 13
4 DGND
DVDD 13
4 DGND
5 AVSS
AVDD 12
5 AVSS
AVDD 12
5 AVSS
AVDD 12
6 AIN3
AIN0 11
6 AIN3
AIN0 11
6 AIN3
AIN0 11
7 AIN2
AIN1 10
7 AIN2
AIN1 10
7 AIN2
AIN1 10
4 DGND
Device 1
8 REFN
Device 2
REFP 9
8 REFN
DVDD 13
Device 3
REFP 9
8 REFN
REFP 9
Figure 69. Connecting Multiple ADS112C04 Devices on the Same I2C Bus
9.1.3 Unused Inputs and Outputs
To minimize leakage currents on the analog inputs, leave unused analog and reference inputs floating, or
connect the inputs to mid-supply or to AVDD. Connecting unused analog or reference inputs to AVSS is possible
as well, but can yield higher leakage currents on other analog inputs than the previously mentioned options.
Do not float unused digital inputs; excessive power-supply leakage current can result. Tie all unused digital
inputs to the appropriate levels, DVDD or DGND, even when in power-down mode. Connections for unused
digital pins are:
• Tie the RESET pin to DVDD if the RESET pin is not used
• If the DRDY output is not used, leave the DRDY pin unconnected or tie the DRDY pin to DVDD using a weak
pullup resistor
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Application Information (continued)
9.1.4 Analog Input Filtering
Analog input filtering serves two purposes: first, to limit the effect of aliasing during the sampling process, and
second, to reduce external noise from being a part of the measurement.
As with any sampled system, aliasing can occur if proper antialias filtering is not in place. Aliasing occurs when
frequency components are present in the input signal that are higher than half the sampling frequency of the
ADC (also known as the Nyquist frequency). These frequency components are folded back and show up in the
actual frequency band of interest below half the sampling frequency. Inside a ΔΣ ADC, the input signal is
sampled at the modulator frequency fMOD and not at the output data rate. Figure 70 shows that the filter response
of the digital filter repeats at multiples of the sampling frequency (fMOD). Signals or noise up to a frequency where
the filter response repeats are attenuated to a certain amount by the digital filter depending on the filter
architecture. Any frequency components present in the input signal around the modulator frequency or multiples
thereof are not attenuated and alias back into the band of interest, unless attenuated by an external analog filter.
Magnitude
Sensor
Signal
Unwanted Signals
Unwanted Signals
Output
Data Rate
fMOD/2
f(MOD)
Frequency
f(MOD)
Frequency
f(MOD)
Frequency
Magnitude
Digital Filter
Aliasing of Unwanted
Signals
Output
Data Rate
fMOD/2
Magnitude
External
Antialiasing Filter
Roll-Off
Output
Data Rate
fMOD/2
Figure 70. Effect of Aliasing
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Application Information (continued)
Many sensor signals are inherently band limited; for example, the output of a thermocouple has a limited rate of
change. In this case the sensor signal does not alias back into the pass band when using a ΔΣ ADC. However,
any noise pick-up along the sensor wiring or the application circuitry can potentially alias into the pass band.
Power-line-cycle frequency and harmonics are one common noise source. External noise can also be generated
from electromagnetic interference (EMI) or radio frequency interference (RFI) sources, such as nearby motors
and cellular phones. Another noise source typically exists on the printed circuit board (PCB) itself in the form of
clocks and other digital signals. Analog input filtering helps remove unwanted signals from affecting the
measurement result.
A first-order resistor-capacitor (RC) filter is (in most cases) sufficient to either totally eliminate aliasing, or to
reduce the effect of aliasing to a level within the noise floor of the sensor. Ideally, any signal beyond fMOD / 2 is
attenuated to a level below the noise floor of the ADC. The digital filter of the ADS112C04 attenuates signals to a
certain degree, as illustrated in the filter response plots in the Digital Filter section. In addition, noise components
are usually smaller in magnitude than the the actual sensor signal. Therefore, using a first-order RC filter with a
cutoff frequency set at the output data rate or 10 times higher is generally a good starting point for a system
design.
Internal to the device, prior to the PGA inputs, is an EMI filter; see Figure 43. The cutoff frequency of this filter is
approximately 31.8 MHz, which helps reject high-frequency interferences.
9.1.5 External Reference and Ratiometric Measurements
The full-scale range (FSR) of the ADS112C04 is defined by the reference voltage and the PGA gain (FSR =
±VREF / Gain). An external reference can be used instead of the integrated 2.048-V reference to adapt the FSR to
the specific system needs. An external reference must be used if VIN is greater than 2.048 V. For example, an
external 5-V reference and an AVDD = 5 V are required in order to measure a single-ended signal that can swing
between 0 V and 5 V.
The reference inputs of the device also allow the implementation of ratiometric measurements. In a ratiometric
measurement the same excitation source that is used to excite the sensor is also used to establish the reference
for the ADC. As an example, a simple form of a ratiometric measurement uses the same current source to excite
both the resistive sensor element (such as an RTD) and another resistive reference element that is in series with
the element being measured. The voltage that develops across the reference element is used as the reference
source for the ADC. These components cancel out in the ADC transfer function because current noise and drift
are common to both the sensor measurement and the reference. The output code is only a ratio of the sensor
element and the value of the reference resistor. The value of the excitation current source itself is not part of the
ADC transfer function.
9.1.6 Establishing Proper Limits on the Absolute Input Voltage
The ADS112C04 can be used to measure various types of input signal configurations: single-ended, pseudodifferential, and fully differential signals (which can be either unipolar or bipolar). However, configuring the device
properly for the respective signal type is important.
Signals where the negative analog input is fixed and referenced to analog ground (VAINN = 0 V) are commonly
called single-ended signals. If the PGA is disabled and bypassed, the absolute input voltages of the ADS112C04
can be as low as 100 mV below AVSS and as large as 100 mV above AVDD. Therefore, the PGA_BYPASS bit
must be set in order to measure single-ended signals when a unipolar analog supply is used (AVSS = 0 V).
Gains of 1, 2, and 4 are still possible in this configuration. Measuring a 0-mA to 20-mA or 4-mA to 20-mA signal
across a load resistor of 100 Ω referenced to GND is a typical example. The ADS112C04 can directly measure
the signal across the load resistor using a unipolar supply, the internal 2.048-V reference, and gain = 1 when the
PGA is bypassed.
If gains larger than 4 are needed to measure a single-ended signal, the PGA must be enabled. In this case, a
bipolar supply is required for the ADS112C04 to meet the absolute input voltage requirement of the PGA.
Signals where the negative analog input (AINN) is fixed at a voltage other the 0 V are referred to as pseudodifferential signals.
Fully differential signals in contrast are defined as signals having a constant common-mode voltage where the
positive and negative analog inputs swing 180° out-of-phase but have the same amplitude.
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Application Information (continued)
The ADS112C04 can measure pseudo-differential and fully differential signals with the PGA enabled or
bypassed. However, the PGA must be enabled in order to use gains greater than 4. The absolute input voltages
of the input signal must meet the absolute input voltage restrictions of the PGA (as explained in the PGA Input
Voltage Requirements section) when the PGA is enabled. Setting the common-mode voltage at or near (AVSS +
AVDD) / 2 in most cases satisfies the PGA absolute input voltage requirements.
Signals where both the positive and negative inputs are always ≥ 0 V are called unipolar signals. These signals
can in general be measured with the ADS112C04 using a unipolar analog supply (AVSS = 0 V). As mentioned
previously, the PGA must be bypassed in order to measure single-ended, unipolar signals when using a unipolar
supply.
A signal is called bipolar when either the positive or negative input can swing below 0 V. A bipolar analog supply
(such as AVDD = 2.5 V, AVSS = –2.5 V) is required in order to measure bipolar signals with the ADS112C04. A
typical application task is measuring a single-ended, bipolar, ±10-V signal where AINN is fixed at 0 V and AINP
swings between –10 V and 10 V. The ADS112C04 cannot directly measure this signal because the 10 V
exceeds the analog power-supply limits. However, one possible solution is to use a bipolar analog supply (AVDD
= 2.5 V, AVSS = –2.5 V), gain = 1, and a resistor divider in front of the ADS112C04. The resistor divider must
divide the voltage down to ≤ ±2.048 V in order to measure the voltage using the internal 2.048-V reference.
9.1.7 Pseudo Code Example
The following list shows a pseudo code sequence with the required steps to set up the device and the
microcontroller that interfaces to the ADC in order to take subsequent readings from the ADS112C04 in
continuous conversion mode. The DRDY pin is used to indicate availability of new conversion data. The default
configuration register settings are changed to gain = 16, continuous conversion mode. This example shows data
collection using manual data read mode.
Power-up;
Delay to allow power supplies to settle and power-on reset to complete; minimum of 500 µs;
Configure the I2C interface of the microcontroller;
Configure the microcontroller GPIO connected to the DRDY pin as a falling edge triggered interrupt
input;
Send the RESET command (06h) to make sure the device is properly reset after power-up;
Write the respective register configurations with the WREG command (40h, 08h, 42h, 08h);
As an optional sanity check, read back all configuration registers with the RREG command (2xh);
Send the START/SYNC command (08h) to start converting in continuous conversion mode;
Loop
{
Wait for DRDY to transition low;
Send the RDATA command (10h) to read 2 bytes of conversion data;
}
Send the POWERDOWN command (02h) to stop conversions and put the device in power-down mode;
TI recommends running an offset calibration before performing any measurements or when changing the gain of
the PGA. The internal offset of the device can, for example, be measured by shorting the inputs to mid-supply
(MUX[3:1] = 1110). The microcontroller then takes multiple readings from the device with the inputs shorted and
stores the average value in the microcontroller memory. When measuring the sensor signal, the microcontroller
then subtracts the stored offset value from each device reading to obtain an offset compensated result; the offset
can be either positive or negative in value.
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9.2 Typical Applications
9.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)
Figure 71 shows the basic connections of a thermocouple measurement system when using an external highprecision temperature sensor for cold-junction compensation. Apart from the thermocouple itself, the only
external circuitry required are two biasing resistors, a simple low-pass, antialiasing filter, and the power-supply
decoupling capacitors.
3.3 V
3.3 V
0.1 PF
0.1 PF
3.3 V
Isothermal Block
REFP
RB2
10 A to
1.5 mA
CCM2
RF2
REFN
AVDD
AIN0
DVDD
2.048-V
Reference
Reference
Mux
TI Device
CDIF
RF1
SCL
AIN1
AINP
Thermocouple
RB1
CCM1
SDA
MUX
3.3 V
AIN2
16-Bit
û ADC
PGA
Digital Filter
and
I2C Interface
AINN
A0
A1
DRDY
RESET
VDD
LM94022
GS1
AIN3
OUT
GS0
Precision
Temperature
Sensor
Low-Drift
Oscillator
GND
AVSS
DGND
Cold-Junction
Compensation
Figure 71. Thermocouple Measurement
9.2.1.1 Design Requirements
Table 24. Design Requirements
DESIGN PARAMETER
(1)
VALUE
Supply voltage
3.3 V
Reference voltage
Internal 2.048-V reference
Update rate
≥10 readings per second
Thermocouple type
K
Temperature measurement range
–200°C to +1250°C
Measurement accuracy at TA = 25°C (1)
0.5°C
Not accounting for the error of the thermocouple and cold-junction temperature measurement; offset
calibration at T(TC) = T(CJ) = 25°C; no gain calibration.
9.2.1.2 Detailed Design Procedure
The biasing resistors RB1 and RB2 are used to set the common-mode voltage of the thermocouple such that the
input voltages do not exceed the absolute input voltage range of the PGA (in this example, to mid-supply AVDD /
2). If the application requires the thermocouple to be biased to GND, either a bipolar supply (for example, AVDD
= 2.5 V and AVSS = –2.5 V) must be used for the device to meet the absolute input voltage requirement of the
PGA, or the PGA must be bypassed. When choosing the values of the biasing resistors, care must be taken so
that the biasing current does not degrade measurement accuracy. The biasing current flows through the
thermocouple and can cause self-heating and additional voltage drops across the thermocouple leads. Typical
values for the biasing resistors range from 1 MΩ to 50 MΩ.
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In addition to biasing the thermocouple, RB1 and RB2 are also useful for detecting an open thermocouple lead.
When one of the thermocouple leads fails open, the biasing resistors pull the analog inputs (AIN0 and AIN1) to
AVDD and AVSS, respectively. The ADC consequently reads a full-scale value, which is outside the normal
measurement range of the thermocouple voltage, to indicate this failure condition.
Although the device digital filter attenuates high-frequency components of noise, performance can be further
improved by providing a first-order, passive RC filter at the inputs. Equation 9 calculates the cutoff frequency that
is created by the differential RC filter formed by RF1, RF2, and the differential capacitor CDIF.
fC = 1 / [2π · (RF1 + RF2) · CDIF]
(9)
Two common-mode filter capacitors (CM1 and CM2) are also added to offer attenuation of high-frequency,
common-mode noise components. Choose a differential capacitor CDIF that is at least an order of magnitude (10
times) larger than the common-mode capacitors (CM1 and CM2) because mismatches in the common-mode
capacitors can convert common-mode noise into differential noise.
The filter resistors RF1 and RF2 also serve as current-limiting resistors. These resistors limit the current into the
analog inputs (AIN0 and AIN1) of the device to safe levels if an overvoltage on the inputs occur. Care must be
taken when choosing the filter resistor values because the input currents flowing into and out of the device cause
a voltage drop across the resistors. This voltage drop shows up as an additional offset error at the ADC inputs.
TI therefore recommends limiting the filter resistor values to below 1 kΩ.
The filter component values used in this design are: RF1 = RF2 = 1 kΩ, CDIF = 100 nF, and CCM1 = CCM2 = 10 nF.
The highest measurement resolution is achieved when matching the largest potential input signal to the FSR of
the ADC by choosing the highest possible gain. From the design requirement, the maximum thermocouple
voltage occurs at T(TC) = 1250°C and is V(TC) = 50.644 mV as defined in the tables published by the National
Institute of Standards and Technology (NIST) using a cold-junction temperature of T(CJ) = 0°C. A thermocouple
produces an output voltage that is proportional to the temperature difference between the thermocouple tip and
the cold junction. If the cold junction is at a temperature below 0°C, the thermocouple produces a voltage larger
than 50.644 mV. The isothermal block area is constrained by the operating temperature range of the device.
Therefore, the isothermal block temperature is limited to –40°C. A K-type thermocouple at T(TC) = 1250°C
produces an output voltage of V(TC) = 50.644 mV – (–1.527 mV) = 52.171 mV when referenced to a cold-junction
temperature of T(CJ) = –40°C. The maximum gain that can be applied when using the internal 2.048-V reference
is then calculated as (2.048 V / 52.171 mV) = 39.3. The next smaller PGA gain setting that the device offers is
32.
The device integrates a high-precision temperature sensor that can be used to measure the temperature of the
cold junction. To measure the internal temperature of the ADS112C04, the device must be set to internal
temperature sensor mode by setting the TS bit to 1 in the configuration register. For best performance, careful
board layout is critical to achieve good thermal conductivity between the cold junction and the device package.
However, the device does not perform automatic cold-junction compensation of the thermocouple. This
compensation must be done in the microcontroller that interfaces to the device. The microcontroller requests one
or multiple readings of the thermocouple voltage from the device and then sets the device to internal temperature
sensor mode (TS = 1) to acquire the temperature of the cold junction. An algorithm similar to the following must
be implemented on the microcontroller to compensate for the cold-junction temperature:
1. Measure the thermocouple voltage, V(TC), between AIN0 and AIN1
2. Measure the temperature of the cold junction, T(CJ), using the temperature sensor mode of the ADS112C04
3. Convert the cold-junction temperature into an equivalent thermoelectric voltage, V(CJ), using the tables or
equations provided by NIST
4. Add V(TC) and V(CJ) and translate the summation back into a thermocouple temperature using the NIST tables
or equations again
In some applications, the integrated temperature sensor of the ADS112C04 cannot be used (for example, if the
accuracy is not high enough or if the device cannot be placed close enough to the cold junction). The additional
analog input channels of the device can be used in this case to measure the cold-junction temperature with a
thermistor, RTD, or an analog temperature sensor. Figure 71 illustrates the LM94022 temperature sensor being
used for cold-junction compensation.
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As shown in Equation 10, the rms noise of the ADS112C04 at gain = 32 and DR = 20 SPS (1.95 µVrms) is
divided by the average sensitivity of a K-type thermocouple (41 µV/°C) to obtain an approximation of the
achievable temperature resolution.
Temperature Resolution = 1.95 µV / 41 µV/°C = 0.05°C
(10)
Table 25 shows the register settings for this design.
Table 25. Register Settings
(1)
REGISTER
SETTING
00h
0Ah
AINP = AIN0, AINN = AIN1, gain = 32, PGA enabled (1)
DESCRIPTION
01h
08h
DR = 20 SPS, normal mode, continuous conversion mode, internal
reference
02h
00h
Conversion data counter disabled, data integrity disabled, burnout
current sources disabled, IDACs off
03h
00h
No IDACs used
To measure the cold junction temperature using the LM90422, change register 00h to B1h (AINP =
AIN3, AINN = AVSS, gain = 1, PGA disabled).
9.2.1.3 Application Curves
Figure 72 and Figure 73 show the measurement results. The measurements are taken at TA = T(CJ) = 25°C. A
system offset calibration is performed at T(TC) = 25°C, which translates to a V(TC) = 0 V when T(CJ) = 25°C. No
gain calibration is implemented. The data in Figure 72 are taken using a precision voltage source as the input
signal instead of a thermocouple. The respective temperature measurement error in Figure 73 is calculated from
the data in Figure 72 using the NIST tables.
0.01
0.2
0.005
0.1
Measurement Error (°C)
Measurement Error (mV)
The design meets the required temperature measurement accuracy given in Table 24. The measurement error
shown in Figure 73 does not include the error of the thermocouple itself nor the measurement error of the coldjunction temperature. Those two error sources are in general larger than 0.2°C and therefore, in many cases,
dominate the overall system measurement accuracy.
0
-0.005
-0.01
-10
0
10
20
30
Thermocouple Voltage (mV)
40
50
0
-0.1
-0.2
-200
D002
Figure 72. Voltage Measurement Error vs V(TC)
0
200
400
600
Temperature (°C)
800
1000
1200
D001
Figure 73. Temperature Measurement Error vs T(TC)
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9.2.2 3-Wire RTD Measurement (–200°C to +850°C)
The ADS112C04 integrates all necessary features (such as dual-matched programmable current sources,
buffered reference inputs, and a PGA) to ease the implementation of ratiometric 2-, 3-, and 4-wire RTD
measurements. Figure 74 shows a typical implementation of a ratiometric 3-wire RTD measurement using the
excitation current sources integrated in the device to excite the RTD as well as to implement automatic RTD
lead-resistance compensation.
RREF
IIDAC1 + IIDAC2
3.3 V
RF3
0.1 PF
10 PA to
1.5 mA
RLEAD3
RLEAD2
RF4
3.3 V
CDIF2
AVDD
0.1 PF
REFN
REFP
DVDD
CCM2
RF2
AIN0
3-Wire RTD
2.048-V
Reference
Reference
Mux
TI Device
CDIF1
RLEAD1
RF1
SCL
AIN1
AINP
SDA
CCM1
MUX
AIN2
16-Bit
û ADC
PGA
Digital Filter
and
I2C Interface
AINN
AIN3
A1
DRDY
(IDAC1)
(IDAC2)
A0
RESET
Precision
Temperature
Sensor
Low-Drift
Oscillator
DGND
AVSS
Figure 74. 3-Wire RTD Measurement
9.2.2.1 Design Requirements
Table 26. Design Requirements
(1)
DESIGN PARAMETER
VALUE
Supply voltage
3.3 V
Update rate
20 readings per second
RTD type
3-wire Pt100
Maximum RTD lead resistance
15 Ω
RTD excitation current
500 µA
Temperature measurement range
–200°C to +850°C
Measurement accuracy at TA = 25°C (1)
±0.2°C
Not accounting for the error of RTD; offset calibration is performed with RRTD = 100 Ω; no gain
calibration.
9.2.2.2 Detailed Design Procedure
The circuit in Figure 74 employs a ratiometric measurement approach. In other words, the sensor signal (that is,
the voltage across the RTD in this case) and the reference voltage for the ADC are derived from the same
excitation source. Therefore, errors resulting from temperature drift or noise of the excitation source cancel out
because these errors are common to both the sensor signal and the reference.
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In order to implement a ratiometric 3-wire RTD measurement using the device, IDAC1 is routed to one of the
leads of the RTD and IDAC2 is routed to the second RTD lead. Both currents have the same value, which is
programmable by the IDAC[2:0] bits in the configuration register. The design of the device ensures that both
IDAC values are closely matched, even across temperature. The sum of both currents flows through a precision,
low-drift reference resistor, RREF. The voltage, VREF, generated across the reference resistor (as shown in
Equation 11) is used as the ADC reference voltage. Equation 11 reduces to Equation 12 because IIDAC1 = IIDAC2.
VREF = (IIDAC1 + IIDAC2) · RREF
VREF = 2 · IIDAC1 · RREF
(11)
(12)
To simplify the following discussion, the individual lead resistance values of the RTD (RLEADx) are set to zero. As
Equation 13 shows, only IDAC1 excites the RTD to produce a voltage (VRTD) proportional to the temperaturedependent RTD value and the IDAC1 value.
VRTD = RRTD (at temperature) · IIDAC1
(13)
The device internally amplifies the voltage across the RTD using the PGA and compares the resulting voltage
against the reference voltage to produce a digital output code proportional to Equation 14 through Equation 16:
Code ∝ VRTD · Gain / VREF
Code ∝ (RRTD (at temperature) · IIDAC1 · Gain) / (2 · IIDAC1 · RREF)
Code ∝ (RRTD (at temperature) · Gain) / (2 · RREF)
(14)
(15)
(16)
As shown in Equation 16, the output code only depends on the value of the RTD, the PGA gain, and the
reference resistor (RREF), but not on the IDAC1 value. The absolute accuracy and temperature drift of the
excitation current therefore does not matter. However, because the value of the reference resistor directly affects
the measurement result, choosing a reference resistor with a very low temperature coefficient is important to limit
errors introduced by the temperature drift of RREF.
The second IDAC2 is used to compensate for errors introduced by the voltage drop across the lead resistance of
the RTD. All three leads of a 3-wire RTD typically have the same length and, thus, the same lead resistance.
Also, IDAC1 and IDAC2 have the same value. Taking the lead resistance into account, use Equation 17 to
calculate the differential voltage (VIN) across the ADC inputs (AIN0 and AIN1):
VIN = IIDAC1 · (RRTD + RLEAD1) – IIDAC2 · RLEAD2
(17)
Equation 17 reduces to Equation 18 when RLEAD1 = RLEAD2 and IIDAC1 = IIDAC2:
VIN = IIDAC1 · RRTD
(18)
In other words, the measurement error resulting from the voltage drop across the RTD lead resistance is
compensated, as long as the lead resistance values and the IDAC values are well matched.
A first-order differential and common-mode RC filter (RF1, RF2, CDIF1, CCM1, and CCM2) is placed on the ADC
inputs, as well as on the reference inputs (RF3, RF4, CDIF2, CCM3, and CCM4). The same guidelines for designing
the input filter apply as described in the K-Type Thermocouple Measurement section. Match the corner
frequencies of the input and reference filter for best performance. For more detailed information on matching the
input and reference filter, see the RTD Ratiometric Measurements and Filtering Using the ADS1148 and
ADS1248 application report.
The reference resistor RREF not only serves to generate the reference voltage for the device, but also sets the
voltages at the leads of the RTD to within the specified absolute input voltage range of the PGA.
When designing the circuit, care must also be taken to meet the compliance voltage requirement of the IDACs.
The IDACs require that the maximum voltage drop developed across the current path to AVSS be equal to or
less than AVDD – 0.9 V in order to operate accurately. This requirement means that Equation 19 must be met at
all times.
AVSS + IIDAC1 · (RLEAD1 + RRTD) + (IIDAC1 + IIDAC2) · (RLEAD3 + RREF) ≤ AVDD – 0.9 V
(19)
The device also offers the possibility to route the IDACs to the same inputs used for measurement. If the filter
resistor values RF1 and RF2 in Figure 74 are small enough and well matched, then IDAC1 can be routed to AIN1
and IDAC2 to AIN0. In this manner, even two 3-wire RTDs sharing the same reference resistor can be measured
with a single device.
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As stated in Table 26, this design example discusses the implementation of a 3-wire Pt100 measurement to be
used to measure temperatures ranging from –200°C to +850°C. The excitation current for the Pt100 is chosen as
IIDAC1 = 500 µA, which means a combined current of 1 mA is flowing through the reference resistor, RREF. As
mentioned previously, besides creating the reference voltage for the ADS112C04, the voltage across RREF also
sets the absolute input voltages for the RTD measurement. In general, choose the largest reference voltage
possible that maintains the compliance voltage of the IDACs and meets the absolute input voltage requirement of
the PGA. Setting the common-mode voltage at or near half the analog supply (in this case 3.3 V / 2 = 1.65 V) in
most cases satisfies the absolute input voltage requirements of the PGA. Equation 20 is then used to calculate
the value for RREF:
RREF = VREF / (IIDAC1 + IIDAC2) = 1.65 V / 1 mA = 1.65 kΩ
(20)
The stability of RREF is critical to achieve good measurement accuracy over temperature and time. Choosing a
reference resistor with a temperature coefficient of ±10 ppm/°C or better is advisable. If a 1.65-kΩ value is not
readily available, another value near 1.65 kΩ (such as 1.62 kΩ or 1.69 kΩ) can certainly be used as well.
As a last step, the PGA gain must be selected in order to match the maximum input signal to the FSR of the
ADC. The resistance of a Pt100 increases with temperature. Therefore, the maximum voltage to be measured
(VINMAX) occurs at the positive temperature extreme. At 850°C, a Pt100 has an equivalent resistance of
approximately 391 Ω as per the NIST tables. The voltage across the Pt100 equates to Equation 21:
VINMAX = VRTD (at 850°C) = RRTD (at 850°C) · IIDAC1 = 391 Ω · 500 µA = 195.5 mV
(21)
The maximum gain that can be applied when using a 1.65-V reference is then calculated as (1.65 V / 195.5 mV)
= 8.4. The next smaller PGA gain setting available in the ADS112C04 is 8. At a gain of 8, the ADS112C04 offers
a FSR value as described in Equation 22:
FSR = ±VREF / Gain = ±1.65 V / 8 = ±206.25 mV
(22)
This range allows for margin with respect to initial accuracy and drift of the IDACs and reference resistor.
After selecting the values for the IDACs, RREF, and PGA gain, make sure to double check that the settings meet
the absolute input voltage requirements of the PGA and the compliance voltage of the IDACs. To determine the
true absolute input voltages at the ADC inputs (AIN0 and AIN1), the lead resistance must be taken into account
as well.
The smallest absolute input voltage occurs on AIN0 at the lowest measurement temperature (–200°C) with
RLEADx = 0 Ω, and is equal to VREF = 1.65 V.
The minimum absolute input voltage must not exceed the limit set in Equation 7 to meet Equation 23:
VAIN0
(MIN)
≥ AVSS + 0.2 V + |VINMAX| · (Gain – 4) / 8 = 0 V + 0.2 V + 97.75 mV = 297.75 mV
(23)
The restriction is satisfied with VAIN0 = 1.65 V.
The largest absolute input voltage (calculated using Equation 24 and Equation 25) occurs on AIN1 at the highest
measurement temperature (850°C).
VAIN1 (MAX) = VREF + (IIDAC1 + IIDAC2) · RLEAD3 + IIDAC1 · (RLEAD1 + RRTD (at 850°C))
VAIN1 (MAX) = 1.65 V + 1 mA · 15 Ω + 500 µA · (15 Ω + 391 Ω) = 1.868 V
VAIN1
(24)
(25)
(MAX)
meets the requirement given by Equation 7 and equates to Equation 26 in this design:
VAINP
(MAX)
≤ AVDD – 0.2 V – |VINMAX| · (Gain – 4) / 8 = 3.3 V – 0.2 V – 97.75 mV = 3.002 V
(26)
The restriction on the compliance voltage (AVDD – 0.9 V = 3.3 V – 0.9 V = 2.4 V) of IDAC1 is met as well.
Table 27 shows the register settings for this design.
Table 27. Register Settings
56
REGISTER
SETTING
00h
36h
AINP = AIN1, AINN = AIN0, gain = 8, PGA enabled
DESCRIPTION
01h
0Ah
DR = 20 SPS, normal mode, continuous conversion mode, external
reference
02h
55h
Conversion data counter disabled, data integrity disabled, burnout
current sources disabled, IDAC = 500 µA
03h
70h
IDAC1 = AIN2, IDAC2 = AIN3
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9.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements
Implementing a 2- or 4-wire RTD measurement is very similar to the 3-wire RTD measurement illustrated in
Figure 74, except that only one IDAC is required.
Figure 75 shows a typical circuit implementation of a 2-wire RTD measurement. The main difference compared
to a 3-wire RTD measurement is with respect to the lead resistance compensation. The voltage drop across the
lead resistors, RLEAD1 and RLEAD2, in this configuration is directly part of the measurement (as shown in
Equation 27) because there is no means to compensate the lead resistance by use of the second current source.
Any compensation must be done by calibration.
VIN = IIDAC1 · (RLEAD1 + RRTD + RLEAD2)
(27)
RREF
IIDAC1
3.3 V
RF3
RLEAD2
RF2
2-Wire RTD
CCM2
3.3 V
RF4
CDIF2
0.1 PF
10 PA to
1.5 mA
AVDD
AIN0
0.1 PF
REFP
2.048-V
Reference
REFN
DVDD
Reference
Mux
TI Device
16-Bit
û ADC
Digital Filter
and
I2C Interface
CDIF1
RLEAD1
RF1
SCL
AIN1
SDA
AINP
CCM1
MUX
PGA
A0
A1
AINN
AIN2
DRDY
RESET
Precision
Temperature
Sensor
AIN3
(IDAC1)
Low-Drift
Oscillator
AVSS
DGND
Figure 75. 2-Wire RTD Measurement
Figure 76 shows a typical circuit implementation of a 4-wire RTD measurement. Similar to the 2-wire RTD
measurement, only one IDAC is required for exciting and measuring a 4-wire RTD in a ratiometric manner. The
main benefit of using a 4-wire RTD is that the ADC inputs are connected to the RTD in the form of a Kelvin
connection. Apart from the input leakage currents of the ADC, there is no current flow through the lead resistors
RLEAD2 and RLEAD3 and therefore no voltage drop is created across them. The voltage at the ADC inputs
consequently equals the voltage across the RTD and the lead resistance is of no concern.
RREF
IIDAC1
3.3 V
RF3
0.1 PF
10 PA to
1.5 mA
RLEAD4
RLEAD3
RF2
4-Wire RTD
RF4
3.3 V
CDIF2
AVDD
0.1 PF
REFP
REFN
DVDD
CCM2
AIN0
2.048-V
Reference
Reference
Mux
TI Device
CDIF1
RLEAD2
RF1
SCL
AIN1
AINP
SDA
CCM1
MUX
RLEAD1
AIN2
PGA
16-Bit
û ADC
Digital Filter
and
I2C Interface
AINN
A0
A1
DRDY
RESET
AIN3
(IDAC1)
Precision
Temperature
Sensor
AVSS
Low-Drift
Oscillator
DGND
Figure 76. 4-Wire RTD Measurement
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As shown in Equation 28, the transfer function of a 2- and 4-wire RTD measurement differs compared to the one
of a 3-wire RTD measurement by a factor of 2 because only one IDAC is used and only one IDAC flows through
the reference resistor, RREF.
Code ∝ (RRTD (at Temperature) · Gain) / RREF
(28)
In addition, the input common-mode voltage and reference voltage is reduced compared to the 3-wire RTD
configuration. Therefore, some further modifications may be required in case the 3-wire RTD design is used to
measure 2- and 4-wire RTDs as well. If the decreased absolute input voltages does not meet the minimum
absolute voltage requirements of the PGA anymore, either increase the value of RREF by switching in a larger
resistor or, alternatively, increase the excitation current and decrease the gain at the same time.
9.2.2.3 Application Curves
Figure 77 and Figure 78 show the measurement results. The measurements are taken at TA = 25°C. A system
offset calibration is performed using a reference resistor of 100 Ω. No gain calibration is implemented. The data
in Figure 77 are taken using precision resistors instead of a 3-wire Pt100. The respective temperature
measurement error in Figure 78 is calculated from the data in Figure 77 using the NIST tables.
0.1
0.2
0.05
0.1
Measurement Error (°C)
Measurement Error (:)
The design meets the required temperature measurement accuracy given in Table 26. However, the
measurement error shown in Figure 78 does not include the error of the RTD itself.
0
-0.05
-0.1
0
50
100
150
200
250
RTD Value (:)
300
350
400
-0.1
-0.2
-200
D003
Figure 77. Resistance Measurement Error vs RRTD
58
0
0
200
400
600
Temperature (°C)
800
1000
D004
Figure 78. Temperature Measurement Error vs T(RTD)
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9.2.3 Resistive Bridge Measurement
The device offers several features to ease the implementation of ratiometric bridge measurements (such as a
PGA with gains up to 128, buffered, and differential reference inputs).
5.0 V
3.3 V
5.0 V
CDIF2
0.1 PF
10 PA to
1.5 mA
RF2
REFP(1)
AVDD
2.048-V
Reference
AIN0
5.0 V
0.1 PF
REFN(1)
Reference
Mux
DVDD
TI Device
CCM2
SCL
AIN1
SDA
AINP
CDIF1
MUX
RF1
AIN2
16-Bit
û ADC
PGA
Digital Filter
and
I2C Interface
AINN
A1
DRDY
RESET
CCM1
AIN3
Precision
Temperature
Sensor
Low-Drift
Oscillator
AVSS
(1)
A0
DGND
Connect reference inputs directly to the bridge excitation voltage through Kelvin connections.
Figure 79. Resistive Bridge Measurement
9.2.3.1 Design Requirements
Table 28. Design Requirements
DESIGN PARAMETER
VALUE
Analog supply voltage
5.0 V
Digital supply voltage
3.3 V
Load cell type
4-wire load cell
Load cell maximum capacity
1 kg
Load cell sensitivity
3 mV/V
Excitation voltage
5V
Noise-free counts
8000
9.2.3.2 Detailed Design Procedure
As shown in Figure 79, the bridge excitation voltage is simultaneously used as the reference voltage for the ADC
to implement a ratiometric bridge measurement. With this configuration, any drift in excitation voltage also shows
up on the reference voltage, consequently canceling out drift error. Either the dedicated reference inputs can be
used, or the analog supply can be used as the reference if the supply is used to excite the bridge.
The PGA offers gains up to 128, which helps amplify the small differential bridge output signal to make optimal
use of the ADC full-scale range. Using a symmetrical bridge with the excitation voltage equal to the supply
voltage of the device ensures that the output signal of the bridge meets the absolute input voltage requirement of
the PGA.
Using a 3-mV/V load cell with a 5-V excitation yields a maximum differential voltage at the ADC inputs of VINMAX
= 15 mV at maximum load. Equation 29 then calculates the maximum gain that can be used.
Gain ≤ VREF / VINMAX = 5 V / 15 mV = 333.3
(29)
Accordingly, gain = 128 is used in this example.
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A first-order differential and common-mode RC filter (RF1, RF2, CDIF1, CCM1, and CCM2) is placed on the ADC
inputs. The reference has an additional capacitor CDIF2 to limit reference noise. Care must be taken to maintain a
limited amount of filtering or the measurement is no longer ratiometric.
The device is capable of 16-bit, noise-free resolution using a gain of 128 at 20 SPS for the specified reference
voltage. Accordingly, the device is able to resolve signals as small as one LSB. Use Equation 30 to calculate the
LSB size:
1 LSB = (2 · VREF / Gain) / 216 = (2 · 5.0 V / 128) / 216 = 1.192 µV
(30)
To find the total number of counts available for the bridge measurement, the maximum output voltage is divided
by the LSB value. Dividing 10 mV by 1.192 µV equates to 8389 total counts available, which meets the design
parameter of 8000 counts.
Table 29 shows the register settings for this design.
Table 29. Register Settings
60
REGISTER
SETTING
00h
4Eh
AINP = AIN1, AINN = AIN2, gain = 128, PGA enabled
DESCRIPTION
01h
0Ah
DR = 20 SPS, normal mode, continuous conversion mode, external
reference
02h
98h
Conversion data counter disabled, data integrity disabled, burnout
current sources disabled, IDACs off
03h
00h
No IDACs used
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10 Power Supply Recommendations
The device requires two power supplies: analog (AVDD, AVSS) and digital (DVDD, DGND). The analog power
supply can be bipolar (for example, AVDD = 2.5 V, AVSS = –2.5 V) or unipolar (for example, AVDD = 3.3 V,
AVSS = 0 V) and is independent of the digital power supply. The digital supply sets the digital I/O levels.
10.1 Power-Supply Sequencing
The power supplies can be sequenced in any order, but in no case must any analog or digital inputs exceed the
respective analog or digital power-supply voltage and current limits. Wait approximately 500 µs after all power
supplies are stabilized before communicating with the device to allow the power-on reset process to complete.
10.2 Power-Supply Decoupling
Good power-supply decoupling is important to achieve optimum performance. As shown in Figure 80 and
Figure 81, AVDD, AVSS (when using a bipolar supply), and DVDD must be decoupled with at least a 0.1-µF
capacitor. Place the bypass capacitors as close to the power-supply pins of the device as possible using lowimpedance connections. TI recommends using multi-layer ceramic chip capacitors (MLCCs) that offer low
equivalent series resistance (ESR) and inductance (ESL) characteristics for power-supply decoupling purposes.
For very sensitive systems, or for systems in harsh noise environments, avoiding the use of vias for connecting
the capacitors to the device pins may offer superior noise immunity. The use of multiple vias in parallel lowers
the overall inductance and is beneficial for connections to ground planes. Connect analog and digital grounds
together as close to the device as possible.
1 A0
SCL 16
2 A1
1 A0
SDA 15
3 RESET
2 A1
3.3 V
DRDY 14
4 DGND
DVDD 13
3.3 V
DRDY 14
4 DGND
DVDD 13
Device
AVDD 12
6 AIN3
AIN0 11
8 REFN
SDA 15
3 RESET
Device
5 AVSS
7 AIN2
SCL 16
3.3 V
0.1 PF
0.1 PF
-2.5 V
0.1 PF
AIN1 10
5 AVSS
AVDD 12
6 AIN3
AIN0 11
7 AIN2
REFP 9
8 REFN
Figure 80. Unipolar Analog Power Supply
2.5 V
0.1 PF
0.1 PF
AIN1 10
REFP 9
Figure 81. Bipolar Analog Power Supply
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11 Layout
11.1 Layout Guidelines
Employing best design practices is recommended when laying out a printed-circuit board (PCB) for both analog
and digital components. This recommendation generally means that the layout separates analog components
[such as ADCs, amplifiers, references, digital-to-analog converters (DACs), and analog MUXs] from digital
components [such as microcontrollers, complex programmable logic devices (CPLDs), field-programmable gate
arrays (FPGAs), radio frequency (RF) transceivers, universal serial bus (USB) transceivers, and switching
regulators]. Figure 82 shows an example of good component placement. Although Figure 82 provides a good
example of component placement, the best placement for each application is unique to the geometries,
components, and PCB fabrication capabilities employed. That is, there is no single layout that is perfect for every
design and careful consideration must always be used when designing with any analog component.
Ground Fill or
Ground Plane
Supply
Generation
Microcontroller
Device
Optional: Split
Ground Cut
Signal
Conditioning
(RC Filters
and
Amplifiers)
Ground Fill or
Ground Plane
Optional: Split
Ground Cut
Ground Fill or
Ground Plane
Interface
Transceiver
Connector
or Antenna
Ground Fill or
Ground Plane
Figure 82. System Component Placement
The following basic recommendations for layout of the ADS112C04 help achieve the best possible performance
of the ADC. A good design can be ruined with a bad circuit layout.
• Separate analog and digital signals. To start, partition the board into analog and digital sections where the
layout permits. Routing digital lines away from analog lines prevents digital noise from coupling back into
analog signals.
• The ground plane can be split into an analog plane (AGND) and digital plane (DGND), but is not necessary.
Place digital signals over the digital plane, and analog signals over the analog plane. As a final step in the
layout, the split between the analog and digital grounds must be connected to together at the ADC.
• Fill void areas on signal layers with ground fill.
• Provide good ground return paths. Signal return currents flow on the path of least impedance. If the ground
plane is cut or has other traces that block the current from flowing right next to the signal trace, another path
must be found to return to the source and complete the circuit. If forced into a larger path, the chance that the
signal radiates increases. Sensitive signals are more susceptible to EMI interference.
• Use bypass capacitors on supplies to reduce high-frequency noise. Do not place vias between bypass
capacitors and the active device. Placing the bypass capacitors on the same layer as close to the active
device yields the best results.
• Consider the resistance and inductance of the routing. Often, traces for the inputs have resistances that react
with the input bias current and cause an added error voltage. Reducing the loop area enclosed by the source
signal and the return current reduces the inductance in the path. Reducing the inductance reduces the EMI
pickup and reduces the high-frequency impedance at the input of the device.
• Watch for parasitic thermocouples in the layout. Dissimilar metals going from each analog input to the sensor
can create a parasitic thermocouple that can add an offset to the measurement. Differential inputs must be
matched for both the inputs going to the measurement source.
• Analog inputs with differential connections must have a capacitor placed differentially across the inputs. Best
input combinations for differential measurements use adjacent analog input lines (such as AIN0, AIN1 and
AIN2, AIN3). The differential capacitors must be of high quality. The best ceramic chip capacitors are C0G
(NPO) that have stable properties and low noise characteristics.
62
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REFP
REFN
11.2 Layout Example
Vias connect to either the bottom layer or
an internal plane. The bottom layer or
internal plane are dedicated GND planes
(GND = DGND = AVSS).
AIN1
AIN2
AIN0
10: AIN1
7: AIN2
11: AIN0
6: AIN3
12: AVDD
5: AVSS
13: DVDD
4: DGND
14: DRDY
3: RESET
15: SDA
2: A1
16: SCL
1: A0
DRDY
SCL
SDA
A0
DVDD
AIN3
RESET
8: REFN
A1
AVDD
9: REFP
Figure 83. Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference
• LM94022/-Q1 1.5-V, SC70, Multi-Gain Analog Temperature Sensor With Class-AB Output
• RTD Ratiometric Measurements and Filtering Using the ADS1148 and ADS1248 Application Report
• Low-Cost, Single-Chip Differential Temperature Measurement Solution Using Precision Delta-Sigma ADCs
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
NXP Semiconductors is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
64
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADS112C04IPW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS112C
ADS112C04IPWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
ADS112C
ADS112C04IRTER
PREVIEW
WQFN
RTE
16
3000
TBD
Call TI
Call TI
-40 to 125
ADS112C04IRTET
PREVIEW
WQFN
RTE
16
250
TBD
Call TI
Call TI
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2018
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS112C04IPWR
Package Package Pins
Type Drawing
TSSOP
PW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Apr-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS112C04IPWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
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