ATMEL AT17LV002-10CC Fpga configuration eeprom memory Datasheet

Features
• EE Reprogrammable 2,097,152 x 1-bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
• In-System Programmable via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX®, APEX™
•
•
•
•
•
•
•
•
•
Devices, Lucent ORCA® FPGAs, Xilinx XC3000™, XC4000™, XC5200™, Spartan®,
Virtex™ FPGAs
Cascadable Read Back to Support Additional Configurators or Higher-density Arrays
Low-power CMOS EEPROM Process
Programmable Reset Polarity
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages (Pin-compatible
Across Product Family)
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Available in 3.3V ± 10% LV and 5V ± 5% C Versions
System-friendly READY Pin
Low-power Standby Mode
Replacement for AT17C/LV020
FPGA
Configuration
EEPROM
Memory
2-megabit
Description
The AT17C002 and AT17LV002 (high-density AT17 Series) FPGA Configuration
EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for programming Field Programmable Gate Arrays. The AT17 Series is packaged
in the popular 8-lead LAP, 20-lead PLCC, 44-lead PLCC and the 44-lead TQFP. The
AT17 Series family uses a simple serial-access procedure to configure one or more
FPGA devices. The user can select the polarity of the reset function by programming
four EEPROM bytes. These devices support a write protection mode and a systemfriendly READY pin, which signifies a “good” power level to the FPGA and can be used
to ensure reliable system power-up.
AT17C002
AT17LV002
The AT17 Series Configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming System and Atmel’s ATDH2225 ISP Cable.
Rev. 2281D–12/01
1
Pin Configuration
8-lead LAP
NC
DATA
NC
VCC
NC
VCC
SER_EN
CEO (A2)
GND
CLK
WP1
RESET/OE
NC
CE
4
5
6
7
8
3
2
1
20
19
8
7
6
5
18
17
16
15
14
9
10
11
12
13
1
2
3
4
NC
SER_EN
NC
READY
CEO(A2)
NC
GND
NC
NC
NC
DATA
CLK
RESET/OE
CE
20-lead PLCC
44-lead TQFP
2
NC
NC
NC
NC
NC
NC
WP1
NC
NC
NC
NC
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
12
13
14
15
16
17
18
19
20
21
22
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO(A2)
NC
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
7
8
9
10
11
12
13
14
15
16
17
NC
RESET/OE
NC
CE
NC
NC
GND
NC
NC
CEO(A2)
NC
WP1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
6
5
4
3
2
1
44
43
42
41
40
44
43
42
41
40
39
38
37
36
35
34
NC
CLK
NC
NC
DATA
NC
VCC
NC
NC
SER_EN
NC
NC
CLK
NC
NC
DATA
NC
VCC
NC
NC
SER_EN
NC
44-lead PLCC
AT17C/LV002
2281D–12/01
AT17C/LV002
Block Diagram
SER_EN
WP1
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
OSC
CONTROL
ROW
ADDRESS
COUNTER
ROW
DECODER
OSC
BIT
COUNTER
POWER ON
RESET
EEPROM
CELL
MATRIX
COLUMN
DECODER
TC
CLK READY
Device Description
RESET/OE
CE
CEO(A2)
DATA
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17 Series Configurator. If CE is held High after the
RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated.
When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET/OE.
3
2281D–12/01
Pin Configurations
8
LAP
Pin
20
PLCC
Pin
44
TQFP
Pin
44
PLCC
Pin
Name
I/O
Description
1
2
40
2
DATA
I/O
Three-state DATA output for configuration. Open-collector bi-directional
pin for programming.
2
4
43
5
CLK
I
Clock input. Used to increment the internal address and bit counter for
reading and programming.
–
5
7
7
WP1(1)
I
WRITE PROTECT (1). Used to protect portions of memory during
programming. Disabled by default due to internal pull-down resistor.
This input pin is not used during FPGA loading operations.
3
6
13
19
RESET/OE
I
Output Enable (active High) and RESET (active Low) when SER_EN is
High. A Low level on RESET/OE resets both the address and bit
counters. A High level (with CE Low) enables the data output driver. The
logic polarity of this input is programmable as either RESET/OE or
RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
4
8
15
21
CE
I
Chip Enable input (active Low). A Low level (with OE High) allows DCLK
to increment the address counter and enables the data output driver. A
High level on CE disables both the address and bit counters and forces
the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the 2-wire Serial Programming mode
(SER_EN Low).
5
10
18
24
GND
6
21
CEO
O
Chip Enable Output (active Low). This output goes Low when the
address counter has reached its maximum value. In a daisy chain of
AT17 Series devices, the CEO pin of one device must be connected to
the CE input of the next device in the chain. It will stay Low as long as
CE is low and OE is High. It will then follow CE until OE goes Low;
thereafter, CEO will stay High until the entire EEPROM is read again.
A2
I
Device selection input, A2. This is used to enable (or select) the device
during programming (i.e., when SER_EN is Low). A2 has an internal
pulldown resistor.
27
–
15
23
29
READY(1)
O
Open collector reset state indicator. Driven Low during power-up reset,
released when power-up is complete. (Recommend a 4.7 kΩ pull-up on
this pin if used).
7
17
35
41
SER_EN
I
Serial enable must be held High during FPGA loading operations.
Bringing SER_EN Low enables the 2-wire Serial Programming Mode.
For non-ISP applications, SER_EN should be tied to VCC.
8
20
38
44
VCC
Note:
4
14
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is
recommended.
+3.3V/+5V power supply pin.
1. This pin is not available on the 8-lead packages.
AT17C/LV002
2281D–12/01
AT17C/LV002
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master Mode, the FPGA
automatically loads the configuration program from an external memory. The AT17
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial Mode.
This document discusses the AT40K, AT40KAL and AT94KAL applications, as well as
Xilinx applications.
Control of
Configuration
Cascading Serial
Configuration
EEPROMs
Most connections between the FPGA device and the AT17 Serial EEPROM are simple
and self-explanatory:
•
The DATA output of the AT17 Series Configurator drives DIN of the FPGA devices.
•
The master FPGA CCLK output drives the CLK input of the AT17 Series
Configurator.
•
The CEO output of any AT17 Series Configurator drives the CE input of the next
Configurator in a cascade chain of EEPROMs.
•
SER_EN must be connected to VCC (except during ISP).
•
The READY pin is available as an open-collector indicator of the device’s reset
status; it is driven Low while the device is in its power-on reset cycle and released
(tri-stated) when the cycle is complete.
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded Configurators provide additional memory.
As the last bit from the first Configurator is read, the clock signal to the Configurator
asserts its CEO output Low and disables its DATA line driver. The second Configurator
recognizes the Low level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded Configurators are
reset if the RESET/OE on each Configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input
can be tied to its inactive (High) level.
AT17 Series Reset
Polarity
The AT17 Series Configurator allows the user to program the reset polarity as either
RESET/OE or RESET/OE. This feature is supported by industry-standard programmer
algorithms.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the 2-wire serial bus. The programming is done at VCC supply only.
Programming super voltages are generated inside the chip. The AT17C parts are
read/write at 5V nominal. The AT17LV parts are read/write at 3.3V nominal.
Standby Mode
The AT17C/LV002 Series Configurator enters a low-power standby mode whenever CE
is asserted High. In this mode, the Configurator consumes less than 0.5 mA of current at
5V. The output remains in a high-impedance state regardless of the state of the OE
input.
5
2281D–12/01
Example Circuits
Figure 1. AT17 Series Device for Programming PSLI Devices
AT17 Series Device
AT40K/AT40KAL/AT94K
RESET
RESET
M2
M1
M0
VCC
SER_EN
DATA
CLK
CE
(2)
RESET/OE(1) READY
DATA0
CCLK
CON
INIT
GND
Notes:
1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
The FPGA CON/DONE output drives the CE input of the AT17 Series Configurator, while the RESET/OE input is driven by
the FPGA INIT pin. This connection works under all normal circumstances, even when the user aborts the configuration
before CON/DONE has gone High. A Low level on the RESET/OE input, during FPGA reset, clears the configurator’s internal address pointer so that the reconfiguration starts at the beginning.
Figure 2. Drop-In Replacement of XC17/ATT17 PROMs for Xilinx/Lucent FPGA Applications
VCC
4.7 kW
XILINX FPGA
PROGRAM
PROGRAM
M2
M1
M0
DIN
CCLK
DONE(3)
INIT
AT17 Series Device
VCC
SER_EN
DATA
CLK
CE
(2)
RESET/OE(1) READY
GND
Notes:
6
1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
3. An internal pull-up resistor is enabled here for DONE.
AT17C/LV002
2281D–12/01
AT17C/LV002
For details of ISP, please refer to the “Programming Specification for Atmel's AT17 and AT17A Series FPGA Configuration
EEPROMs”, available on the Atmel web site, at http://www.atmel.com/atmel/acrobat/doc0437.pdf.
Figure 3. In-System Programming of AT17 Series for PSLI Applications
VCC VCC
4.7 kW
4.7 kW
DATA 1
SCLK 3
2
5
6
7
8
9
10
4
VCC
GND
AT17 Series Device
AT40K/AT40KAL/AT94K
RESET
RESET
M2
M1
M0
DATA0
CCLK
CON
INIT
SER_EN
SER_EN
DATA
CLK
CE
(2)
RESET/OE(1) READY
GND
Notes:
1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
Figure 4. In-System Programming of AT17 Series for Xilinx/Lucent FPGA Applications
VCC VCC
4.7 kW
DATA 1
SCLK 3
2
5
6
7
8
9
10
VCC
VCC
4.7 kW
4
VCC
4.7 kW
XILINX FPGA
PROGRAM
PROGRAM
4.7 kW
M2
M1
M0
DIN
CCLK
DONE(3)
INIT
AT17 Series Device
GND
SER_EN
SER_EN
DATA
CLK
CE
(1)
READY(2)
RESET/OE
GND
Notes:
1. Reset polarity must be set to active Low.
2. Use of the optional READY pin is not available on the AT17C/LV65/128/256 devices.
3. An internal pull-up resistor is enabled here for DONE.
7
2281D–12/01
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65 °C to +150°C
Voltage on Any Pin
with Respect to Ground ..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
*NOTICE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended
periods of time may affect device reliability.
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
Operating Conditions
AT17C002
Symbol
VCC
8
Description
AT17LV002
Min
Max
Min
Max
Units
Commercial
Supply voltage relative to GND,
-0°C to +70°C
4.75
5.25
3.0
3.6
V
Industrial
Supply voltage relative to GND,
-40°C to +85°C
4.5
5.5
3.0
3.6
V
Military
Supply voltage relative to GND,
-55°C to +125°C
4.5
5.5
3.0
3.6
V
AT17C/LV002
2281D–12/01
AT17C/LV002
DC Characteristics
VCC = 5V ± 5% Commercial, 5V ± 10% Industrial/Military
Symbol
Description
Min
Max
Units
VIH
High-Level Input Voltage
2.0
VCC
V
VIL
Low-level input voltage
0.0
0.8
V
VOH
High-level Output Voltage (IOH = -4 mA)
VOL
Low-level Output Voltage (IOL = +4 mA)
VOH
High-level Output Voltage (IOH = -4 mA)
VOL
Low-level Output Voltage (IOL = +4 mA)
VOH
High-level Output Voltage (IOH = -4 mA)
VOL
Low-level Output Voltage (IOL = +4 mA)
0.4
V
ICCA
Supply Current, Active Mode
10
mA
IL
Input or Output Leakage Current (VIN = VCC or GND)
10
µA
Commercial
0.5
mA
ICCS1
Supply Current, Standby Mode, CMOS
Industrial/Military
0.75
mA
ICCS2
Supply Current, Standby Mode, TTL
1
mA
3.86
V
Commercial
0.32
3.76
V
V
Industrial
0.37
3.7
V
V
Military
-10
Commercial/Industrial
DC Characteristics
VCC = 3.3V ± 10%
Symbol
Description
Min
Max
Units
VIH
High-level input voltage
2.0
VCC
V
VIL
Low-level input voltage
0.0
0.8
V
VOH
High-level Output Voltage (IOH = -2.5 mA)
VOL
Low-level Output Voltage (IOL = +3 mA)
VOH
High-level Output Voltage (IOH = -2 mA)
VOL
Low-level Output Voltage (IOL = +3 mA)
VOH
High-level Output Voltage (IOH = -2 mA)
VOL
Low-level Output Voltage (IOL = +2.5 mA)
ICCA
Supply Current, Active Mode
IL
Input or Output Leakage Current (VIN = VCC or GND)
ICCS
Supply Current, Standby Mode
2.4
V
Commercial
0.4
2.4
V
V
Industrial
0.4
2.4
V
V
Military
0.4
V
5
mA
10
µA
Commercial
200
µA
Industrial/Military
200
µA
-10
9
2281D–12/01
AC Characteristics
CE
TSCE
TSCE
THCE
RESET/OE
TLC
THOE
THC
CLK
TOE
TOH
TCAC
TDF
TCE
DATA
TOH
AC Characteristics when Cascading
RESET/OE
CE
CLK
TCDF
DATA
FIRST BIT
LAST BIT
TOCK
TOCE
TOOE
CEO
TOCE
10
AT17C/LV002
2281D–12/01
AT17C/LV002
.
AC Characteristics for AT17C002
VCC = 5V ± 5% Commercial, VCC = 5V ± 10% Industrial/Military
Commercial
Symbol
Description
TOE(2)
OE to Data Delay
(2)
TCE
TCAC
(2)
Min
Max
Industrial/Military(1)
Max
Units
30
35
ns
CE to Data Delay
45
45
ns
CLK to Data Delay
50
50
ns
TOH
Data Hold From CE, OE or CLK
TDF(3)
CE or OE to Data Float Delay
TLC
CLK Low Time
20
20
ns
THC
CLK High Time
20
20
ns
TSCE
CE Setup Time to CLK (to guarantee proper counting)
20
25
ns
THCE
CE Hold Time from CLK (to guarantee proper counting)
0
0
ns
THOE
OE High Time (guarantees counter is reset)
20
20
ns
FMAX
Maximum Input Clock Frequency
15
15
MHz
Notes:
0
Min
0
50
ns
50
ns
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
AC Characteristics for AT17C002 when Cascading
VCC = 5V ± 5% Commercial/VCC = 5V ± 10% Industrial/Military
Commercial
Symbol
Description
TCDF (3)
CLK to Data Float Delay
TOCK(2)
TOCE(2)
TOOE(2)
FMAX
Notes:
Max
Units
50
50
ns
CLK to CEO Delay
35
40
ns
CE to CEO Delay
35
35
ns
RESET/OE to CEO Delay
30
30
ns
Maximum Input Clock Frequency
Min
12.5
Max
Industrial/Military(1)
Min
12.5
MHz
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
11
2281D–12/01
AC Characteristics for AT17LV002
VCC = 3.3V ± 10%
Commercial
Symbol
Description
TOE(2)
OE to Data Delay
(2)
TCE
TCAC
(2)
Min
Max
Industrial/Military(1)
Max
Units
50
55
ns
CE to Data Delay
55
60
ns
CLK to Data Delay
55
60
ns
TOH
Data Hold From CE, OE or CLK
TDF(3)
CE or OE to Data Float Delay
TLC
CLK Low Time
25
25
ns
THC
CLK High Time
25
25
ns
TSCE
CE Setup Time to CLK (to guarantee proper counting)
30
35
ns
THCE
CE Hold Time from CLK (to guarantee proper counting)
0
0
ns
THOE
OE High Time (guarantees counter is reset)
25
25
ns
FMAX
Maximum Input Clock Frequency
15
10
MHz
Notes:
0
Min
0
50
ns
50
ns
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
AC Characteristics for AT17LV002 when Cascading
VCC = 3.3V ± 10%
Commercial
Symbol
Description
TCDF(3)
CLK to Data Float Delay
TOCK(2)
TOCE(2)
TOOE(2)
FMAX
Notes:
12
Max
Units
50
50
ns
CLK to CEO Delay
50
55
ns
CE to CEO Delay
35
40
ns
RESET/OE to CEO Delay
35
35
ns
Maximum Input Clock Frequency
Min
12.5
Max
Industrial/Military(1)
Min
10
MHz
1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.
AT17C/LV002
2281D–12/01
AT17C/LV002
Thermal Resistance Coefficients(1)
θJC [°C/W]
θJA [°C/W]
Airflow = 0 ft/min
8CN4
45
159.60
Plastic Leaded Chip Carrier
(PLCC)
20J
35
90
Thin Plastic Quad Flat
Package (TQFP)
44A
17
62
Plastic Leaded Chip Carrier
(PLCC)
44J
15
50
Package Type
Leadless Array Package
(LAP)
Note:
1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site, at
http://www.atmel.com/atmel/acrobat/doc0636.pdf.
13
2281D–12/01
Ordering Information – 5V Devices
Memory Size
Ordering Code
Package
Operation Range
2-Mbit
AT17C002-10CC
AT17C002-10JC
AT17C002-10TQC
AT17C002-10BJC
8CN4
20J
44A
44J
Commercial
(0°C to 70°C)
AT17C002-10CI
AT17C002-10JI
AT17C002-10TQI
AT17C002-10BJI
8CN4
20J
44A
44J
Industrial
(-40°C to 85°C)
Ordering Information – 3.3V Devices
Memory Size
Ordering Code
Package
Operation Range
2-Mbit
AT17LV002-10CC
AT17LV002-10JC
AT17LV002-10TQC
AT17LV002-10BJC
8CN4
20J
44A
44J
Commercial
(0°C to 70°C)
AT17LV002-10CI
AT17LV002-10JI
AT17LV002-10TQI
AT17LV002-10BJI
8CN4
20J
44A
44J
Industrial
(-40°C to 85°C)
Package Type
8CN4
8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOIC Packages
20J
20-lead, Plastic J-leaded Chip Carrier (PLCC)
44A
44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
44J
44-lead, Plastic J-leaded Chip Carrier (PLCC)
14
AT17C/LV002
2281D–12/01
AT17C/LV002
Packaging Information
8CN4 – LAP
Marked Pin1 Indentifier
E
A
A1
D
Top View
Side View
Pin1 Corner
L1
0.10 mm
TYP
8
1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
2
7
3
6
b
5
4
e1
L
Bottom View
SYMBOL
MIN
NOM
MAX
A
0.94
1.04
1.14
A1
0.30
0.34
0.38
b
0.45
0.50
0.55
D
5.89
5.99
6.09
E
4.89
5.99
6.09
e
1.27 BSC
e1
1.10 REF
NOTE
1
L
0.95
1.00
1.05
1
L1
1.25
1.30
1.35
1
Note: 1. Metal Pad Dimensions.
11/14/01
R
1150 E.Cheyenne Mtn Blvd.
Colorado Springs, CO 80906
TITLE
8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP)
DRAWING NO.
8CN4
REV.
A
15
2281D–12/01
20J – PLCC
PIN NO. 1
1.14(0.045) X 45˚
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
D1
A1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
9.779
–
10.033
D1
8.890
–
9.042
E
9.779
–
10.033
E1
8.890
–
9.042
D2/E2
7.366
–
8.382
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
20J
B
AT17C/LV002
2281D–12/01
AT17C/LV002
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
11.75
12.00
12.25
D1
9.90
10.00
10.10
E
11.75
12.00
12.25
E1
9.90
10.00
10.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
44A
B
17
2281D–12/01
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
E1
D2/E2
B1
E
B
e
A2
D1
A1
D
A
0.51(0.020)MAX
COMMON DIMENSIONS
(Unit of Measure = mm)
45˚ MAX (3X)
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
SYMBOL
MIN
NOM
MAX
A
4.191
–
4.572
A1
2.286
–
3.048
A2
0.508
–
–
D
17.399
–
17.653
D1
16.510
–
16.662
E
17.399
–
17.653
E1
16.510
–
16.662
D2/E2
14.986
–
16.002
B
0.660
–
0.813
B1
0.330
–
0.533
e
NOTE
Note 2
Note 2
1.270 TYP
10/04/01
R
18
2325 Orchard Parkway
San Jose, CA 95131
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
REV.
44J
B
AT17C/LV002
2281D–12/01
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© Atmel Corporation 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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Printed on recycled paper.
2281D–12/01/xM
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