IDT AMB0480XXRJ Advanced memory buffer for fully buffered dimm module Datasheet

IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
ADVANCED MEMORY BUFFER
FOR FULLY BUFFERED DIMM
MODULES
IDTAMB0480
PRODUCT
BRIEF
FEATURES:
DESCRIPTION:
•
•
•
•
•
The fully buffered dual in-line memory module (FB-DIMM) is the next
generation memory architecture to meet the growing memory requirement of
servers and workstations. The IDT Advanced Memory Buffer (AMB) chip is the
essential building block located on each FB-DIMM. The IDT AMB receives
commands and data from the host controller to control and write/read data to/
from the DRAMs on the DIMM. Commands and write data are sent southbound
from the host controller to AMBs in a daisy chain fashion and interpreted by the
target AMB. Status and read data are sent northbound from AMBs to the host
controller also in a daisy chain fashion, passing through non-target AMBs. This
unique channel structure alleviates buffer loading issues common in registered
DIMM technology, enabling designers to use a large number of DIMMs within
a single system.
IDTAMB0480 complies with the latest JEDEC defined FB-DIMM Architecture
and Protocol Specification and supports DDR2-533 and DDR2-667 DRAM.
It also enables serial data transfer at 3.2 and 4.0Gbps. The IDTAMB0480
supports servers, workstations, storage devices and communication applications
that support the next generation FB-DIMM architecture.
Advanced Memory Buffer for Fully buffered DIMMs
3.2 and 4 Gbit/s serial speeds (DDR2-533 and 667 DRAM)
Support for up to eight DIMMs per channel
Repeater Mode for extending FB-DIMM links
Northbound and Southbound single lane fail over and channel
error detection
Voltage and Timing margin high-speed I/O test capability
Fully Supports the FB-DIMM configuration register set
Test features supported include:
- Integrated thermal sensor and status indicator
- Supports MEMBIST, IBIST and Virtual Host mode
- Transparent mode and direct access mode for DRAM testing
Complies with JEDEC Architecture and Protocol Specification
Available in 655 ball FCBGA package
•
•
•
•
•
EXPANDED FEATURES:
•
•
•
•
•
•
Wide range DDR Timing Control
Superfine adjustment for DDR timing
Wide range of DDR slew rate control
Slew rate controllable independent of output impedance
High speed SMBus in test mode
IBIST IDT PRBS Generator
FDB MEMORY CHANNEL
Up to 8 modules
Host
Memory
Controller
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
IDT
AMB
IDT
AMB
IDT
AMB
IDT
AMB
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
DDR2
14
10
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
APRIL 2006
1
c
2006 Integrated Device Technology, Inc.
DSC - 7042/2
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
10 x 2
10 x 2
PS[9:0]/PS[9:0]
SS[9:0]/SS[9:0]
Southbound Lanes
Re-sync
FIFO
SIPO
PISO
10 x 12b
De-skew
Re-skew
FIFO
FIFO
3
SA[2:0]
SCL
SDA
10 x 12b
Link Init FSM
SMBus
SB Link
Controller
CSRs
Thermal
DDR Link
Sensor
CSRs
and Control
4
CLK[3:0]
IBIST Rx
IBIST Tx
CLK[3:0]
19
DDR State
FBDRES
Termination
FSM
and CSRs
RASB/CASB/WEB
External MemBIST,
4
DDR Calibration and
CS[1:0]A/CKE[1:0]A
DDR IOBIST
CS[1:0]B/CKE[1:0]B
Reset
Control
ODTA
32 x 144b
REF clock
SCK
RASA/CASA/WEA
& CRC Check
SB clock
RESET
A[15:0]B/BA[2:0]B
3
Cmnd Decode
Core Control
BFUNC
A[15:0]A/BA[2:0]A
Controller
Failover
ODTB
Write Data
Phase-locked
FIFO
18
Loop
SCK
DQS[17:0]
DQS[17:0]
PLLTSTO
Clock
DDR clocks
Generator
DLL
144b
72
CB[7:0]/DQ[63:0]
NB clock
168b
144b
CRC Gen
& Read FIFO
Sync and Idle
IBIST Tx
Pattern Gen
Vref
DDRC_B18
IBIST Rx
DDRC_C18
Impedance
Control
NB Link
CSRs
FSM
Link Init FSM
Re-skew
De-skew
FIFO
FIFO
14 x 12b
14 x 12b
PISO
SIPO
Re-sync
FIFO
Northbound Lanes
PN[13:0]/PN[13:0]
14 x 2
SN[13:0]/SN[13:0]
14 x 2
2
DDRC_C12
DDRC_C14
and Control
Failover
DDRC_B12
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS
1
2
3
4
5
6
7
8
9
10
11
14
15
A
TEST
DQS
VSS DQ26 DQ12 VDD 10 DQ13 VDD DQS1 DQ10 VDD LO VDD
VDD
B
VDD DQS3 DQS3 VSS DQ14 DQS VSS DQ11 DQS1 VSS DDRC TEST VDD
_B12
LO
10
VSS
C VSS DQS2 DQ18 VSS DQ4 DQS9 VSS DQ15 DQ9 VSS DQ8
12
DDRC
_C12
13
VSS
DDRC
_C14
DQS
17
D DQ19 DQS2 VSS DQ16 DQ24 VSS DQS9 DQ7 VSS DQ3 DQS0 VSS DQS8 DQS8 VDD
E DQ21 VSS DQ17 DQ29 VSS DQ25 DQ6 VSS DQ5 DQ1 VSS DQ0 CB1 VSS CB2
F
VSS DQ20 DQ23 VSS DQ31 DQ27 VSS
TEST
TEST VSS DQS0 DQ2 VDD
LO
CB0
CB3
G DQS DQS NC
NC
NC VSS DQS DQS NC
12
12
NC
NC
H DQ22 VSS NC
NC
NC DQ28 DQ30 VSS NC
NC
NC
VSS VDD VSS VDD
VSS CLK2 NC
NC
NC
NC BA1A VSS CKE
1A
NC
NC
VDD
K CLK2 CLK0 NC
NC
NC
VSS WEA RASA NC
NC
NC
VSS VCC VSS VCC
L CLK0 VSS NC
NC
NC
A0A
CKE
VSS
0A
NC
NC
NC
VCC
M ODT
RFU NC
0A
NC
NC CASA VSS BA2A NC
NC
NC
VSS VCC VSS VCC
N CS1A CS0A NC
NC
NC
VSS BA0A A10A NC
NC
NC
VCC
P A6A VSS NC
NC
NC
A2A
A3A
NC
NC
NC
VSS VCC VSS VCC
R VSS A8A
NC
NC
NC A11A VSS A5A
NC
NC
NC
VCC
A13A NC
NC
NC
NC
NC
NC
VSS VCC VSS VCC
NC
NC
NC A15A A14A A12A NC
NC
NC
RFU
VCC
VCC
VSS VSS VSS
11
J
T
A4A
11
A1A
VSS A9A A7A
BFUNC
RFU RFU RFU
VSS VDD VSS
VSS VCC VSS
VSS VCC VSS
VSS VCC VSS
U PN0
PN0
V
PN1
PN1 VSS SN0
SN0
W
PN2
PN2 VSS SN1
SN1 SN3 SN4
SN5 SN13 SN12 SN6
SN7 SN8
SN9 SN10
Y
PN3
PN3 VSS SN2
SN2 SN3 SN4
SN5 SN13 SN12 SN6
SN7 SN8
SN9 SN10
VCC
FBD
CC
VSS V
VSS
FBD
RFU
(1)
RFU
(1)
FBD
FBD
VSS VSS
AA VSS PN4 PN4 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AB
AC
VSS
RESET
(1)
PN5 PN13 RFU
VSS PN5 PN13
RFU
(1)
PN12 PN6 PN7
PN8 PN9
VSS
APLL
VCC
APLL
PN10 PN11
PN12 PN6 PN7
PN8 PN9
FBD
RES
PLL
TSTO
PN10 PN11
FCBGA
TOP VIEW, LEFT SIDE
NOTE:
1. These pin positions are reserved for forward clocks to be used in future implementations.
3
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
16
17
18
19
20
21
COMMERCIAL TEMPERATURE RANGE
22
23
24
25
26
27
28
A
VDD TEST VDD DQ52 DQS15 VDD DQ49 DQS6 VDD DQ48 DQ38 VDD
B
VDD TEST DDRC VSS DQS15 DQ53 VSS DQS6 DQ50 VSS DQS13 DQS13 VSS
LO _B18
DDRC
_C18
29
DQ54 VSS DQ55 DQ51 VSS DQS7 DQ56 VSS DQ46 DQS14 VDD
C
DQS17
D
CB6
E
VSS CB5
F
CB4
VDD DQ62 DQ60 VSS TEST TEST VSS DQ37 DQ35 VSS DQS5 DQ43 VSS
G
TEST
LO
RFU RFU
NC
NC
NC DQS4 DQS4 VSS
NC
NC
NC DQS5 DQ40
H
VSS VDD VSS
NC
NC
NC VSS DQ34 DQ32 NC
NC
NC VSS DQ42
J
VDD
VSS VDD
NC
NC
NC RASB VSS RFU
NC
NC
NC CLK3 VSS
K
VSS VCC VSS
NC
NC
NC ODT CS1B VSS
NC
NC
NC CLK1 CLK3
L
VCC
VSS VCC
NC
NC
NC VSS CASB WEB
NC
NC
NC
M
VSS VCC VSS
NC
NC
NC CS0B VSS BA1B NC
NC
NC
N
VCC
VSS VCC
NC
NC
NC A0B A2B
VSS NC
NC
NC BA0B BA2B
P
VSS VCC VSS
NC
NC
NC
NC
NC
NC
VSS
CKE1B
R
VCC
VSS VCC
NC
NC
NC A6B
VSS A10B NC
NC
NC
A3B
VSS
T
VSS VCC VSS
NC
NC
NC A11B A9B
NC
NC A7B A5B
U
VSS Vcc
RFU
NC
NC
NC A8B A15B A14B SA0
V
Vcc
VSS
Vcc
FBD
VSS Vcc
FBD
W
VSS SS0
SS1
SS2
SS3
SS4
SS9
SS5
SS6
SS7
Y
VSS SS0
SS1
SS2
SS3
SS4
SS9
SS5
SS6
SS7
VSS
CB7 VSS DQS16 DQ63 VSS DQ59 DQS7 VSS DQ36 DQ44 VSS DQS14 DQ47
FBD
FBD
DQS16
VSS DQ61 DQ57 VSS DQ58 DQ39 VSS DQ33 DQ45 VSS DQ41
0B
RFU
(1)
VSS A4B A1B
RFU
(1)
VSS NC
SCL SDA
CKE0B
VSS
PS8
PS8
VSS A13B A12B SA2 SA1 PS7
PS7
SS8
VSS PS6
PS6
SS8
VSS PS5
PS5
AA
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS PS9
AB
VSS SN11 VSS SCK
TESTLO_
AB20
PS0
PS1
PS2
PS3
PS4 RFU
AC RFU SN11 VSS SCK
TESTLO_
AC20
PS0
PS1
PS2
PS3
PS4 RFU
FCBGA
TOP VIEW, RIGHT SIDE
NOTE:
1. These pin positions are reserved for forward clocks to be used in future implementations.
4
VSS CLK1
PS9 VSS
(1)
VDD VSS
SPD
(1)
VSS
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
655 BALL BGA PACKAGE ATTRIBUTES
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
5
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
ADVANCED MEMORY BUFFER SIGNALS BY BALL NUMBER
Ball No.
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B 18
B19
B20
B21
B22
B23
B24
B25
Signal
VSS
DQ26
DQ12
VDD
DQS10
DQ13
VDD
DQS1
DQ10
VDD
TESTLO
VDD
VDD
VDD
TEST
VDD
DQ52
DQS15
VDD
DQ49
DQS6
VDD
DQ48
DQ38
VDD
VDD
DQS3
DQS3
VSS
DQ14
DQS10
VSS
DQ11
DQS1
VSS
DDRC_B12
TESTLO
VDD
VSS
VDD
TESTLO
DDRC_B18
VSS
DQS15
DQ53
VSS
DQS6
DQ50
VSS
Ball No.
B26
B27
B28
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
Ball No.
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
E27
E28
E29
F1
F2
F3
F4
F5
F6
F7
F8
Signal
DQS13
DQS13
VSS
VSS
DQS2
DQ18
VSS
DQ4
DQS9
VSS
DQ15
DQ9
VSS
DQ8
DDRC_C12
VSS
DDRC_C14
DQS17
DQS17
VSS
DDRC_C18
DQ54
VSS
DQ55
DQ51
VSS
DQS7
DQ56
VSS
DQ46
DQS14
VDD
DQ19
DQS2
VSS
DQ16
DQ24
VSS
DQS9
DQ7
VSS
DQ3
DQS0
VSS
DQS8
DQS8
VDD
CB6
CB7
6
Signal
VSS
DQS16
DQ63
VSS
DQ59
DQS7
VSS
DQ36
DQ44
VSS
DQS14
DQ47
DQ21
VSS
DQ17
DQ29
VSS
DQ25
DQ6
VSS
DQ5
DQ1
VSS
DQ0
CB1
VSS
CB2
VSS
CB5
DQS16
VSS
DQ61
DQ57
VSS
DQ58
DQ39
VSS
DQ33
DQ45
VSS
DQ41
VSS
DQ20
DQ23
VSS
DQ31
DQ27
VSS
TESTLO
Ball No.
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
F27
F28
F29
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
G21
G22
G23
G24
G25
G26
G27
G28
Signal
TEST
VSS
DQS0
DQ2
VDD
CB0
CB3
CB4
VDD
DQ62
DQ60
VSS
TEST
TEST
VSS
DQ37
DQ35
VSS
DQS5
DQ43
VSS
DQS11
DQS11
NC
NC
NC
VSS
DQS12
DQS12
NC
NC
NC
BFUNC
RFU
RFU
RFU
TESTLO
RFU
RFU
NC
NC
NC
DQS4
DQS4
VSS
NC
NC
NC
DQS5
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
ADVANCED MEMORY BUFFER SIGNALS BY BALL NUMBER (CONT.)
Ball No.
G29
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H29
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
Signal
DQ40
DQ22
VSS
NC
NC
NC
DQ28
DQ30
VSS
NC
NC
NC
VSS
VDD
VSS
VDD
VSS
VDD
VSS
NC
NC
NC
VSS
DQ34
DQ32
NC
NC
NC
VSS
DQ42
VSS
CLK2
NC
NC
NC
BA1A
VSS
CKE1A
NC
NC
NC
VDD
VSS
VDD
VSS
VDD
VSS
VDD
NC
Ball No.
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
Signal
NC
NC
RASB
VSS
RFU
NC
NC
NC
CLK3
VSS
CLK2
CLK0
NC
NC
NC
VSS
WEA
RASA
NC
NC
NC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
NC
NC
NC
ODT0B
CS1B
VSS
NC
NC
NC
CLK1
CLK3
CLK0
VSS
NC
NC
NC
A0A
CKE0A
VSS
NC
NC
Ball No.
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
L26
L27
L28
L29
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
M21
M22
M23
M24
M25
M26
M27
M28
M29
N1
7
Signal
NC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
NC
NC
NC
VSS
CASB
WEB
NC
NC
NC
VSS
CLK1
ODT0A
RFU
NC
NC
NC
CASA
VSS
BA2A
NC
NC
NC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
NC
NC
NC
CS0B
VSS
BA1B
NC
NC
NC
CKE0B
VSS
CS1A
Ball No.
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
N26
N27
N28
N29
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
Signal
CS0A
NC
NC
NC
VSS
BA0A
A10A
NC
NC
NC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
NC
NC
NC
A0B
A2B
VSS
NC
NC
NC
BA0B
BA2B
A6A
VSS
NC
NC
NC
A2A
A1A
A3A
NC
NC
NC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
NC
NC
NC
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
ADVANCED MEMORY BUFFER SIGNALS BY BALL NUMBER (CONT.)
Ball No.
P22
P23
P24
P25
P26
P27
P28
P29
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
Signal
VSS
A4B
A1B
NC
NC
NC
VSS
CKE1B
VSS
A8A
NC
NC
NC
A11A
VSS
A5A
NC
NC
NC
VCC
VSS
VCC
VSS
VCC
VSS
VCC
NC
NC
NC
A6B
VSS
A10B
NC
NC
NC
A3B
VSS
A4A
A13A
NC
NC
NC
VSS
A9A
A7A
NC
NC
NC
Ball No.
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
T26
T27
T28
T29
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
U27
U28
U29
V1
Ball No.
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Signal
VSS
VCC
VSS
VCC
VSS
VCC
VSS
NC
NC
NC
A11B
A9B
VSS
NC
NC
NC
A7B
A5B
PN0
PN0
NC
NC
NC
A15A
A14A
A12A
NC
NC
NC
RFU
VCCFBD
VSS
VSS
VSS
VCCFBD
RFU
NC
NC
NC
A8B
A15B
A14B
SA0
SCL
SDA
PS8
PS8
PN1
NOTE:
1. These pin positions are reserved for forward clocks to be used in future implementations.
8
Signal
PN1
VSS
SN0
SN0
VCCFBD
VSS
VCCFBD
VSS
RFU(1)
RFU(1)
VCCFBD
VSS
VSS
VSS
VCCFBD
VSS
VCCFBD
VSS
VCCFBD
RFU(1)
RFU(1)
VSS
A13B
A12B
SA2
SA1
PS7
PS7
PN2
PS2
VSS
SN1
SN1
SN3
SN4
SN5
SN13
SN12
SN6
SN7
SN8
SN9
SN10
VSS
SS0
SS1
SS2
SS3
Ball No.
W21
W22
W23
W24
W25
W26
W27
W28
W29
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
Signal
SS4
SS9
SS5
SS6
SS7
SS8
VSS
PS6
PS6
PN3
PN3
VSS
SN2
SN2
SN3
SN4
SN5
SN13
SN12
SN6
SN7
SN8
SN9
SN10
VSS
SS0
SS1
SS2
SS3
SS4
SS9
SS5
SS6
SS7
SS8
VSS
PS5
PS5
VSS
PN4
PN4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
ADVANCED MEMORY BUFFER SIGNALS BY BALL NUMBER (CONT.)
Ball No.
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AC3
AC4
Signal
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PS9
PS9
VSS
VSS
RESET
PN5
PN13
RFU(1)
PN12
PN6
PN7
PN8
PN9
VSSAPLL
VCCAPLL
PN10
PN11
VSS
PN11
VSS
SCK
TESTLO_AB20
PS0
PS1
PS2
PS3
PS4
RFU(1)
VDDSPD
VSS
VSS
PN5
Ball No.
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AC27
Signal
PN13
RFU(1)
PN12
PN6
PN7
PN8
PN9
FBDRES
PLLTSTO
PN10
PN11
RFU
SN11
VSS
SCK
TESTLO_AC20
PS0
PS1
PS2
PS3
PS4
RFU(1)
VSS
NOTE:
1. These pin positions are reserved for forward clocks to be used in future implementations.
9
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Signal
Channel Interface
PN[13:0]
PN[13:0]
SN[13:0]
Type
SN[13:0]
PS[9:0]
PS[9:0]
SS[9:0]
I
I
I
O
SS[9:0]
FBDRES
DRAM Interface
CB[7:0]
DQ[63:0]
DQS[17:0]
DQS[17:0]
A0A-A15A,
A0B-A15B
BA0A-BA2A,
BA0B-BA2B
RASA, RASB
CASA, CASB
WEA, WEB
CS0A-CS1A,
CS0B-CS1B
CKE0A-CKE1A,
CKE0B-CKE1B
ODT0A, ODT0B
CLK[3:0]
CLK[3:0]
DDR Compensation
DDRC_C14
DDRC_B18
DDRC_C18
DDRC_B12
DDRC_C12
O
O
I
Description
O
A
Northbound Output Data: High speed serial signal. Read path from AMB toward host on primary side of the DIMM connector.
Northbound Output Data Complement
Northbound Input Data: High speed serial signal. Read path from the previous AMB toward this AMB on secondary side of the DIMM
connector.
Northbound Input Data Complement
Southbound Input Data: High speed serial signal. Write path from host toward AMB on primary side of the DIMM connector.
Southbound Input Data Complement
Southbound Output Data: High speed serial signal. Write path from this AMB toward next AMB on secondary side of the DIMM connector.
These output buffers are disabled for the last AMB on the channel.
Southbound Output Data Complement
External 100Ω precision resistor connected to VCC. On-die termination calibrated against this resistor.
I/O
I/O
I/O
I/O
O
Check bits
Data
Data Strobe: DDR2 data and check-bit strobe.
Data Strobe Complement: DDR2 data and check-bit strobe complements.
Address: Used for providing multiplexed row and column address to SDRAM.
O
Bank Active: Used to select the bank within a rank.
O
O
O
O
O
Row Address Strobe: Used with CS, CAS, and WE to specify the SDRAM command.
Column Address Strobe: Used with CS, RAS, and WE to specify the SDRAM command.
Write Enable: Used with CS, CAS, and RAS to specify the SDRAM command.
Chip Select: Used with CAS, RAS, and WE to specify the SDRAM command. These signals are used for selecting one of two SDRAM
ranks. CS0 is used to select the first rank and CS1 is used to select the second rank.
Clock Enable: DIMM command register enable.
O
O
O
DIMM On-Die-Termination: Dynamic ODT enables for each DIMM on the channel.
Clock: Clocks to DRAMs. CLK0 and CLK1 are always used. CLK2 and CLK3 are used when the AMB is configured for dual rank DIMMs.
Clock Complement: Clocks to DRAMs.
A
A
A
A
A
DDR Compensation Common: Common return (ground) pin for DDRC_B18 and DDRC_C18
DDR Compensation Ball Resistor (825Ω) connected to Compensation Common above
DDR Compensation Ball Resistor (121Ω) connected to Compensation Common above
DDR Compensation Ball Resistor (82Ω) connected to VSS
DDR Compensation Ball Resistor (82Ω) connected to VDD
10
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONT.)
Signal
Clocking
SCK
Type
I
SCK
I
PLLTSTO
O
VCCA PLL
A
VSSA PLL
A
System Management
SCL
I/O
SDA
I/O
SA[2:0]
Reset
RESET
Miscellaneous Test
TEST (4 pins)
NC
TESTLO (5 pins)
A
TESTLO_AB20
A
TESTLO_AC20
A
Power Supplies
VCC (24 pins)
A
VCCFBD (8 pins)
A
VDD (24 pins)
A
VSS (156 pins)
A
VDDSPD
A
Other Pins
BFUNC
I
RFU (18 pins)
NC
Other No Connect Pins
NC (129 pins)
NC
Description
AMB Clock: This is one of the two differential reference clock inputs to the Phase Locked Loop in the AMB core. Phase Locked Loops in
the AMB will shift this to all frequencies required by the core, DDR channels, and FBD Channel.
AMB Clock Complement: This is the other differential reference clock input to the Phase Locked Loop in the AMB core. Phase Locked Loops
in the AMB will shift this to all frequencies required by the core, DDR channels, and FBD Channel.
PLL Clock Observability Output: This pin can be used to observe VCO, reference clock, core clock, etc. For system debug and design
characterization.
VCC: PLL Analog Voltage for the core PLL
VSS: PLL Analog Voltage for the core PLL
SMBus Clock
SMBus Address/Data
DIMM Select ID
Power Good Reset
Pin for debug and test. Must be floated on DIMM.
Pin for debug and test. Must be tied to Ground on DIMM
Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD, the other resistor is connected to VSS.
Pin for debug and test. Connected to two resistors. One resistor is connected to VCCFBD, the other resistor is connected to VSS.
1.5V nominal supply for core I/O
1.5V nominal supply for FBD high speed I/O
1.8V nominal supply for DDR I/O
Ground
3.3V nominal supply for SMB receivers and ESD diodes
Buffer Function Bit: When BFUNC = 0, AMB is used as a regular buffer on FBDIMM. When BFUNC = 1, AMB is used as either a repeater
or a buffer for LAI function. On FB-DIMM, BFUNC is tied to Ground
Reserved for Future Use. Must be floated on DIMM. RFU pins denoted by “a” are reserved for forwarded clocks in future AMB
implementations.
No Connect pins
11
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL, POWER, AND THERMAL
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VDD
Description
Supply voltage DRAM Interface
VIN (DDR2). Voltage on any DDR2 interface
VOUT (DDR2) pin relative to Vss(2)
Min
Max
Unit
-0.5
+2.3
V
0.5
+2.3
V
ADVANCED MEMORY BUFFER
NORMAL MODE DC ELECTRICAL
PARAMETERS
Parameter
Min
Typ
Max
Unit
1.425
1.5
1.59
V
IINK
Input Clamp Current
(VIN < 0 or VIN > VDD)
+30
mA
VCC link / core(1,2,3,4)
VDD
1.7
1.8
1.9
V
IOUTK
Output Clamp Current
(VOUT < 0 or VOUT > VDD)
+30
mA
VDDSPD
3.0
3.3
3.6
V
IOUT
Continous Output Current
(VOUT = 0 to VDD)
+30
mA
N/A
Continuous current through
each VDD or GND
+100
mA
VCC
Supply voltage for Core
and High Speed Interface
-0.3
+1.75
V
TJ
Junction Temperature
+125
°C
TSTG
Storage Temperature Range
–55
+100
°C
NOTES:
1. AMB 1.5V voltage regulation as measured at the package Balls.
2. DC defined as 0 KHz to 30 KHz.
3. DC + AC specified as 1.5V +6%, -5% 30KHz to 1 MHz.
4. There is also a +7%, -5% tolerance allowed for current load steps associated with
initialization/error-recovery state transitions, such as into and out of EI, IBIST, and
MEMBIST. For these transitions, a temporary voltage overshoot is expected and
acceptable as long as it is within +7% (step transition for 20μs and maximum duty cycle
of 10-6 %). Transitions between Active and Idle states are not included in this +7%,
-5% tolerance.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed. This value is limited to 2.3V maximum.
12
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
DDR BIAS
RB18
DDRC_B18
RC12
DDRC_C12
VDD
AMB0480
RB 12
DDRC_C14
DDRC_B12
VSS
RC18
DDRC_C18
PLL AND CHANNEL BIAS
L
R
VCCAPLL
VCC
PLLTSTO
C1
VSS
AMB0480
C2
RPLLTST
VSSAPLL
RFBDRES
VCCFBD
FBDRES
NOTES:
1. Refer to JEDEC PC2-4200/5300/6400 DDR2 FULLY BUFFERED DIMM DESIGN SPECIFICATIONS, rev 2.0.
2. The resistor R must be 0Ω and the inductor L needs to be replaced with a 0Ω resistor. The resistor RFBDRES = 100Ω and Resistor RPLLTST = 51Ω.
3. It is not recommended to use a serpentine copper trace in place of the resistor R. This resistor value needs to be AMB manufacturer defined and not set to a single fixed value.
Some raw cards have implemented the resistor with a serpentine copper trace on the DIMM PCB, while others use a discrete resistor. The limitation of using the copper trace
has been discussed in JEDEC, highlighting that the resistor implemented as a serpentine copper trace is not a generic solution. The raw card artwork now allows the option of
bypassing any serpentine trace with a 0Ω resistor to VCC.
13
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
MISCELLANEOUS BIAS
TEST_F9
NC
TEST_A17
TESTLO_F8
TEST_F21
TESTLO_A13
TEST_F22
TESTLO_B13
NC
NC
NC
TESTLO_B17
VDD
TESTLO_G16
AMB0480
BFUNC
R2
R1
VSS
HVM
SA0
TESTLO_AC20
RSA0
SPD
SA0
TESTLO_AB20
R4
R3
Gold Finger
VSS
VSS
NOTES:
1. Refer to JEDEC PC2-4200/5300/6400 DDR2 FULLY BUFFERED DIMM DESIGN SPECIFICATIONS, rev 2.0.
2. Component values for the AMB0480 are summarized in the BIAS COMPONENT table.
BIAS COMPONENTS - RECOMMENDED VALUES AMB0480
Schematic Diagram
Reference
RC12
Value
82Ω
DDR Bias
RB12
82Ω
RB18
RC18
R
L
C1
C2
RPLLTSTO
RFBDRES
R1
R2
R3
R4
RSA0
825Ω
121Ω
0Ω
0Ω
10μF
10μF
51Ω
100Ω
Not loaded
Not loaded
0Ω
0Ω
825Ω
PLL and Channel
Miscellaneous
Description
The impedance of the pull up (PRU) and pull down (PRD) on the AMB DDR Outputs is relatedto RB12
& RC12 as follows:
RC12 = RB12 = 5.3125 * Desired Output Impedance
A resistor value of 82Ω results in an impedance at a JEDEC nominal value of 15Ω. The user can adjust
these value to optimize the DDR output impedance for a DIMM raw card configuration.
Resistor R must be 0Ω
Inductor L needs to be replaced with a 0Ω resistor
14
IDTAMB0480
ADVANCED MEMORY BUFFER FOR FULLY BUFFERED DIMM
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDTAMB
XXXX
Device Type
XX
Revision
XX
Package
X
Temp. Range
X
Shipping
Carrier
Blank
8
Tray
Tape and Reel
Blank
Commercial (0°C to +70°C)
RJ
BJG
RH
HJG
Ball Grid Array - RoHS Compliant
BGA - Green
Ball Grid Array with heat spreader - RoHS Compliant
(1)
BGA with heat spreader- Green
(1)
XX
Device Revision
0480
Advanced Memory Buffer for Fully Buffered DIMM Modules
NOTE:
1. Contact factory for availability.
Device Revision
A5
Status
Active
AMB revision A1.5
Other Ordering Information
AMB0480xxRJ8
AMB0480xxRJ
AMB0480xxRH8
AMB0480xxRH
AMB in bare die packaged in tape/reel
AMB in bare die packaged in tray
AMB with heatspreader packaged in tape/reel
AMB with heatspreader packaged in tray
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
15
for Tech Support:
[email protected]
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