AKM AK4621EF 24-bit 192khz stereo audio codec Datasheet

[AK4621]
AK4621
24-Bit 192kHz Stereo Audio CODEC
GENERAL DESCRIPTION
The AK4621 is a high performance 24-bit CODEC that supports up to 192kHz recording and playback.
The on-board analog-to-digital converter has a high dynamic range due to AKM’s Enhanced Dual-Bit
architecture. The DAC utilizes AKM’s Advanced Multi-Bit architecture that achieves low out-of-band noise
and high jitter tolerance through the use of Switched Capacitor Filter (SCF) technology. The AK4621 is
ideal for Pro Audio sound cards, Digital Audio Workstations, DVD-R, hard disk, CD-R recording/playback
systems, and musical instrument recording.
FEATURES
□ 24-bit 2-channel ADC
- Full Differential Inputs
- Selectable Digital Filter
1. ADC Sharp Roll Off Filter (GD=39/fs)
Passband: 0 ~ 21.8kHz (@fs=48kHz)
Stopband Attenuation: 100dB
2. ADC Short Delay Sharp Roll Off Filter (GD=14/fs)
Passband: 0 ~ 21.7kHz (@fs=48kHz)
Stopband Attenuation: 80dB
- S/(N+D): 102dB
- S/N: 115dB
- Digital High-pass Filter for Offset Cancellation
- Overflow Flag
2
- Audio Interface Format: MSB justified or I S
□ 24-bit 2-channel DAC
- Selectable Digital Filter
1. DAC Sharp Roll Off Filter (GD=27/fs)
Passband: 0 ~ 21.8kHz (@fs=48kHz)
Stopband Attenuation: 70dB
2. DAC Slow Roll Off Filter (GD=27/fs)
Passband: 0 ~ 8.9kHz (@fs=48kHz)
Stopband Attenuation: 73dB
3. DAC Short Delay Sharp Roll Off Filter (GD=7/fs)
Passband: 0 ~ 21.8kHz (@fs=48kHz)
Stopband Attenuation: 70dB
- Switched-cap Low Pass Filter
- Differential Outputs
- S/(N+D): 100dB
- S/N: 115dB
- De-emphasis for 32kHz, 44.1kHz, 48kHz Sampling
- Output Digital Attenuator: 0dB ~ – 72dB, Linear 256 + 16steps
- Zero Detection Function
2
- Audio Interface Format: MSB justified, LSB justified, I S
□ High Jitter Tolerance
□ Sampling Rate: 32kHz ~ 216kHz
□ μP Interface: 3-wire Serial Interface
□ Master Clock: 128fs/192fs/256fs/384fs/512fs/768fs/1024fs
MS1258-E-01
2011/01
-1-
[AK4621]
□ Power Supply
Analog: 4.75 ~ 5.25V (typ. 5.0V)
Digital: 3.0 ~ 3.6V (typ. 3.3V)
Digital I/O: DVDD ~ 5.25V (typ. 5.0V)
□ Package: 30pin VSOP
□ Ta: -10 ~ 70 °C
■ Block Diagram
AVDD VSS1 VCOM VREF
DVDD TVDD VSS2
AINL+
AINLADC
PDN
HPF
AINR+
AINR-
LRCK
BICK
OVFL/DZFL
OVF
Audio
Interface
SDTO
SDTI
OVFR/DZFR
MCLK
AOUTL+
DATT
SMUTE
AOUTL-
DFS0
DAC
AOUTR+
AOUTR-
Control
Register I/F
P/S
SDFIL DEM0 CSN/ CCLK/ CDTI/
DIF CKS1 CKS0
Figure 1. Block Diagram
MS1258-E-01
2011/01
-2-
[AK4621]
■ Ordering Guide
AK4621EF
AKD4621
−10 ∼ +70°C
30pin VSOP (0.65mm pitch)
Evaluation board for AK4621
■ Pin Layout
VCOM
1
30
AOUTR+
AINR+
2
29
AOUTR-
AINR-
3
28
AOUTL+
AINL+
4
27
AOUTL-
AINL-
5
26
VSS2
VREF
6
25
DVDD
VSS1
7
24
TVDD
AVDD
8
23
SDFIL
P/S
9
22
DEM0
MCLK
10
21
PDN
LRCK
11
20
DFS0
BICK
12
19
CSN/DIF
SDTO
13
18
CCLK/CKS1
SDTI
14
17
CDTI/CKS0
OVFR/DZFR
15
16
OVFL/DZFL
Top View
MS1258-E-01
2011/01
-3-
[AK4621]
■ Compatibility with AK4620B
1. Function
Function
Max fs
ADC Inputs
Input analog PGA
Input digital ATT
ADC S/(N+D)
ADC DR, S/N
AK4620B
AK4621
216kHz
Differential
←
Differential
-
-
Single-ended
0 ~ +18dB
0.5dB/step
Mute,-63.5dB ~ 0dB
0.5dB/step
90dB
110dB
Mute,-63.5dB ~ 0dB
0.5dB/step
100dB
113dB
102dB
115dB
ADC Digital Filter Type
Sharp Roll-off
Sharp Roll-off
ADC Digital Filter SA
ADC Digital Filter GD
DAC S/(N+D)
DAC DR, S/N
100dB
43.2/fs
97dB (0dBFS)
115dB
100dB
39/fs
100dB (-1dBFS)
←
DAC Digital Filter Type
Sharp Roll-off
Slow Roll-off
Sharp Roll-off
DAC Digital Filter SA
DAC Digital Filter GD
75dB
28/fs
Mute, -48dB ~ 0dB
Linear 256 steps
72dB
28/fs
Mute, -48dB ~ 0dB
Linear 256 steps
70dB
27/fs
Output digital Attenuator
DAC DSD mode
DAC Zero-data detection
Parallel Mode
Short Delay
Sharp Roll-off
80dB
14/fs
X
X
X
Slow Roll-off
Short Delay
Sharp Roll-off
70dB
7/fs
73dB
27/fs
Mute, -72dB ~ 0dB
Linear 16 + 256 steps
←
←
X: Available, -: Not Available
2. Register (difference from AK4620B)
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
Register Name
Power Down Control
Reset Control
Clock and Format Control
Deem and Volume Control
Reserved
Reserved
Lch DATT Control
Rch DATT Control
Lch Extension DATT Control
Rch Extension DATT Control
D7
SLOW
D/P
DIF2
SMUTE
IATTL7
IATTR7
DATTL7
DATTR7
0
0
D6
D5
D4
D3
DZFB
ZOE
ZOS
SDDA
DCKS
DCKB
SDAD
AML
DIF1
DIF0
CMODE
CKS1
HPRN
HPLN
ZCEI
ZTM1
IATTL6
IATTL5
IATTL4
IATTL3
IATTR6
IATTR5
IATTR4
IATTR3
DATTL6 DATTL5 DATTL4 DATTL3
DATTR6 DATTR5 DATTR4 DATTR3
0
EXTE
0
EATTL3
0
0
0
EATTR3
These bits were added in the AK4621.
These bits were deleted in the AK4621.
MS1258-E-01
D2
PWVR
AMR
CKS0
ZTM0
IATTL2
IATTR2
DATTL2
DATTR2
EATTL2
EATTR2
D1
PWAD
RSTAD
DFS1
DEM1
IATTL1
IATTR1
DATTL1
DATTR1
EATTL1
EATTR1
D0
PWDA
RSTDA
DFS0
DEM0
IATTL0
IATTR0
DATTL0
DATTR0
EATTL0
EATTR0
2011/01
-4-
[AK4621]
PIN/FUNCTION
No.
Pin Name
I/O
Function
Common Voltage Output Pin, (AVDD)/2
1
VCOM
O
Bias voltage of ADC inputs and DAC outputs.
2
AINR+
I
Rch Positive Input Pin
3
AINRI
Rch Negative Input Pin
4
AINL+
I
Lch Positive Input Pin
5
AINLI
Lch Negative Input Pin
Voltage Reference Input Pin, AVDD
6
VREF
I
Used as a voltage reference by ADC & DAC. VREF is connected externally to filtered
AVDD.
7
VSS1
Analog Ground Pin
8
AVDD
Analog Power Supply Pin, 4.75 ∼ 5.25V
Parallel/Serial Mode Select Pin
9
P/S
I
“L”: Serial Mode, “H”: Parallel Mode
Do not change this pin during PDN pin = “H”.
10 MCLK
I
Master Clock Input Pin
11 LRCK
I
Input/Output Channel Clock Pin
12 BICK
I
Audio Serial Data Clock Pin
13 SDTO
O
Audio Serial Data Output Pin
14 SDTI
I
Audio Serial Data Input Pin
OVFR
O
Rch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
15
DZFR
O
Rch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
OVFL
O
Lch Over Flow Flag Pin (in Parallel mode or when ZOS bit=“0” in Serial Mode)
16
DZFL
O
Lch Zero Detection Flag Pin (when ZOS bit=“1” in Serial Mode)
CDTI
I
Control Data Input Pin (in Serial Mode)
17
CKS0
I
Master Clock Select Pin (in Parallel Mode)
CCLK
I
Control Data Clock Pin (in Serial Mode)
18
CKS1
I
Master Clock Select Pin (in Parallel Mode)
CSN
I
Chip Select Pin in Serial Mode (in Serial Mode)
19
Digital Audio Interface Select Pin (in Parallel Mode)
DIF
I
“L”: 24bit MSB justified, “H”: I2S compatible
20 DFS0
I
Double Speed Sampling Mode Pin
Power-Down Mode Pin
21 PDN
I
“L”: Power down reset and initialize the control register, “H”: Power up
22 DEM0
I
De-emphasis Control Pin
Digital Filter Select Pin
23 SDFIL
I
“L”: Short Delay Sharp Roll Off Filter (ADC), Short Delay Sharp Roll Off Filter (DAC)
“H”: Sharp Roll Off Filter (ADC), Sharp Roll Off Filter (DAC)
24 TVDD
Digital I/O Power Supply Pin, DVDD ∼ 5.25V
25 DVDD
Digital Power Supply Pin, 3.0 ∼ 3.6V
26 VSS2
Digital Ground Pin
27 AOUTLO
Lch Negative Analog Output Pin
28 AOUTL+
O
Lch Positive Analog Output Pin
29 AOUTRO
Rch Negative Analog Output Pin
30 AOUTR+
O
Rch Positive Analog Output Pin
Note 1. All digital input pins (P/S, MCLK, LRCK, BICK, SDTI, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN,
DEM0 and SDFIL) must not be left floating.
MS1258-E-01
2011/01
-5-
[AK4621]
■ Handling of Unused Pin
The unused I/O pin must be processed appropriately as below.
Classification
Analog Input
Analog Output
Digital Output
Pin Name
AINL+, AINLAINR+, AINRAOUTL+, AOUTL-, AOUTR+, AOUTROVFL/DZFL, OVFR/DZFR
Setting
AINL+ pin is connected to AINL- pin.
AINR+ pin is connected to AINR- pin.
These pins must be open.
These pins must be open.
ABSOLUTE MAXIMUM RATINGS
(VSS1=VSS2=0V; Note 2, Note 3)
Parameter
Symbol
min
max
Units
Power Supplies:
Analog
AVDD
-0.3
6.0
V
Digital
DVDD
-0.3
6.0
V
Digital I/O
TVDD
-0.3
6.0
V
Input Current, Any Pin Except Supplies
IIN
mA
±10
Analog Input Voltage
(Note 4)
VINA
-0.3
AVDD+0.3
V
Digital Input Voltage
(Note 5)
VIND
-0.3
TVDD+0.3
V
Ambient Temperature (power applied)
Ta
-10
70
°C
Storage Temperature
Tstg
-65
150
°C
Note 2. All voltages with respect to ground.
Note 3. VSS1 and VSS2 must be connected to the same analog ground plane.
Note 4. AINL+, AINL-, AINR+ and AINR- pins
Note 5. P/S, MCLK, LRCK, BICK, SDTI, CDTI/CKS0, CCLK/CKS1, CSN/DIF, DFS0, PDN, DEM0 and SDFIL pins.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V; Note 2)
Parameter
Symbol
min
typ
Power Supplies
Analog
AVDD
4.75
5.0
(Note 6) Digital
DVDD
3.0
3.3
Digital I/O
TVDD
DVDD
5.0
Voltage Reference
VREF
3.0
Note 2. All voltages with respect to ground.
Note 6: The power up sequence among AVDD, DVDD and TVDD is not critical.
max
5.25
3.6
5.25
AVDD
Units
V
V
V
V
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS1258-E-01
2011/01
-6-
[AK4621]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD=5V, DVDD=3.3V, TVDD=5V; VSS1=VSS2=0V; VREF=AVDD; fs=48kHz; Signal Frequency
=1kHz; 24bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified)
Parameter
min
typ
max
Units
ADC Analog Input Characteristics:
Resolution
24
Bits
Input Voltage
(Note 7)
Vpp
±2.62
±2.82
±3.02
Input Resistance
fs=48kHz
13
kΩ
fs=96kHz
13
kΩ
fs=192kHz
13
kΩ
S/(N+D)
fs=48kHz
-1dBFS
92
102
dB
BW=20kHz
-60dBFS
52
dB
fs=96kHz
-1dBFS
101
dB
BW=40kHz
-60dBFS
48
dB
fs=192kHz
-1dBFS
101
dB
BW=40kHz
-60dBFS
48
dB
Dynamic Range
(-60dBFS with A-weighted)
115
dB
S/N
(A-weighted)
105
115
dB
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0
0.3
dB
Gain Drift
(Note 12)
20
ppm/°C
Power Supply Rejection
(Note 8)
50
dB
DAC Analog Output Characteristics:
Parameter
min
typ
max
Units
Resolution
24
Bits
Dynamic Characteristics
S/(N+D)
fs=48kHz
−1dBFS
90
100
dB
BW=20kHz
52
dB
−60dBFS
fs=96kHz
−1dBFS
97
dB
BW=40kHz
49
dB
−60dBFS
fs=192kHz
−1dBFS
97
dB
BW=40kHz
49
dB
−60dBFS
115
dB
Dynamic Range (−60dBFS with A-weighted) (Note 9, Note 10)
S/N
(A-weighted) (Note 10, Note 11)
107
115
dB
Interchannel Isolation (1kHz)
90
110
dB
DC Accuracy
Interchannel Gain Mismatch
0
0.3
dB
Gain Drift
(Note 12)
20
ppm/°C
Output Voltage
(Note 13)
Vpp
±2.6
±2.8
±3.0
Load Capacitance
25
pF
Load Resistance
(Note 14)
2
kΩ
Note 7. Full scale (0dB) of the input voltage. Vin (typ) = ±2.82Vpp x VREF/5.
Note 8. PSR is applied to AVDD, DVDD, TVDD with 1kHz, 50mVpp. VREF pin is held a constant voltage.
Note 9. 100dB at 16bit data and 114dB at 20bit data.
Note 10. By Figure 20. External LPF Circuit Example 2.
Note 11. S/N does not depend on input bit length.
Note 12. The voltage on VREF is held +5V externally.
Note 13. Full scale voltage (0dB). Output voltage scales with the voltage of VREF.
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = 5.6Vpp x VREF/5.
Note 14. For AC-load.
MS1258-E-01
2011/01
-7-
[AK4621]
Parameter
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
AVDD
DVDD+TVDD (fs=48kHz)
(fs=96kHz)
(fs=192kHz)
Power-down mode (PDN pin = “L”)
(Note 15)
AVDD
DVDD+TVDD
Note 15. All digital input pins are held TVDD or VSS2.
MS1258-E-01
min
typ
max
Units
-
34
11
20
27
51
30
41
mA
mA
mA
mA
-
10
10
100
100
μA
μA
2011/01
-8-
[AK4621]
ADC SHARP ROLL OFF FILTER CHARACTERISTICS (fs=48kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Normal Speed Mode; SDAD bit = “0”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 16) −0.005dB
0
21.8
kHz
−0.02dB
22.0
kHz
22.3
kHz
−0.06dB
24.0
kHz
−6.0dB
Stopband
(Note 16)
SB
26.5
kHz
Passband Ripple
PR
dB
±0.005
Stopband Attenuation
SA
100
dB
Group Delay
(Note 17)
GD
39
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF):
Frequency Response (Note 16) −3dB
FR
1.0
Hz
6.5
Hz
−0.1dB
ADC SHARP ROLL OFF FILTER CHARACTERISTICS (fs=96kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Double Speed Mode; SDAD bit = “0”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 16) −0.005dB
0
43.7
kHz
−0.02dB
44.1
kHz
44.5
kHz
−0.06dB
48.0
kHz
−6.0dB
Stopband
(Note 16)
SB
53.0
kHz
Passband Ripple
PR
dB
±0.005
Stopband Attenuation
SA
100
dB
Group Delay
(Note 17)
GD
39
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF):
Frequency Response (Note 16) −3dB
FR
2.0
Hz
13.0
Hz
−0.1dB
MS1258-E-01
2011/01
-9-
[AK4621]
ADC SHARP ROLL OFF FILTER CHARACTERISTICS (fs=192kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Quad Speed Mode; SDAD bit = “0”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 16) −0.005dB
0
87.0
kHz
−0.02dB
88.2
kHz
89.0
kHz
−0.06dB
96.0
kHz
−6.0dB
Stopband
(Note 16)
SB
106.0
kHz
Passband Ripple
PR
dB
±0.01
Stopband Attenuation
SA
100
dB
Group Delay
(Note 17)
GD
36
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF):
Frequency Response (Note 16) −3dB
FR
4.0
Hz
26.0
Hz
−0.1dB
Note 16: The passband and stopband frequencies scale with fs. Each response refers to that of 1kHz
Note 17: The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the
setting of 24bit data both channels to the ADC output register for ADC. If the signal is outputted to the SDTO pin,
group delay is increased 0.5/fs from the above value.
MS1258-E-01
2011/01
- 10 -
[AK4621]
ADC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs=48kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Normal Speed Mode; SDAD bit = “1”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 16) −0.01dB
0
21.7
kHz
−0.1dB
22.1
kHz
23.8
kHz
−3.0dB
24.4
kHz
−6.0dB
Stopband
(Note 16)
SB
28.2
kHz
Passband Ripple
PR
dB
±0.01
Stopband Attenuation
SA
80
dB
Group Delay
(Note 17)
GD
14
1/fs
Group Delay Distortion
±0.01
ΔGD
μs
ADC Digital Filter (HPF):
Frequency Response (Note 16) −3dB
FR
1.0
Hz
6.5
Hz
−0.1dB
ADC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs=96kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Double Speed Mode; SDAD bit = “1”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 16) −0.01dB
0
43.3
kHz
−0.1dB
44.2
kHz
47.6
kHz
−3.0dB
48.9
kHz
−6.0dB
Stopband
(Note 16)
SB
55.9
kHz
Passband Ripple
PR
dB
±0.01
Stopband Attenuation
SA
80
dB
Group Delay
(Note 17)
GD
14
1/fs
Group Delay Distortion
±0.013
ΔGD
μs
ADC Digital Filter (HPF):
Frequency Response (Note 16) −3dB
FR
2.0
Hz
13.0
Hz
−0.1dB
ADC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs=192kHz)
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Quad Speed Mode; SDAD bit = “1”)
Parameter
Symbol
min
typ
max
Units
ADC Digital Filter (Decimation LPF):
PB
Passband
(Note 16) −0.01dB
0
76.1
kHz
−0.1dB
81.1
kHz
99.9
kHz
−3.0dB
106.7
kHz
−6.0dB
Stopband
(Note 16)
SB
141.1
kHz
Passband Ripple
PR
dB
±0.01
Stopband Attenuation
SA
79
dB
Group Delay
(Note 17)
GD
11
1/fs
Group Delay Distortion
0
ΔGD
μs
ADC Digital Filter (HPF):
Frequency Response (Note 16) −3dB
FR
4.0
Hz
26.0
Hz
−0.1dB
MS1258-E-01
2011/01
- 11 -
[AK4621]
DAC SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 48kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Normal Speed Mode; DEM = OFF;
SLOW bit = “0”, SDDA bit = “0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.04dB
PB
0
21.8
kHz
-6.0dB
24.0
kHz
Stopband
(Note 18)
SB
26.2
kHz
Passband Ripple
PR
±0.06
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 19)
GD
27
1/fs
Digital Filter + SCF
dB
Frequency Response: 0 ∼ 20.0kHz
± 0.2
DAC SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Double Speed Mode; DEM = OFF;
SLOW bit = “0”, SDDA bit = “0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.04dB
PB
0
43.5
kHz
-6.0dB
48.0
kHz
Stopband
(Note 18)
SB
52.4
kHz
Passband Ripple
PR
±0.06
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 19)
GD
27
1/fs
Digital Filter + SCF
dB
Frequency Response: 0 ∼ 40.0kHz
± 0.3
DAC SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Quad Speed Mode; DEM = OFF;
SLOW bit = “0”, SDDA bit = “0”)
Parameter
symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.02B
PB
0
87.0
kHz
-6.0dB
95.9
kHz
Stopband
(Note 18)
SB
105
kHz
Passband Ripple
PR
±0.06
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 19)
GD
27
1/fs
Digital Filter + SCF
+0/-1
dB
Frequency Response: 0 ∼ 80.0kHz
Note 18. The passband and stopband frequencies scale with fs. Each response refers to that of 1kHz.
Note 19. Delay time caused by digital filtering. This time is from setting the 16/20/24bit data of both channels to input
register to the output of analog signal.
MS1258-E-01
2011/01
- 12 -
[AK4621]
DAC SLOW ROLL OFF FILTER CHARACTERISTICS (fs = 48kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Normal Speed Mode; DEM = OFF;
SLOW bit = “1”, SDDA bit = “0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.07dB
PB
0
8.9
kHz
-3.0dB
19.8
kHz
Stopband
(Note 18)
SB
42.6
kHz
±0.07
Passband Ripple
PR
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 19)
GD
27
1/fs
Digital Filter + SCF
+0/-5
dB
Frequency Response: 0 ∼ 20.0kHz
DAC SLOW ROLL OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Double Speed Mode; DEM = OFF;
SLOW bit = “1”, SDDA bit = “0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.07dB
PB
0
17.7
kHz
-3.0dB
39.5
kHz
Stopband
(Note 18)
SB
85.1
kHz
Passband Ripple
PR
±0.07
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 19)
GD
27
1/fs
Digital Filter + SCF
+0/-4
dB
Frequency Response: 0 ∼ 40.0kHz
DAC SLOW ROLL OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Quad Speed Mode; DEM = OFF;
SLOW bit = “1”, SDDA bit = “0”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.07dB
PB
0
35.5
kHz
-3.0dB
79.0
kHz
Stopband
(Note 18)
SB
170.7
kHz
Passband Ripple
PR
±0.07
dB
Stopband Attenuation
SA
73
dB
Group Delay
(Note 19)
GD
27
1/fs
Digital Filter + SCF
+0/-5
dB
Frequency Response: 0 ∼ 80.0kHz
MS1258-E-01
2011/01
- 13 -
[AK4621]
DAC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 48kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Normal Speed Mode; DEM = OFF;
SLOW bit = “0”, SDDA bit = “1”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.04dB
PB
0
21.8
kHz
-6.0dB
24.0
kHz
Stopband
(Note 18)
SB
26.2
kHz
Passband Ripple
PR
±0.06
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 19)
GD
7
1/fs
Digital Filter + SCF
dB
Frequency Response: 0 ∼ 20.0kHz
± 0.2
DAC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 96kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Double Speed Mode; DEM = OFF;
SLOW bit = “0”, SDDA bit = “1”)
Parameter
Symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.03dB
PB
0
43.5
kHz
-6.0dB
48.0
kHz
Stopband
(Note 18)
SB
52.4
kHz
Passband Ripple
PR
±0.06
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 19)
GD
7
1/fs
Digital Filter + SCF
dB
Frequency Response: 0 ∼ 40.0kHz
± 0.3
DAC SHORT DELAY SHARP ROLL OFF FILTER CHARACTERISTICS (fs = 192kHz)
(Ta = 25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; Quad Speed Mode; DEM = OFF;
SLOW bit = “0”, SDDA bit = “1”)
Parameter
symbol
min
typ
max
Units
Digital Filter
Passband
(Note 18) -0.02dB
PB
0
87.0
kHz
-6.0dB
96.2
kHz
Stopband
(Note 18)
SB
104.9
kHz
Passband Ripple
PR
±0.06
dB
Stopband Attenuation
SA
70
dB
Group Delay
(Note 19)
GD
7
1/fs
Digital Filter + SCF
+0/-1
dB
Frequency Response: 0 ∼ 80.0kHz
MS1258-E-01
2011/01
- 14 -
[AK4621]
DC CHARACTERISTICS
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
High-Level Output Voltage (Iout=-100μA)
VOH
DVDD-0.5
VOL
Low-Level Output Voltage (Iout=100μA)
Input Leakage Current
Iin
-
typ
-
max
TVDD
30%DVDD
0.5
±10
Units
V
V
V
V
μA
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=4.75 ∼ 5.25V; DVDD=3.0 ∼ 3.6V, TVDD=DVDD ∼ 5.25V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
fCLK
8.192
55.296
MHz
Pulse Width Low
tCLKL
0.4/fCLK
ns
Pulse Width High
tCLKH
0.4/fCLK
ns
LRCK Frequency
(Note 20)
fsn
32
54
kHz
Normal Speed Mode (DFS0=“0”, DFS1=“0”)
fsd
54
108
kHz
Double Speed Mode (DFS0=“1”, DFS1=“0”)
fsq
108
216
kHz
Quad Speed Mode (DFS0=“0”, DFS1=“1”)
45
55
%
Duty Cycle
PCM Audio Interface Timing
BICK Period
Normal Speed Mode
tBCK
1/128fsn
ns
Double Speed Mode
tBCK
1/64fsd
ns
Quad Speed Mode
tBCK
1/64fsq
ns
BICK Pulse Width Low
tBCKL
33
ns
Pulse Width High
tBCKH
33
ns
LRCK Edge to BICK “↑”
(Note 21)
tLRB
20
ns
tBLR
20
ns
BICK “↑” to LRCK Edge
(Note 21)
tLRS
20
ns
LRCK to SDTO (MSB) (Except I2S mode)
tBSD
20
ns
BICK “↓” to SDTO
tSDH
20
ns
SDTI Hold Time
tSDS
20
ns
SDTI Setup Time
Note 20. When the normal/double/quad speed modes are switched, the AK4621 must be reset by the PDN pin or RSTN
bit.
Note 21. BICK rising edge must not occur at the same time as LRCK edge.
MS1258-E-01
2011/01
- 15 -
[AK4621]
Parameter
Symbol
min
Control Interface Timing
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
50
CDTI Hold Time
tCDH
50
CSN “H” Time
tCSW
150
CSN “↓” to CCLK “↑”
tCSS
50
tCSH
50
CCLK “↑” to CSN “↑”
Reset Timing
PDN Pulse Width
(Note 22)
tPD
150
tPDV
RSTAD “↑” to SDTO Valid
(Note 23)
Note 22. The AK4621 can be reset by bringing the PDN pin “L”.
Note 23. These cycles are the number of LRCK rising from RSTAD bit.
MS1258-E-01
typ
max
Units
-
-
ns
ns
ns
ns
ns
ns
ns
ns
516
-
ns
1/fs
2011/01
- 16 -
[AK4621]
■ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 2. Clock Timing
VIH
VIL
LRCK
tBLR
tLRB
VIH
VIL
BICK
tLRS
tBSD
50%TVDD
SDTO
tSDS
tSDH
VIH
VIL
SDTI
Figure 3. Audio Interface Timing
MS1258-E-01
2011/01
- 17 -
[AK4621]
VIH
CSN
VIL
tCSH
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
A4
VIH
VIL
Figure 4. WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
tCSS
VIH
CCLK
CDTI
VIL
D3
D2
D1
D0
VIH
VIL
Figure 5. WRITE Data Input Timing
tPD
PDN
VIL
Figure 6. Power Down & Reset Timing
MS1258-E-01
2011/01
- 18 -
[AK4621]
OPERATION OVERVIEW
■ System Clock Input
The AK4621 requires MCLK, BICK and LRCK external clocks. MCLK must be synchronized with LRCK but the phase
is not critical. The AK4621 is automatically placed in power-down state when MCLK is stopped more than 9.38µs during
a normal operation (PDN pin =“H”), then the digital output becomes “0” data and the analog output becomes Hi-Z. When
MCLK and LRCK are input again, the AK4621 exit power-down state and starts the operation. After exiting system reset
(PDN pin =“L”→“H”) at power-up and other situations, the AK4621 is in power-down mode until MCLK is supplied.
As the AK4621 includes the phase detect circuit for LRCK, the AK4621 is reset automatically when the synchronization
is out of phase by changing the clock frequencies.
1. Serial mode (P/S pin= “L”)
As shown in Table 1, Table 2 and Table 3, select the MCLK frequency by setting CMODE, CKS1-0 and DFS1-0 bits.
These registers are changed when RSTAD bit = RSTDA bit = “0”.
DFS1 bit
0
0
1
1
(default)
MCLK
MCLK
MCLK
Normal Speed
Double Speed
Quad Speed
(DFS1-0 = “00”)
(DFS1-0 = “01”)
(DFS1-0 = “10”)
0
0
256fs
N/A
N/A
0
1
512fs
256fs
128fs
1
0
1024fs
512fs
256fs
1
1
N/A
Auto Setting Mode (*)
N/A
0
0
384fs
N/A
N/A
0
1
768fs
384fs
192fs
Table 2. Master Clock frequency in Serial Mode (“*”; refer to Table 3.) (N/A: Not Available)
CMODE bit
0
0
0
0
1
1
DFS0 bit
Mode
Sampling Rate
0
Normal speed
32kHz-54kHz
1
Double speed
54kHz-108kHz
0
Quad speed
108kHz-216kHz
1
N/A
Table 1. Sampling Speed in Serial Mode (N/A: Not Available)
CKS1 bit
CKS0 bit
(default)
The Auto Setting Mode detects MCLK/LRCK ratio and selects Normal/Double/Quad speed mode automatically (Table
3).
MCLK/LRCK ratio
Mode
Sampling Rate
512 or 768
Normal speed
32kHz-54kHz
256 or 384
Double speed
54kHz-108kHz
128 or 192
Quad speed
108kHz-216kHz
Table 3. Auto Setting Mode in Serial Mode (DFS1-0 bits = “01”, CMODE bit = “0”, CKS1-0 bits = “11”)
MS1258-E-01
2011/01
- 19 -
[AK4621]
2. Parallel mode (P/S pin= “H”)
As shown in Table 4, Table 5 and Table 6, select the MCLK frequency with the CKS0-1 and DFS0 pins. These pins must
be changed when the PDN pin = “L”.
DFS0 pin
L
H
Mode
Sampling Rate
Normal speed
32kHz-54kHz
Double speed
54kHz-108kHz
Table 4. Sampling Speed in Parallel Mode
MCLK
MCLK
Normal Speed
Double Speed
(DFS0 pin = “L”)
(DFS0 pin = “H”)
L
L
256fs
N/A
L
H
512fs
256fs
H
L
384fs
Auto Setting Mode (*)
H
H
1024fs
512fs
Table 5. Master Clock Frequency in Parallel Mode (“*”; refer to Table 6.) (N/A: Not Available)
CKS1 pin
CKS0 pin
The Auto Setting Mode detects MCLK/LRCK ratio and selects Normal/Double/Quad speed mode automatically.
(Table 6).
MCLK/LRCK ratio
Mode
Sampling Rate
512 or 768
Normal speed
32kHz-54kHz
256 or 384
Double speed
54kHz-108kHz
128 or 192
Quad speed
108kHz-216kHz
Table 6. Auto Setting Mode in Parallel Mode (DFS0 pin = “H”, CKS1 pin = “H”, CKS0 pin = “L”)
MCLK (Normal speed)
256fs
512fs
1024fs
384fs
768fs
MCLK (Quad speed)
128fs
256fs
192fs
fs=44.1kHz
11.2896MHz
22.5792MHz
45.1584MHz
16.9344MHz
33.8688MHz
fs=48kHz
12.288MHz
24.576MHz
49.152MHz
18.432MHz
36.864MHz
MCLK (Double speed)
N/A
256fs
512fs
N/A
384fs
fs=88.2kHz
N/A
22.5792MHz
45.1584MHz
N/A
33.8688MHz
fs=96kHz
N/A
24.576MHz
49.152MHz
N/A
36.864MHz
fs=176.4kHz
fs=192kHz
22.5792MHz 24.576MHz
45.1584MHz 49.152MHz
33.8688MHz 36.864MHz
Table 7. Master Clock Frequency Example (N/A: Not Available)
MS1258-E-01
2011/01
- 20 -
[AK4621]
■ Audio Serial Interface Format
Five serial modes are supported and selected by the DIF2-0 bits in Serial Mode (two modes by DIF pin in Parallel Mode)
as shown in Table 8 and Table 9. In all modes the serial data has MSB first, 2’s complement format. The SDTO is clocked
out on the falling edge of BICK and the SDTI is latched on the rising edge. Mode2 can be used for 20 and 16 MSB
justified formats by zeroing the unused LSBs.
Mode
0
1
2
3
4
DIF2
0
0
0
0
1
DIF1
0
0
1
1
0
Mode
2
3
DIF0
0
1
0
1
0
DIF pin
L
H
SDTO
SDTI
24bit, MSB justified
16bit, LSB justified
24bit, MSB justified
20bit, LSB justified
24bit, MSB justified
24bit, MSB justified
24bit, I2S
24bit, I2S
24bit, MSB justified
24bit, LSB justified
Table 8. Audio Data Format (Serial Mode)
LRCK
H/L
H/L
H/L
L/H
H/L
SDTO
SDTI
LRCK
24bit, MSB justified
24bit, MSB justified
H/L
24bit, I2S
24bit, I2S
L/H
Table 9. Audio Data Format (Parallel Mode)
BICK
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
≥ 48fs
(default)
BICK
≥ 48fs
≥ 48fs
LRCK
0
1
2
3
17
18
19
20
30
31
0
1
2
3
17
18
19
20
31
0
1
BICK(64fs)
SDTO(o)
23 22 21
SDTI(i)
7
Don’t Care
6
5
4
3
15 14 13 12 11
23 22 21
2
1
7
Don’t Care
0
6
5
4
3
15 14 13 12 11
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
23
2
1
0
Rch Data
Figure 7. Mode 0 Timing
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
12 11 10
Don’t Care
19 18
0
8
23 22
7
1
0
12 11 10
Don’t Care
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
19 18
0
8
23
7
1
0
Rch Data
Figure 8. Mode 1 Timing
MS1258-E-01
2011/01
- 21 -
[AK4621]
LRCK
0
1
2
18
19
20
21
22
23
24
25
0
1
2
18
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
23
Rch Data
Figure 9. Mode 2 Timing
LRCK
0
1
2
3
19
20
21
22
23
24
25
0
1
2
3
19
20
21
22
23
24
25
0
1
BICK(64fs)
SDTO(o)
23 22
5
4
3
2
1
0
23 22
5
4
3
2
1
0
SDTI(i)
23 22
5
4
3
2
1
0
Don’t Care 23 22
5
4
3
2
1
0 Don’t Care
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 10. Mode 3 Timing
LRCK
0
1
2
8
9
10
20
21
31
0
1
2
8
9
10
20
21
31
0
1
BICK(64fs)
SDTO(o)
SDTI(i)
23 22
16 15 14
Don’t Care
23:MSB, 0:LSB
23 22
0
12 11
23 22
1
0
16 15 14
Don’t Care
Lch Data
23 22
0
12 11
23
1
0
Rch Data
Figure 11. Mode 4 Timing
MS1258-E-01
2011/01
- 22 -
[AK4621]
■ Output Volume
The AK4621 includes channel independent digital output volumes (DATT) with 256 levels and extension digital output
volumes (EATT) with 16 levels at linear steps including MUTE. When EXTE bit = “1”, the extension digital output
volumes are enabled. These volumes are in front of the DAC. If the extension digital output volumes are disabled, the
volumes can attenuate the input data from 0dB to −48dB and mute. If the extension digital output volumes are enabled,
the volumes can attenuate the input data from 0dB to −72dB and mute. When changing levels, transitions are executed via
soft changes, eliminating any switching noises. The transition time of 1 level, all 256 levels and all 256+16 is shown in
Table 10. Volume calculating formula is shown in Table 13.
Transition Time
255 to 0
255+15 to 0
1 Level
(EXTE bit = “0”)
(EXTE bit = “1”)
Normal Speed Mode
4LRCK
1020LRCK
1080LRCK
Double Speed Mode
8LRCK
2040LRCK
2160LRCK
Quad Speed Mode
16LRCK
4080LRCK
4320LRCK
Table 10. Output Digital Volume Transition Time
Sampling Speed
DATTL7-0 bits
EATTL3-0 bits
DATT_DATA
GAIN(0dB)
DATTR7-0 bits
EATTR3-0 bits
FFH
255
+0
FEH
254
-0.034
FDH
253
-0.068
FH
:
:
:
02H
2
-42.11
01H
1
-48.13
00H
Mute
Table 11. Output Digital Volume Setting (EXTE bit = “0”)
DATTL7-0 bits
DATTR7-0 bits
FFH
FEH
FDH
:
02H
01H
DATT_DATA
EATTL3-0 bits
EATT_DATA
EATTR3-0 bits
(default)
GAIN(0dB)
255
254
253
:
2
1
+0
-0.034
-0.068
FH
:
-42.11
-48.13
FH
15
-48.72
EH
14
-49.32
:
:
:
00H
2H
2
-66.22
1H
1
-72.25
0H
Mute
Note 24. If the volume is set from DATT gain to EATT gain or from EATT gain to DATT gain, these register must be
wrote continuously within 4LRCK cycles in Normal Speed Mode. When the volume setting is not complete
within 4LRCK cycles, the volume transition may stop.
Table 12. Output Digital Volume Setting (EXTE bit = “1”)
MS1258-E-01
2011/01
- 23 -
[AK4621]
DATTL7-0 bits
DATTR7-0 bits
FFH
:
01H
00H
EATTL3-0 bits
EATTR3-0 bits
GAIN(dB)
FH
20 log10 (DATT_DATA / 255)
FH
20 log10 (EATT_DATA / 4095)
:
1H
Table 13. Output Digital Volume Formula
■ Overflow Detection
The ADC has a channel independent overflow detection function. This function is enabled in parallel control mode, or
when the ZOS bit = ZOE bit = “0” in serial control mode. OVFL/R pins go to “H” if each Lch/Rch analog input overflows
(exceeds -0.3dBFS). The output of each OVFL/R pin has same group delay as ADC against analog inputs. OVFL/R pin is
“L” for 516/fs (=10.8ms @fs=48kHz) after the PDN pin = “↑”, and then overflow detection is enabled.
■ Zero Detection
The DAC has a channel-independent zero detect function. The zero detect function is enabled when the ZOS bit = “1” and
the ZOE bit = “0” in serial control mode. When the input data at both channels is continuously zero for 8192 LRCK
cycles, the DZF pin of each channel goes to “H”. The DZF pin of each channel immediately returns to “L” if the input data
of each channel is not zero after DZF “H”. If the RSTDA bit is “0”, the DZF pins of both channels go to “H”. The DZF
pins of both channels return to “L” in 2~3fs if the input data of each channel is not zero. Zero detect function can be
disabled by the ZOE bit. In this case, the DZF pins of both channels are always “L”. The DZFB bit can invert the polarity
of the DZF pin.
■ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz at fs=48kHz.
The digital high pass filter cut-off frequency scales with the sampling rate (fs). In parallel mode, the HPF is always
enabled. In serial mode, the HPF can control each channel by HPLN/HPRN bits.
MS1258-E-01
2011/01
- 24 -
[AK4621]
■ Digital Filter
The AK4621 has two kinds of Digital Filter for ADC and three kinds of Digital Filter for DAC. The outputs of ADC and
DAC can be controlled by using the SDFIL pin or SDAD/SDDA/SLOW bits.
SDFIL pin
L
H
ADC
DAC
Short Delay Sharp Roll Off Filter Short Delay Sharp Roll Off Filter
Sharp Roll Off Filter
Sharp Roll Off Filter
Table 14. Digital Filter Selection in Parallel Mode
SDAD bit
ADC
0
Sharp Roll Off Filter
(default)
1
Short Delay Sharp Roll Off Filter
Table 15. ADC Digital Filter Selection in Serial Mode
SDDA bit
SLOW bit
DAC
0
0
Sharp Roll Off Filter
(default)
0
1
Slow Roll Off Filter
1
0
Short Delay Sharp Roll Off Filter
1
1
N/A
Table 16. DAC Digital Filter Selection in Serial Mode (N/A: Not Available)
■ De-emphasis Filter
The DAC includes a digital de-emphasis filter (tc=50/15μs for 32kHz, 44.1kHz or 48kHz sampling rates) by an integrated
IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter. This filter is always OFF in double and quad speed
modes. The DEM0 pin and DEM0 bit are OR’d in serial control mode. In parallel control mode, the DEM1 bit is fixed to
“0” and only the DEM0 pin can be controlled (44.1kHz or OFF).
No
0
1
2
3
DEM1
DEM0
Mode
0
0
44.1kHz
(default)
0
1
OFF
1
0
48kHz
1
1
32kHz
Table 17. De-emphasis control (Normal Speed Mode)
MS1258-E-01
2011/01
- 25 -
[AK4621]
■ Soft Mute Operation
Soft mute operation is performed in the digital domain of the DAC input. When the SMUTE bit goes to “1”, the output
signal is attenuated by −∞ during ATT_DATA × ATT transition time (Table 10) from the current ATT level. When
SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during
ATT_DATA × ATT transition time. If soft mute is cancelled before attenuating to −∞ after starting the operation, the
attenuation is discontinued and returns to ATT level by the same cycle. The soft mute is effective for changing the signal
source without stopping the signal transmission.
S M U T E bit
(1)
(1)
AT T _Level
(3)
A ttenuation
-∞
GD
(2)
GD
(2)
AOUT
D ZF pin
(4)
8192/fs
Notes:
(1) ATT_DATA × ATT transition time (Table 10). For example, in Normal Speed Mode, if the EATT is disabled, this
time is 1020LRCK cycles (1020/fs). If the EATT is enabled, this time is 1080LRCK cycles (1080/fs).
(2) Analog output corresponding to digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating −∞, the attenuation is discontinued and returned to ATT level by the
same cycle.
(4) When the input data at each channel is continuously zero for 8192 LRCK cycles, the DZF pin of each channel goes
to “H”. The DZF pin immediately returns to “L” if input data are not zero after going to “H”.
Figure 12. Soft Mute and Zero Detection
MS1258-E-01
2011/01
- 26 -
[AK4621]
■ Power Down & Reset
The ADC and DAC of AK4621 are placed in power-down mode by bringing the PDN pin = “L”. Each digital filter is also
reset at the same time. The internal register values are initialized by bringing the PDN pin to “L”. This reset must always
be done after power-up. As both control registers of the ADC and the DAC go to the reset state (RSTAD bit = RSTDA bit
= “0”), each register must be cleared after executing the reset. In the case of the ADC, an analog initialization cycle starts
after exiting the power-down or reset state. The output data (SDTO) is available after 516 cycles of LRCK clock. This
initialization cycle does not affect the DAC operation. Power down mode can be also controlled by the registers (PWAD
bit, PWDA bit).
Power Supply
PDN pin
RSTAD/RSTDA bit
PWAD/PWDA bit
PWVR bit
ADC Internal State
(1)
PD
Reset
(1)
(1)
INITA
Normal
GD (2)
PD
INITA
Normal
GD (2)
PD
INITA
Normal
GD (2)
ADC In (Analog)
ADC Out (Digital)
DAC Internal State
“0” data (3)
“0” data (3)
PD
Reset
Normal
PD
Normal
(4)
DATT
DAC In (Digital)
DAC Out (Analog)
External Mute
Example
Clock In
MCLK, LRCK, BICK
FFH
“0” data (3)
PD
(4)
FFH*1 FFH=>XXH
XXH
Normal
(4)
XXH*2 XXH=>YYH
YYH
YYH*3 YYH=>ZZH
ZZH
“0”data
(5)
VCOM
Hi-Z
(6)
Mute On (7)
(6)
(5)
Hi-Z
GD (2)
(6)
FADE
(6)
GD (2)
FADE
Mute On (7)
(5)
Hi-Z
(6)
GD (2)
(6)
FADE
Mute On (7)
(8)
Stop
Don’t care
Notes:
(1) After exiting power down and reset state, the analog part of ADC is initialized (516/fs).
(2) Digital output corresponding to analog input and analog input corresponding to digital input have group delay
(GD).
(3) ADC output is “0” data in power-down state.
(4) After exiting power down and reset state, ATT value fades in/out.
*1 When RSTDA is “L” and DATT value is written to “XXH”, DATT value changes from FFH to XXH
according to fade operation.
*2 When PWDA is “L” and DATT value is written to “YYH”, DATT value changes from XXH to YYH
according to fade operation.
*3 When the external clocks (MCLK, SCLK, LRCK) are stopped and DATT value is written to “ZZH”, DATT
value changes from YYH to ZZH according to fade operation.
(5) In the power-down mode, the DAC output is VCOM level. In the reset state, the DAC output is floating (Hi-z).
(6) Click noise occurs after RSTDA bit or PWDA bit is changed.
(7) Mute the analog output externally if the click noise (6) influences system application.
(8) When MCLK is stopped more than 9.38µs, the AK4621 becomes power down mode. Then ADC output is “0” data
and DAC output is floating (Hi-Z).
Figure 13. Reset & Power down sequence in serial mode
MS1258-E-01
2011/01
- 27 -
[AK4621]
In parallel mode, both ADC and DAC are powered up when releasing internal reset state by the PDN pin = “H”. When the
PDN pin is “L”, after exiting power down mode ADC s output “0” during first 516/fs cycles. DAC does not have the
initialization cycle and the operation of fade-in.
Power Supply
PDN pin
(1)
ADC Internal State
PD
(1)
(1)
INITA
Normal
GD (2)
PD
INITA
Normal
GD (2)
PD
INITA
Normal
GD (2)
ADC In (Analog)
ADC Out (Digital)
DAC Internal State
DAC In (Digital)
DAC Out (Analog)
External Mute
Example
Clock In
MCLK, LRCK, BICK
“0” data (3)
“0” data (3)
PD
Normal
“0”data
(4)
Hi-Z
GD (2)
(5)
Mute On (6)
PD
PD
Normal
(4)
Hi-Z
(5)
“0” data (3)
GD (2)
GD (2)
(4)
Hi-Z
(5)
Mute On (6)
Normal
(5)
(5)
Mute On (6)
(7)
Stop
Don’t care
Notes:
(1) After exiting power down and reset state, the analog part of ADC is initialized (516/fs).
(2) Digital output corresponding to analog input and analog input corresponding to digital input have group delay
(GD).
(3) ADC output is “0” data in power-down state.
(4) DAC output is floating (Hi-z) in power-down state.
(5) Click noise occurs at the rising/falling edge of PDN.
(6) Mute the analog output externally if the click noise (5) influences system application.
(7) When MCLK is stopped more than 9.38µs, the AK4621 becomes power down mode. Then ADC output is “0” data
and DAC output is floating (Hi-Z).
Figure 14. Reset & Power Down Sequence in parallel mode
MS1258-E-01
2011/01
- 28 -
[AK4621]
■ Serial Control Interface
The internal registers may be written by the 3-wire μP interface pins: CSN, CCLK, CDTI. The data on this interface
consists of Chip address (2bits, C0/1) Read/Write (1 bit), Register address (MSB first, 5 bits) and Control data (MSB first,
8 bits). Address and data are clocked in on the rising edge of CCLK and data is latched after the 16th rising edge of
CCLK, following a high-to-low transition of CSN. Operation of the control serial port may be completely asynchronous
with the audio sample rate. The maximum clock speed of the CCLK is 5MHz. The chip address is fixed to “10”. The
access to the chip address except for “10” is invalid. PDN pin = “L” resets the registers to their default values.
Function
Parallel mode
Serial mode
Overflow detection
X
X
DAC Slow Roll Off Filter
X
Zero detection
X
Soft Mute
X
DATT
X
HPF OFF
X
16/20/24 bit LSB justified format of DAC
X
MCLK = 256fs @ Quad Speed
X
De-emphasis: 32kHz, 48kHz
X
Table 18. Function List (X: available, -: not available)
CSN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (Fixed to “10”)
READ/WRITE (Fixed to “1”:WRITE)
Register Address
Control data
Figure 15. Control I/F Timing
* READ command is not supported.
* The control data can not be written when the CCLK rising edge is 15times or less or 17times or more during CSN is “L”.
MS1258-E-01
2011/01
- 29 -
[AK4621]
■ Register Map
Addr
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
Register Name
Power Down Control
Reset Control
Clock and Format Control
Deem and Volume Control
Reserved
Reserved
Lch DATT Control
Rch DATT Control
Lch Extension DATT Control
Rch Extension DATT Control
D7
SLOW
0
DIF2
SMUTE
0
0
DATTL7
DATTR7
0
0
D6
DZFB
0
DIF1
HPRN
0
0
DATTL6
DATTR6
0
0
D5
ZOE
0
DIF0
HPLN
0
0
DATTL5
DATTR5
EXTE
0
D4
ZOS
SDAD
CMODE
0
0
0
DATTL4
DATTR4
0
0
D3
SDDA
0
CKS1
0
0
0
DATTL3
DATTR3
EATTL3
EATTR3
D2
PWVR
0
CKS0
0
0
0
DATTL2
DATTR2
EATTL2
EATTR2
D1
PWAD
RSTAD
DFS1
DEM1
0
0
DATTL1
DATTR1
EATTL1
EATTR1
D0
PWDA
RSTDA
DFS0
DEM0
0
0
DATTL0
DATTR0
EATTL0
EATTR0
Note 25: Data must not be written to addresses 0AH through 1FH.
PDN pin = “L” resets the registers to their default values.
■ Control Register Setup Sequence
When the PDN pin goes “L” to “H” upon power-up etc., the AK4621 will be ready for normal operation by the sequence
below. In this case, all control registers are set to default values and the AK4621 is in the reset state.
(1) Set the clock mode and the audio data interface mode.
(2) Cancel the reset state by setting RSTAD bit or RSTDA bit to “1”. Refer to Reset Contorl Register (01H).
(3) ADC output and DAC output must be muted externally until canceling each reset state.
The clock mode must be changed after setting RSTAD bit and RSTDA bit to “0”. At that time, ADC outputs and DAC
outputs must be muted externally.
MS1258-E-01
2011/01
- 30 -
[AK4621]
■ Register Definitions
Addr
00H
Register Name
Power Down Control
Default
D7
SLOW
0
D6
DZFB
0
D5
ZOE
0
D4
ZOS
0
D3
SDDA
0
D2
PWVR
1
D1
PWAD
1
D0
PWDA
1
PWDA: DAC power down
0: Power down
1: Power up (default)
When PWDA bit = “0”, only the DAC block is powered down and the AOUT becomes Hi-z immediately.
In this time, all registers are not initialized, and register writings are valid. After exiting power down mode,
the OATT fades in/out the setting value of the control register (06H, 07H, 08H, 09H). The analog output
must be muted externally as a pop noise may occur when entering and exiting this mode.
PWAD: ADC power down
0: Power down
1: Power up (default)
When PWAD bit = “0”, only the ADC block is powered-down and the SDTO pin becomes “L”
immediately. After exiting power down mode, the ADC outputs “0” during first 516 LRCK cycles.
PWVR: Vref power down
0: Power down
1: Power up (default)
When PWVR bit = “0”, all blocks are powered down. Both ADC and DAC cannot operate. In this time, all
registers are not initialized, and register writings are valid. Only the VRFE block can be powered up by
setting PWAD = PWDA bit = “0” and PWVR bit = “1”.
SDDA: DAC Short Delay Sharp Roll Off Filter Enable (Table 16)
Default: Disable
ZOS: Zero-detection/ Overflow-detection control for OVFL/DZFL and OVFR/DZFR pins.
0: Overflow detection for ADC input (default)
1: Zero detection for DAC input.
ZOE: Zero-detection / Overflow-detection Disable
0: Enable (default)
1: Disable. Outputs “L”.
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection (default)
1: DZF goes “L” at Zero Detection
SLOW: DAC Slow Roll Off Filter Enable (Table 16)
Default: Disable
MS1258-E-01
2011/01
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[AK4621]
Addr
01H
Register Name
Reset Control
Default
D7
0
0
D6
0
0
D5
0
0
D4
SDAD
0
D3
0
0
D2
0
0
D1
D0
RSTAD
RSTDA
0
0
RSTDA: DAC reset
0: Reset (default)
1: Normal Operation
When RSTDA bit =“0”, the internal timing of DAC is reset and the AOUT becomes VCOM voltage
immediately. In this time, all registers are not initialized, and register writings are valid. After exiting the
power down mode, the OATT fades in the setting values of the control register (06H, 07H, 08H, 09H). The
analog outputs must be muted externally since a pop noise may occur when entering to and exiting from
this mode.
RSTAD: ADC reset
0: Reset (default)
1: Normal Operation
When RSTAD bit =“0”, the internal timing of ADC is reset and the SDTO pin becomes “L” immediately.
In this time, all registers are not initialized, and register writings are valid. After exiting the power down
mode, the ADCs output “0” during first 516 LRCK cycles.
SDAD: ADC Short Delay Sharp Roll Off Filter Enable (Table 15)
Default: Disable
Addr
02H
Register Name
Clock and Format Control
Default
D7
DIF2
0
D6
DIF1
1
D5
DIF0
0
D4
CMODE
0
D3
CKS1
0
D2
CKS0
0
D1
DFS1
0
D0
DFS0
0
DFS1-0: Sampling Speed Control (Table 1)
Default: Normal speed
CMODE, CKS1-0: Master Clock Frequency Select (Table 2)
Default: 256fs
DIF2-0: Audio data interface modes (Table 8)
000: Mode 0
001: Mode 1
010: Mode 2 (default)
011: Mode 3
100: Mode 4
Default: 24bit MSB justified for both ADC and DAC
MS1258-E-01
2011/01
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[AK4621]
Addr
03H
Register Name
D7
Deem and Volume Control
D6
HPRN
0
SMUTE
Default
0
D5
HPLN
0
D4
0
0
D3
0
0
D2
0
0
D1
DEM1
0
D0
DEM0
1
DEM1-0: De-emphasis response (Table 17)
00: 44.1kHz
01: OFF (default)
10: 48kHz
11: 32kHz
HPLN/RN: Left/Right channel Digital High Pass Filter Disable
0: Enable (default)
1: Disable
SMUTE: DAC Input Soft Mute control
0: Normal operation (default)
1: DAC outputs soft-muted
The soft mute is independent of the output ATT and performed digitally.
Addr
06H
07H
Register Name
Lch DATT Control
Rch DATT Control
Default
D7
D6
D5
D4
D3
D2
D1
D0
DATTL7
DATTR7
DATTL6
DATTR6
DATTL5
DATTR5
DATTL4
DATTR4
DATTL3
DATTR3
DATTL2
DATTR2
DATTL1
DATTR1
DATTL0
DATTR0
1
1
1
1
1
1
1
1
D2
EATTL2
EATTR2
1
D1
EATTL1
EATTR1
1
D0
EATTL0
EATTR0
1
DATT7-0: DAC Output Attenuation Level, Linear step. (Table 12, Table 13)
Default: 00H (0dB)
Addr
08H
09H
Register Name
Lch Extension DATT Control
Rch Extension DATT Control
Default
D7
0
0
0
D6
0
0
0
D5
EXTE
0
0
D4
0
0
0
D3
EATTL3
EATTR3
1
EATT3-0: DAC Output Extension Attenuation Level; Linear step. (Table 12, Table 13)
Default: FH
EXTE: Extension DATT Enable
0: Disable (default)
1: Enable
MS1258-E-01
2011/01
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[AK4621]
SYSTEM DESIGN
Figure 16 shows the system connection diagram. An evaluation board (AKD4621) is available for fast evaluation as well
as suggestions for peripheral circuitry.
0.1u
10u
+
1
VCOM
AOUTR+
30
Rch
Input
Buffer
2
AINR +
AOUTR-
29
3
AINR -
AOUTL+
28
Lch
Input
Buffer
4
AINL+
AOUTL-
27
5
AINL-
VSS2
26
6
VREF
DVDD
25
7
VSS1
TVDD
24
8
AVDD
SDFIL
23
9
P/S
DEM0
22
10 MCLK
PDN
21
11 LRCK
DFS0
20
CSN/DIF
19
13 SDTO
CCLK/CKS1
18
14 SDTI
CDTI/CKS0
17
15 OVFR/DZFR
OVFL/DZFL
16
4.75 ∼ 5.25V
Analog Supply +
10u
0.1u
Audio
DSP
AK4621
12 BICK
0.1u
Rch
LPF
Rch Out
Lch
LPF
Lch Out
0.1u
3.0 ∼ 3.6V
Digital Supply
DVDD ∼ 5.25V
Digital Supply
Mode
Setting/
uP
Notes:
- VSS1 and VSS2 must be connected to the same analog ground plane.
- When AOUT+/- drives some capacitive load, some resistance must be added in series between AOUT+/- and
capacitive load.
- All digital input pins must not be left floating.
Figure 16. Typical Connection Diagram
MS1258-E-01
2011/01
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[AK4621]
Digital Ground
Analog Ground
System
Controller
1
VCOM
AOUTR+
30
2
AINR+
AOUTR-
29
3
AINR-
AOUTL+
28
4
AINL+
AOUTL-
27
5
AINL-
VSS2
26
6
VREF
DVDD
25
7
VSS1
TVDD
24
8
AVDD
NC
23
9
P/S
DEM0
22
10
MCLK
PDN
21
11
LRCK
DFS0
20
12
BICK
CSN/DIF
19
13
SDTO
CCLK/CKS1
18
14
SDTI
CDTI/CKS0
17
15
OVFR/DZFR
OVFL/DZFL
16
AK4621
Figure 17. Ground Layout
1. Ground and Power Supply Decoupling
The AK4621 requires careful attention to power supply and grounding layout. To minimize coupling from digital noise,
decoupling capacitors must be connected to AVDD, DVDD and TVDD respectively. AVDD is supplied from the analog
supply in the system, and DVDD and TVDD are supplied from the digital supply in the system. Power lines of AVDD,
DVDD and TVDD must be distributed separately from the point with low impedance of regulator etc. The power up
sequence is not critical among AVDD, DVDD and TVDD. VSS1 and VSS2 must be connected to one analog
ground plane. Decoupling capacitors must be as near to the AK4621 as possible, with the small value ceramic capacitor
being the nearest.
2. Voltage Reference
The differential voltage between VREF and VSS1 sets the analog input/output range. The VREF pin is normally connected
to AVDD with a 0.1μF ceramic capacitor. VCOM is the signal ground of this chip. A 10μF electrolytic capacitor in parallel
with a 0.1μF ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current
may be drawn from the VCOM pin. All signals, especially clocks, must be kept away from the VREF and VCOM pins in
order to avoid unwanted coupling into the AK4621.
3. ADC Output
The ADC output data format is 2’s complement. The DC offset, including the ADC’s own DC offset, is removed by the
internal HPF (fc=1.0Hz@fs=48kHz). The AK4621 samples the analog inputs at 128fs (@Normal Speed Mode), 64fs
(@Double Speed Mode) or 32fs (@Quad Speed Mode). The digital filter rejects noise above the stopband except for
multiples of 128fs (@Normal Speed Mode), 64fs (@Double Speed Mode) or 32fs (@Quad Speed Mode).
MS1258-E-01
2011/01
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[AK4621]
4. Analog Inputs
The AK4621 can accept input voltages from VSS1 to AVDD. The input signal range scales with the VREF voltage and is
nominally 2.82Vpp (VREF = 5V), centered around the internal common voltage (about VA/2). Figure 18 shows an input
buffer circuit example. This is a fully differential input buffer circuit with an inverted amplifier (gain: −10dB). The
capacitor of 10nF between AINL+/− (AINR+/−) decreases the clock feedthrough noise of the modulator, and it composes
a 1st order LPF (fc=360kHz) with a 22Ω resistor before the capacitor. This circuit also has a 1st order LPF (fc=370kHz)
composed of op-amp. Refer to an evaluation board for details.
910
4.7k
Analog In
4.7k
470p
VP+
47μ
VP9.3Vpp
3k
22
910
10k
0.1μ 10μ
47μ
Bias
VA = 5V
VP+ = 15V
VP- = -15V
3k
AK4621
10n
470p
10k
AIN+
Bias
NJM5532
VA
2.82Vpp
22
Bias
AIN2.82Vpp
Figure 18. Input Buffer Example
MS1258-E-01
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[AK4621]
5. Analog Outputs
The analog outputs are fully differential and 2.8Vpp (typ. VREF = 5V), centered around VCOM. The differential outputs
are summed externally: Vout = (AOUT+)-(AOUT-) between AOUT+ and AOUT-. If the summing gain is 1, the output
range is 5.6Vpp (typ. VREF = 5V). The bias voltage of the external summing circuit is supplied externally. The input data
format is 2’s complement. The output voltage is a positive full scale for 7FFFFFH(@24bit) and a negative full scale for
800000H(@24bit). The ideal AOUT is 0V for 000000H(@24bit).
The internal switched-capacitor filter and the external LPF attenuate the noise generated by the delta-sigma modulator
beyond the audio passband.
Figure 19 shows an example of external LPF circuit summing the differential outputs by an op-amp. Figure 20 shows an
example of differential outputs and LPF circuit example by three op-amps.
AK4621
AOUT-
4.7k
4.7k
200
330p
+Vop
AOUT+
2.2n
4.7k
4.7k
Analog
Out
200
330p
-Vop
Figure 19. External LPF Circuit Example 1 (fc = 136kHz, Q=0.694)
Frequency Response
Gain
20kHz
−0.01dB
40kHz
−0.06dB
80kHz
−0.59dB
Table 19. Frequency Response of External LPF Circuit Example 1
MS1258-E-01
2011/01
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[AK4621]
+15
3.3n
+
AOUTL- +
3.9n
10k
330
180
7
3
2 +
4
-15
10u
0.1u
6
NJM5534D
+
0.1u
620
620
3.3n
+
100u
180
AOUT L+ +
3.9n
10k
330
7
3
+
2 4
2 - 4
3 + 7
100
6
Lch
1.0n NJM5534D
10u
0.1u
6
NJM5534D
+
0.1u
10u
+
10u
0.1u
1.2k
680
+10u
1.0n
1.2k
680
0.1u
560
10u
560
100u
Figure 20. External LPF Circuit Example 2
1st Stage
2nd Stage
Total
Cut-off Frequency
182kHz
284kHz
Q
0.637
Gain
+3.9dB
-0.88dB
+3.02dB
20kHz
-0.025
-0.021
-0.046dB
Frequency
40kHz
-0.106
-0.085
-0.191dB
Response
80kHz
-0.517
-0.331
-0.848dB
Table 20. Frequency Response of External LPF Circuit Example 2
MS1258-E-01
2011/01
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[AK4621]
PACKAGE
30pin VSOP (Unit: mm)
*9.7±0.1
1. 5MAX
0.3
30
15
1
0.24± 0. 06
A
7.6± 0.2
5.6±0.1
16
0.65
0.12 M
+0.06
0.17 -0.05
0.45± 0.2
+0.1 0
-0 .05
0.08 S
0.10
1.2± 0.10
D etail A
0° ~ 8°
N OTE: Dimension "* " does not include mold flash.
■ Package & Lead frame material
Package molding compound: Epoxy Resin, Halogen (bromine and chlorine) free
Lead frame material: Cu Alloy
Lead frame surface treatment: Solder (Pb free) plate
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[AK4621]
MARKING
AKM
AK4621EF
XXXXYYYYZ
YYYY:
XXXX, Z:
Date code
Internal control code
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[AK4621]
REVISION HISTORY
Date (YY/MM/DD)
10/12/07
11/01/26
Revision
00
01
Reason
First Edition
Description
Change
Page/Line
Contents
Digital filter names were changed.
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z Descriptions of external circuits, application circuits, software and other related information contained in this
document are provided only to illustrate the operation and application examples of the semiconductor products. You
are fully responsible for the incorporation of these external circuits, application circuits, software and other related
information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third
parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,
intellectual property, or other rights in the application or use of such information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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