Cypress CY62256LL 256k (32k x 8) static ram Datasheet

CY62256
256K (32K x 8) Static RAM
Functional Description[1]
Features
• High speed
— 55 ns
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive: –40°C to 125°C
• Voltage range
— 4.5V – 5.5V
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in a Pb-free and non Pb-free standard 28-pin
narrow SOIC, 28-pin TSOP-1, 28-pin Reverse TSOP-1
and 28-pin DIP packages
The CY62256 is a high-performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and Tri-state drivers. This device has an
automatic power-down feature, reducing the power
consumption by 99.9% when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Logic Block Diagram
I/O0
INPUTBUFFER
I/O1
32K × 8
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
I/O3
I/O4
I/O5
CE
WE
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
A12
A11
A1
A0
A13
A14
OE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05248 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY62256
Product Portfolio
Power Dissipation
Operating, ICC
(mA)
VCC Range (V)
Product
CY62256L
Com’l/Ind’l
CY62256LL
Commercial
CY62256LL
Industrial
CY62256LL
Automotive
Standby, ISB2
(µA)
Min.
Typ.[2]
Max.
Speed
(ns)
Typ.[2]
Max.
Typ.[2]
Max.
4.5
5.0
5.5
55/70
25
50
2
50
70
25
50
0.1
5
55/70
25
50
0.1
10
55
25
50
0.1
15
Pin Configurations
Narrow SOIC
Top View
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DIP
Top View
VCC
WE
A4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A10
A11
A11
A10
A9
A8
A7
A6
A5
VCC
WE
A4
A3
A2
A1
OE
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TSOP I
Top View
(not to scale)
8
9
7
6
5
4
3
2
1
28
27
26
25
24
23
22
20
19
18
17
16
15
14
13
12
11
10
9
8
TSOP I
Reverse Pinout
Top View
(not to scale)
10
11
12
13
14
15
16
17
18
19
20
21
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A14
A13
A12
A12
A13
A14
I/O0
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A0
Pin Definitions
Pin Number
Type
Description
1–10, 21, 23–26
Input
A0–A14. Address Inputs
11–13, 15–19,
Input/Output
I/O0–/O7. Data lines. Used as input or output lines depending on operation
27
Input/Control
WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted
20
Input/Control
CE. When LOW, selects the chip. When HIGH, deselects the chip
22
Input/Control
OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are Tri-stated, and act as input
data pins
14
Ground
GND. Ground for the device
28
Power Supply VCC. Power supply for the device
Note:
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA = 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
Document #: 38-05248 Rev. *F
Page 2 of 14
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CY62256
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current.................................................... > 200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) .............................................. –0.5V to +7V
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
Range
Ambient Temperature (TA)[4]
VCC
Commercial
0°C to +70°C
5V ± 10%
Industrial
–40°C to +85°C
5V ± 10%
Automotive
–40°C to +125°C
5V ± 10%
Electrical Characteristics Over the Operating Range
CY62256−55
Parameter
Description
Test Conditions
Min.
Typ.[2]
CY62256−70
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = −1.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1 mA
VIH
Input HIGH Voltage
2.2
VCC
+0.5V
VIL
Input LOW Voltage
–0.5
IIX
Input Leakage Current
IOZ
Output Leakage Current GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply
Current
ISB1
ISB2
Unit
Max.
2.4
V
0.4
GND < VI < VCC
VCC = 5.5V,
IOUT = 0 mA,
f = fMax = 1/tRC
2.4
Min. Typ.[2]
0.4
V
2.2
VCC
+0.5V
V
0.8
–0.5
0.8
V
–0.5
+0.5
–0.5
+0.5
µA
–0.5
+0.5
–0.5
+0.5
µA
mA
L
25
50
25
50
LL
25
50
25
50
Automatic CE
VCC = 5.5V, CE > VIH,
Power-down Current— VIN > VIH or VIN < VIL,
TTL Inputs
f = fMax
L
0.4
0.6
0.4
0.6
LL
0.3
0.5
0.3
0.5
VCC = 5.5V,
Automatic CE
Power-down Current— CE > VCC − 0.3V
CMOS Inputs
VIN > VCC − 0.3V, or
VIN < 0.3V, f = 0
L
2
50
2
50
0.1
5
0.1
5
LL - Ind’l
0.1
10
0.1
10
LL - Auto
0.1
15
LL - Com’l
mA
µA
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = VCC(typ.)
Max.
Unit
6
pF
8
pF
Thermal Resistance[5]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
DIP
SOIC
TSOP
RTSOP
Unit
Still Air, soldered on a 4.25 x 1.125 inch,
2-layer printed circuit board
75.61
76.56
93.89
93.89
°C/W
43.12
36.07
24.64
24.64
°C/W
Notes:
3. VIL (min.) = −2.0V for pulse durations of less than 20 ns.
4. TA is the “Instant-On” case temperature.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05248 Rev. *F
Page 3 of 14
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CY62256
AC Test Loads and Waveforms
R1 1800Ω
R1 1800Ω
5V
5V
ALL INPUT PULSES
3.0V
OUTPUT
OUTPUT
R2
990Ω
100 pF
INCLUDING
JIG AND
SCOPE
R2
990Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
90%
10%
90%
10%
GND
< 5 ns
< 5 ns
(b)
THEVENIN EQUIVALENT
639Ω
OUTPUT
1.77V
Data Retention Characteristics
Parameter
Conditions[6]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Typ.[2]
Min.
Max.
2.0
Unit
V
VCC = 2.0V, CE > VCC − 0.3V,
VIN > VCC − 0.3V, or VIN < 0.3V
2
50
µA
0.1
5
µA
LL - Ind’l
0.1
10
µA
LL - Auto
0.1
10
µA
L
LL - Com’l
tCDR[5]
Chip Deselect to Data Retention Time
tR[5]
Operation Recovery Time
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 2V
VCC(min)
tR
CE
Note:
6. No input may exceed VCC + 0.5V.
Document #: 38-05248 Rev. *F
Page 4 of 14
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CY62256
Switching Characteristics Over the Operating Range[7]
CY62256−55
Parameter
Description
Min.
Max.
CY62256−70
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
55
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
tLZOE
OE LOW to Low-Z[8]
55
5
OE HIGH to
tLZCE
CE LOW to Low-Z[8]
tHZCE
CE HIGH to
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
70
5
ns
25
5
20
0
ns
ns
25
0
55
ns
ns
5
20
High-Z[8, 9]
ns
5
5
High-Z[8, 9]
tHZOE
70
ns
ns
70
ns
Write Cycle[10, 11]
tWC
Write Cycle Time
55
70
ns
tSCE
CE LOW to Write End
45
60
ns
tAW
Address Set-up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
50
ns
tSD
Data Set-up to Write End
25
30
ns
tHD
Data Hold from Write End
0
0
ns
High-Z[8, 9]
tHZWE
WE LOW to
tLZWE
WE HIGH to Low-Z[8]
20
5
25
5
ns
ns
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100 pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can
terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05248 Rev. *F
Page 5 of 14
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CY62256
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[12, 13]
tRC
ADDRESS
tOHA
DATA OUT
tAA
DATA VALID
PREVIOUS DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
t RC
CE
tACE
OE
t HZOE
tHZCE
tDOE
t LZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
DATA OUT
tLZCE
t PD
t PU
ICC
VCC
SUPPLY
CURRENT
50%
50%
ISB
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
tWC
ADDRESS
CE
tAW
tSA
WE
tHA
t PWE
OE
tSD
DATA I/O
NOTE 17
tHD
DATAINVALID
t HZOE
Notes:
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05248 Rev. *F
Page 6 of 14
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CY62256
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[10, 15, 16]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
t HD
DATAINVALID
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
tWC
ADDRESS
CE
tAW
t HA
tSA
WE
tSD
DATA I/O
NOTE 17
DATA INVALID
t HZWE
Document #: 38-05248 Rev. *F
t HD
tLZWE
Page 7 of 14
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CY62256
Typical DC and AC Characteristics
1.4
1.0
0.8
0.6
VIN = 5.0V
TA = 25°C
0.4
2.5
1.0
2.0
0.8
0.6
VCC = 5.0V
VIN = 5.0V
0.4
4.5
5.0
5.5
25
1.4
1.6
1.3
1.4
NORMALIZED tAA
NORMALIZED tAA
125
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
1.2
1.1
TA = 25°C
1.0
1.2
1.0
VCC = 5.0V
0.8
0.9
4.5
5.0
5.5
VCC = 5.0V
VIN = 5.0V
–0.5
−55
0.6
−55
6.0
25
125
AMBIENT TEMPERATURE (°C)
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOLTAGE (V)
25
105
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
0.8
4.0
1.0
0.0
0.0
−55
6.0
ISB
1.5
0.5
0.2
ISB
0.0
4.0
1.2
OUTPUT SINK CURRENT (mA)
0.2
3.0
ICC
ISB2 µA
1.2
NORMALIZED ICC
NORMALIZED ICC, ISB
1.4
ICC
STANDBY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
80
60
VCC = 5.0V
TA = 25°C
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
120
100
80
VCC = 5.0V
TA = 25°C
60
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
Document #: 38-05248 Rev. *F
Page 8 of 14
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CY62256
Typical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
2.5
25.0
2.0
1.5
1.0
20.0
15.0
VCC = 4.5V
TA = 25°C
10.0
NORMALIZED ICC vs. CYCLE TIME
1.00
VCC =5.0V
TA = 2 5°C
VIN = 0.5V
0.75
5.0
0.5
0.0
0.0
1.25
NORMALIZED ICC
3.0
DELTA tAA (ns)
NORMALIZED IPO
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
1.0
2.0
3.0
4.0
5.0
0.0
0
SUPPLY VOLTAGE (V)
200
400
600
800 1000
CAPACITANCE (pF)
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Truth Table
CE
WE
OE
Inputs/Outputs
H
X
X
High-Z
Deselect/Power-down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High-Z
Output Disabled
Active (ICC)
Document #: 38-05248 Rev. *F
Mode
Power
Page 9 of 14
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CY62256
Ordering Information
Speed
(ns)
55
Ordering Code
CY62256LL−55SNI
Package
Diagram
Package Type
51-85092
28-pin (300-mil Narrow Body) SNC
CY62256LL−55SNXI
51-85071
28-pin TSOP I (Pb-free)
CY62256LL−55SNE
51-85092
28-pin (300-mil Narrow Body) SNC
CY62256LL−55SNXE
51-85071
28-pin TSOP I
28-pin TSOP I (Pb-free)
CY62256LL−55ZRXE
51-85074
28-pin Reverse TSOP I (Pb-free)
CY62256LL−70PC
51-85017
28-pin (600-Mil) Molded DIP
CY62256LL−70PXC
CY62256L−70SNC
51-85092
28-pin (300-mil Narrow Body) SNC
28-pin (300-mil Narrow Body) SNC (Pb-free)
CY62256LL−70SNC
28-pin (300-mil Narrow Body) SNC
CY62256LL−70SNXC
28-pin (300-mil Narrow Body) SNC (Pb-free)
51-85071
CY62256LL−70ZXC
CY62256L–70SNI
28-pin TSOP I
28-pin TSOP I (Pb-free)
51-85092
28-pin (300-mil Narrow Body) SNC
CY62256L–70SNXI
28-pin (300-mil Narrow Body) SNC (Pb-free)
CY62256LL−70SNI
28-pin (300-mil Narrow Body) SNC
CY62256LL−70SNXI
28-pin (300-mil Narrow Body) SNC (Pb-free)
CY62256LL−70ZXI
51-85071
28-pin TSOP I (Pb-free)
CY62256LL−70ZRI
51-85074
28-pin Reverse TSOP I
CY62256LL−70ZRXI
Commercial
28-pin (600-Mil) Molded DIP (Pb-free)
CY62256L−70SNXC
CY62256LL−70ZC
Automotive
28-pin (300-mil Narrow Body) SNC (Pb-free)
CY62256LL−55ZXE
70
Industrial
28-pin (300-mil Narrow Body) SNC (Pb-free)
CY62256LL−55ZXI
CY62256LL−55ZE
Operating
Range
Industrial
28-pin Reverse TSOP I (Pb-free)
Please contact your local Cypress sales representative for availability of these parts
Document #: 38-05248 Rev. *F
Page 10 of 14
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CY62256
Package Diagrams
28-pin (600-mil) Molded DIP (51-85017)
14
MIN.
MAX.
DIMENSIONS IN INCHES
REFERENCE JEDEC Ms-020
1
0.530
0.550
15
28
0.070
0.090
SEATING PLANE
1.380
1.480
0.140
0.195
0.155
0.200
0.115
0.160
0.009
0.012
0.015
0.060
0.090
0.110
0.055
0.065
0.600
0.625
0.014
0.022
3° MIN.
0.610
0.700
51-85017-*B
28-pin (300-mil) SNC (Narrow Body) (51-85092)
51-85092-*B
Document #: 38-05248 Rev. *F
Page 11 of 14
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CY62256
Package Diagrams (continued)
28-pin Thin Small Outline Package Type 1 (8 x 13.4 mm) (51-85071)
51-85071-*G
Document #: 38-05248 Rev. *F
Page 12 of 14
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CY62256
Package Diagrams (continued)
28-pin Reverse Thin Small Outline Package Type 1 (8x13.4 mm) (51-85074)
51-85074-*F
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05248 Rev. *F
Page 13 of 14
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62256
Document History Page
Document Title: CY62256, 256K (32K x 8) Static RAM
Document Number: 38-05248
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
113454
03/06/02
MGN
Description of Change
Change from Spec number: 38-00455 to 38-05248
Remove obsolete parts from ordering info, standardize format
*A
115227
05/23/02
GBI
Changed SN Package Diagram
*B
116506
09/04/02
GBI
Added footnote 1
Corrected package description in Ordering Information table
*C
238448
See ECN
AJU
Added Automotive product information
*D
344595
See ECN
SYT
Added Pb-free packages on page# 10
*E
395936
See ECN
SYT
Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”
Added CY62256L–70SNXI package in the Ordering Information on Page # 10
*F
493277
See ECN
VKN
Updated Ordering Information table
Document #: 38-05248 Rev. *F
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