Cypress CY14B512Q1 512-kbit (64 k ã 8) serial (spi) nvsram Datasheet

512-Kbit (64 K × 8) Serial (SPI) nvSRAM
512-Kbit (64 K × 8) Serial (SPI) nvSRAM
Features
■
■
512-Kbit nonvolatile static random access memory (nvSRAM)
❐ Internally organized as 64 K × 8
❐ STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
❐ RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
❐ Automatic STORE on power-down with a small capacitor
(except for CY14B512Q1)
■
High reliability
❐ Infinite read, write, and RECALL cycles
❐ 1 million STORE cycles to QuantumTrap
❐ Data retention: 20 years
■
High speed serial peripheral interface (SPI)
❐ 40 MHz clock rate
❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)
■
Write protection
❐ Hardware protection using Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4,1/2, or entire array
■
Industry standard configurations
❐ Industrial temperature
❐ CY14B512Q1 has identical pin configuration to industry
standard 8-pin NV memory
❐ 8-pin dual flat no-lead (DFN) package and 16-pin small
outline integrated circuit (SOIC) package
❐ Restriction of hazardous substances (RoHS) compliant
Functional Overview
The
Cypress
CY14B512Q1/CY14B512Q2/CY14B512Q3
combines a 512-Kbit nvSRAM[1] with a nonvolatile element in
each memory cell with serial SPI interface. The memory is
organized as 64 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cell provides highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down
(except for CY14B512Q1). On power-up, data is restored to the
SRAM from the nonvolatile memory (RECALL operation). The
STORE and RECALL operations can also be initiated by the user
through SPI instruction.
Configuration
Low power consumption
❐ Single 3 V +20%, –10% operation
❐ Average active current of 10 mA at 40 MHz operation
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14B512Q1
No
Yes
CY14B512Q2
Yes
Yes
CY14B512Q3
Yes
Yes
No
No
Yes
Logic Block Diagram
VCC
CS
QuantumTrap
64 K X 8
Instruction decode
Write protect
Control logic
WP
SCK
STORE
SRAM Array
HOLD
RECALL
64 K X 8
Instruction
register
Address
Decoder
VCAP
Power Control
STORE/RECALL
Control
HSB
D0-D7
A0-A15
SI
Data I/O register
SO
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Status Register
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation
Document #: 001-53873 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 12, 2011
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CY14B512Q1
CY14B512Q2
CY14B512Q3
Contents
Pinouts .............................................................................. 3
Device Operation .............................................................. 5
SRAM Write................................................................. 5
SRAM Read ................................................................ 5
STORE Operation ....................................................... 5
AutoStore Operation.................................................... 6
Software STORE Operation ........................................ 6
Hardware STORE and HSB pin Operation ................. 6
RECALL Operation...................................................... 6
Hardware RECALL (Power-Up) .................................. 6
Software RECALL ....................................................... 7
Disabling and Enabling AutoStore............................... 7
Serial Peripheral Interface ............................................... 7
SPI Overview............................................................... 7
SPI Modes................................................................... 8
SPI Operating Features.................................................... 9
Power-Up .................................................................... 9
Power On Reset .......................................................... 9
Power-Down................................................................ 9
Active Power and Standby Power Modes ................... 9
SPI Functional Description.............................................. 9
Status Register ............................................................... 10
Read Status Register (RDSR) Instruction ................. 10
Write Status Register (WRSR) Instruction ................ 10
Write Protection and Block Protection......................... 11
Write Enable (WREN) Instruction.............................. 11
Write Disable (WRDI) Instruction .............................. 11
Block Protection ........................................................ 11
Write Protect (WP) Pin .............................................. 12
Memory Access .............................................................. 12
Document #: 001-53873 Rev. *E
Read Sequence (READ) instruction..........................
Write Sequence (WRITE) instruction ........................
Software STORE (STORE) instruction......................
Software RECALL (RECALL) instruction ..................
AutoStore Enable (ASENB) Instruction .....................
AutoStore Disable (ASDISB) Instruction ...................
HOLD Pin Operation .................................................
Best Practices.................................................................
Maximum Ratings...........................................................
DC Electrical Characteristics ........................................
Data Retention and Endurance .....................................
Capacitance ....................................................................
Thermal Resistance........................................................
AC Test Conditions ........................................................
AC Switching Characteristics .......................................
AutoStore or Power-Up RECALL ..................................
Software Controlled STORE and RECALL Cycles ......
Hardware STORE Cycle .................................................
Ordering Information......................................................
Ordering Code Definition...........................................
Package Diagrams..........................................................
Acronyms .......................................................................
Document Conventions .................................................
Units of Measure .......................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC Solutions .........................................................
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Page 2 of 27
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For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Pinouts
Figure 1. Pin Diagram - 8-Pin DFN[2, 3, 4]
CY14B512Q1
CS
O
SO
1
2
WP
3
VSS
4
EXPOSED
PAD
CY14B512Q2
O
8
VCC
CS
7
HOLD
SO
6
SCK
5
SI
1
2
VCAP
3
VSS
4
Top View
(not to scale)
EXPOSED
PAD
8
VCC
7
HOLD
6
SCK
5
SI
Top View
(not to scale)
Figure 2. Pin Diagram - 16-Pin SOIC
NC
1
16
VCC
NC
2
15
NC
NC
3
14
VCAP
13
SO
12
SI
SCK
CY14B512Q3
NC
4
WP
5
HOLD
6
11
7
10
8
9
NC
VSS
Top View
not to scale
CS
HSB
Table 1. Pin Definitions
Pin Name
I/O Type
Description
CS
Input
Chip select. Activates the device when pulled LOW. Driving this pin HIGH puts the device in low
power standby mode.
SCK
Input
Serial clock. Runs at speeds up to maximum of fSCK. Serial input is latched at the rising edge of
this clock. Serial output is driven at the falling edge of the clock.
SI
Input
SO
Output
Serial input. Pin for input of all SPI instructions and data.
WP
Input
Write protect. Implements hardware write protection in SPI.
HOLD
Input
HOLD pin. Suspends serial operation.
HSB
Input/output
Hardware STORE Busy:
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then
a weak internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
Power supply
AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It
must never be connected to ground.
Serial output. Pin for output of data through SPI.
Notes
2. HSB pin is not available in 8 DFN packages.
3. CY14B512Q1 part does not have VCAP pin and does not support AutoStore.
4. CY14B512Q2 part does not have WP pin.
Document #: 001-53873 Rev. *E
Page 3 of 27
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CY14B512Q1
CY14B512Q2
CY14B512Q3
Table 1. Pin Definitions
Pin Name
I/O Type
NC
No connect
VSS
Power supply
Ground.
VCC
Power supply
Power supply (2.7 V to 3.6 V).
EXPOSED
PAD
No connect
Document #: 001-53873 Rev. *E
Description
No connect: This pin is not connected to the die.
The EXPOSED PAD on the bottom of 8-pin DFN package is not connected to the die. It is
recommended to connect the EXPOSED PAD to ground. Thermal vias can be used to increase
thermal conductivity.
Page 4 of 27
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Device Operation
SRAM Write
CY14B512Q1/CY14B512Q2/CY14B512Q3 is a 512-Kbit
nvSRAM memory with a nonvolatile element in each memory
cell. All the reads and writes to nvSRAM happen to the SRAM
which gives nvSRAM the unique capability to handle infinite
writes to the memory. The data in SRAM is secured by a STORE
sequence taht transfers the data in parallel to the nonvolatile
QuantumTrap cells. A small capacitor (VCAP) is used to
AutoStore the SRAM data in nonvolatile cells when power goes
down providing power-down data security. The QuantumTrap
nonvolatile elements built in the reliable SONOS technology
make nvSRAM the ideal choice for secure data storage.
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
enables the user to perform infinite write operations. A write cycle
is performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, two bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
The 512-Kbit memory array is organized as 64 K words × 8 bits.
The memory is accessed through a standard SPI interface that
enables very high clock speeds up to 40 MHz with zero cycle
delay read and write cycles. This device supports SPI modes 0
and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave.
The device is enabled using the chip select (CS) pin and
accessed through serial input (SI), serial output (SO), and serial
clock (SCK) pins.
This device provides the feature for hardware and software write
protection through the WP pin and WRDI instruction respectively
along with mechanisms for block write protection (one quarter,
one half, or full array) using BP0 and BP1 pins in the Status
Register. Further, the HOLD pin can be used to suspend any
serial communication without resetting the serial sequence.
CY14B512Q1/CY14B512Q2/CY14B512Q3 uses the standard
SPI opcodes for memory access. In addition to the general SPI
instructions for read and write, it provides four special
instructions which enable access to four nvSRAM specific
functions: STORE, RECALL, AutoStore Disable (ASDISB), and
AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB) pin and also reflected on
the RDY bit of the Status Register.
The device is available in three different pin configurations that
enable the user to choose a part which fits in best in their
application. The feature summary is given in Table 2.
Table 2. Feature Summary
Feature
CY14B512Q1 CY14B512Q2 CY14B512Q3
WP
Yes
No
Yes
VCAP
No
Yes
Yes
HSB
No
No
Yes
AutoStore
No
Yes
Yes
Power-Up RECALL
Yes
Yes
Yes
Hardware STORE
No
No
Yes
Software STORE
Yes
Yes
Yes
Software RECALL
Yes
Yes
Yes
Document #: 001-53873 Rev. *E
The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined in the memory access
section of SPI protocol description.
SRAM Read
A read cycle is performed at the SPI bus speed and the data is
read out with zero cycle delay after the READ instruction is
executed. The READ instruction is issued through the SI pin of
the nvSRAM and consists of the READ opcode and two bytes of
address. The data is read out on the SO pin.
This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.
The SPI read cycle sequence is defined in the memory access
section of SPI protocol description.
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The device STOREs data to the
nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated,
read/write
to
CY14B512Q1/CY14B512Q2/CY14B512Q3 is inhibited until the
cycle is completed.
The HSB signal or the RDY bit in the Status Register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Page 5 of 27
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The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (VCAP) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from VCC to
charge the capacitor connected to the VCAP pin. When the
voltage on the VCC pin drops below VSWITCH during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the VCAP capacitor. The AutoStore operation is not
initiated if no write cycle was performed since the last RECALL.
Note If a capacitor is not connected to VCAP pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
specified in AutoStore Disable (ASDISB) Instruction on page 14.
If AutoStore is enabled without a capacitor on the VCAP pin, the
device attempts an AutoStore operation without sufficient charge
to complete the STORE. This corrupts the data stored in the
nvSRAM and Status Register. To resume normal functionality,
the WRSR instruction must be issued to update the nonvolatile
bits BP0, BP1 and WPEN in the Status Register.
Figure 3 shows the proper connection of the storage capacitor
(VCAP) for AutoStore operation.
Refer to DC Electrical Characteristics on page 16 for the size of
the VCAP.
Note After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (tHHHD) with standard output high
current and then remains HIGH by an internal 100 kΩ pull-up
resistor.
Note For successfull last data byte STORE, a hardware store
should be initiated atleast one clock cycle after the last data bit
D0 is recieved.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
Note CY14B512Q1/CY14B512Q2 do not have HSB pin. RDY bit
of the SPI Status Register may be probed to determine the
Ready or Busy status of nvSRAM.
Figure 3. AutoStore Mode
VCC
0.1 uF
10 kOhm
AutoStore Operation
VCC
CS
Note CY14B512Q1 does not support AutoStore operation. The
user must perform Software STORE operation by using the SPI
STORE instruction to secure the data.
VSS
Software STORE Operation
Software STORE enables the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction irrespective of whether a write
has been performed since the last NV operation.
A STORE cycle takes tSTORE time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status Register or the HSB pin may be polled to find the
Ready or Busy status of the nvSRAM. After the tSTORE cycle time
is completed, the SRAM is activated again for read and write
operations.
Hardware STORE and HSB pin Operation
The HSB pin in CY14B512Q3 is used to control and
acknowledge STORE operations. If no STORE or RECALL is in
progress, this pin can be used to request a Hardware STORE
cycle. When the HSB pin is driven LOW, nvSRAM conditionally
initiates a STORE operation after tDELAY duration. An actual
STORE cycle starts only if a write to the SRAM was performed
since the last STORE or RECALL cycle. Reads and writes to the
memory are inhibited for tSTORE duration or as long as HSB pin
is LOW.
The HSB pin also acts as an open drain driver (internal 100 kΩ
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
Document #: 001-53873 Rev. *E
VCAP
VCAP
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. A RECALL may be
initiated in two ways: Hardware RECALL, initiated on power-up;
and Software RECALL, initiated by a SPI RECALL instruction.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. All memory accesses are inhibited while a RECALL
cycle is in progress. The RECALL operation does not alter the
data in the nonvolatile elements.
Hardware RECALL (Power-Up)
During power-up, when VCC crosses VSWITCH, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power-Up RECALL cycle takes tFA time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the Ready status of the device.
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Page 6 of 27
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Software RECALL
Software RECALL enables the user to initiate a RECALL
operation to restore the content of nonvolatile memory on to the
SRAM. A Software RECALL is issued by using the SPI
instruction for RECALL.
A Software RECALL takes tRECALL time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
Disabling and Enabling AutoStore
If the application does not require the AutoStore feature, it can
be disabled by using the ASDISB instruction. If this is done, the
nvSRAM does not perform a STORE operation at power-down.
AutoStore can be re-enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if the user
need this setting to survive the power cycle, a STORE operation
must be performed following AutoStore Disable or Enable
operation.
Note CY14B512Q2/CY14B512Q3 has AutoStore Enabled from
the factory. In CY14B512Q1, VCAP pin is not present and
AutoStore option is not available. The AutoStore Enable and
Disable instructions to CY14B512Q1 are ignored.
Note If AutoStore is disabled and VCAP is not required, then the
VCAP pin must be left open. VCAP pin must never be connected
to ground. Power-Up RECALL operation cannot be disabled in
any case.
Serial Peripheral Interface
SPI Overview
The SPI is a four-pin interface with chip select (CS), serial input
(SI), serial output (SO), and serial clock (SCK) pins.
CY14B512Q1/CY14B512Q2/CY14B512Q3 provides serial
access to nvSRAM through SPI interface. The SPI bus on this
device can run at speeds up to 40 MHz.
The SPI is a synchronous serial interface which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using a CS pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both these modes, data is clocked into the nvSRAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are as follows:
SPI Master
The SPI master device controls the operations on a SPI bus. A
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
the operations must be initiated by the master activating a slave
device by pulling the CS pin of the slave LOW. The master also
generates the SCK and all the data transmission on SI and SO
lines are synchronized with this clock.
Document #: 001-53873 Rev. *E
SPI Slave
The SPI slave device is activated by the master through the chip
select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. SPI slave never initiates a communication on the SPI bus
and acts on the instruction from the master.
CY14B512Q1/CY14B512Q2/CY14B512Q3 operates as a SPI
slave and may share the SPI bus with other SPI slave devices.
Chip Select (CS)
For selecting any slave device, the master needs to pull-down
the corresponding CS pin. Any instruction can be issued to a
slave device only while the CS pin is LOW. When the device is
not selected, data through the SI pin is ignored and the serial
output pin (SO) remains in a high-impedance state.
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active chip
select cycle.
Serial Clock (SCK)
Serial clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
CY14B512Q1/CY14B512Q2/CY14B512Q3 enables SPI modes
0 and 3 for data communication. In both these modes, the inputs
are latched by the slave device on the rising edge of SCK and
outputs are issued on the falling edge. Therefore, the first rising
edge of SCK signifies the arrival of the first bit (MSB) of SPI
instruction on the SI pin. Further, all data inputs and outputs are
synchronized with SCK.
Data Transmission - SI and SO
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as Master Out Slave
In (MOSI) and SO is referred to as Master In Slave Out (MISO).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
CY14B512Q1/CY14B512Q2/CY14B512Q3 has two seperate
pins for SI and SO, which can be connected with the master as
shown in Figure 4.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
most significant bit (MSB). This is valid for both address and data
transmission.
The 512-Kbit serial nvSRAM requires a 2-byte address for any
read or write operation.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14B512Q1/CY14B512Q2/CY14B512Q3 uses the standard
opcodes for memory accesses. In addition to the memory
accesses, it provides additional opcodes for the nvSRAM
specific functions: STORE, RECALL, AutoStore Enable, and
AutoStore Disable. Refer to Table 3 on page 9 for details.
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Page 7 of 27
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Invalid Opcode
Status Register
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin till the next
falling edge of CS and the SO pin remains tristated.
CY14B512Q1/CY14B512Q2/CY14B512Q3 has an 8-bit Status
Register. The bits in the Status Register are used to configure
the SPI bus. These bits are described in the Table 5 on page 10.
Figure 4. System Configuration using SPI nvSRAM
SCK
M OSI
M IS O
SCK
SI
SO
SCK
SI
SO
u C o n tro lle r
C Y14B 512Q x
CS
C Y14B 512Q x
HO LD
CS
HO LD
CS1
HO LD 1
CS2
HO LD 2
SPI Modes
CY14B512Q1/CY14B512Q2/CY14B512Q3 may be driven by a
microcontroller with its SPI peripheral running in either of the
following two modes:
The two SPI modes are shown in Figure 5 and Figure 6. The
status of clock when the bus master is in standby mode and not
transferring data is:
■
SCK remains at 0 for Mode 0
SCK remains at 1 for Mode 3
■
SPI Mode 0 (CPOL=0, CPHA=0)
■
■
SPI Mode 3 (CPOL=1, CPHA=1)
CPOL and CPHA bits must be set in the SPI controller for the
either Mode 0 or Mode 3. The device detects the SPI mode from
the status of SCK pin when the device is selected by bringing the
CS pin LOW. If SCK pin is LOW when the device is selected, SPI
Mode 0 is assumed and if SCK pin is HIGH, it works in SPI
Mode 3.
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge after the clock toggles, is considered. The output data
is available on the falling edge of SCK.
Figure 6. SPI Mode 3
Figure 5. SPI Mode 0
CS
CS
0
1
2
3
4
5
6
1
2
3
4
5
6
7
SCK
SCK
SI
0
7
7
6
5
4
MSB
Document #: 001-53873 Rev. *E
3
2
1
0
LSB
SI
7
MSB
6
5
4
3
2
1
0
LSB
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Page 8 of 27
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SPI Operating Features
Active Power and Standby Power Modes
Power-Up
When CS is LOW, the device is selected, and is in the active
power mode. The device consumes ICC current, as specified in
DC Electrical Characteristics on page 16. When CS is HIGH, the
device is deselected and the device goes into the standby power
mode if a STORE or RECALL cycle is not in progress. If a
STORE or RECALL cycle is in progress, the device goes into the
standby power mode after the STORE or RECALL cycle is
completed. In the standby power mode, the current drawn by the
device drops to ISB.
Power-up is defined as the condition when the power supply is
turned on and VCC crosses Vswitch voltage. During this time, the
CS must be allowed to follow the VCC voltage. Therefore, CS
must be connected to VCC through a suitable pull-up resistor. As
a built in safety feature, CS is both edge sensitive and level
sensitive. After power-up, the device is not selected until a falling
edge is detected on CS. This ensures that CS is HIGH, before
going LOW to start the first operation.
As described earlier, nvSRAM performs a Power-Up RECALL
operation after power-up and therefore, all memory accesses are
disabled for tFA duration after power-up. The HSB pin can be
probed to check the Ready or Busy status of nvSRAM after
power-up.
Power On Reset
A power on reset (POR) circuit is included to prevent inadvertent
writes. At power-up, the device does not respond to any
instruction until the VCC reaches the POR threshold voltage
(VSWITCH). After VCC transitions the POR threshold, the device
is internally reset and performs an Power-Up RECALL operation.
During Power-Up RECALL all device accesses are inhibited.
The device is in the following state after POR:
■
Deselected (after power-up, a falling edge is required on CS
before any instructions are started).
■
Standby power mode
■
Not in the HOLD condition
Status Register state:
❐ Write Enable (WEN) bit is reset to ‘0’.
❐ WPEN, BP1, BP0 unchanged from previous STORE
operation.
❐ Don’t care bits 4-6 are reset to ‘0’.
The WPEN, BP1, and BP0 bits of the Status Register are
nonvolatile bits and remain unchanged from the previous
STORE operation.
■
Before selecting and issuing instructions to the memory, a valid
and stable VCC voltage must be applied. This voltage must
remain valid until the end of the instruction transmission.
SPI Functional Description
The CY14B512Q1/CY14B512Q2/CY14B512Q3 uses an 8-bit
instruction register. Instructions and their operation codes are
listed in Table 3. All instructions, addresses, and data are
transferred with the MSB first and start with a HIGH to LOW CS
transition. There are, in all, 10 SPI instructions that provide
access to most of the functions in nvSRAM. Further, the WP,
HOLD and HSB pins provide additional functionality driven
through hardware.
Table 3. Instruction Set
Instruction
Category
Status Register
control
instructions
SRAM
Read/Write
instructions
Special NV
instructions
Power-Down
At power-down (continuous decay of VCC), when VCC drops from
the normal operating voltage and below the VSWITCH threshold
voltage, the device stops responding to any instruction sent to it.
If a write cycle is in progress and the last data bit D0 has been
received when the power goes down, it is allowed tDELAY time to
complete the write. After this, all memory accesses are inhibited
and a conditional AutoStore operation is performed (AutoStore is
not performed if no writes have happened since the last RECALL
cycle). This feature prevents inadvertent writes to nvSRAM from
happening during power-down.
However, to completely avoid the possibility of inadvertent writes
during power-down, ensure that the device is deselected and is
Reserved
Instruction
Name
Opcode
Operation
WREN
0000 0110 Set Write Enable
latch
WRDI
0000 0100 Reset Write
Enable latch
RDSR
0000 0101 Read Status
Register
WRSR
0000 0001 Write Status
Register
READ
0000 0011 Read data from
memory array
WRITE
0000 0010 Write data to
memory array
STORE
0011 1100 Software STORE
RECALL
0110 0000 Software RECALL
ASENB
0101 1001 AutoStore Enable
ASDISB
0001 1001 AutoStore Disable
- Reserved - 0001 1110
The SPI instructions are divided based on their functionality in
the following types:
❐ Status Register access: RDSR and WRSR instructions
❐ Write protection functions: WREN and WRDI instructions
along with WP pin and WEN, BP0, and BP1 bits
❐ SRAM memory access: READ and WRITE instructions
❐ nvSRAM special instructions: STORE, RECALL, ASENB,
and ASDISB
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
in standby power mode, and the CS follows the voltage applied
on VCC.
Document #: 001-53873 Rev. *E
Page 9 of 27
[+] Feedback
Status Register
The Status Register bits are listed in Table 3. The Status Register consists of a Ready bit (RDY) and data protection bits BP1, BP0,
WEN, and WPEN. The RDY bit can be polled to check the Ready or Busy status while a nvSRAM STORE or Software RECALL cycle
is in progress. The Status Register can be modified by WRSR instruction and read by RDSR instruction. However, only the WPEN,
BP1, and BP0 bits of the Status Register can be modified by using the WRSR instruction. The WRSR instruction has no effect on
WEN and RDY bits. The default value shipped from the factory for WEN, BP0, BP1, bits 4-6 and WPEN bits is ‘0’.
Table 4. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN (0)
X(0)
X(0)
X(0)
BP1 (0)
BP0 (0)
WEN(0)
RDY
Table 5. Status Register Bit Definition
Bit
Definition
Description
Bit 0 (RDY)
Ready
Read only bit indicates the ready status of device to perform a memory access. This bit is
set to ‘1’ by the device while a STORE or Software RECALL cycle is in progress.
Bit 1 (WEN)
Write Enable
WEN indicates if the device is Write Enabled. This bit defaults to ‘0’ (disabled) on power-up.
WEN = '1' --> Write Enabled
WEN = '0' --> Write Disabled
Bit 2 (BP0)
Block protect bit ‘0’
Used for block protection. For details see Table 6 on page 11.
Bit 3 (BP1)
Block protect bit ‘1’
Used for block protection. For details see Table 6 on page 11.
Bit 4-6
Don’t care
Bits are writable and volatile. On power-up, bits are written with ‘0’.
Bit 7 (WPEN) Write protect enable bit Used for enabling the function of Write Protect Pin (WP). For details see Table 7 on page 12.
Read Status Register (RDSR) Instruction
The RDSR instruction provides access to the Status Register.
This instruction is used to probe the Write Enable status of the
device or the Ready status of the device. RDY bit is set by the
device to ‘1’ whenever a STORE or Software RECALL cycle is
in progress. The block protection and WPEN bits indicate the
extent of protection employed.
This instruction is issued after the falling edge of CS using the
opcode for RDSR.
Write Status Register (WRSR) Instruction
The WRSR instruction enables the user to write to the Status
Register. However, this instruction cannot be used to modify bit
0 and bit 1 (RDY and WEN). The BP0 and BP1 bits can be used
to select one of four levels of block protection. Further, WPEN bit
must be set to ‘1’ to enable the use of write protect (WP) pin.
WRSR instruction is a write instruction and needs writes to be
enabled (WEN bit set to ‘1’) using the WREN instruction before
it is issued. The instruction is issued after the falling edge of CS
using the opcode for WRSR followed by 8 bits of data to be
stored in the Status Register. Since only bits 2, 3, and 7 can be
modified by WRSR instruction; therefore, it is recommended to
leave the bits 4-6 as ‘0’ while writing to the Status Register.
Note In CY14B512Q1/CY14B512Q2/CY14B512Q3, the values
written to Status Register are saved to nonvolatile memory only
after a STORE operation. If AutoStore is disabled (or while using
CY14B512Q1), any modifications to the Status Register must be
secured by performing a Software STORE operation.
Note CY14B512Q2 does not have WP pin. Any modification to
bit 7 of the Status Register has no effect on the functionality of
CY14B512Q2.
Figure 7. Read Status Register (RDSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
0
1
0
MSB
1
2
3
4
5
6
7
SCK
SI
SO
0
0
0
0
HI-Z
0
1
0
LSB
D7 D6 D5 D4 D3 D2 D1 D0
MSB
Document #: 001-53873 Rev. *E
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Data
LSB
Page 10 of 27
[+] Feedback
Figure 8. Write Status Register (WRSR) Instruction Timing
CS
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
Data in
Opcode
SI
0
0
0
0
0
0
0
1 D7 X
MSB
X
X D3 D2 X
X
LSB
HI-Z
SO
Write Protection and Block Protection
Write Disable (WRDI) Instruction
CY14B512Q1/CY14B512Q2/CY14B512Q3 provides features
for both software and hardware write protection using WRDI
instruction and WP. Additionally, this device also provides block
protection mechanism through BP0 and BP1 pins of the Status
Register.
Write Disable instruction disables the write by clearing the WEN
bit to ‘0’ in order to protect the device against inadvertent writes.
This instruction is issued following the falling edge of CS followed
by opcode for WRDI instruction. The WEN bit is cleared on the
rising edge of CS following a WRDI instruction.
Figure 10. WRDI Instruction
The Write Enable and disable status of the device is indicated by
WEN bit of the Status Register. The write instructions (WRSR
and WRITE) and nvSRAM special instruction (STORE,
RECALL, ASENB, and ASDISB) need the write to be enabled
(WEN bit = ‘1’) before they can be issued.
Write Enable (WREN) Instruction
On power-up, the device is always in the Write Disable state. The
following WRITE, WRSR, or nvSRAM special instruction must
therefore be preceded by a Write Enable instruction. If the device
is not Write Enabled (WEN = ‘0’), it ignores the write instructions
and returns to the standby state when CS is brought HIGH. A
new CS falling edge is required to re-initiate serial
communication. The instruction is issued following the falling
edge of CS. When this instruction is used, the WEN bit of Status
Register is set to ‘1’. WEN bit defaults to ‘0’ on power-up.
Note After completion of a write instruction (WRSR or WRITE)
or nvSRAM special instruction (STORE, RECALL, ASENB, and
ASDISB) instruction, WEN bit is cleared to ‘0’. This is done to
provide protection from any inadvertent writes. Therefore,
WREN instruction must be used before a new write instruction is
issued.
Figure 9. WREN Instruction
0
1
2
3
4
5
6
7
SCK
SO
0
0
0
0
0
0
1
1
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
0
HI-Z
SO
Block Protection
Block protection is provided using the BP0 and BP1 pins of the
Status Register. These bits can be set using WRSR instruction
and probed using the RDSR instruction. The nvSRAM is divided
into four array segments. One-quarter, one-half, or all of the
memory segments can be protected. Any data within the
protected segment is read only. Table 6 shows the function of
block protect bits.
Table 6. Block Write Protect Bits
Level
CS
SI
CS
Status Register
Bits
BP1
Array Addresses Protected
BP0
0
0
0
None
1 (1/4)
0
1
0xC000-0xFFFF
2 (1/2)
1
0
0x8000-0xFFFF
3 (All)
1
1
0x0000-0xFFFF
HI-Z
Document #: 001-53873 Rev. *E
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Page 11 of 27
[+] Feedback
Write Protect (WP) Pin
After the CS line is pulled LOW to select a device, the read
opcode is transmitted through the SI line followed by two bytes
of address (A15-A0). After the last address bit is transmitted on
the SI pin, the data (D7-D0) at the specific address is shifted out
on the SO line on the falling edge of SCK starting with D7. Any
other data on SI line after the last address bit is ignored.
The write protect pin (WP) is used to provide hardware write
protection. WP pin enables all normal read and write operations
when held HIGH. When the WP pin is brought LOW and WPEN
bit is ‘1’, all write operations to the Status Register are inhibited.
The hardware write protection function is blocked when the
WPEN bit is ‘0’. This enables the user to install the device in a
system with the WP pin tied to ground, and still write to the Status
Register.
CY14B512Q1/CY14B512Q2/CY14B512Q3 allows reads to be
performed in bursts through SPI which can be used to read
consecutive addresses without issuing a new READ instruction.
If only one byte is to be read, the CS line must be driven HIGH
after one byte of data comes out. However, the read sequence
may be continued by holding the CS line LOW and the address
is automatically incremented and data continues to shift out on
SO pin. When the last data memory address (0xFFFF) is
reached, the address rolls over to 0x0000 and the device
continues to read.
WP pin can be used along with WPEN and block protect bits
(BP1 and BP0) of the Status Register to inhibit writes to memory.
When WP pin is LOW and WPEN is set to ‘1’, any modifications
to the Status Register are disabled. Therefore, the memory is
protected by setting the BP0 and BP1 bits and the WP pin inhibits
any modification of the Status Register bits, providing hardware
write protection.
Write Sequence (WRITE) instruction
Note WP going LOW when CS is still LOW has no effect on any
of the ongoing write operations to the Status Register.
CY14B512Q2 does not have WP pin and therefore does not
provide hardware write protection.
The write operations on this device are performed through the SI
pin. To perform a write operation, if the device is Write Disabled,
then the device must first be Write Enabled through the WREN
instruction. When the writes are enabled (WEN = ‘1’), WRITE
instruction is issued after the falling edge of CS. A WRITE
instruction constitutes transmitting the WRITE opcode on SI line
followed by 2 bytes of address (A15-A0) and the data (D7-D0)
which is to be written.
Table 7 summarizes all the protection features of this device
Table 7. Write Protection Operation
Unprotected
WEN Protected
Blocks
Blocks
Status
Register
WPEN
WP
X
X
0
Protected
Protected
0
X
1
Protected
Writable
Writable
1
LOW
1
Protected
Writable
Protected
1
HIGH
1
Protected
Writable
Writable
CY14B512Q1/CY14B512Q2/CY14B512Q3 enables writes to be
performed in bursts through SPI which can be used to write
consecutive addresses without issuing a new WRITE instruction.
If only one byte is to be written, the CS line must be driven HIGH
after the D0 (LSB of data) is transmitted. However, if more bytes
are to be written, CS line must be held LOW and address is
incremented automatically. The following bytes on the SI line are
treated as data bytes and written in the successive addresses.
When the last data memory address (0xFFFF) is reached, the
address rolls over to 0x0000 and the device continues to write.
The WEN bit is reset to ‘0’ on completion of a WRITE sequence.
Protected
Memory Access
All memory accesses are done using the READ and WRITE
instructions. These instructions cannot be used while a STORE
or RECALL cycle is in progress. A STORE cycle in progress is
indicated by the RDY bit of the Status Register and the HSB pin.
Note When a burst write reaches a protected block address, it
continues the address increment into the protected space but
does not write any data to the protected memory. If the address
roll over takes the burst write to unprotected space, it resumes
writes. The same operation is true if a burst write is initiated
within a write protected block.
Read Sequence (READ) instruction
The read operations on this device are performed by giving the
instruction on the SI and reading the output on SO pin. The
following sequence needs to be followed for a read operation:
Figure 11. Read Instruction Timing
CS
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SCK
0
0
0
0
0
SO
Document #: 001-53873 Rev. *E
0
12 13 14 15 0
1
2
3
4
5
6
7
16-bit Address
Op-Code
SI
~
~ ~
~
0
1
1 15 14 13 12 11 10 9
MSB
HI-Z
8
3
2
1
0
LSB
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
Data
Page 12 of 27
[+] Feedback
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Figure 12. Burst Mode Read Instruction Timing
1
2
3
4
5
6
0
7
1
2
3
4
5
6
7
Op-Code
0
0
0
0
0
1
2
3
4
5
6
7
0
0
7
1
2
3
4
5
6
7
16-bit Address
0
1
0
1
15 14 13 12 11 10
9
~
~
SI
12 13 14 15
~
~
0
SCK
~
~
CS
8
MSB
3
2
1
0
LSB
Data Byte N
~
~
Data Byte 1
HI-Z
SO
D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
MSB
MSB
LSB
LSB
Figure 13. Write Instruction Timing
CS
1
2
3
4
5
6
0
7
1
2
3
4
5
6
7
SCK
Op-Code
SI
0
0
0
0
0
~
~ ~
~
0
12 13
14 15
0
1
2
3
4
5
6
7
16-bit Address
0
1
0
15 14 13 12 11 10
9
8
MSB
2
3
1
0
D7 D6 D5 D4 D3 D2 D1 D0
LSB MSB
LSB
Data
HI-Z
SO
Figure 14. Burst Mode Write Instruction Timing
CS
2
3
4
5
6
7
0
1
2
3
4
5
6
7
12 13 14 15
0
1
2
3
4
5
6
7
0
0
0
0
0
0
1
0
15 14 13 12 11 10
9
8
3
2
SO
Document #: 001-53873 Rev. *E
1
0
2
3
4
5
6
7
D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0
LSB MSB
MSB
1
~
~
0
~
~
SI
16-bit Address
0
Data Byte N
Data Byte 1
Op-Code
7
~
~
1
~
~
0
SCK
LSB
HI-Z
Page 13 of 27
[+] Feedback
nvSRAM Special Instructions
AutoStore Enable (ASENB) Instruction
CY14B512Q1/CY14B512Q2/CY14B512Q3
provides
four
special instructions which enables access to the nvSRAM
specific functions: STORE, RECALL, ASDISB, and ASENB.
Table 8 lists these instructions.
The AutoStore Enable instruction enables the AutoStore on
CY14B512Q1. This setting is not nonvolatile and needs to be
followed by a STORE sequence if this is desired to survive the
power cycle.
Table 8. nvSRAM Special Instructions
To issue this instruction, the device must be Write Enabled (WEN
= ‘1’). The instruction is performed by transmitting the ASENB
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the ASENB
instruction.
Function Name
Opcode
STORE
0011 1100
Software STORE
Operation
RECALL
0110 0000
Software RECALL
ASENB
0101 1001
AutoStore Enable
ASDISB
0001 1001
AutoStore Disable
Software STORE (STORE) instruction
When a STORE instruction is executed, nvSRAM performs a
Software STORE operation. The STORE operation is performed
irrespective of whether a write has taken place since the last
STORE or RECALL operation.
To issue this instruction, the device must be Write Enabled (WEN
bit = ‘1’). The instruction is performed by transmitting the STORE
opcode on the SI pin following the falling edge of CS. The WEN
bit is cleared on the positive edge of CS following the STORE
instruction.
Figure 15. Software STORE Operation
Note If ASDISB and ASENB instructions are executed in
CY14B512Q1, the device is busy for the duration of software
sequence processing time (tSS). However, ASDISB and ASENB
instructions have no effect on CY14B512Q1 as AutoStore is
internally disabled.
Figure 17. AutoStore Enable Operation
CS
0
1
2
3
4
5
6
7
SCK
SI
0
1
0
1
1
0
0
1
HI-Z
SO
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
1
1
1
1
0
0
HI-Z
SO
Software RECALL (RECALL) instruction
When a RECALL instruction is executed, nvSRAM performs a
Software RECALL operation. To issue this instruction, the device
must be Write Enabled (WEN = ‘1’).
The instruction is performed by transmitting the RECALL opcode
on the SI pin following the falling edge of CS. The WEN bit is
cleared on the positive edge of CS following the RECALL
instruction.
Figure 16. Software RECALL Operation
0
1
2
3
4
5
6
7
SCK
SO
AutoStore is enabled by default in CY14B512Q2/CY14B512Q3.
The ASDISB instruction disables the AutoStore. This setting is
not nonvolatile and needs to be followed by a STORE sequence
if this is desired to survive the power cycle.
To issue this instruction, the device must be Write Enabled
(WEN = ‘1’). The instruction is performed by transmitting the
ASDISB opcode on the SI pin following the falling edge of CS.
The WEN bit is cleared on the positive edge of CS following the
ASDISB instruction.
Figure 18. AutoStore Disable Operation
CS
0
0
1
1
0
0
0
0
1
2
3
4
5
6
7
SCK
SI
CS
SI
AutoStore Disable (ASDISB) Instruction
SO
0
0
0
1
1
0
0
1
HI-Z
0
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
HI-Z
Document #: 001-53873 Rev. *E
Page 14 of 27
[+] Feedback
Best Practices
HOLD Pin Operation
The HOLD pin is used to pause the serial communication. When
the device is selected and a serial sequence is underway, HOLD
is used to pause the serial communication with the master device
without resetting the ongoing serial sequence. To pause, the
HOLD pin must be brought LOW when the SCK pin is LOW. CS
pin must remain LOW along with HOLD pin to pause serial
communication. While the device serial communication is
paused, inputs to the SI pin are ignored and the SO pin is in the
high impedance state. To resume serial communication, the
HOLD pin must be brought HIGH when the SCK pin is LOW
(SCK may toggle during HOLD).
nvSRAM products have been used effectively for over 27 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■
The nonvolatile cells in this nvSRAM product are delivered from
Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system
manufacturing test to ensure these system routines work
consistently.
■
Power-up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, AutoStore Enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
■
The VCAP value specified in this datasheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum VCAP value because
the nvSRAM internal algorithm calculates VCAP charge and
discharge time based on this maximum VCAP value. Customers
that want to use a larger VCAP value to make sure there is extra
STORE charge and STORE time should discuss their VCAP
size selection with Cypress to understand any impact on the
VCAP voltage level at the end of a tRECALL period.
Figure 19. HOLD Operation
SCK
HOLD
~
~
CS
SO
Document #: 001-53873 Rev. *E
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Page 15 of 27
[+] Feedback
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CY14B512Q1
CY14B512Q2
CY14B512Q3
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Transient voltage (< 20 ns) on
any pin to ground potential .................. –2.0 V to VCC + 2.0 V
Storage temperature ................................ –65 °C to +150 °C
Package power dissipation
capability (TA = 25 °C) .................................................. 1.0 W
Maximum accumulated storage time
Surface mount lead soldering
temperature (3 seconds) .......................................... +260 °C
At 150 °C ambient temperature................... .... 1000 h
At 85 °C ambient temperature.................. ... 20 Years
DC output current (1 output at a time, 1 s duration).....15 mA
Ambient temperature with
power applied ........................................... –55 °C to +150 °C
Static discharge voltage.......................................... > 2001 V
(per MIL-STD-883, method 3015)
Supply voltage on VCC relative to VSS .........–0.5 V to + 4.1 V
Latch up current..................................................... > 200 mA
DC voltage applied to outputs
in high Z state ...................................... –0.5 V to VCC + 0.5 V
Table 9. Operating Range
Input voltage ........................................ –0.5 V to VCC + 0.5 V
Range
Ambient Temperature
VCC
–40 °C to +85 °C
2.7 V to 3.6 V
Industrial
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7 V to 3.6 V)
Parameter
Description
Test Conditions
Min
Typ[5]
Max
Unit
2.7
3.0
3.6
V
–
–
10
mA
VCC
Power supply voltage
ICC1
Average Vcc current
ICC2
Average VCC current during STORE All inputs don’t care, VCC = Max
Average current for duration tSTORE
–
–
10
mA
ICC4
Average VCAP current during
AutoStore cycle
All inputs don’t care. Average current for
duration tSTORE
–
–
5
mA
ISB
VCC standby current
CS > (VCC – 0.2 V). VIN < 0.2 V or > (VCC
– 0.2 V). Standby current level after
nonvolatile cycle is complete. Inputs are
static. f = 0 MHz
–
–
5
mA
IIX[6]
Input leakage current (except HSB)
VCC = Max, VSS < VIN < VCC
–1
–
+1
µA
Input leakage current (for HSB)
VCC = Max, VSS < VIN < VCC
–100
–
+1
µA
IOZ
Off state output leakage current
VCC = Max, VSS < VOUT < VCC
–1
–
+1
µA
At fSCK = 40 MHz
Values obtained without output loads
(IOUT = 0 mA)
VIH
Input HIGH voltage
2.0
–
VCC + 0.5
V
VIL
Input LOW voltage
VSS – 0.5
–
0.8
V
VOH
Output HIGH voltage
IOUT = –2 mA
2.4
–
VOL
Output LOW voltage
IOUT = 4 mA
–
VCAP
Storage capacitor
Between VCAP pin and VSS, 5 V rated
61
68
–
V
0.4
V
180
µF
Notes
5. Typical values are at 25 °C, VCC= VCC (Typ). Not 100% tested.
6. The HSB pin has IOUT = -2 µA for VOH of 2.4 V when both active high and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested.
Document #: 001-53873 Rev. *E
Page 16 of 27
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CY14B512Q1
CY14B512Q2
CY14B512Q3
Data Retention and Endurance
Parameter
Description
DATAR
Data retention
NVC
Nonvolatile STORE operations
Min
Unit
20
Years
1,000
K
Max
Unit
6
pF
8
pF
Capacitance
Parameter[7]
Description
Test Conditions
CIN
Input capacitance
COUT
Output pin capacitance
TA = 25 °C, f = 1 MHz,
VCC = VCC (Typ)
Thermal Resistance
Parameter [7]
Description
ΘJA
Thermal resistance
(junction to ambient)
ΘJC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA / JESD51.
16-SOIC
8-DFN
Unit
55.17
17.7
°C / W
2.64
18.8
°C / W
Figure 20. AC Test Loads and Waveforms
577 Ω
577 Ω
3.0 V
3.0 V
R1
R1
Output
Output
30 pF
R2
789 Ω
5 pF
R2
789 Ω
AC Test Conditions
Input pulse levels.................................................... 0 V to 3 V
Input rise and fall times (10% to 90%)......................... < 3 ns
Input and output timing reference levels........................ 1.5 V
Note
7. These parameters are guaranteed by design and are not tested.
Document #: 001-53873 Rev. *E
Page 17 of 27
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AC Switching Characteristics
Cypress
Parameter
fSCK
tCL
tCH
tCS
tCSS
tCSH
tSD
tHD
tHH
tSH
tCO
tHHZ[8]
tHLZ[8]
tOH
tHZCS
Alt.
Parameter
fSCK
tWL
tWH
tCE
tCES
tCEH
tSU
tH
tHD
tCD
tV
tHZ
tLZ
tHO
tDIS
40 MHz
Description
Min
–
11
11
20
10
10
5
5
5
5
–
–
–
0
–
Clock frequency, SCK
Clock pulse width lOW
Clock pulse width HIGH
CS high time
CS setup time
CS hold time
Data in setup time
Data in hold time
HOLD hold time
HOLD setup time
Output valid
HOLD to output high Z
HOLD to output low Z
Output hold time
Output disable time
Unit
Max
40
–
–
–
–
–
–
–
–
–
9
15
15
–
25
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 21. Synchronous Data Timing (Mode 0)
tCS
CS
tCH
tCL
tCSH
~
~
tCSS
SCK
tSD
tHD
VALID IN
SI
tCO
SO
tOH
HI-Z
tHZCS
HI-Z
Figure 22. HOLD Timing
~
~
CS
SCK
tHH
tHH
tSH
tSH
HOLD
tHHZ
tHLZ
SO
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Note
8. These parameters are guaranteed by design and are not tested.
Document #: 001-53873 Rev. *E
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CY14B512Q1
CY14B512Q2
CY14B512Q3
AutoStore or Power-Up RECALL
Parameter
Power-Up RECALL duration
tFA [9]
tSTORE
CY14B512Q1/CY14B512Q2/CY14B512Q3
Min
Max
–
20
Description
[10]
tDELAY [11]
VSWITCH
tVCCRISE
[12]
Unit
ms
STORE cycle duration
–
8
ms
Time allowed to complete SRAM write cycle
–
25
ns
–
150
2.65
–
V
μs
–
1.9
V
Low voltage trigger level
VCC rise time
VHDIS[12]
HSB output disable voltage
tLZHSB[12]
tHHHD[12]
HSB hign to nvSRAM active time
–
5
μs
HSB high active time
–
500
ns
Switching Waveforms
Figure 23. AutoStore or Power-Up RECALL[13]
VCC
VSWITCH
VHDIS
t VCCRISE
tHHHD
Note
10
tSTORE
Note
tHHHD
14
Note
10
tSTORE
Note
14
HSB OUT
tDELAY
tLZHSB
AutoStore
tLZHSB
tDELAY
POWERUP
RECALL
tFA
tFA
Read & Write
Inhibited
(RWI)
POWER-UP
RECALL
Read & Write
BROWN
OUT
AutoStore
POWER-UP
RECALL
Read & Write
POWER
DOWN
AutoStore
Notes
9. tFA starts from the time VCC rises above VSWITCH.
10. If an SRAM write has not taken place since the last nonvolatile cycle, AutoStore or Hardware STORE is not initiated.
11. On a Hardware STORE and AutoStore initiation, SRAM write operation continues to be enabled for time tDELAY.
12. These parameters are guaranteed by design and are not tested.
13. Read and write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.
14. During power-up and power-down, HSB glitches when HSB pin is pulled up through an external resistor.
Document #: 001-53873 Rev. *E
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CY14B512Q1
CY14B512Q2
CY14B512Q3
Software Controlled STORE and RECALL Cycles
Parameter
tRECALL
tSS
[15, 16]
Max
RECALL duration
–
200
μs
Soft sequence processing time
–
100
μs
Figure 25. Software RECALL Cycle[16]
CS
CS
0
1
2
3
4
5
6
7
0
SCK
1
2
3
4
5
6
7
SCK
0
0
1
1
1
1
0
0
SI
0
1
1
0
0
0
0
0
tRECALL
tSTORE
HI-Z
RWI
HI-Z
RWI
RDY
RDY
Figure 26. AutoStore Enable Cycle
Figure 27. AutoStore Disable Cycle
CS
CS
0
1
2
3
4
5
6
0
7
1
2
3
4
5
6
7
SCK
SCK
SI
0
1
0
1
1
0
0
SI
1
0
0
0
1
1
0
0
1
tSS
tSS
RWI
Unit
Min
Figure 24. Software STORE Cycle[16]
SI
CY14B512Q1/CY14B512Q2/CY14B512Q3
Description
HI-Z
RDY
RWI
HI-Z
RDY
Notes
15. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
16. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-53873 Rev. *E
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CY14B512Q1
CY14B512Q2
CY14B512Q3
Hardware STORE Cycle
Parameter
tPHSB
CY14B512Q3
Description
Hardware STORE pulse width
Switching Waveforms
Min
Max
15
–
Unit
ns
Figure 28. Hardware STORE Cycle[17]
Write Latch set
~
~
tPHSB
HSB (IN)
tSTORE
tHHHD
~
~
tDELAY
HSB (OUT)
tLZHSB
RWI
tPHSB
HSB (IN)
HSB pin is driven HIGH to VCC only by Internal
100 K: resistor, HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven LOW.
tDELAY
RWI
~
~
HSB (OUT)
~
~
Write Latch not set
Note
17. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
Document #: 001-53873 Rev. *E
Page 21 of 27
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CY14B512Q1
CY14B512Q2
CY14B512Q3
Ordering Information
Package
Diagram
Ordering Code
CY14B512Q2-LHXI
001-50671
Package Type
8-pin DFN (With VCAP)
Operating
Range
Availability
Industrial
For samples only
The above part is Pb-free.Contact your local Cypress sales representative for availability of this part.
Ordering Code Definition
CY 14 B 512 Q 1-LH X I T
Option:
T - Tape and Reel
Blank - Std.
Pb-free
Temperature:
I - Industrial (-40 to 85 °C)
Package:
SF - 16 SOIC
LH - 8 DFN
1 - With WP
2 - With VCAP
3 - With VCAP, WP and HSB
Voltage:
B - 3.0 V
Q - Serial (SPI) nvSRAM
Density:
512 - 512 Kb
14 - nvSRAM
Cypress
Document #: 001-53873 Rev. *E
Page 22 of 27
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CY14B512Q1
CY14B512Q2
CY14B512Q3
Package Diagrams
Figure 29. 8-pin (300 mil) DFN Package, 001-50671
001-50671 *B
Document #: 001-53873 Rev. *E
Page 23 of 27
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CY14B512Q1
CY14B512Q2
CY14B512Q3
Figure 30. 16-pin (300 mil) SOIC, 51-85022
51-85022 *C
Document #: 001-53873 Rev. *E
Page 24 of 27
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Acronyms
Document Conventions
Acronym
Description
Units of Measure
CPHA
Clock phase
CPOL
Clock polarity
°C
degrees Celsius
Dual flat no-lead
Hz
Hertz
DFN
EEPROM
Electrically erasable programmable
read-only memory
EIA
Electronic Industries Alliance
I/O
Input/output
nvSRAM
nonvolatile static random access memory
RoHS
Restriction of hazardous substances
SOIC
Small outline integrated circuit
SONOS
SPI
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Silicon-oxide-nitride-oxide-silicon
Serial peripheral interface
Document #: 001-53873 Rev. *E
Symbol
Unit of Measure
kbit
1024 bits
kHz
kilo Hertz
KΩ
kilo ohms
μA
micro Amperes
mA
milli Ampere
μF
micro Farads
MHz
mega Hertz
μs
micro seconds
ms
milli seconds
ns
nano seconds
pF
pico Farads
V
Volts
Ω
ohms
W
Watts
Page 25 of 27
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CY14B512Q1
CY14B512Q2
CY14B512Q3
Document History Page
Document Title: CY14B512Q1/CY14B512Q2/CY14B512Q3 512-Kbit (64 K × 8) Serial (SPI) nvSRAM
Document Number: 001-53873
Orig. of
Submission
Rev.
ECN No.
Description of Change
Change
Date
**
2733272 GVCH/AESA
07/08/09
New data sheet
*A
2758904
GVCH
09/02/2009 Moved data sheet status from Preliminary to Final
Removed commercial temperature related specs
Added thermal resistance values for 16-SOIC and DFN package
Added note to Write Sequence (WRITE) description
*B
2839453 GVCH/PYRS
01/06/10
Changed STORE cycles to QuantumTrap from 200K to 1 Million
Added Contents
Updated Figure 3
*C
3013837
GVCH
09/02/2010 Added watermark as “For Evaluation Samples Only. Production will be supported with the next revision silicon in SOIC package”
Updated Figure 1 to show the pad in the pin diagrams.
Changed ground naming convention from GND to VSS
Table 1: Updated to give information on the EXPOSED PAD.
Table 1: Added more clarity on HSB pin operation
Hardware STORE and HSB pin Operation: Added more clarity on HSB pin
operation
Updated Power-Down description
Power On Reset: Added status of bits 4-6
Table 5: Added definition of bits 4-6
Updated Figure 8, Figure 21, Figure 22, and Figure 23
Updated footnote 14
Added Figure 26 and Figure 27
Removed tDHSB parameter
Updated Figure 28
Removed inactive parts from Ordering Information and added Ordering code
definition.
Added Acronyms and Units of Measure table.
*D
3038143
GVCH
09/24/2010 Added watermark as “For Evaluation Samples only. Production will be
upported with the next revision silicon in SOIC package.”
Updated HOLD Pin Operation, Figure 19 and Figure 22 to indicate that CS pin
must remain LOW along with HOLD pin to pause serial communication.
*E
3135772
GVCH
01/12/2011 Hardware STORE and HSB pin Operation: Added more clarity on HSB pin
operation
Updated tLZHSB parameter description
Fixed typo in Figure 23.
Document #: 001-53873 Rev. *E
Page 26 of 27
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Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
For Evaluation Samples only. Production will be supported with the next revision silicon in SOIC package.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-53873 Rev. *E
Revised January 12, 2011
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