MGA-636P8 High Linearity Low Noise Amplifier Data Sheet Description Features Avago Technologies’ MGA-636P8 is an economical, easyto-use GaAs MMIC Low Noise Amplifier (LNA). This LNA has low noise and high linearity achieved through the use of Avago Technologies’ proprietary 0.25 mm GaAs Enhancement-mode pHEMT process. It is housed in the miniature 2.0 x 2.0 x 0.75 mm3 8-pin Dual-Flat-Non-Lead (DFN) package. The device is designed for optimum use from 450 MHz up to 1.5 GHz. The compact footprint and low profile coupled with low noise, high gain and high linearity make this an ideal choice as a low noise amplifier for cellular infrastructure applications such as LTE, GSM, CDMA, W-CDMA, CDMA2000 & TD-SCDMA. For optimum performance at lower frequency from 1.5 GHz up to 2.5 GHz, MGA-637P8 is recommended. For optimum performance at higher frequency from 2.5 GHz up to 4 GHz, MGA-638P8 is recommended. All these 3 products, MGA-636P8, MGA-637P8 and MGA-638P8 share the same package and pinout configuration. • High linearity performance. Pin Configuration and Package Marking [2] [3] [8] 36X [7] [6] [5] [4] TOP VIEW Pin 1 – Not Used Pin 2 – RFinput Pin 3 – Vbias2 Pin 4 – Not Used Center paddle – GND [8] [7] [6] [5] GND • GaAs E-pHEMT Technology[1]. • Low cost small package size. • Integrated with active bias and option to access FET gate. • Integrated power down control pin. Specifications 700 MHz; 4.8 V, 108 mA • 18.8 dB Gain • 0.44 dB Noise Figure • 11 dB Input Return Loss • +23.7 dBm Input IP3 • +23.8 dBm Output Power at 1 dB gain compression Applications 2.0 x 2.0 x 0.75 mm3 8-lead DFN [1] • Low Noise Figure. [1] [2] [3] [4] BOTTOM VIEW • Cellular infrastructure applications such as LTE, GSM, CDMA, W-CDMA, CDMA2000 & TD-SCDMA. • Other low noise applications. Note: 1. Enhancement mode technology employs positive Vgs, thereby eliminating the need of negative gate voltage associated with conventional depletion mode devices. Pin 5 – Vbias1 Pin 6 – PwrDwn Pin 7 – RFoutput Pin 8 – Not Used Note: Package marking provides orientation and identification “36” = Product Code “X” = Month Code It is recommended to ground Pin1, 4 and 8 which are Not Used. Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model = 70 V ESD Human Body Model = 300 V Refer to Avago Application Note A004R: Electrostatic Discharge, Damage and Control. Simplified Schematic [1] Vdd C6 R2 C4 L3 C1 RFin L1 C3 [8] [NU] [2] [RFinput] [7] [RFoutput] [3] [Vbias2] Bias [4] [NU] R1 L2 [1] [NU] C2 RFout [6] [PwrDwn] [5] [Vbias1] Rb C7 C5 C8 PwrDwn Vbias1 Note: 1. Device is turned ON when PwrDwn pin is applied with 0 V or left open. Device is turned OFF when PwrDwn pin is applied with 3.3 V. Absolute Maximum Rating [1] TA=25° C Thermal Resistance Symbol Parameter Units Absolute Maximum Vdd Device Voltage, RF output to ground V 5.5 Idd Drain Current mA 130 Vbias1 Bias Voltage V 5.5 VPwrDwn Power Down Voltage V 5.5 Pin,max CW RF Input Power dBm +24 Pdiss Total Power Dissipation W 0.72 Tj Junction Temperature °C 150 Tstg Storage Temperature °C -65 to 150 2 Thermal Resistance [2] (Vdd = 4.8 V, Idd = 108 mA) θjc = 79.6°C/W Notes: 1. Operation of this device in excess of any of these limits may cause permanent damage. 2. Thermal resistance measured using Infra-Red Measurement Technique. 3. Power dissipation with unit turned on. Board temperature Tc is 25° C. Derate at 12.6 mW/°C for TC > 93° C. Electrical Specifications [1, 4] TA = 25° C, Vdd = Vbias1 = 4.8 V, RF measurement at 700 MHz, measured on demo board in Figure 5 with component listed in Table1. Symbol Parameter and Test Condition Units Min. Typ. Max. Idd Drain Current mA 89 108 126 IPwrDwn Current at VPwrDwn pin when VPwrDwn =3.3 V (Power Down mode) mA – 0.15 – Gain Gain dB 17.5 18.8 20.5 NF[2] Noise Figure dB – 0.44 0.8 IIP3[3] Input Third Order Intercept Point dBm 22 23.7 – OP1dB Output Power at 1dB Gain Compression dBm – 23.8 – IRL Input Return Loss, 50 Ω source dB – 11 – ORL Output Return Loss, 50 Ω load dB – 21 – Notes: 1. Measurements at 700 MHz obtained using demo board described in Figure 5. 2. For NF data, board losses of the input have not been de-embedded. 3. IIP3 test condition: FRF1 = 700 MHz, FRF2 = 701 MHz with input power of -10 dBm per tone. 4. Use proper bias, heatsink and derating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application note for more details. Product Consistency Distribution Charts [1, 2] LSL 80 90 USL 100 110 120 USL 0.2 130 0.4 0.5 0.6 0.7 0.8 LSL LSL 23 24 Figure 3. IIP3, LSL = 22 dBm, nominal = 23.7 dBm 0.9 Figure 2. NF, nominal = 0.44 dB, USL = 0.8 dB Figure 1. Idd, LSL = 89 mA , nominal = 108 mA, USL = 126 mA 22 0.3 25 17 USL 18 19 20 Figure 4. Gain, LSL = 17.5 dB, nominal = 18.8 dB, USL = 20.5 dB Notes: 1. Distribution data sample size is 500 samples taken from 3 different wafer lots. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 2. Circuit trace losses have not been de-embedded from measurements above. 3 Demo Board Layout Demo Board Schematic Avago Technologies BTS LNA Nov 2010 Vdd C6 R2 RFin L3 C1 C2 L1 L2 C4 C6 C3 Rb C4 RFout L3 C1 RFin R1 L1 C5 C8 C7 C3 [8] [NU] [2] [RFinput] [7] [RFoutput] [3] [Vbias2] Bias [4] [NU] R1 L2 [1] [NU] [5] [Vbias1] Rb C7 Vbias1 C8 PwrDwn Vdd PwrDwn RFout [6] [PwrDwn] C5 Vbias1 C2 Truth Table Figure 5. Demo Board Layout Diagram – Recommended PCB material is 10 mils Rogers RO4350. – Suggested component values may vary according to layout and PCB material. VPwrDwn(V) LNA Mode 0 or open Power Down Mode 3.3 Figure 6. Demo Board Schematic Diagram Notes: • The schematic is shown with the assumption that similar PCB is used for all MGA-636P8, MGA-637P8 and MGA-638P8. • Detail of the components needed for this product is shown in Table 1. Table 1. Component list for 700 MHz matching Part Size Value Detail Part Number C1, C2, C4 0402 100 pF (Murata) GRM1555C1H101JD01D C3 0402 27 pF (Murata) GRM1555C1H270JA01D C5, C6, C7, C8 0402 4.7 mF (Murata) GRM188R60J475KE19D L1, L2 0402 33 nH (Toko) LL1005-FHL33NJ L3 0402 Not Used Rb 0402 Not Used R1 0402 51 ohm (Rohm) MCR004YZPJ510 R2 0402 0 ohm (Rohm) MCR01MZPJ000 Notes: C1, C2 are DC blocking capacitors L1 input match for NF L2 output match for IP3 C3, C4, C5, C6, C7, C8 are bypass capacitors R1 is a stabilizing resistor Rb is the biasing resistor (not used) 4 Typical Performance 0.5 0.5 0.4 0.4 0.3 0.3 Fmin (dB) Fmin (dB) RF performance at TA = 25° C, Vdd = 4.8 V, Idd = 100 mA, measured using 50 ohm input and output board unless stated otherwise. IIP3 test condition: FRF1-FRF2 = 1 MHz with input power of -10 dBm per tone. 0.2 0.1 0 0.1 70 80 90 Idd (mA) 100 Gain(dB) Gain(dB) 70 80 90 Idd (mA) 100 110 80 90 Idd (mA) 100 110 IIP3 (dBm) Figure 11. IIP3 vs Idd at 4.8 V Tuned for Optimum IIP3 and Fmin at 700 MHz 5 80 90 Idd (mA) 100 110 22 20 18 16 14 12 10 8 6 4 2 0 70 80 90 Idd (mA) 100 110 Figure 10. Gain vs Idd at 4.8 V Tuned for Optimum IIP3 and Fmin at 900 MHz IIP3 (dBm) 70 70 Figure 8. Fmin vs Idd at 4.8 V at 900 MHz Figure 9. Gain vs Idd at 4.8 V Tuned for Optimum IIP3 and Fmin at 700 MHz 30 29 28 27 26 25 24 23 22 21 20 0 110 Figure 7. Fmin vs Idd at 4.8 V at 700 MHz 22 20 18 16 14 12 10 8 6 4 2 0 0.2 30 29 28 27 26 25 24 23 22 21 20 70 80 90 Idd (mA) 100 110 Figure 12. IIP3 vs Idd at 4.8 V Tuned for Optimum IIP3 and Fmin at 900 MHz 22 0.7 20 0.6 18 0.5 16 Gain (dB) Fmin (dB) 0.8 0.4 0.3 0.2 100 mA 90 mA 80 mA 0.1 0 500 700 800 900 Frequency (MHz) 1700 1900 Figure 13. Fmin vs Frequency and Idd at 4.8 V 34 IIP3 (dBm) 32 30 28 26 24 500 700 800 900 Frequency (MHz) 1700 1900 Figure 15. IIP3 vs Frequency for Optimum IIP3 and Fmin at 4.8 V 100 mA 6 12 10 8 6 500 700 800 900 Frequency (MHz) 1700 1900 Figure 14. Gain vs Frequency for Optimum IIP3 and Fmin at 4.8 V 100 mA 36 22 14 Below is the table showing the MGA-636P8 Reflection Coefficient Parameters tuned for Maximum IIP3, Vdd = 4.8 V, Idd = 100 mA. Frequency (GHz) Gamma Load position Magnitude Angle IIP3 (dBm) 0.50 0.36 -57.7 22.6 0.70 0.36 -57.6 28.4 0.80 0.36 -43.2 28.2 0.90 0.27 -39.9 28.9 1.70 0.27 -27.9 34.9 1.90 0.27 0.3 35.7 RFinput Reference Plane [1] [NU] [8] [NU] [2] [RFinput] [7] [RFoutput] [3] [Vbias2] Bias [4] [NU] RFoutput Reference Plane [6] [PwrDwn] [5] [Vbias1] Figure 16. RFinput and RFoutput Reference Plane Notes: 1. The Maximum IIP3 values are calculated based on Load pull measurements on approximately 100 different impedances using Focus Load pull test system. 2. Measurements are conducted on 0.010 inch thick ROGER 4350. The input reference plane is at the end of the RFin pin and the output reference plane is at the end of the RFout pin as shown in Figure 16. 7 Typical Performance 0.8 24.0 0.7 22.0 0.6 20.0 0.5 Gain (dB) NF (dB) RF performance at TA = 25° C, Vdd = Vbias1 = 4.8 V, Idd = 108 mA, LNA mode, measured on demo board in Figure 5. Signal = CW unless stated otherwise. Application Test Circuit is shown in Figure 6 and Table 1. IIP3 test condition: FRF1-FRF2 = 1 MHz with input power of -10 dBm per tone. 0.4 0.3 0.2 0.0 0 IIP3 (dBm) OP1dB(dBm) 800 1000 1200 1400 Frequency (MHz) 600 800 1000 1200 1400 1600 1800 2000 Frequency (MHz) Figure 18. Gain vs Frequency vs Temperature 85° C 25° C -40° C Figure 19. IIP3 vs Frequency vs Temperature 8 10.0 400 200 400 600 800 1000 1200 1400 1600 1800 2000 Frequency (MHz) 600 16.0 12.0 Figure 17. NF vs Frequency vs Temperature 36 34 32 30 28 26 24 22 20 18 16 14 12 10 400 18.0 14.0 85° C 25° C -40° C 0.1 85° C 25° C -40° C 1600 1800 2000 28 27 26 25 24 23 22 21 20 19 18 400 85° C 25° C -40° C 600 800 1000 1200 1400 Frequency (MHz) Figure 20. OP1dB vs Frequency vs Temperature 1600 1800 2000 3.0 2.0 1.5 1.0 0.5 3 4 5 6 Frequency (GHz) Figure 21. Input Return Loss, Output Return Loss, Gain, Reverse Isolation vs Frequency 0 1 2 0.0 8 10 12 14 Frequency (GHz) Figure 22. k-factor vs Frequency vs Temperature 120 100 100 80 80 Idd (mA) 120 60 0 2 4 40 20 20 0 0 9 16 18 20 85° C 25° C -40° C 0.0 1.0 Rb (ohm) Figure 23. Idd vs Rb 6 60 40 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500 6000 6500 7000 7500 8000 8500 9000 9500 10000 Idd (mA) 100° C 85° C 25° C -40° C 2.5 k-factor dB(S(1,2)) dB(S(2,2)) dB(S(1,1)) dB(S(2,1)) 25 20 15 10 5 0 -5 -10 -15 -20 -25 -30 -35 Figure 24. Idd vs VPwrDwn 2.0 VPwrDwn (V) 3.0 4.0 Typical Scattering Parameters, Vdd = 4.8 V, Idd = 108 mA LNA SPAR (100 MHz – 20 GHz) Freq (GHz) S11 (dB) S11 (ang) S21 (dB) S21 (ang) S12 (dB) S12 (ang) S22 (dB) S22 (ang) 0.1 -3.611 -62.842 30.561 136.999 -34.551 62.629 -15.454 -100.227 0.5 -10.75 -141.835 21.562 98.647 -25.1 65.794 -21.768 173.774 0.7 -11.393 -159.056 19.067 89.008 -22.486 65.115 -23.274 176.757 0.9 -11.693 -171.846 17.088 81.239 -20.477 63.144 -23.435 -175.622 1.0 -12.003 -176.697 16.247 77.798 -19.607 61.903 -24.023 -169.048 1.5 -12.658 161.534 12.916 62.727 -16.314 54.394 -22.335 -157.583 1.7 -12.53 154.197 11.855 57.342 -15.332 51.078 -20.648 -161.025 1.9 -12.404 147.907 10.906 52.163 -14.463 47.752 -19.362 -164.643 2.0 -12.379 145.023 10.472 49.657 -14.065 46.022 -18.873 -166.072 2.5 -12.524 132.944 8.569 37.635 -12.364 37.489 -17.143 -171.539 3 -13.356 123.107 7.083 26.504 -10.943 28.854 -15.991 -174.201 3.5 -14.336 114.678 5.844 15.468 -9.794 19.876 -15.602 -179.46 4 -15.464 103.233 4.756 5.444 -8.846 11.572 -14.891 177.251 4.5 -16.075 89.916 3.908 -5.273 -7.978 2.026 -13.836 161.01 5 -15.98 79.553 3.084 -15.148 -7.323 -6.929 -12.579 146.587 5.5 -15.742 62.755 2.344 -25.098 -6.757 -16.231 -11.308 133.363 6 -15.688 50.395 1.686 -34.558 -6.287 -25.298 -10.288 121.972 7 -17.293 40.867 0.539 -52.328 -5.474 -42.892 -9.2 104.475 8 -23.851 68.823 -0.256 -69.296 -4.831 -60.283 -9.074 95.197 9 -19.948 145.615 -1.09 -85.871 -4.478 -77.706 -9.337 88.367 10 -15.337 144.42 -1.671 -102.123 -4.108 -95.651 -8.526 78.112 11 -14.047 129.044 -2.544 -120.208 -4.249 -115.535 -7.598 48.997 12 -12.433 104.57 -3.529 -135.218 -4.696 -132.217 -6.371 28.359 13 -9.432 93.835 -4.488 -151.951 -5.197 -150.835 -4.998 26.293 14 -6.416 81.489 -5.847 -162.095 -6.312 -163.011 -5.407 16.024 15 -5.585 68.225 -5.445 -168.582 -5.676 -170.476 -8.272 15.731 16 -5.651 57.754 -5.184 172.519 -5.19 168.847 -6.291 6.112 17 -4.91 46.32 -6.704 156.563 -6.646 151.286 -4.337 -20.813 18 -4.432 34.876 -7.895 144.747 -7.778 138.297 -3.486 -31.185 19 -3.638 18.869 -8.76 131.758 -8.607 124.14 -2.747 -26.804 20 -3.147 2.127 -8.894 121.339 -8.745 112.553 -2.767 -18.826 RFinput Reference Plane [1] [NU] [8] [NU] [2] [RFinput] [7] [RFoutput] [3] [Vbias2] Bias [4] [NU] Figure 25. RFinput and RFoutput Reference Plane 10 [6] [PwrDwn] [5] [Vbias1] RFoutput Reference Plane Typical Noise Parameters, Vdd = 4.8 V, Idd = 108 mA Part Number Ordering Information Part Number No. of Devices Container Rn/50 MGA-636P8-BLKG 100 Antistatic Bag -31.8 0.038 MGA-636P8-TR1G 3000 7 inch Reel 11.5 0.037 0.081 33.2 0.037 0.386 0.082 54.8 0.038 0.5 0.092 228 0.043 0.582 0.094 271 0.043 Freq GHz Fmin dB Γopt Mag. Γopt Ang. 0.5 0.472 0.078 0.7 0.432 0.080 0.8 0.379 0.9 1.7 1.9 Notes: 1. The Fmin values are based on noise figure measurements at 100 different impedances using Focus source pull test system. From these measurements a true Fmin is calculated. 2. Scattering and noise parameters are measured on coplanar waveguide made on 0.010 inch thick ROGER 4350. The input reference plane is at the end of the RFinput pin and the output reference plane is at the end of the RFoutput pin as shown in Figure 25. DFN2X2 Package Dimensions PIN 1 DOT BY MARKING 2.00±0.10 0.20 Ref. 2.00±0.10 36X 0.0–0.05 TOP VIEW 0.75±0.10 SIDE VIEW 0.60±0.05 Exp. DAP PIN #1 IDENTIFICATION R0.10 0.35±0.05 1.20±0.05 Exp. DAP 0.50 Bsc 0.25±0.05 BOTTOM VIEW 11 1.50 Ref. Notes: 1. All dimensions are in millimeters. 2. Dimensions are inclusive of plating. 3. Dimensions are exclusive of mold ash and metal burr. Recommended PCB Land Pattern and Stencil Design 2.20 2.16 1.75 0.563x 0.502x 1.75 0.00 0.80 0.506x 0.228x 0.458x 0.05 (all SM gaps) 0.303x R0.154x PCB Land Pattern 0.1702x 0.408x Stencil Design 1.75 0.563x 0.506x 0.50 Metal surface 0.21 1.50 Soldermask Open R0.154x 0.172x Combines PCB & Stencil Design All Dimension are in millimeters Notes: 1. Stencil thickness is 0.1 mm (4 mils). 2. All dimensions are in mm unless otherwise specified. 12 1.50 0.258x 0.21 1.72 0.482x 1.50 1.20 0.50 0.506x Device Orientation REEL 4 mm 8 mm 36X CARRIER TAPE USER FEED DIRECTION 36X COVER TAPE Tape Dimensions D P PO P2 E F W + + D1 t1 Tt KO 10° MAX AO DESCRIPTION LENGTH WIDTH DEPTH PITCH BOTTOM HOLE DIAMETER PERFORATION DIAMETER PITCH POSITION CARRIER TAPE WIDTH CAVITY COVER TAPE DISTANCE 13 10° MAX BO THICKNESS WIDTH TAPE THICKNESS CAVITY TO PERFORATION (WIDTH DIRECTION) CAVITY TO PERFORATION (LENGTH DIRECTION) SYMBOL A0 B0 K0 P D1 D P0 E W t1 C Tt F SIZE (mm) 2.30 ± 0.05 2.30 ± 0.05 1.00 ± 0.05 4.00 ± 0.10 1.00 + 0.25 1.50 ± 0.10 4.00 ± 0.10 1.75 ± 0.10 8.00 ± 0.30 8.00 ± 0.10 0.254 ± 0.02 5.4 ± 0.10 0.062 ± 0.001 3.50 ± 0.05 SIZE (INCHES) 0.091 ± 0.004 0.091 ± 0.004 0.039 ± 0.002 0.157 ± 0.004 0.039 + 0.002 0.060 ± 0.004 0.157 ± 0.004 0.069 ± 0.004 0.315 ± 0.012 0.315 ± 0.004 0.010 ± 0.0008 0.205 ± 0.004 0.0025 ± 0.0004 0.138 ± 0.002 P2 2.00 ± 0.05 0.079 ± 0.002 36X 36X Reel Dimensions – 7 inch 6.25mm EMBOSSED LETTERS LETTERING THICKNESS: 1.6mm SLOT HOLE "a" SEE DETAIL "X" Ø178.0±0.5 SLOT HOLE "b" FRONT BACK 6 PS SLOT HOLE(2x) 180° APART. SLOT HOLE "a": 3.0±0.5mm(1x) SLOT HOLE "b": 2.5±0.5mm(1x) FRONT VIEW 12.4 45° 1.5 MIN. +1.5* -0.0 +0.5 Ø13.0 -0.2 Ø20.2 MIN. BACK 45° Ø55.0±0.5 FRONT EMBOSSED RIBS RAISED: 0.25mm, WIDTH: 1.25mm Ø178.0±0.5 Ø51.2±0.3 BACK VIEW For product information and a complete list of distributors, please go to our web site: SEE DETAIL "Y" DETAIL "X" Ø178.0±0.5 R5.2 ° R10.65 120 65° 18.0* MAX. www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. AV02-2991EN - March 7, 2013 3.5 DETAIL "Y" (Slot Hole) 1.0 6 PS RECYCLE LOGO