DM9081
10BASE-T Hub Controller
General Description
The 10BASE-T Hub Controller (DM9081) provides a
system level solution for designing IEEE-compliant 802.3
repeaters that incorporate 10BASE-T transceivers. This
device integrates the repeater functions specified by
section 9 of the IEEE 802.3 standard. The Twisted Pair
transceiver is compliant with 10BASE-T standards. The
DM9081 provides eight integral Twisted Pair Media
Attachment Units (MAUs) and two Attachment Unit
Interface (AUI) ports in a 100-pin QFP package.
The total number of ports per repeater unit can be
increased by connecting multiple DM9081 chips via
their expansion ports. The DM9081 supports LED drivers
to monitor port status. It displays Link, Carrier Sense,
Collision, Partition, and Bit Rate Error Status. In
minimum mode, Link, Carrier Sense, and Collision Status
can be displayed without external TTL devices.
Block Diagram
PREAMBLE
TX
MUX
JAM SIGNAL
FIFO
AUI
PORT1
RXP1
RXN1
CDP1
CDN1
TXP1
TXN1
AUI
PORT2
RXP2
RXN2
CDP2
CDN2
TXP2
TXN2
TP
PORT0
RXD0+
RXD0TPO0+
DTPO0+
DTPO0TPO0-
DATA IN
MANCHESTER
DECODER
RX
MUX
RX_CLK
PLL
NRZ DATA
MUX
MANCHESTER
ENCODER
DATA OUT
*
*
*
*
*
EXPIN#
EXPOUT#
EXPANSION
PORT
STATE
MACHINE
DAT
Final
Version: DM9081-DS-F01
April 22, 1997
AUI1_CRS_LED
LED PORT2
AUI2_CRS_LED
TIMER
COL_LED
LED_LATCH
TCK
TP_LINK_LED
TP_PAR_LED
TRAFFIC_LED
TP_JAB_LED
TP_POL_LED
TP_BIT_LED
AUI_LED
LED PORT1
TP
PORT7
RXD7+
RXD7TPO7+
DTPO7+
DTPO7TPO7-
1
DM9081
Table of Contents
General Description....................................................... 1
Block Diagram .............................................................. 1
T TP Ports Partition Status ...........................................11
T Traffic Status............................................................11
T TP Port Link Status ..................................................11
T DM9081 Chip External Components ........................12
Table Of Contents.......................................................... 2
Absolute Maximum Ratings.........................................13
Features......................................................................... 3
DC Electrical Characteristics .......................................13
Pin Configuration .......................................................... 3
AC Characteristics .......................................................14
Pin Description.............................................................. 4
Functional Description .................................................. 6
T Repeater function ....................................................... 6
T Signal Regeneration ................................................... 6
T Collision Function...................................................... 6
T Auto Partition/Reconnection ...................................... 6
T Fragment Extension ................................................... 6
T Link Integrity Test ..................................................... 6
T Jabber Lockup Protection ........................................... 7
T Reset .......................................................................... 7
T Expansion Port........................................................... 7
T External Logic ........................................................... 8
T LED Functions........................................................... 9
T Collision Status.......................................................... 9
T AUI1 Port Status ........................................................ 9
T AUI2 Port Status ........................................................ 9
T Minimum Mode ......................................................... 9
T TP Port Status ............................................................ 9
T Normal Mode........................................................... 10
T LED Latch ............................................................... 10
T AUI Ports Status ...................................................... 11
T TP Ports Bit Rate Error Status .................................. 11
T TP Ports Jabber Status.............................................. 11
2
Timing Waveforms
T Expansion Port Input Timing ...................................15
T Expansion Port Output Timing .................................15
T Expansion Port Collision Timing..............................16
T AUI Transmit Timing...............................................16
T AUI Receive Timing.................................................17
T AUI Collision Timing...............................................17
T Transmit Timing ......................................................17
T Receive Timing ........................................................18
T Link Integrity Timing...............................................18
Layout Recommendation
T Decoupling ...............................................................19
T Power Plane..............................................................19
Package Information ....................................................21
Ordering Information ...................................................22
Company Overview......................................................22
Contact Windows.........................................................22
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Version: DM9081-DS-F01
April 22, 1997
DM9081
Features
T Repeater functions comply with IEEE 802.3 Repeater
T
T
T
T
T
T Built-in Traffic LED indicates Hub global 10MHz
Unit specification
Eight Integral 10BASE-T transceivers utilize the
required pre-distortion transmission technique
Two Attachment Unit Interface (AUI) ports allow
connection with 10BASE5 (Ethernet) and 10BASE2
(Cheapernet) networks
Design a Dumb Hub in minimum mode by using
minimum external logic that can respond to Link,
Carrier Sense and Collision Status from LED
Supports one LED output per port for additional status
indicators such as Link, Partition, Carrier Sense, etc.
Built-in Jabber LED reports global Jabber information
of the DM9081 Hub
bandwidth utilization status
T Expandable to accommodate two DM9081 connections,
with no external logic required
T On board PLL, Manchester encoder/decoder and FIFO
T Expandable to accommodate increased number of
T
T
repeater ports. Recommended IC cascade number: under
3 and inclusive
Preamble loss effects eliminated by deep FIFO
Each port can be isolated (partitioned) and reconnected
separately
Twisted Pair Link Test capability
Full amplitude and timing regeneration for
retransmitted signals
Low power CMOS process with single 5V supply
100-pin QFP package
T
T
T
T
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Version: DM9081-DS-F01
April 22, 1997
DV D D
AGND
AV D D
82
81
DTPO0-
83
TPO0-
86
DTPO0+
DGND
87
TPO0+
TPO1+
88
84
DTPO1+
89
85
DTPO1-
TPO2+
94
90
DTPO2+
95
91
DTPO296
DV D D
TPO297
TPO1-
DGND
98
92
TPO3+
99
93
DTPO3+
100
Pin Configuration
DTPO3-
1
80
CDP2
TPO3-
2
79
CDN2
DV D D
3
78
RXP2
DV D D
4
77
RXN2
LI/RX7
5
LED_LATCH
76
TXP2
LI/RX6
6
AUI_LED
75
TXN2
LI/RX5
7
TP_BIT_LED
74
CDP1
LI/RX4
8
TP_POL_LED
73
CDN1
DV D D
9
72
RXP1
LI/RX3
10 TP_JAB_LED
71
RXN1
LI/RX2
11 TRAFFIC_LED
70
TXP1
LI/RX1
12 TP_PAR_LED
69
TXN1
LI/RX0
13 TP_LINK_LED
68
AGND
DGND
14
67
AV D D
66
RXD0+
65
RXD0-
AUI1_CRS_LED
15
AUI1_CRS_LED
16
COL_LED
17
64
RXD1+
RESET#
18
63
RXD1-
TESTPIN1
19
62
RXD2+
TESTPIN0
20
61
RXD2-
DGND
21
60
RXD3+
EXPIN#
22
59
RXD3-
DAT
23
58
RXD4+
EXPOUT#
24
57
RXD4-
TCK
25
56
RXD5+
NC
26
55
RXD5-
X2
27
54
RXD6+
X1
28
53
RXD6-
NC
29
52
RXD7+
DV D D
30
51
RXD7-
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TPO4-
DTPO4-
DTPO4+
TPO4+
DGND
TPO5-
DTPO5+
DTPO5+
TPO5+
DV D D
TPO6-
DTPO6+
DTPO6-
TPO6+
DGND
TPO7+
DTPO7-
DTPO7+
TPO7+
DV D D
DM9081F
3
DM9081
Pin Description
Pin No.
Transceiver
100, 1
99, 2
34, 31
33, 32
39, 36
38, 37
44, 41
43, 42
49, 46
48, 47
84, 87
85, 86
89, 92
90, 91
94, 97
95, 96
52, 51
54, 53
56, 55
58, 57
60, 59
62, 61
64, 63
66, 65
70, 69
76, 75
72, 71
78, 77
74, 73
80, 79
Expansion Port
24
4
Pin Name
I/O
Description
DTPO3+/TPO3+/TPO4+/DTPO4+/TPO5+/DTPO5+/TPO6+/DTPO6+/TPO7+/DTPO7+/TPO0+/DTPO0+/TPO1+/DTPO1+/TPO2+/DTPO2+/RXD7+/RXD6+/RXD5+/RXD4+/RXD3+/RXD2+/RXD1+/RXD0+/TXP1, TXN1
TXP2, TXN2
RXP1, RXN1
RXP2, RXN2
CDP1, CDN1
CDP2, CDN2
O
TP Driver Outputs. The TPO+/- output generate 10Mbits/s Manchesterencoded data. The DTPO+/- outputs are one-half bit time delayed and
inverted with respect to TPO+/-. These four outputs provide the TP drivers
with pre-distortion capability
I
10BASE-T Port Different Data Receivers
O
I
AUI Port Different Data Drivers. The outputs are source followers that
require a 270Ω pull-down resistor
AUI Port Differential Receive Input Pair
I
AUI Port Different Collision Input Pair
EXPOUT#
O
22
EXPIN#
I
23
DAT
I/O,Z
The assertion of this signal indicates that DM9081 is transmitting data on
DAT pins. It is active low
The assertion of this signal indicates that DM9081 is receiving data on
DAT pins. The receiving data will be broadcast to the other ports. It is
active low and is internally pulled high with a 100KΩ resistor
The DAT pins of all DM9081 chips are inter-connected. The active
DM9081 drives DAT with repeated data or jam signals in NRZ format.
The inactive DM9081 receives the repeated data or jam signals from the
DAT pin
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April 22, 1997
DM9081
Pin Description
Pin No.
Pin Name
Miscellaneous
3, 4, 9, 30,
DVDD
40, 50, 83,
93
14, 21, 35,
DGND
45, 88, 98
18
RESET#
I/O
P
Digital Power
P
Digital Ground
I
Active low to reset the internal logic of DM9081. It should be synchronized to
X2 if multiple DM9081s
are used
These two pins are used to select LED display mode. Normal mode is selected
if both pins are connected to VDD. Minimum mode is selected if both pins are
connected to GND. Other settings are prohibited
These pins should be left open
A 20MHz oscillator or crystal should be attached to this pin
This pin is used in crystal connection only. It is left open when using an
oscillator
Analog Power
Analog Ground
20, 19
TESTPIN0
TESTPIN1
I
26, 29
27
28
NC
X2
X1
I
O
67, 81
AVDD
68, 82
AGND
LED Display Pins
5
LED_LATCH
(LI/RX7)
6
AUI_LED
(LI/RX6)
7
TP_BIT_LED
(LI/RX5)
8
TP_POL_LED
(LI/RX4)
10
TP_JAB_LED
(LI/RX3)
11
TRAFFIC_LED
(LI/RX2)
12
TP_PAR_LED
(LI/RX1)
P
P
O
O
O
O
O
O
O
13
TP_LINK_LED
(LI/RX0)
O
15
16
17
25
AUI1_CRS_LED
AUI2_CRS_LED
COL_LED
TCK
O
O
O
O
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Version: DM9081-DS-F01
April 22, 1997
Description
This pin is used to latch the serial LED information from pins 6 to 13
In minimum mode, this pin sends out TP7 Link and Carrier Sense status
This pin transmits AUI port status synchronous to TCK
In minimum mode, this pin sends out TP6 Link and Carrier Sense status
This pin sends out global bit rate error status of the DM9081 Hub
In minimum mode, this pin sends out TP5 Link and Carrier Sense status
In minimum mode, this pin sends out TP4 Link and Carrier Sense status
This pin transmits global jabber status of the DM9081 Hub
In minimum mode, this pin sends out TP3 Link and Carrier Sense status
This pin sends out utilization of 10MHz bandwidth synchronous to TCK
In minimum mode, this pin sends out TP2 Link and Carrier Sense status
This pin sends out the partition status synchronous to TCK for the eight TP
ports
In minimum mode, this pin sends out TP1 Link and Carrier Sense status
This pin sends out the link and carrier sense status synchronous to TCK for
the eight TP ports
In minimum mode, this pin sends out TP0 Link and Carrier Sense status
Active low for 52ms when AUI Port 1 detects carrier
Active low for 52ms when AUI Port 2 detects carrier
Active low for 26ms when collision is detected
A 10MHz clock synchronous to X2
5
DM9081
Functional Description
The DM9081 Integrated Multiport Controller is a single
chip implementation of an IEEE 802.3 Ethernet repeater
(Hub). The DM9081 chip provides eight integral
10BASE-T ports plus two AUI ports, comprising the basic
repeater. The DM9081 is also expandable, enabling the
implementation of high port count repeaters based on
more than one DM9081 chip. The DM9081 chip complies
with the full set of repeater basic functions, as defined in
Section 9 of ISO 8802.3 (ANSI/IEEE 802.3C). These
functions are summarized below.
Repeater Function
When any single network port senses the start of a packet
on its receive lines, the DM9081 chip will broadcast the
received data to all other network ports. The repeated data
will also be presented on the expansion port to provide
multiple DM9081 chip repeater applications.
Signal Regeneration
When re-transmitting a packet, the DM9081 chip makes
sure that the outgoing packet complies with the 802.3
specification in terms of preamble instructions, voltage
amplitude and timing characteristics. Data packets
repeated by the DM9081 chip will contain a minimum of
62 preamble bits before the start of Frame Delimiter.
Finally, signal symmetry is restored to data packets
repeated by the DM9081 chip, removing jitter and
distortion caused by network cabling.
Collision Function
The DM9081 will detect and respond to collision
conditions as specified in IEEE 802.3. A multiple
DM9081 repeater (Hub) implementation also complies
with the 802.3 specification. Specifically, a repeater based
on one or more DM9081 chips will handle the transmit
collision and one-port-left collision conditions correctly.
6
Auto Partition/Reconnection
The DM9081 monitors any TP ports or AUI ports and
partitions them once certain criteria are met. TP ports and
AUI ports will be partitioned under extended duration or
when frequent collisions occur. Each TP port and the AUI
port are partitioned separately, and are independent of
other network ports. The DM9081 chip will cause the port
to partition under either of following conditions.
1. A collision condition exists continuously for 1024-bit
times (for example, when the AUI port SQE signal is
active and the TP port is transmitting simultaneously
and receiving).
2. Whenever each of 32 consecutive attempts to transmit to
that port results in a collision.
Any partitioned port can be reconnected if a packet longer
than 512-bit times is transmitted or received from that port
without collision.
Fragment Extension
If the total packet length received by the DM9081 is less
than 96 bits, including preamble, the DM9081 chip will
extend the repeated packet length to 96 bits by appending
a Jam sequence to the original fragment.
Link Integrity Test
The integral TP ports implement the Link Test function,
as specified in the 802.3 10BASE-T standard. The
DM9081 will transmit Link Test pulses to any TP port
after that port transmitter has been inactive for more than
8ms but less than 17 ms. Conversely, if a TP port does not
receive any data packets or Link Test pulses for more than
65ms but less than 132ms, that port will enter link fail
state. A port in link fail state will be disabled by the
DM9081 chip (repeater transmit functions are disabled)
until it receives either four consecutive Link Test pulses or
a data packet. Note, however, that the DM9081 chip will
always transmit Link Test pulses to all TP ports regardless
of whether the port is enabled, partitioned, or in link fail
state.
Final
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April 22, 1997
DM9081
Jabber Lockup Protection
Reset
The DM9081 chip implements a built-in jabber protection
scheme to ensure that the network is not disabled due to
transmission of excessively long data packets. This
protection scheme will automatically interrupt the
transmitter circuits of the DM9081 for 96-bit times if the
DM9081 chip has been transmitting continuously for more
than 65,536-bit times. This is referred to as MAU Jabber
Lockup Protection (MJLP).
An internal circuit ensures that a minimum reset pulse is
generated for all internal circuits. For a RESET input with
a slow rising edge, the input buffer threshold may be
crossed several times due to ripples on the input waveform.
During reset, the output signals are placed in their inactive
states. This means that all analog signals are placed in
their idle states, bidirectional signals are not driven, active
LOW signals are driven HIGH, and all active HIGH
signals and the LED_LATCH pin are driven LOW. In a
multiple DM9081 chip repeater, the RESET signal should
be applied simultaneously to all DM9081 chips, and
should be synchrononized to the external X2 clock. Table
1 summarizes the state of the DM9081 chip following
reset.
Function
DAT
Transmitters (TP and AUI)
RECEIVERS (TP and AUI)
AUI Partition/Reconnection
TP Port Partition/Reconnection
LINK Test Function for TP Ports
Active Low Output
Active High Output
State after Reset
Hi-Impedance
Idle
Enabled
Reconnect
Reconnect
Enabled
High
Low
Pull Up/Pull Down
NO
NC
Terminate
N/A
N/A
N/A
NO
NO
Table 1. Initial State of DM9081
Expansion Port
The DM9081 chip expansion port is comprised of three
pins: a bi-directional signal (DAT), an input signal
(EXPIN#), and an output signal (EXPOUT#). These
signals are used for multiple-DM9081 chip repeater
applications. In this configuration, all DM9081 chips must
be synchronized with a common clock connected to the X2
inputs. An external synchronnous reset is required. The
DM9081 expansion scheme allows the use of multiple
DM9081 chips in either a single repeater or a modular
multiple repeater with backplane architecture. The DAT
pins of all DM9081 chips must be interconnected. The
DAT pin is a bidirectional I/O pin that can be used to
transfer data or a jam signal between the DM9081 chips.
Final
Version: DM9081-DS-F01
April 22, 1997
The data sent over the DAT line is in NRZ format, and is
synchronized to the common clock.
In the multiple DM9081 configuration, the DM9081 chip
asserts the EXPOUT# pin to indicate that it is active and is
ready to drive the DAT pin. An external logic senses the
EXPOUT# line from all the DM9081 chips and asserts the
EXPIN# line to each DM9081. The active DM9081 asserts
EXPOUT#, and sends data or jam on the DAT line. Other
inactive DM9081 detect EXPIN# asserted, and receive
data on the DAT line. If more than one DM9081 chip
asserts EXPOUT# lines, then all DM9081s will broastcast
jam signals.
7
DM9081
External Logic
A simple logic scheme is required when more than two
DM9081 chips are connected to increase the total number
of repeater ports. The external logic should have one input
EXPIN1# =
EXPIN2# =
EXPIN3# =
.
.
.
EXPINn# =
EXPOUT2# &
EXPOUT1# &
EXPOUT1# &
.
.
.
EXPOUT1# &
The above equations are in positive logic, i.e., a variable is
true when asserted. An example of three banked DM9081
chips is shown in Figure 1. The cascade IC number
recommended: under 3 and inclusive.
(EXPOUT#) and one output (EXPIN#) for each DM9081
chip. This function is easily implemented in a PAL device,
using the following logical equations:
EXPOUT3# &
EXPOUT3# &
EXPOUT2# &
.
.
.
EXPOUT2# &
….. EXPOUTn#
….. EXPOUTn#
….. EXPOUTn#
.
.
.
….. EXPOUTN-1#
Note that if the design includes only two DM9081 chips,
then EXPOUT1# is connected to EXPIN2#, EXPOUT2# is
connected to EXPIN1#, and no external logic is required.
A single PAL16L8 performs the arbitration function for a
repeater based on several DM9081 chips.
Figure 1. Multiple DM9081 Devices
8
Final
Version: DM9081-DS-F01
April 22, 1997
DM9081
LED Functions
AUI2 Port Status
The DM9081 provides LED functions to monitor the TP
and AUI ports.
The AUI2_CRS_LED displays the AUI2 port status of the
DM9081. When the DM9081 receives a data packet from
the AUI2 port, the AUI2_CRS_LED pin will drive low for
52ms, then drive high at least 78ms until it responds to the
next packet.
Collision Status
The COL_LED pin displays the collision status of the
DM9081. When the DM9081 detects a collision, the
COL_LED will drive low for more than 26ms and less
than 52ms.
AUI1 Port Status
The AUI1_CRS_LED displays the AUI1 port status of the
DM9081. When the DM9081 receives a data packet from
AUI1 port, the AUI1_CRS_LED pin will drive low for
52ms, then drive high at least 78ms until it responds to the
next packet.
Minimum Mode
In minimum mode, TESTPIN0 and TESTPIN2 should be
pulled low and LI/RXn (n = 0~7) pins drive the LED
without using external TTL logic. The description is given
below in "TP Ports Status."
TP Ports Status
The LI/RXn (n=0~7) pin sends out the status for TP ports
0-7 of the DM9081. In link test fail state, the LI/RXn pin
is driven high. In link test pass, the LI/RXn pin is driven
low. When TP port receives a packet, the LI/RXn pin is
driven high for 78ms, then driven low at least 52ms until
it responds to the next packet. An example is shown in
Figure 2.
Figure 2. Minimum Mode Implementation
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Version: DM9081-DS-F01
April 22, 1997
9
DM9081
Normal Mode
LED Latch
In normal mode, TESTPIN0 and TESTPIN1 must be
pulled high. The COL_LED, AUI1_CRS_LED and
AUI2_CRS_LED pins are defined as minimum mode,
whereas the other LED drive pins require external devices
to display the status from the LED pins. These pins
transmit information from the DM9081 by first sending
Bit 7. A detailed timing diagram is given in Figure 3. The
shift logic and latch device shown in Figure 4 is used to
convert received serial data into byte- oriented data. The
output data is used to drive the LED.
The LED_LATCH pin is used to latch the byte-oriented
data. The rising edge of the TCK clock, occurring on the
high state LED_LATCH, is used to strobe in the state of
the following LED pins.
TCK
LI_RXn
B1
B0
B7
B6
B5
B4
B3
B2
B1
B0
B7
B6
B5
B4
B3
B2
B1
LED_LATCH
Figure 3. Serial LED Signal Timing
Figure 4. Normal Mode Implementation
10
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Version: DM9081-DS-F01
April 22, 1997
DM9081
AUI Ports Status
Traffic Status
The AUI_LED pin transmits the status of DM9081's two
AUI ports on the falling edge of TCK. Figure 5 shows a
typical external hardware setup employed to convert a
serial bit stream into parallel form. The accuracy of the
AUI signals is within 8 Bit Times (BT). The contents of
the output data for the AUI_LED are as followed:
The TRAFFIC_LED pin transmits a utilization report for
the 10MHz bandwidth on the falling edge of TCK. Figure
4 shows a typical external hardware configuration
employed to convert the serial bit stream into parallel form.
The accuracy of the traffic signals is 8 bit. The
corresponding bit is set to low, if the following conditions
are met. The contents of the output data for the
TRAFFIC_LED are as followed:
Bit 0:
Bit 1:
Bit 2:
Bit 3:
Bit 4:
Bit 5:
Bit 6:
Bit 7:
AUI port 1 partition status (0: if partition)
AUI port 1 bit rate error status (0: if bit rate error)
AUI port 1 jabber status (0: if jabber)
AUI port 1 loopback status (0: if loopback error)
AUI port 2 partition status (0: if partition)
AUI port 2 bit rate error status (0: if bit rate error)
AUI port 2 jabber status (0: if jabber)
AUI port 2 loopback status (0: if loopback error)
TP Ports Bit Rate Error Status
Bit 0:
Bit 1:
Bit 2:
Bit 3:
Bit 4:
Bit 5:
Bit 6:
Bit 7:
The TP_BIT_LED pin sends out global bit rate error
information of the DM9081's Hub.
As shown above, if all 8 bits are active low, the utilization
is in excess of 87.5% for the 10MHz bandwidth.
TP Ports Jabber Status
TP Ports Link Status
The TP_JAB_LED pin sends out global jabber information
of the DM9081's Hub.
The TP_LINK_LED transmits link information for the
DM9081's eight TP ports on the falling edge of TCK.
Figure 5 shows a typical external hardware configuration
employed to convert the serial bit stream into parallel form.
The accuracy of the link signals is within 8 bit. If a TP port
is line fail, its corresponding bit is set to high. If a TP port
is line pass, its corresponding bit is set to low. When this
port receives a packet, its corresponding bit is set high for
78ms, then driven low at least 52ms until it responds to
the next packet. The contents of the output data for the
TP_LINK_LED are as followed:
TP Ports Partition Status
The TP_PAR_LED pin transmits partition information for
the DM9081's eight TP ports on the falling edge of TCK.
Figure 4 shows a typical external hardware configuration
employed to convert the serial bit stream into parallel form.
The accuracy of the partition signals is 8 bit. If a TP port is
in partition status, its corresponding bit is set to low. The
contents of the output data for the TP_PAR_LED are as
followed:
Bit 0: TP port 0 partition status
Bit 1: TP port 1 partition status
Bit 2: TP port 2 partition status
Bit 3: TP port 3 partition status
Bit 4: TP port 4 partition status
Bit 5: TP port 5 partition status
Bit 6: TP port 6 partition status
Bit 7: TP port 7 partition status
Final
Version: DM9081-DS-F01
April 22, 1997
Bit 0:
Bit 1:
Bit 2:
Bit 3:
Bit 4:
Bit 5:
Bit 6:
Bit 7:
Over 1% utilization of 10MHz bandwidth
Over 6.25% utilization of 10MHz bandwidth
Over 12.5% utilization of 10MHz bandwidth
Over 25% utilization of 10MHz bandwidth
Over 37.5% utilization of 10MHz bandwidth
Over 50% utilization of 10MHz bandwidth
Over 62.5% utilization of 10MHz bandwidth
Over 87.5% utilization of 10MHz bandwidth
TP port 0 link/receive status
TP port 1 link/receive status
TP port 2 link/receive status
TP port 3 link/receive status
TP port 4 link/receive status
TP port 5 link/receive status
TP port 6 link/receive status
TP port 7 link/receive status
11
DM9081
DM9081 Chip External Components
Figure 5 shows a typical twisted pair port external
components schematic diagram. The resistor used should
have a 1% tolerance to ensure compliance with 10BASE-T
networks. The filters and pulse transformers are necessary
devices that have a major impact on the performance and
compliance of the 10BASE-T repeater ports. Specifically,
the transmitted waveforms are heavily influenced by the
filter characteristics, and the twisted pair receivers employ
several criteria to continuously monitor the incoming
signals' amplitude and timing characteristics to determine
the necessity and the time to assert the internal carrier
sense. For these reasons, it is crucial that the values of the
resistors and the tolerances of the external components
comply with given specifications. Several manufacturers
produce modules that combine the functions of the
transmit filters, receive filters, and pulse transformers into
one package.
Figure 5. Typical Single TP Port Using External Components
Figure 6. Typical Single AUI Port Using Components
12
Final
Version: DM9081-DS-F01
April 22, 1997
DM9081
Absolute Maximum Ratings*
*Comments
Supply Voltage (VDD) ..............................-0.5V to +7.0V
DC Input Voltage (VIN)....................-0.5V to VCC +0.5V
DC Output Voltage (VOUT) ..............-0.5V to VCC +0.5V
Storage Temperature Range (Tstg) ........ -65°C to +150°C
Power Dissipation (PD) ...........................................1.2W
Lead Temp. (TL) (Soldering, 10sec.) ..................... 260°C
ESD Rating (Rzap=1.5K, Czap=100pF) ................2000V
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device.
These are stress ratings only. Functional operation of this
device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied or intended. Exposure to the absolute
maximum rating conditions for extended periods may
affect device reliability.
DC Electrical Characteristics (VDD=5V ± 5%, TA=0°C to 70°C, unless otherwise specified.)
Symbol
VIL
VIH
VOL
VOH
IIL
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Leakage Current
(also DAT as Input)
X2 Crystal Input Low Voltage
X2 Crystal Input High Voltage
Crystal Input Low Current
Crystal Input High Current
VILX
VIHX
IILX
IIHX
AUI Port
VOD
Differential Output Voltage (TXP,
TXN)
VOB
Differential Output Voltage
Imbalance (TXP, TXN)
VU
Undershoot Voltage
(TXP, TXN)
VDS
Differential Squelch Threshold
(RXP/RXN and CDP/CDN)
VCM
Differential Input Common Mode
Voltage
(RXP/RXN and CDP/CDN)
Twisted Pair Port
VTIDF
TP Input Voltage
TPO+/TPO-/DTPO+/DTPO-:
VOL
Low
VOH
High
DC Output Series Impedance:
RTP0
TP Drives
RTPI
RXD+/RXD- Input Resistance
Final
Version: DM9081-DS-F01
April 22, 1997
Min.
-0.5
2.0
2.4
-
Typ.
Max.
0.8
DVDD+0.5
0.4
10
Unit
V
V
V
V
uA
Conditions
DGND=0.0V, Except DAT
Except DAT
IOL=4mA
IOH=-4mA
DGND<VIN<DVDD
-0.5
3.8
-
1.0
DVDD+0.5
10
10
V
V
uA
uA
DGND=0.0V
DGND=0.0V
VIN=DGND
VIN=DVDD
550
1200
mV
-
40
mV
-
100
mV
175
300
mV
78Ω termination, and 270Ω
from each to GND
78Ω termination, and 270Ω
from each to GND
78Ω termination, and 270Ω
from each to GND
Negative pulse
VDD/2
V
350
2000
mV
4.9
0.1
-
V
V
16
10
24
Ω
KΩ
13
DM9081
DC Electrical Characteristics (continued)
Symbol
Parameter
Power Supply Current
IDD
Power Supply Current (idle)
Power Supply Current
(Transmitting with TP Port load)
Min.
Typ.
Max.
Unit
-
130
240
-
mA
mA
Conditions
AC Characteristics
Symbol
Parameter
AUI Port
tCB
Collision Turn-on Time
tCE
Collision Turn-off Time
tCIDL
CDP High To Idle Time
tCPH
Collision High-Pulse Width
tCP
Collision Period
tRIDL
RXP High To Idle Time
Twisted Pair Port
tTPDY
DTPO- To TPO+ & DTPO+ To TPO- Delay
tRD
Receive Delay From RXD To RXP/RXN
tROFF
RXD+ High To Idle Time
tLP
Transmitted Link Integrity Pulse Period
tLPWT
Link Integrity Pulse Width For TPO+
tLPWD
Link Integrity Pulse Width For DTPO
Jabber Timing
tJMT
Maximum Transmit Time for TPO
tJCB
Time from Jabber to Enable CI Output
tJU
Unjab Time
14
Min.
0
0
250
40
80
250
47
0
200
8
80
40
45
0
250
Typ.
50
100
Max.
Unit
900
900
350
60
120
350
ns
ns
ns
ns
ns
ns
53
500
16
100
50
24
120
60
ns
ns
ns
ms
ns
ns
50
55
900
750
ms
ms
ms
450
Conditions
Final
Version: DM9081-DS-F01
April 22, 1997
DM9081
Timing Waveforms
Expansion Port Input Timing
Symbol
tDJSET
tDJHOLD
Parameter
DAT Setup Time
DAT Hold Time
Min.
60
Typ.
Max.
20
-
Unit
ns
ns
Conditions
X2
TCK
EXPOUT
EXPIN
tD J S E T
DAT
IN
tD J H O L D
Expansion Port Output Timing
Symbol
tHRL
tHRH
tHDR
tHDZ
Parameter
TCK Rising Edge to EXPOUT# Driven Low
TCK Rising Edge to EXPOUT# Driven High
TCK Rising Edge to DAT Driven
TCK Rising Edge to DAT Not Driven
Min.
-
Typ.
Max.
20
20
20
20
Unit
ns
ns
ns
ns
Conditions
CL=100pF
CL=100pF
CL=100pF
CL=100pF
X2
TCK
tH R L
tH R H
EXPOUT
EXPIN
DAT
Final
Version: DM9081-DS-F01
April 22, 1997
tH D R
tH D Z
OUT
15
DM9081
Expansion Port Collision Timing
Symbol
tDOFF
Parameter
Min.
-
DAT Data Off
Typ.
Max.
20
Unit
ns
Conditions
CL=100pF
X2
TCK
EXPOUT
EXPIN
t DOFF
DAT
OUT
AUI Transmit Timing
Symbol
tTXTD
tTXTR
tTXTF
tTXRM
Parameter
X2 Rising Edge To TXP/TXN Toggle
TXP, TXN Rise Time (10% to 90%)
TXP, TXN Fall Time (90% to 10%)
TXP, TXN Rise & Fall Time Mismatch
1
X2
tT X T D
Min.
2.5
2.5
0
1
tT X T R
Typ.
1
Max.
30
5.0
5.0
1.0
1
Unit
ns
ns
ns
ns
0
Conditions
1
0
tT X T F
TXP
TXN
16
Final
Version: DM9081-DS-F01
April 22, 1997
DM9081
AUI Receive Timing
Symbol
tPWORX
tPWKRX
Parameter
RXP/RXN Pulse Width Accept/Reject Threshold
RXP/RXN Pulse Width Maintain/Turn-Off Threshold
Min.
15
136
Typ.
Max.
45
200
Unit
ns
ns
Conditions
|VIN|>|VASQ|
|VIN|>|VASQ|
tP W K R X
RXP/RXN
VASQ
tP W K R X
tP W O R X
AUI Collision Timing
Symbol
tPWOCD
tPWKCD
Parameter
CDP/CDN Pulse Width Accept/Reject Threshold
CDP/CDN Pulse Width Maintain/Turn-off Threshold
Min.
10
90
Typ.
Max.
26
160
Unit
ns
ns
Conditions
|VIN|>|VASQ|
|VIN|>|VASQ|
CDP/CDN
VASQ
tP W O C D
tP W K C D
Transmit Timing
Symbol
tPREDY
tIDL
Parameter
DTPO- to TPO+ and DTPO+ To TPO- Delay
TPO+ High To Idle Time
Min.
47
250
Typ.
Max.
53
350
Unit
ns
ns
Conditions
t IDL
TPO+
TPO-
tP R E D Y
DTPRDTPR+
Final
Version: DM9081-DS-F01
April 22, 1997
17
DM9081
Receive Timing
Symbol
tROFF
Parameter
RXD+ High To Idle Time
Min.
200
Typ.
Max.
Unit
ns
Conditions
Unit
ms
ns
ns
Conditions
tR O F F
R X D+
R X D-
Link Integrity Timing
Symbol
tLP
tLPWT
tLPWD
Parameter
Transmitted Link Integrity Pulse Period
Link Integrity Pulse Width For TPO+
Link Integrity Pulse Width For DTPO+/-
Min.
8
80
40
Typ.
16
100
50
Max.
24
120
60
tL P
T P O+
tL P W T
T P O-
tL P W D
D T P O+
tL P W D
D T P O-
18
Final
Version: DM9081-DS-F01
April 22, 1997
DM9081
Layout Recommendation
Decoupling
The DM9081 contains both analog and digital elements.
Separate power pins are provided for the analog sections,
the digital portion of TP line drivers, the TP line drivers,
and the digital core logic. Care should be taken in board
design to minimize coupling of noise from the power
supply and digital logic to the analog power pins.
Decoupling capacitors should be placed as close to the
appropriate VDD and GND pins as possible. Figure 7
shows the recommended decoupling values for the
DM9081 chip.
Figure 7. DM9081 Device Power Supply Decouping Recommendations
Final
Version: DM9081-DS-F01
April 22, 1997
19
DM9081
Power Plane
The board power planes must be separated into analog and
digital portions. The +5V and ground planes can be laid
out according to the configuration shown in Figure 8. The
analog portion should be located under the analog power
pins of the DM9081 chip and the AUI logic. The digital
portion should be located close enough to the 10BASE-T
filter to attach a 0.1mF capacitor to the filter ground pin.
Extending the digital power plane under the 10BASE-T
filter is not recommended. The analog and digital power
planes should be connected at a single point with either a
1.8-2.2Ω or 120Z ferrite bead. In the diagram below, a
47mF capacitor is used in parallel with a 0.1mF capacitor
to connect the analog and digital planes. Shielded RJ-45
connectors are recommended. The shielded pins should be
tied to the frame ground. Depending on the characteristics
of the 10BASE-T filter, either the frame ground or a void
in the planes should be extended under the filters. Consult
the filter manufacturer to determine if the frame ground is
needed to minimize the effects of cross-talk within the
filters.
Figure 8. DM9081 Device Power Plane Recommendations
20
Final
Version: DM9081-DS-F01
April 22, 1997
DM9081
Package Information
QFP 100L Outline Dimensions
Unit: Inches/mm
HD
D
80
30
51
F
E
1
31
e
GE
81
HE
100
b 50
GD
c
~~
D
See Detail F
Seating Plane
y
A
A1
A2
GD
L
L1
Symbol
Dimensions In Inches
Dimensions In mm
A
0.130 Max.
3.30 Max.
A1
0.004 Min.
0.10 Min.
A2
0.112Ř 0.005
2.85Ř 0.13
b
0.012 +0.004
0.31 +0.10
-0.002
-0.05
0.006 +0.004
0.15 +0.10
-0.002
-0.05
D
0.551Ř 0.005
14.00Ř 0.13
E
0.787Ř 0.005
20.00Ř 0.13
e
0.026 Ř 0.006
0.65Ř 0.15
F
0.742 NOM.
18.85 NOM.
GD
0.693 NOM.
17.60 NOM.
GE
0.929 NOM.
23.60 NOM.
HD
0.740Ř 0.012
18.80Ř 0.31
HE
0.976Ř 0.012
24.79Ř 0.31
L
0.047Ř 0.008
1.19Ř 0.20
L1
0.095Ř 0.008
2.41Ř 0.20
y
0.006 Max.
0.15 Max.
θ
0° ~ 12°
0° ~ 12°
c
Detail F
Note:
1. Dimensions D&E do not include resin fins.
2. Dimensions GD & GE are for PC Board surface mount pad pitch
design reference only.
3. All dimensions are based on metric system.
Final
Version: DM9081-DS-F01
April 22, 1997
21
DM9081
Ordering Information
Part Number
DM9081F
Company Overview
Pin Count
100
Package
QFP
! " #
$ % # % Products
Disclaimer
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+* , -((,. & *(),/0. ( &,* &( ,.
1'(1* " 1 2 " 2 2 " 1 & % # # ' # # % # ( #) 3 ! 3 Contact Windows
For additional information about DAVICOM products, contact the sales department at:
Headquarters
Asia Operation:
DAVICOM Semiconductor, Inc.
1135 Kern Ave.
Sunnyvale, CA 94086
TEL: 408-736-8600
FAX: 408-736-8688
Email: [email protected]
Taipei Sales Office:
Hsin-chu Office:
8F, No. 3, Lane 235, Bao-chiao Road,
Hsin-tien City, Taipei, Taiwan, R.O.C.
TEL: 886-2-915-3030
FAX: 886-2-915-7575
Email: [email protected]
4F, No. 17, Park Avenue II,
Science-based Park,
Hsin-chu City, Taiwan, R.O.C.
TEL: 886-3-579-8797
FAX: 886-3-579-8858
Customer Service Hot Line: 080-035035
WARNING
$ % # " " 4 Final
Version: DM9081-DS-F01
April 22, 1997