IS61(64)LF12832A IS64VF12832A IS61(64)LF12836A IS61(64)VF12836A IS61(64)LF25618A IS61(64)VF25618A ISSI 128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • Power Supply LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VF: VDD 2.5V -5% +10%, VDDQ 2.5V -5% +10% • JEDEC 100-Pin TQFP, 119-pin PBGA, and 165-pin PBGA packages • Automotive temperature available • Lead-free available ® PRELIMINARY INFORMATION AUGUST 2005 DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 words by 32 bits. The IS61(64)LF/VF12836A is organized as 131,072 words by 36 bits. The IS61(64)LF/VF25618A is organized as 262,144 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -6.5 6.5 7.5 133 -7.5 7.5 8.5 117 Units ns ns MHz Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 1 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® BLOCK DIAGRAM MODE A0' Q0 CLK CLK BINARY COUNTER CE ADV ADSC ADSP A1' Q1 128Kx32; 128Kx36; 256Kx18 MEMORY ARRAY CLR A0, A1 17/18 A 15/16 D 17/18 Q ADDRESS REGISTER CE CLK 32, 36, or 18 GW BWE BW(a-d) x18: a,b x32/x36: a-d D 32, 36, or 18 Q DQ(a-d) BYTE WRITE REGISTERS CLK CE 32, 36, or 18 2/4/8 Q CE2 D CE2 ENABLE REGISTER INPUT REGISTERS CLK DQa - DQd OE CE CLK OE 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI 165-PIN BGA 119-PIN BGA 165-Ball, 13x15 mm BGA 119-Ball, 14x22 mm BGA ® BOTTOM VIEW BOTTOM VIEW Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 3 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® 119 BGA PACKAGE PIN CONFIGURATION 128K X 36 (TOP VIEW) A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ A CE2 A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A NC NC A A A Vss Vss Vss BWc Vss NC Vss BWd Vss Vss Vss MODE A NC ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1 * A0 * VDD A NC A A A Vss Vss Vss BWb Vss NC Vss BWa Vss Vss Vss NC A NC A CE2 A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A NC NC VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A 4 Pin Name Address Inputs Symbol OE Pin Name Output Enable A0, A1 Synchronous Burst Address Inputs ZZ Power Sleep Mode ADV MODE Burst Sequence Selection ADSP Synchronous Burst Address Advance Address Status Processor NC No Connect ADSC Address Status Controller DQa-DQd Data Inputs/Outputs GW Global Write Enable DQPa-Pd Output Power Supply CLK Synchronous Clock VDD Power Supply CE, CE2, CE2 Synchronous Chip Select VDDQ Output Power Supply BWx (x=a-d) Synchronous Byte Write Controls Vss Ground BWE Byte Write Enable Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® 119 BGA PACKAGE PIN CONFIGURATION 256KX18 (TOP VIEW) A B C D E F G H J K L M N P R T U 1 2 3 4 5 6 7 VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ A CE2 A NC DQb NC DQb NC VDD DQb NC DQb NC DQPb A A NC A A A Vss Vss Vss BWb Vss NC Vss Vss Vss Vss Vss MODE A NC ADSP ADSC VDD NC CE OE ADV GW VDD CLK NC BWE A1 * A0* VDD NC NC A A A Vss Vss Vss Vss Vss NC Vss BWa Vss Vss Vss NC A NC A CE2 A DQPa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol OE Pin Name Output Enable A0, A1 Synchronous Burst Address Inputs ZZ Power Sleep Mode ADV MODE Burst Sequence Selection ADSP Synchronous Burst Address Advance Address Status Processor NC No Connect ADSC Address Status Controller DQa-DQb Data Inputs/Outputs GW Global Write Enable DQPa-Pb Output Power Supply CLK Synchronous Clock VDD Power Supply CE, CE2, CE2 Synchronous Chip Select VDDQ Output Power Supply BWx (x=a,b) Synchronous Byte Write Controls Vss Ground BWE Byte Write Enable Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 5 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® 165 PBGA PACKAGE PIN CONFIGURATION 128K X 36 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWc BWb CE2 BWE ADSC ADV A NC B NC A CE2 BWd BWa CLK GW OE ADSP A NC C DQPc NC VDDQ Vss Vss Vss Vss Vss VDDQ NC D DQc DQc VDDQ VDD Vss Vss Vss VDD VDDQ DQb DQb E DQc DQc VDDQ VDD Vss Vss Vss VDD VDDQ DQb DQb F DQc DQc VDDQ VDD Vss Vss Vss VDD VDDQ DQb DQb G DQc DQc VDDQ VDD Vss Vss Vss VDD VDDQ DQb DQb H NC NC NC VDD Vss Vss Vss VDD NC NC ZZ J DQd DQd VDDQ VDD Vss Vss Vss VDD VDDQ DQa DQa K DQd DQd VDDQ VDD Vss Vss Vss VDD VDDQ DQa DQa L DQd DQd VDDQ VDD Vss Vss Vss VDD VDDQ DQa DQa M DQd DQd VDDQ VDD Vss Vss Vss VDD VDDQ DQa DQa N DQPd NC VDDQ Vss NC NC NC Vss VDDQ NC DQPa P NC NC A A NC A1* NC A A A NC R MODE NC A A NC A0* NC A A A A DQPb Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol Pin Name BWE Byte Write Enable A0, A1 Synchronous Burst Address Inputs ADV OE Output Enable ZZ Power Sleep Mode ADSP Synchronous Burst Address Advance Address Status Processor MODE Burst Sequence Selection ADSC Address Status Controller NC DQx DQPx VDD VDDQ No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply Vss Ground GW Global Write Enable CLK Synchronous Clock CE, CE2, CE2 Synchronous Chip Select BWx (x=a,b,c,d) Synchronous Byte Write Controls 6 Isolated Output Power Supply 3.3V/2.5V Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® 165 PBGA PACKAGE PIN CONFIGURATION 256K X 18 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWb NC CE2 BWE ADSC ADV A A B NC A CE2 NC BWa CLK GW OE ADSP A NC C NC NC VDDQ Vss Vss Vss Vss Vss VDDQ NC DQPa D NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa E NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa F NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa G NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa H NC NC NC VDD Vss Vss Vss VDD NC NC ZZ J DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa NC K DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa NC L DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa NC M DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa NC N DQPb NC VDDQ Vss NC NC NC Vss VDDQ NC NC P NC NC A A NC A1* NC A A A NC R MODE NC A A NC A0* NC A A A A Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A Pin Name Address Inputs Symbol BWE Byte Write Enable A0, A1 Synchronous Burst Address Inputs ADV OE Output Enable ZZ Power Sleep Mode ADSP Synchronous Burst Address Advance Address Status Processor MODE Burst Sequence Selection ADSC Address Status Controller GW Global Write Enable CLK Synchronous Clock CE, CE2, CE2 Synchronous Chip Select No Connect Data Inputs/Outputs Data Inputs/Outputs 3.3V/2.5V Power Supply BWx (x=a,b) Synchronous Byte Write Controls NC DQx DQPx VDD VDDQ Vss Ground Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 Pin Name Isolated Output Power Supply 3.3V/2.5V 7 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® PIN CONFIGURATION 100-PIN TQFP (128K x 32) DQPc DQPb DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa DQPa NC DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd DQPd 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A A A CE CE2 BWd BWc BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-PIN TQFP (128K x 36) (3 Chip-Enable option) (3 Chip-Enable option) PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Data Input/Output DQPa-DQPd Parity Data Input/Output A Synchronous Address Inputs GW Synchronous Global Write Enable ADSC Synchronous Controller Address Status MODE Burst Sequence Mode Selection ADSP Synchronous Processor Address Status OE Output Enable ADV Synchronous Burst Address Advance VDD 3.3V/2.5V Power Supply BWa-BWd Synchronous Byte Write Enable VDDQ BWE Isolated Output Buffer Supply: 3.3V/2.5V Synchronous Byte Write Enable Vss Ground ZZ Snooze Enable CE, CE2, CE2 Synchronous Chip Enable CLK 8 DQa-DQd Synchronous Clock Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® PIN CONFIGURATION A A CE CE2 NC NC BWb BWa CE2 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 100-PIN TQFP (256K x 18) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC MODE A A A A A1 A0 NC NC VSS VDD NC NC A A A A A A A NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb NC VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC (3 Chip-Enable Option) PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs ADSC Synchronous Controller Address Status ADSP Synchronous Processor Address Status ADV Synchronous Burst Address Advance BWa-BWb Synchronous Byte Write Enable BWE Synchronous Byte Write Enable CE, CE2, CE2 Synchronous Chip Enable CLK Synchronous Clock DQa-DQb Synchronous Data Input/Output Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 DQPa-DQPb Parity Data I/O; DQPa is parity for DQa1-8; DQPb is parity for DQb1-8 GW Synchronous Global Write Enable MODE Burst Sequence Mode Selection OE Output Enable VDD 3.3V/2.5V Power Supply VDDQ Isolated Output Buffer Supply: 3.3V/2.5V Vss Ground ZZ Snooze Enable 9 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® TRUTH TABLE(1-8) ADDRESS CE OPERATION CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ Deselect Cycle, Power-Down None H X X L X L X X X L-H High-Z Deselect Cycle, Power-Down None L X L L L X X X X L-H High-Z Deselect Cycle, Power-Down None L H X L L X X X X L-H High-Z Deselect Cycle, Power-Down None L X L L H L X X X L-H High-Z Deselect Cycle, Power-Down None L H X L H L X X X L-H High-Z Snooze Mode, Power-Down None X X X H X X X X X X High-Z Read Cycle, Begin Burst External L L H L L X X X L L-H Q Read Cycle, Begin Burst External L L H L L X X X H L-H High-Z Write Cycle, Begin Burst External L L H L H L X L X L-H D Read Cycle, Begin Burst External L L H L H L X H L L-H Q Read Cycle, Begin Burst External L L H L H L X H H L-H High-Z Read Cycle, Continue Burst Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Next X X X L H H L H H L-H High-Z Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H High-Z Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D NOTE: 1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. 2. For WRITE, L means one or more byte write enable signals (BWa-d) and BWE are LOW or GW is LOW. WRITE = H for all BWx, BWE, GW HIGH. 3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s and DQPb. BWc enables WRITEs to DQc’s and DQPc. BWd enables WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH during the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification. PARTIAL TRUTH TABLE Function Read Read Write Byte 1 Write All Bytes Write All Bytes 10 GW BWE BWa BWb BWc BWd H H H H L H L L L X X H L L X X H H L X X H H L X X H H L X Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or No Connect) External Address A1 A0 1st Burst Address A1 A0 2nd Burst Address A1 A0 3rd Burst Address A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 LINEAR BURST ADDRESS TABLE (MODE = VSS) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol TSTG PD IOUT VIN, VOUT VIN Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to Vss for I/O Pins Voltage Relative to Vss for for Address and Control Inputs VDD Voltage on VDD Supply Relative to Vss Value Unit –55 to +150 °C 1.6 W 100 mA –0.5 to VDDQ + 0.5 V –0.5 to VDD + 0.5 V –0.5 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 11 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® OPERATING RANGE (IS61/64LFxxxxx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C VDD 3.3V ± 5% 3.3V ± 5% VDDQ 3.3V/2.5V ± 5% 3.3V/2.5V ± 5% Automotive -40°C to +125°C 3.3V ± 5% 3.3V/2.5V ± 5% OPERATING RANGE (IS61/64VFxxxxx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C VDD 2.5V -5% +10% 2.5V -5% +10% VDDQ 2.5V -5% +10% 2.5V -5% +10% Automotive -40°C to +125°C 2.5V -5% +10% 2.5V -5% +10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 3.3V 2.5V Symbol Parameter Test Conditions Min. Max. Min. Max. Unit VOH Output HIGH Voltage IOH = –4.0 mA (3.3V) IOH = –1.0 mA (2.5V) 2.4 — 2.0 — V VOL Output LOW Voltage IOL = 8.0 mA (3.3V) IOL = 1.0 mA (2.5V) — 0.4 — 0.4 V VIH Input HIGH Voltage 2.0 VDD + 0.3 1.7 VDD + 0.3 V VIL Input LOW Voltage –0.3 0.8 –0.3 0.7 V ILI Input Leakage Current VSS ≤ VIN ≤ VDD(1) –5 5 –5 5 µA ILO Output Leakage Current VSS ≤ VOUT ≤ VDDQ, OE = VIH –5 5 –5 5 µA 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter ICC AC Operating Supply Current Test Conditions Temp. range 6.5 MAX x18 x32/x36 7.5 MAX x18 x32/x36 155 160 175 Device Selected, OE = VIH, ZZ ≤ VIL, All Inputs ≤ 0.2V or ≥ VDD – 0.2V, Cycle Time ≥ tKC min. Com. Ind. AUTO. typ.(2) 175 180 190 175 180 190 120 Unit 155 160 175 mA 110 ISB Standby Current TTL Input Device Deselected, VDD = Max., All Inputs ≤ VIL or ≥ VIH, ZZ ≤ VIL, f = Max. Com. Ind. Auto. 90 100 120 90 100 120 90 100 120 90 100 120 mA ISBI Standby Current CMOS Input Device Deselected, VDD = Max., VIN ≤ VSS + 0.2V or ≥VDD – 0.2V f=0 Com. Ind. Auto. typ. 70 75 90 70 75 90 70 75 90 70 75 90 mA ZZ>VIH Com. Ind. Auto. typ. 30 35 45 30 35 45 mA ISB2 Sleep Mode 40 40 30 35 45 30 35 45 25 25 Note: 1. MODE pin has an internal pullup and should be tied to VDD or VSS. It exhibits ±100 µA maximum leakage current when tied to ≤ VSS + 0.2V or ≥ VDD – 0.2V. 2. Typical values are measured at VDD = 3.3V, TA = 25oC and not 100% tested. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, VDD = 3.3V. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 13 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 AC TEST LOADS 317 Ω 3.3V ZO = 50Ω OUTPUT 50Ω 1.5V Figure 1 14 OUTPUT 5 pF Including jig and scope 351 Ω Figure 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω +2.5V ZO = 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 1,538 Ω 1.25V Figure 3 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 Figure 4 15 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) 6.5 Min. Max. 7.5 Min. Max. Symbol Parameter fmax Clock Frequency — 133 — 117 MHz tKC Cycle Time 7.5 — 8.5 — ns tKH Clock High Time 2.2 — 2.5 — ns tKL Clock Low Time 2.2 — 2.5 — ns Clock Access Time — 6.5 — 7.5 ns tKQ (2) tKQX tKQLZ Unit Clock High to Output Invalid 2.5 — 2.5 — ns (2,3) Clock High to Output Low-Z 2.5 — 2.5 — ns (2,3) Clock High to Output High-Z — 3.8 — 4.0 ns tKQHZ tOEQ Output Enable to Output Valid — 3.2 — 3.4 ns (2) Output Enable to Output Invalid 2.5 — 2.5 — ns (2,3) Output Enable to Output Low-Z 0 — 0 — ns (2,3) Output Disable to Output High-Z — 3.5 — 3.5 ns tAS Address Setup Time 1.5 — 1.5 — ns tWS Read/Write Setup Time 1.5 — 1.5 — ns tCES Chip Enable Setup Time 1.5 — 1.5 — ns tAVS Address Advance Setup Time 1.5 — 1.5 — ns tDS Data Setup Time 1.5 — 1.5 — ns tAH Address Hold Time 0.5 — 0.5 — ns tWH Write Hold Time 0.5 — 0.5 — ns tCEH Chip Enable Hold Time 0.5 — 0.5 — ns tAVH Address Advance Hold Time 0.5 — 0.5 — ns tDH Data Hold Time 0.5 — 0.5 — ns tPDS ZZ High to Power Down — 2 — 2 cyc tPUS ZZ Low to Power Down — 2 — 2 cyc tOEQX tOELZ tOEHZ Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. 16 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® READ/WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE inactive ADSP tSS tSH ADSC ADV tAS Address tAH RD1 RD2 WR1 tWS tWH tWS tWH RD3 GW BWE tWS tWH WR1 BWd-BWa tCES tCEH tCES tCEH tCES tCEH CE Masks ADSP CE CE2 and CE2 only sampled with ADSP or ADSC CE2 Unselected with CE2 CE2 tOEHZ OE tKQ tOEQX DATAOUT High-Z 2c 2d tKQHZ tKQHZ High-Z 1a tDS Single Read Flow-through tDH Single Write Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 2b tKQX tKQX tKQX tKQ DATAIN 2a 1a tKQLZ tKQ Burst Read Unselected 17 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® WRITE CYCLE TIMING tKC CLK tSS tSH tKH tKL ADSP is blocked by CE1 inactive ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS tAVH ADV tAS Address tAH WR1 WR3 WR2 tWS tWH tWS tWH tWS tWH GW BWE BWd-BWa WR1 tCES tCEH tCES tCEH tCES tCEH tWS tWH WR2 WR3 CE1 Masks ADSP CE Unselected with CE2 CE2 and CE3 only sampled with ADSP or ADSC CE2 CE2 OE DATAOUT High-Z tDS DATAIN High-Z Single Write 18 tDH 1a BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d Burst Write 3a Write Unselected Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Min. Max. Unit ISB2 Current during SNOOZE MODE ZZ ≥ Vih — 60 mA tPDS ZZ active to input ignored — 2 cycle tPUS ZZ inactive to input sampled 2 — cycle tZZI ZZ active to SNOOZE current — 2 cycle tRZZI ZZ inactive to exit SNOOZE current 0 — ns SNOOZE MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z Don't Care Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 19 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® ORDERING INFORMATION (VDD = 3.3V/VDDQ = 2.5V/3.3V) Commercial Range: 0°C to +70°C Configuration Access Time Order Part Number Package 128Kx32 6.5 IS61LF12832A-6.5TQ IS61LF12832A-6.5B2 IS61LF12832A-6.5B3 100 TQFP 119 PBGA 165 PBGA 128Kx32 7.5 IS61LF12832A-7.5TQ IS61LF12832A-7.5B2 100 TQFP 119 PBGA IS61LF12832A-7.5B3 165 PBGA 128Kx36 6.5 IS61LF12836A-6.5TQ IS61LF12836A-6.5B2 IS61LF12836A-6.5B3 100 TQFP 119 PBGA 165 PBGA 128Kx36 7.5 IS61LF12836A-7.5TQ IS61LF12836A-7.5B2 100 TQFP 119 PBGA IS61LF12836A-7.5B3 165 PBGA 256Kx18 6.5 IS61LF25618A-6.5TQ IS61LF25618A-6.5B2 IS61LF25618A-6.5B3 100 TQFP 119 PBGA 165 PBGA 256Kx18 7.5 IS61LF25618A-7.5TQ IS61LF25618A-7.5B2 IS61LF25618A-7.5B3 100 TQFP 119 PBGA 165 PBGA 20 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® ORDERING INFORMATION (VDD = 3.3V/VDDQ = 2.5V/3.3V) Industrial Range: -40°C to +85°C Configuration Access Time Order Part Number Package 128Kx32 6.5 IS61LF12832A-6.5TQI IS61LF12832A-6.5B2I IS61LF12832A-6.5B3I 100 TQFP 119 PBGA 165 PBGA 128Kx32 7.5 IS61LF12832A-7.5TQI IS61LF12832A-7.5TQLI IS61LF12832A-7.5B2I 100 TQFP 100 TQFP, Lead-free 119 PBGA IS61LF12832A-7.5B3I 165 PBGA 128Kx36 6.5 IS61LF12836A-6.5TQI IS61LF12836A-6.5B2I IS61LF12836A-6.5B3I 100 TQFP 119 PBGA 165 PBGA 128Kx36 7.5 IS61LF12836A-7.5TQI IS61LF12836A-7.5TQLI IS61LF12836A-7.5B2I 100 TQFP 100 TQFP, Lead-free 119 PBGA IS61LF12836A-7.5B3I 165 PBGA 256Kx18 6.5 IS61LF25618A-6.5TQI IS61LF25618A-6.5B2I IS61LF25618A-6.5B3I 100 TQFP 119 PBGA 165 PBGA 256Kx18 7.5 IS61LF25618A-7.5TQI IS61LF25618A-7.5TQLI IS61LF25618A-7.5B2I IS61LF25618A-7.5B3I 100 TQFP 100 TQFP, Lead-free 119 PBGA 165 PBGA Order Part Number Package Automotive Range: -40°C to +125°C Configuration Access Time 128Kx32 7.5 IS64LF12832A-7.5TQA3 IS64LF12832A-7.5TQLA3 100 TQFP 100 TQFP, Lead-free 128Kx36 7.5 IS64LF12836A-7.5TQA3 100 TQFP 256Kx18 7.5 IS64LF25618A-7.5TQA3 100 TQFP Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 21 IS61(64)LF12832A, IS61(64)LF12836A, IS61(64)LF25618A IS64VF12832A, IS61(64)VF12836A, IS61(64)VF25618A ISSI ® ORDERING INFORMATION (VDD = 2.5V /VDDQ = 2.5V) Commercial Range: 0°C to +70°C Configuration Access Time Order Part Number Package 128Kx36 6.5 IS61VF12836A-6.5TQ IS61VF12836A-6.5B2 IS61VF12836A-6.5B3 100 TQFP 119 PBGA 165 PBGA 128Kx36 7.5 IS61VF12836A-7.5TQ IS61VF12836A-7.5B2 100 TQFP 119 PBGA IS61VF12836A-7.5B3 165 PBGA 256Kx18 6.5 IS61VF25618A-6.5TQ IS61VF25618A-6.5B2 IS61VF25618A-6.5B3 100 TQFP 119 PBGA 165 PBGA 256Kx18 7.5 IS61VF25618A-7.5TQ IS61VF25618A-7.5B2 100 TQFP 119 PBGA IS61VF25618A-7.5B3 165 PBGA Industrial Range: -40°C to +85°C Configuration Access Time Order Part Number Package 128Kx36 6.5 IS61VF12836A-6.5TQI IS61VF12836A-6.5B2I IS61VF12836A-6.5B3I 100 TQFP 119 PBGA 165 PBGA 128Kx36 7.5 IS61VF12836A-7.5TQI IS61VF12836A-7.5B2I IS61VF12836A-7.5B3I 100 TQFP 119 PBGA 165 PBGA 256Kx18 6.5 IS61VF25618A-6.5TQI IS61VF25618A-6.5B2I IS61VF25618A-6.5B3I 100 TQFP 119 PBGA 165 PBGA 256Kx18 7.5 IS61VF25618A-7.5TQI IS61VF25618A-7.5B2I IS61VF25618A-7.5B3I 100 TQFP 119 PBGA 165 PBGA Automotive Range: -40°C to +125°C Configuration Access Time Order Part Number 128Kx32 7.5 IS64VF12832A-7.5TQLA3 100 TQFP, Lead-free 128Kx36 7.5 IS64VF12836A-7.5TQA3 100 TQFP 256Kx18 7.5 IS64VF25618A-7.5TQA3 100 TQFP 22 Package Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 08/11/05 ISSI PACKAGING INFORMATION ® Plastic Ball Grid Array Package Code: B (119-pin) φ b (119X) E A 7 6 5 4 D2 D1 e A2 A3 E2 Sym. Min. N0. Leads Max. SEATING PLANE INCHES Min. Max. Notes: 119 A — 2.41 — 0.095 A1 0.50 0.70 0.020 0.028 A2 0.80 1.00 0.032 0.039 A3 1.30 1.70 0.051 0.067 A4 0.56 BSC 0.60 0.90 0.024 0.035 D 21.80 22.20 0.858 0.874 20.32 BSC 0.800 BSC D2 19.40 19.60 0.764 0.772 E 13.80 14.20 0.543 0.559 E1 E2 e 7.62 BSC 11.90 12.10 1.27 BSC 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusion and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. 0.022 BSC b D1 E1 A1 A4 MILLIMETERS 1 A B C D E F G H J K L M N P R T U 30ϒ D 3 2 0.300 BSC 0.469 0.476 0.050 BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 02/12/03 ISSI PACKAGING INFORMATION ® Ball Grid Array Package Code: B (165-pin) BOTTOM VIEW TOP VIEW A1 CORNER 1 2 3 4 A1 CORNER φ b (165X) 5 6 7 8 9 10 11 10 11 9 8 7 6 5 4 3 2 1 A A B B C C D D E E e F F G G D D1 H H J J K K L L M M N N P P R R e E1 E A2 A A1 BGA - 13mm x 15mm MILLIMETERS Sym. Min. N0. Leads Nom. Max. Notes: 1. Controlling dimensions are in millimeters. INCHES Min. 165 Nom. Max. 165 A — — 1.20 — A1 0.25 0.33 0.40 0.010 — 0.047 0.013 0.016 A2 — 0.79 — — 0.031 — D 14.90 15.00 15.10 0.587 0.591 0.594 D1 13.90 14.00 14.10 0.547 0.551 0.555 E 12.90 13.00 13.10 0.508 0.512 0.516 E1 9.90 10.00 10.10 0.390 0.394 0.398 e — 1.00 — — 0.039 — b 0.40 0.45 0.50 0.016 0.018 0.020 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 06/11/03 ISSI PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ D D1 E E1 N L1 L C 1 e SEATING PLANE A2 A b A1 Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max Millimeters Symbol Min Max Ref. Std. No. Leads (N) 100 A — 1.60 — 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. C 0o 7o 0o 7o 128 — 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03 Inches Min Max — 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. ®