Eon EN29LV800T70RTI 8 megabit (1024k x 8-bit / 512k x 16-bit) flash memory boot sector flash memory, cmos 3.0 volt-only Datasheet

EN29LV800
EN29LV800
da0.
8 Megabit (1024K x 8-bit / 512K x 16-bit) Flash Memory
Boot Sector Flash Memory, CMOS 3.0 Volt-only
FEATURES
• Single power supply operation
- Full voltage range: 2.7-3.6 volt read and write
operations for battery-powered applications.
- Regulated voltage range: 3.0-3.6 volt read
and write operations and for compatibility with
high performance 3.3 volt microprocessors.
• Manufactured on 0.28 µm process technology
• High performance
- Access times as fast as 70 ns
• Low power consumption (typical values at 5
MHz)
- 7 mA typical active read current
- 15 mA typical program/erase current
- 1 µA typical standby current (standard access
time to active mode)
• Flexible Sector Architecture:
- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
- One 8 Kword, two 4 Kword, one 16 Kword
and fifteen 32 Kword sectors (word mode)
- Supports full chip erase
- Individual sector erase supported
- Sector protection:
Hardware locking of sectors to prevent
program or erase operations within individual
sectors
Additionally, temporary Sector Group
Unprotect allows code changes in previously
locked sectors.
• High performance program/erase speed
- Byte/Word program time: 8µs typical
- Sector erase time: 500ms typical
• JEDEC Standard program and erase
commands
• JEDEC standard DATA polling and toggle
bits feature
• Single Sector and Chip Erase
• Sector Unprotect Mode
• Embedded Erase and Program Algorithms
• Erase Suspend / Resume modes:
Read or program another Sector during
Erase Suspend Mode
• 0.28 µm double-metal double-poly
triple-well CMOS Flash Technology
• Low Vcc write inhibit < 2.5V
• >100K program/erase endurance cycle
• 48-pin TSOP (Type 1)
• Commercial Temperature Range
GENERAL DESCRIPTION
The EN29LV800 is an 8-Megabit, electrically erasable, read/write non-volatile flash memory,
organized as 1,048,576 bytes or 524,288 words. Any byte can be programmed typically in 10µs.
The EN29LV800 features 3.0V voltage read and write operation, with access times as fast as 55ns to
eliminate the need for WAIT states in high-performance microprocessor systems.
The EN29LV800 has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable (WE)
controls, which eliminate bus contention issues. This device is designed to allow either single Sector
or full chip erase operation, where each Sector can be individually protected against program/erase
operations or temporarily unprotected to erase or program. The device can sustain a minimum of
100K program/erase cycles on each Sector.
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Rev 0.4 Release Date: 2002/01/29
Tel: 408-235-8680
Fax: 408-235-8685
EN29LV800
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard
TSOP
TABLE 1. PIN DESCRIPTION
Pin Name
A0-A18
DQ0-DQ14
DQ15 / A-1
CE#
OE#
RESET#
RY/BY#
WE#
Vcc
Vss
NC
BYTE#
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Function
Addresses
15 Data Inputs/Outputs
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
Chip Enable
Output Enable
Hardware Reset Pin
Ready/Busy Output
Write Enable
Supply Voltage
(2.7-3.6V)
Ground
Not Connected to anything
Byte/Word Mode
A16
BYTE#
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
CE#
A0
FIGURE 1. LOGIC DIAGRAM
EN29LV800
DQ0 – DQ15
(A-1)
A0 - A18
Reset
CE
OE
WE
RY/BY
Byte
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Tel: 408-235-8680
Fax: 408-235-8685
EN29LV800
TABLE 2A. TOP BOOT BLOCK SECTOR ARCHITECTURE
Sect
or
ADDRESS RANGE
SECTOR
SIZE
(Kbytes /
Kwords)
A18
A17
A16
A15
A14
A13
A12
(X16)
(X8)
18
7E000h-7FFFFh
FC000h-FFFFFh
16/8
1
1
1
1
1
1
X
17
7D000h-7DFFFh
FA000h-FBFFFh
8/4
1
1
1
1
1
0
1
16
7C000h-7CFFFh
F8000h-F9FFFh
8/4
1
1
1
1
1
0
0
15
78000h-7BFFFh
F0000h – F7FFFh
32/16
1
1
1
1
0
X
X
14
70000h-77FFFh
E0000h - EFFFFh
64/32
1
1
1
0
X
X
X
13
68000h-6FFFFh
D0000h - DFFFFh
64/32
1
1
0
1
X
X
X
12
60000h-6FFFFh
C0000h - CFFFFh
64/32
1
1
0
0
X
X
X
11
58000h-5FFFFh
B0000h - BFFFFh
64/32
1
0
1
1
X
X
X
10
50000h-57FFFh
A0000h - AFFFFh
64/32
1
0
1
0
X
X
X
9
48000h-4FFFFh
90000h - 9FFFFh
64/32
1
0
0
1
X
X
X
8
40000h-47FFFh
80000h - 8FFFFh
64/32
1
0
0
0
X
X
X
7
38000h-3FFFFh
70000h - 7FFFFh
64/32
0
1
1
1
X
X
X
6
30000h-37FFFh
60000h - 6FFFFh
64/32
0
1
1
0
X
X
X
5
28000h-2FFFFh
50000h – 5FFFFh
64/32
0
1
0
1
X
X
X
4
20000h-27FFFh
40000h – 4FFFFh
64/32
0
1
0
0
X
X
X
3
18000h-1FFFFh
30000h – 3FFFFh
64/32
0
0
1
1
X
X
X
2
10000h-17FFFh
20000h - 2FFFFh
64/32
0
0
1
0
X
X
X
1
08000h-0FFFFh
10000h - 1FFFFh
64/32
0
0
0
1
X
X
X
0
00000h-07FFFh
00000h - 0FFFFh
64/32
0
0
0
0
X
X
X
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Rev 0.4 Release Date: 2002/01/29
Tel: 408-235-8680
Fax: 408-235-8685
EN29LV800
TABLE 2B. BOTTOM BOOT BLOCK SECTOR ARCHITECTURE
Sect
or
ADDRESS RANGE
SECTOR
SIZE
(Kbytes/
Kwords)
A18
A17
A16
A15
A14
A13
A12
(X16)
(X8)
18
78000h-7FFFFh
F0000h – FFFFFh
64/32
1
1
1
1
X
X
X
17
70000h-77FFFh
E0000h – EFFFFh
64/32
1
1
1
0
X
X
X
16
68000h-6FFFFh
D0000h – DFFFFh
64/32
1
1
0
1
X
X
X
15
60000h-67FFFh
C0000h – CFFFFh
64/32
1
1
0
0
X
X
X
14
58000h-5FFFFh
B0000h - BFFFFh
64/32
1
0
1
1
X
X
X
13
50000h-57FFFh
A0000h - AFFFFh
64/32
1
0
1
0
X
X
X
12
48000h-4FFFFh
90000h – 9FFFFh
64/32
1
0
0
1
X
X
X
11
40000h-47FFFh
80000h – 8FFFFh
64/32
1
0
0
0
X
X
X
10
38000h-3FFFFh
70000h –7FFFFh
64/32
0
1
1
1
X
X
X
9
30000h-37FFFh
60000h – 6FFFFh
64/32
0
1
1
0
X
X
X
8
28000h-2FFFFh
50000h – 5FFFFh
64/32
0
1
0
1
X
X
X
7
20000h-27FFFh
40000h – 4FFFFh
64/32
0
1
0
0
X
X
X
6
18000h-1FFFFh
30000h – 3FFFFh
64/32
0
0
1
1
X
X
X
5
10000h-17FFFh
20000h – 2FFFFh
64/32
0
0
1
0
X
X
X
4
08000h-0FFFFh
10000h – 1FFFFh
64/32
0
0
0
1
X
X
X
3
04000h-07FFFh
08000h – 0FFFFh
32/16
0
0
0
0
1
X
X
2
03000h-03FFFh
06000h – 07FFFh
8/4
0
0
0
0
0
1
1
1
02000h-02FFFh
04000h – 05FFFh
8/4
0
0
0
0
0
1
0
0
00000h-01FFFh
00000h – 01FFFh
16/8
0
0
0
0
0
0
X
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Rev 0.4 Release Date: 2002/01/29
Tel: 408-235-8680
Fax: 408-235-8685
EN29LV800
PRODUCT SELECTOR GUIDE
Product Number
EN29LV800
Regulated Voltage Range: Vcc=3.0 – 3.6 V
-70R
Speed Option
Full Voltage Range: Vcc=2.7 – 3.6 V
-90
Max Access Time, ns (tacc)
70
90
Max CE# Access, ns (tce)
70
90
Max OE# Access, ns (toe)
30
35
BLOCK DIAGRAM
RY/BY
Vcc
Vss
DQ0-DQ15 (A-1)
Block Protect Switches
Erase Voltage Generator
Input/Output Buffers
State
Control
WE
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE
OE
Vcc Detector
Timer
Address Latch
STB
STB
Data Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
A0-A18
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Rev 0.4 Release Date: 2002/01/29
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EN29LV800
TABLE 3. OPERATING MODES
8M FLASH USER MODE TABLE
Operation
Read
Write
CMOS Standby
TTL Standby
Output Disable
Hardware Reset
Temporary
Sector Unprotect
CE#
L
L
Vcc ± 0.3V
H
L
X
OE#
L
H
X
X
H
X
WE
#
H
L
X
X
H
X
X
X
X
Reset#
H
H
Vcc ± 0.3V
H
H
L
A0A18
AIN
AIN
X
X
X
X
DQ0-DQ7
DOUT
DIN
High-Z
High-Z
High-Z
High-Z
DQ8-DQ15
Byte#
Byte#
= VIL
= VIH
DOUT
High-Z
DIN
High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
VID
AIN
DIN
DIN
X
Notes:
L=logic low= VIL, H=Logic High= VIH, VID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!),
DIN=Data In, DOUT=Data Out, AIN=Address In
TABLE 4. DEVICE IDENTIFICTION (Autoselect Codes)
8M FLASH MANUFACTURER/DEVICE ID TABLE
Description
Mode
Manufacturer ID:
EON
Device ID
Word
OE
WE
A18
to
A12
A11
to
A10
A9
L
L
H
X
X
VID
L
L
H
X
X
X
SA
(top boot
block)
Byte
L
L
H
Device ID
Word
L
L
H
(bottom boot
block)
Byte
L
L
H
L
L
H
Sector Protection
Verification
2
CE
A7
A6
A5
to
A2
A1
A0
DQ8
to
DQ15
DQ7 to
DQ0
H
X
L
X
L
L
X
1Ch
VID
X
X
L
X
L
H
22h
DAh
X
DAh
X
VID
X
X
L
X
L
H
22h
5Bh
X
5Bh
X
VID
X
X
L
X
H
L
A8
1
01h
X
X
(Protected)
00h
(Unprotected)
Note:
1. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh. A further Manufacturing ID must be
read with A8=H.
2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.
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EN29LV800
USER MODE DEFINITIONS
Word / Byte Configuration
The signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the
byte or word configuration. When the Byte# Pin is set at logic ‘1’, then the device is in word
configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.
On the other hand, if the Byte# Pin is set at logic ‘0’, then the device is in byte configuration, and only
data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14
are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
Standby Mode
The EN29LV800 has a CMOS-compatible standby mode, which reduces the current to < 1µA
(typical). It is placed in CMOS-compatible standby when the CE pin is at VCC ± 0.5. RESET# and
BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode,
which reduces the maximum VCC current to < 1mA. It is placed in TTL-compatible standby when the
CE pin is at VIH. When in standby modes, the outputs are in a high-impedance state independent of
the OE input.
Read Mode
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status data. After completing a programming operation in
the Erase Suspend mode, the system may once again read array data with the same exception. See
“Erase Suspend/Erase Resume Commands” for more additional information.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset Command” additional details.
Output Disable Mode
When the CE or OE pin is at a logic high level (VIH), the output from the EN29LV800 is disabled.
The output pins are placed in a high impedance state.
Auto Select Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection
verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for
programming equipment to automatically match a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can also be accessed in-system through the
command register.
When using programming equipment, the autoselect mode requires VID (10.5 V to 11.5 V) on
address pin A9. Address pins A8, A6, A1, and A0 must be as shown in Autoselect Codes table. In
addition, when verifying sector protection, the sector address must appear on the appropriate highest
order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions
table shows the remaining address bits that are don’t-care. When all necessary bits have been set as
required, the programming equipment may then read the corresponding identifier code on DQ15–
DQ0.
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EN29LV800
To access the autoselect codes in-system; the host system can issue the autoselect command via
the command register, as shown in the Command Definitions table. This method does not require
VID. See “Command Definitions” for details on using the autoselect mode.
Write Mode
Write operations, including programming data and erasing sectors of memory, require the host
system to write a command or command sequence to the device. Write cycles are initiated by
placing the byte or word address on the device’s address inputs while the data to be written is input
on DQ[7:0] in Byte Mode (BYTE# = L) or on DQ[15:0] in Word Mode (BYTE# = H). The host system
must drive the CE# and WE# pins Low and the OE# pin High for a valid write operation to take place.
All addresses are latched on the falling edge of WE# and CE#, whichever happens later. All data is
latched on the rising edge of WE# or CE#, whichever happens first. The system is not required to
provide further controls or timings. The device automatically provides internally generated program /
erase pulses and verifies the programmed /erased cells’ margin. The host system can detect
completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7]
(Data# Polling) and DQ[6] (Toggle) status bits.
The ‘Command Definitions’ section of this document provides details on the specific device
commands implemented in the EN29LV800.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The
hardware sector unprotection feature re-enables both program and erase operations in previously
protected sectors.
There are two methods to enabling this hardware protection circuitry. The first one requires only that
the RESET# pin be at VID and then standard microprocessor timings can be used to enable or
disable this feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings.
When doing Sector Unprotect, all the other sectors should be protected first.
The second method is meant for programming equipment. This method requires VID be applied to
both OE# and A9 pin and non-standard microprocessor timings are used. This method is described
in a separate document called EN29LV800 Supplement, which can be obtained by contacting a
representative of Eon Silicon Devices, Inc.
Temporary Sector Unprotect
Start
This feature allows temporary unprotection of previously protected
sector groups to change data while in-system. The Sector
Unprotect mode is activated by setting the RESET# pin to VID.
During this mode, formerly protected sectors can be programmed
or erased by simply selecting the sector addresses. Once is
removed from the RESET# pin, all the previously protected sectors
are protected again. See accompanying figure and timing
diagrams for more details.
Notes:
1. All protected sectors unprotected.
2. Previously protected sectors protected
again.
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Rev 0.4 Release Date: 2002/01/29
Reset#=VID (note 1)
Perform Erase or Program
Operations
Reset#=VIH
Temporary Sector
Unprotect Completed (note 2)
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EN29LV800
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for tacc + 30ns. The automatic sleep mode is
independent of the CE#, WE# and OE# control signals. Standard address access timings provide
new data when addresses are changed. While in sleep mode, output is latched and always
available to the system. ICC4 in the DC Characteristics table represents the automatic sleep more
current specification.
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EN29LV800
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which
might otherwise be caused by false system level signals during Vcc power up and power down
transitions, or from system noise.
Low VCC Write Inhibit
When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during
Vcc power up and power down. The command register and all internal program/erase circuits are
disabled, and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The
system must provide the proper signals to the control pins to prevent unintentional writes when Vcc is
greater than VLKO.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE , CE or W E do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE = VIL, CE = VIH, or W E = VIH. To initiate a
write cycle, CE and W E must be a logical zero while OE is a logical one. If CE , W E , and OE
are all logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with CE = VIL, W E = VIL and OE = VIH, the device will not accept commands on the rising edge of
WE.
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Rev 0.4 Release Date: 2002/01/29
Tel: 408-235-8680
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EN29LV800
COMMAND DEFINITIONS
The operations of the EN29LV800 are selected by one or more commands written into the
command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program,
Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data
sequences written at specific addresses via the command register. The sequences for the
specified operation are defined in the Command Definitions table (Table 5). Incorrect addresses,
incorrect data values or improper sequences will reset the device to Read Mode.
Table 5. EN29LV800 Command Definitions
Cycles
Bus Cycles
Command
Sequence
Read
Reset
Autoselect
Manufacturer
ID
Device ID
Top Boot
Device ID
Bottom Boot
Sector Protect
Verify
1
1
Word
1
Write Cycle
Add
Data
RA
xxx
4
4
4
Byte
Word
Byte
Word
Unlock Bypass
Byte
Unlock Bypass Program
Unlock Bypass Reset
Word
Chip Erase
Byte
Word
Sector Erase
Byte
Erase Suspend
Erase Resume
AA
AA
3
2
2
6
6
1
1
555
AAA
555
AAA
XXX
XXX
555
AAA
555
AAA
xxx
xxx
4
2AA
555
55
2AA
555
2AA
555
2AA
AA
AAA
4
rd
Write Cycle
Add
Data
555
555
4
3
Write Cycle
Add
Data
AA
555
AAA
555
AAA
nd
th
5
Write Cycle
Add
Data
th
6
th
Write Cycle
Add
Data
Write Cycle
Add
Data
2AA
555
2AA
555
55
555
AAA
10
55
SA
30
RD
F0
AAA
Word
Program
2
555
Byte
Word
Byte
Word
Byte
st
55
55
AA
A0
90
AA
AA
555
AAA
555
AAA
2AA
555
2AA
555
PA
XXX
2AA
555
2AA
555
90
90
555
55
555
AA
90
AAA
90
AAA
55
55
555
AAA
555
AAA
A0
000/
001
000/
001
X01
X02
X01
X02
(SA)
X02
(SA)
X04
7F/
1C
7F/
1C
22DA
DA
225B
5B
XX00
XX01
00
01
PA
PD
20
PD
00
55
55
555
AAA
555
AAA
80
80
555
AAA
555
AAA
AA
AA
B0
30
Address and Data values indicated in hex
RA = Read Address: address of the memory location to be read. This is a read cycle.
RD = Read Data: data read from location RA during Read operation. This is a read cycle.
PA = Program Address: address of the memory location to be programmed. X = Don’t-Care
PD = Program Data: data to be programmed at location PA
SA = Sector Address: address of the Sector to be erased or verified. Address bits A18-A12 uniquely select any Sector.
Reading Array Data
The device is automatically set to reading array data after power up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array
data using the standard read timings, with the only difference in that if it reads at an address within erase
suspended sectors, the device outputs status data. After completing a programming operation in the
Erase Suspend mode, the system may once again read array data with the same exception.
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The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or
while in the autoselect mode. See next section for details on Reset.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’tcare for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data. Once erasure begins, however, the device
ignores reset commands until the operation is complete. The reset command may be written between the
sequence cycles in a program command sequence before programming begins. This resets the device to
reading array data (also applies to programming in Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must be written to return to reading array data (also
applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to
reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices
codes, and determine whether or not a sector is protected. The Command Definitions table shows the
address and data requirements. This is an alternative to the method that requires V ID on address bit A9
and is intended for PROM programmers.
Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.
Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number of
times, without needing another command sequence.
The system must write the reset command to exit the autoselect mode and return to reading array data.
Word / Byte Programming Command
The device may be programmed by byte or by word, depending on the state of the Byte# Pin.
Programming the EN29LV800 is performed by using a four bus-cycle operation (two unlock write
cycles followed by the Program Setup command and Program Data Write cycle). When the program
command is executed, no additional CPU controls or timings are necessary. An internal timer
terminates the program operation automatically. Address is latched on the falling edge of CE or
W E , whichever is last; data is latched on the rising edge of CE or W E , whichever is first.
Programming status may be checked by sampling data on DQ7 ( DATA polling) or on DQ6 (toggle
bit). ). When the program operation is successfully completed, the device returns to read mode and
the user can read the data programmed to the device at that address. Note that data can not be
programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When
programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return
the device to Read mode.
Unlock Bypass
To speed up programming operation, the Unlock Bypass Command may be used. Once this feature
is activated, the shorter two cycle Unlock Bypass Program command can be used instead of the
normal four cycle Program Command to program the device. This mode is exited after issuing the
Unlock Bypass Reset Command. The device powers up with this feature disabled.
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Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required
to provide any controls or timings during these operations. The Command Definitions table shows the
address and data requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.
The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete,
the device returns to reading array data and addresses are no longer latched.
Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in
“AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing
waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by
the address of the sector to be erased, and the sector erase command. The Command Definitions table
shows the address and data requirements for the sector erase command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or
DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the
algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC
Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing
waveforms.
Erase Suspend / Resume Command
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for erasure. This command is valid only during the
sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation
or Embedded Program algorithm. Addresses are don’t-cares when writing the Erase Suspend command.
When the Erase Suspend command is written during a sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation.
After the erase operation has been suspended, the system can read array data from or program data to
any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)
Normal read and write timings and command definitions apply. Reading at any address within erasesuspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status”
for information on these status bits.
After an erase-suspended program operation is complete, the system can once again read array data
within non-suspended sectors. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more
information. The Autoselect command is not supported during Erase Suspend Mode.
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The system must write the Erase Resume command (address bits are don’t-care) to exit the erase
suspend mode and continue the sector erase operation. Further writes of the Resume command are
ignored. Another Erase Suspend command can be written after the device has resumed erasing.
WRITE OPERATION STATUS
DQ7: DATA Polling
The EN29LV800 provides DATA Polling on DQ7 to indicate to the host system the status of the
embedded operations. The DATA Polling feature is active during the Byte Programming, Sector
Erase, Chip Erase, Erase Suspend. (See Table 6)
When the Byte Programming is in progress, an attempt to read the device will produce the
complement of the data last written to DQ7. Upon the completion of the Byte Programming, an
attempt to read the device will produce the true data last written to DQ7. For the Byte Programming,
DATA polling is valid after the rising edge of the fourth WE or C E pulse in the four-cycle sequence.
When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the
DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7
output during the read. For Chip Erase, the DATA polling is valid after the rising edge of the sixth
W E or CE pulse in the six-cycle sequence. For Sector Erase, DATA polling is valid after the last
rising edge of the sector erase W E or C E pulse.
DATA Polling must be performed at any address within a sector that is being programmed or erased
and not a protected sector. Otherwise, DATA polling may give an inaccurate result if the address
used is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the
output enable ( OE ) is low. This means that the device is driving status information on DQ7 at one
instant of time and valid data at the next instant of time. Depending on when the system samples the
DQ7 output, it may read the status of valid data. Even if the device has completed the embedded
operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid
data on DQ0-DQ7 will be read on the subsequent read attempts.
The flowchart for DATA Polling (DQ7) is shown on Flowchart 5. The DATA Polling (DQ7) timing
diagram is shown in Figure 8.
RY/BY: Ready/Busy
The RY/BY is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY status is valid after the rising edge of the final WE pulse in the
command sequence. Since RY/BY is an open-drain output, several RY/BY pins can be tied together
in parallel with a pull-up resistor to Vcc.
In the output is low, signifying Busy, the device is actively erasing or programming. This includes
programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is
ready to read array data (including during the Erase Suspend mode), or is in the standby mode.
DQ6: Toggle Bit I
The EN29LV800 provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the
embedded programming and erase operations. (See Table 6)
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During an embedded Program or Erase operation, successive attempts to read data from the device
at any address (by toggling OE or CE ) will result in DQ6 toggling between “zero” and “one”. Once
the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be
read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the
rising edge of the fourth WE pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is valid
after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after the
last rising edge of the Sector Erase W E pulse.
In Byte Programming, if the sector being written to is protected, DQ6 will toggles for about 2 µs, then
stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all
selected blocks are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read
mode without changing data in all protected blocks.
Toggling either CE or OE will cause DQ6 to toggle.
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is
shown in Figure 9.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase
cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the device has
successfully completed its operation and has returned to read mode, the user must check again to see if
the DQ6 is toggling after detecting a “1” on DQ5.
The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the output on DQ3 can be used to determine whether or
not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.)
When sector erase starts, DQ3 switches from “0” to “1.” This device does not support multiple sector
erase command sequences so it is not very meaningful since it immediately shows as a “1” after the first
30h command. Future devices may support this feature.
DQ2: Erase Toggle Bit II
The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle
Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when
the system reads at addresses within those sectors that have been selected for erasure. (The system may
use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer to Table 5 to compare outputs for DQ2 and
DQ6.
Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm. See
also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing
diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.
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Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, a system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still toggling, the device did not complete the operation
successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read
cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Flowchart 6).
Write Operation Status
Standard
Mode
Erase
Suspend
Mode
Operation
DQ7
DQ6
DQ5
DQ3
DQ2
RY/BY
#
Embedded Program
Algorithm
DQ7#
Toggle
0
N/A
No
toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
1
No
Toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
DQ7#
Toggle
0
N/A
N/A
0
Reading within Erase
Suspended Sector
Reading within Non-Erase
Suspended Sector
Erase-Suspend Program
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Table 6. Status Register Bits
DQ
Name
Logic Level
‘1’
7
DATA
‘0’
POLLING
DQ7
6
TOGGLE
BIT
DQ7
‘-1-0-1-0-1-0-1-’
DQ6
‘-1-1-1-1-1-1-1-‘
5
ERROR BIT
3
ERASE
TIME BIT
2
TOGGLE
BIT
‘1’
‘0’
‘1’
‘0’
‘-1-0-1-0-1-0-1-’
DQ2
Definition
Erase Complete or
erase Sector in Erase
suspend
Erase On-Going
Program Complete or
data of non-erase Sector
during Erase Suspend
Program On-Going
Erase or Program On-going
Read during Erase Suspend
Erase Complete
Program or Erase Error
Program or Erase On-going
Erase operation start
Erase timeout period on-going
Chip Erase, Erase or Erase
suspend on currently
addressed
Sector. (When DQ5=1, Erase
Error due to currently
addressed Sector. Program
during Erase Suspend ongoing at current address
Erase Suspend read on
non Erase Suspend Sector
Notes:
DQ7 DATA Polling: indicates the P/E C status check during Program or Erase, and on completion before checking bits
DQ5 for Program or Erase Success.
DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged.
Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.
DQ5 Error Bit: set to “1” if failure in programming or erase
DQ3 Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).
DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector.
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EMBEDDED ALGORITHMS
Flowchart 1. Embedded Program
START
Write Program
Command Sequence
(shown below)
Data Poll Device
Verify Data?
Increment
Address
Last
No
Address?
Yes
Programming Done
Flowchart 2. Embedded Program Command Sequence
See the Command Definitions section for more information on WORD mode.
555H / AAH
2AAH / 55H
555H / A0H
PROGRAM ADDRESS / PROGRAM DATA
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Flowchart 3. Embedded Erase
START
Write Erase
Command Sequence
Data Poll from
System or Toggle Bit
successfully
completed
Data =FFh?
No
Yes
Erase Done
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Flowchart 4. Embedded Erase Command Sequence
See the Command Definitions section for more information on WORD mode.
Chip Erase
Sector Erase
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/80H
555H/80H
555H/AAH
555H/AAH
2AAH/55H
2AAH/55H
555H/10H
Sector Address/30H
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Flowchart 5. DATA Polling
Algorithm
Start
Read Data
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read Data (1)
Notes:
(1) This second read is necessary in case the
first read was done at the exact instant when
the status data was in transition.
Yes
DQ7 = Data?
No
Fail
Pass
Start
Flowchart 6. Toggle Bit Algorithm
Read Data twice
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Data twice (2)
Notes:
(1) This second set of reads is necessary in case
the first set of reads was done at the exact
instant when the status data was in transition.
No
DQ6 = Toggle?
Yes
Fail
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Pass
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Flowchart 7a. In-System Sector Protect Flowchart
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
No
Temporary Sector
Unprotect Mode
First Write
Cycle =
60h?
Yes
Set up sector
address
Sector Protect: Write 60h
to sector addr with
A6 = 0, A1 = 1, A0 = 0
Wait 150 µs
Verify Sector Protect:
Write 40h to sector
address with
A6 = 0, A1 = 1, A0 = 0
Increment
PLSCNT
Reset
PLSCNT = 1
Wait 0.4 µs
Read from sector
address with
A6 = 0, A1 = 1, A0
No
PLSCNT = 25?
No
Data = 01h?
Yes
Yes
Device failed
Protect another
sector?
Yes
No
Remove VID
from RESET#
Write reset
command
Sector Protect
Algorithm
Sector Protect
complete
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Flowchart 7b. In-System Sector Unprotect Flowchart
START
PLSCNT = 1
Protect all sectors:
The indicated
portion of the sector
protect algorithm
must be performed
for all unprotected
sectors prior to
issuing the first
sector unprotect
address (see
Diagram 7a.)
RESET# = VID
Wait 1 µS
No
Temporary Sector
Unprotect Mode
First Write
Cycle = 60h?
Yes
No
All sectors
protected?
Yes
Set up first sector
address
Sector Unprotect: Write 60H to
sector address with A6 = 1,
A1 = 1, A0 = 0
Wait 15 ms
Increment
PLSCNT
Verify Sector Unprotect:
Write 40h to sector address
with A6 = 1, A1 = 1, A0 =0
Wait 0.4 µS
No
PLSCCNT =
1000?
Sector
Unprotect
Algorithm
Yes
Device failed
Read from sector address with
A6 = 1, A1 = 1, A0 = 0
No
Set up next sector
address
Data = 00h?
Yes
Last sector
verified?
No
Yes
Remove VID from
RESET#
Write reset
command
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Table 7. DC Characteristics
(Ta = 0°C to 70°C or - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
Parameter
Test Conditions
ILI
Input Leakage Current
ILO
Output Leakage Current
Min
Max
Unit
0V≤ VIN ≤ Vcc
±5
µA
0V≤ VOUT ≤ Vcc
±5
µA
8
16
mA
6
18
mA
7
20
mA
0.4
1.0
mA
1
5.0
µA
25
50
mA
1
5.0
µA
0.8
Vcc ±
0.3
0.45
V
Supply Current (read) TTL
ICC1
(read) CMOS Byte
CE# = VIL; OE# = VIH;
f = 5MHz
(read) CMOS Word
Supply Current (Standby - TTL)
ICC2
Supply Current (Standby - CMOS)
ICC3
Supply Current (Program or Erase)
ICC4
Automatic Sleep Mode
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
CE# = VIH,
BYTE# = RESET# =
Vcc ± 0.3V
(Note 1)
CE# = BYTE# =
RESET# = Vcc ± 0.3V
(Note 1)
Byte program, Sector or
Chip Erase in progress
VIH = Vcc ± 0.3 V
VIL = Vss ± 0.3 V
-0.5
0.7 x
Vcc
IOL = 4.0 mA
Output High Voltage TTL
IOH = -2.0 mA
Output High Voltage CMOS
IOH = -100 µA,
VOH
VID
A9 Voltage (Electronic Signature)
IID
A9 Current (Electronic Signature)
VLKO
Supply voltage (Erase and
Program lock-out)
0.85 x
Vcc
Vcc 0.4V
10.5
A9 = VID
2.3
Typ
V
V
V
V
11.5
V
100
µA
2.5
V
Notes
1. BYTE# pin can also be GND ± 0.3V. BYTE# and RESET# pin input buffers are always enabled so that
they draw power if not at full CMOS supply voltages.
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Test Conditions
3.3 V
2.7 kΩ
Device Under Test
CL
6.2 kΩ
Note: Diodes are IN3064 or equivalent
Test Specifications
Test Conditions
Output Load
Output Load Capacitance, CL
-55
-70
-90
Unit
100
pF
1 TTL Gate
30
100
Input Rise and Fall times
5
5
5
ns
Input Pulse Levels
Input timing measurement
reference levels
Output timing measurement
reference levels
0.0-3.0
0.0-3.0
0.0-3.0
V
1.5
1.5
1.5
V
1.5
1.5
1.5
V
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AC CHARACTERISTICS
Hardware Reset (Reset#)
Parameter
Std
tREADY
tREADY
tRP
tRH
Description
Reset# Pin Low to Read or Write
Embedded Algorithms
Reset# Pin Low to Read or Write
Non Embedded Algorithms
Reset# Pulse Width
Reset# High Time Before Read
Test
Setup
Speed options
-70R
-90
Unit
Max
20
µs
Max
500
nS
Min
Min
500
50
nS
nS
Reset# Timings
RY/BY#
0V
CE#
OE#
tRH
RESET#
tRP
tREADY
Reset Timings NOT During Automatic Algorithms
RY/BY#
tREADY
CE#
OE#
RESET#
tRP
tRH
Reset Timings During Automatic Algorithms
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AC CHARACTERISTICS
Word / Byte Configuration (Byte#)
Speed
Std
Parameter
tBCS
tCBH
tRBH
Description
Byte# to CE# switching setup time
CE# to Byte# switching hold time
RY/BY# to Byte# switching hold time
-70R
0
0
0
Min
Min
Min
Unit
-90
0
0
0
ns
ns
ns
CE
OE
Byte
tBCS
tCBH
Byte timings for Read Operations
CE
WE
Byte
tBCS
tRBH
RY/BY
Byte timings for Write Operations
Note: Switching BYTE# pin not allowed during embedded operations
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Table 8. AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbols
JEDEC
Standard
Speed Options
Test
Setup
Description
Min
-70R
70
-90
90
Unit
ns
Max
70
90
ns
Max
70
90
ns
tAVAV
tRC
Read Cycle Time
tAVQV
tACC
Address to Output Delay
CE = VIL
OE = VIL
tELQV
tCE
Chip Enable To Output Delay
OE = VIL
tGLQV
tOE
Output Enable to Output Delay
Max
30
35
ns
tEHQZ
tDF
Chip Enable to Output High Z
Max
20
20
ns
tGHQZ
tDF
Output Enable to Output High Z
Max
20
20
ns
tAXQX
tOH
Output Hold Time from
Min
0
0
ns
Addresses, CE or OE ,
whichever occurs first
Notes:
For - 50
Vcc = 3.0V ± 5%
Output Load : 1 TTL gate and 30pF
Input Rise and Fall Times: 5ns
Input Rise Levels: 0.0 V to Vcc
Timing Measurement Reference Level, Input and Output: 1.5 V
For all others:
Vcc = 3.0V ± 5%
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 5 ns
Input Pulse Levels: 0.0 V to Vcc
Timing Measurement Reference Level, Input and Output: 1.5 V
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
Output Valid
Outputs
HIGH Z
Reset#
RY/BY#
0V
Figure 5. AC Waveforms for READ Operations
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EN29LV800
Table 9. AC CHARACTERISTICS
Write (Erase/Program) Operations
Parameter
Symbols
Speed Options
JEDEC
Standard
Description
tAVAV
tWC
Write Cycle Time
tAVWL
tAS
tWLAX
-70R
-90
Unit
Min
70
90
ns
Address Setup Time
Min
0
0
ns
tAH
Address Hold Time
Min
45
45
ns
tDVWH
tDS
Data Setup Time
Min
30
45
ns
tWHDX
tDH
Data Hold Time
Min
0
0
ns
tOES
Output Enable Setup Time
Min
0
0
ns
MIn
0
0
ns
Min
10
10
ns
Min
0
0
ns
tOEH
Read
Toggle and
DATA Polling
Read Recovery Time before
Output Enable
Hold Time
tGHWL
tGHWL
tELWL
tCS
CE SetupTime
Min
0
0
ns
tWHEH
tCH
CE Hold Time
Min
0
0
ns
tWLWH
tWP
Write Pulse Width
Min
35
45
ns
tWHDL
tWPH
Write Pulse Width High
Min
20
20
ns
tWHWH1
tWHWH1
Programming Operation
(Word AND Byte Mode)
Typ
8
8
µs
Max
200
200
µs
tWHWH2
Write ( OE High to W E Low)
tWHWH2
Sector Erase Operation
Typ
0.5
0.5
s
tVCS
Vcc Setup Time
Min
50
50
µs
tVIDR
Rise Time to VID
Min
500
500
ns
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EN29LV800
Table 10. AC CHARACTERISTICS
Write (Erase/Program) Operations
Alternate CE Controlled Writes
Parameter
Symbols
Speed Options
JEDEC
Standard
Description
tAVAV
tWC
Write Cycle Time
tAVEL
tAS
tELAX
-70R
-90
Unit
Min
70
90
ns
Address Setup Time
Min
0
0
ns
tAH
Address Hold Time
Min
45
45
ns
tDVEH
tDS
Data Setup Time
Min
30
45
ns
tEHDX
tDH
Data Hold Time
Min
0
0
ns
tOES
Output Enable Setup Time
Min
0
0
ns
tOEH
Output Enable
0
0
0
ns
10
10
10
ns
Min
0
0
ns
Min
0
0
ns
Min
0
0
ns
Min
35
45
ns
Min
20
20
ns
Typ
8
8
µs
Max
200
200
µs
Typ
0.5
0.5
s
Min
50
50
µs
Min
500
500
ns
Read
Hold Time
Toggle and
Data Polling
Read Recovery Time before
Write ( OE High to CE Low)
tGHEL
tGHEL
tWLEL
tWS
W E SetupTime
tEHWH
tWH
W E Hold Time
tELEH
tCP
Write Pulse Width
tEHEL
tCPH
Write Pulse Width High
tWHWH1 tWHWH1
tWHWH2 tWHWH2
tVCS
tVIDR
Programming Operation
(byte AND word mode)
Sector Erase Operation
Vcc Setup Time
Rise Time to VID
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EN29LV800
Table 11. ERASE AND PROGRAMMING PERFORMANCE
Typ
Limits
Max
Unit
Sector Erase Time
0.5
2
sec
Chip Erase Time
8
Byte Programming Time
8
200
µs
Word Programming Time
8
200
µs
Byte
6.2
18
Word
3.1
9
Parameter
Chip Programming
Time
Erase/Program Endurance
Comments
Excludes 00H programming prior
to erasure
sec
Excludes system level overhead
sec
100K
Minimum 100K cycles
(preliminary)
cycles
Table 12. LATCH UP CHARACTERISTICS
Parameter Description
Input voltage with respect to V ss on all pins except I/O pins
(including A9, Reset and OE )
Min
Max
-1.0 V
12.0 V
Input voltage with respect to V ss on all I/O Pins
-1.0 V
Vcc + 1.0 V
Vcc Current
-100 mA
100 mA
Note : These are latch up characteristics and the device should never be put under
these conditions. Refer to Absolute Maximum ratings for the actual operating limits.
Table 14. 32-PIN TSOP PIN CAPACITANCE @ 25°C, 1.0MHz
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
Table 15. DATA RETENTION
Parameter Description
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
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AC CHARACTERISTICS
Figure 6. AC Waveforms for Chip/Sector Erase Operations Timings
Erase Command Sequence (last 2 cycles)
tWC
Addresses
tAS
0x2AA
Read Status Data (last two cycles)
tAH
SA
VA
VA
0x555 for chip
erase
CE#
tGHWL
tCH
OE#
tWP
WE#
tCS
tWPH
tWHWH2 or tWHWH3
0x55
Data
tDS
0x30
tDH
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout=true data at read address.
2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command
sequence.
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EN29LV800
Figure 7. Program Operation Timings
Program Command Sequence (last 2 cycles)
tWC
Addresses
tAS
0x555
Program Command Sequence (last 2 cycles)
tAH
PA
PA
PA
CE#
tGHWL
tWP
OE#
WE#
tCH
tWPH
tWHWH1
tCS
Data
PD
OxA0
Status
DOUT
tDS
tDH
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address.
2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid
command sequence.
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EN29LV800
Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm
Operations
tRC
Addresses
VA
VA
VA
tACC
tCH
tCE
CE#
tOE
OE#
tOEH
tDF
WE#
tOH
DQ[7]
Complement
DQ[6:0]
Complement
Status
Data
Status Data
True
Valid Data
True
Valid Data
tBUSY
RY/BY#
Notes:
1. VA=Valid Address for reading Data# Polling status data
2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.
Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm
Operations
tRC
Addresses
VA
VA
VA
VA
tACC
tCH
tCE
CE#
tOE
OE#
tOEH
WE#
tDF
tOH
DQ6, DQ2
tBUSY
Valid Status
Valid Status
Valid Status
(first read)
(second read)
(stops toggling)
Valid Data
RY/BY#
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EN29LV800
Figure 10. Alternate CE# Controlled Write Operation Timings
0x555 for Program
0x2AA for Erase
PA for Program
SA for Sector Erase
0x555 for Chip Erase
Addresses
VA
tWC
tAS
tAH
WE#
tWH
tGHEL
OE#
tCP
tWS
tCPH
tCWHWH1 / tCWHWH2 / tCWHWH3
CE#
tDS
tBUSY
tDH
Status
Data
0xA0 for Program
0x55 for Erase
DOUT
PD for Program
0x30 for Sector Erase
0x10 for Chip Erase
RY/BY#
tRH
Reset#
Notes:
PA = address of the memory location to be programmed.
PD = data to be programmed at byte address.
VA = Valid Address for reading program or erase status
Dout = array data read at VA
Shown above are the last two cycles of the program or erase command sequence and the last status read
cycle
Reset# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command
sequence.
Figure 11. DQ2 vs. DQ6
Enter
Embedded
Erase
WE#
Enter Erase
Suspend
Program
Erase
Suspend
Erase
Enter
Suspend
Read
Erase
Resume
Enter
Suspend
Program
Erase
Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
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EN29LV800
Figure 12. Sector Protect/Unprotect Timing Diagram
VID
RESET#
Vcc
0V
0V
tVIDR
tVIDR
SA,
A6,A1,A0
Data
60h
Valid
Valid
Valid
60h
40h
Status
Sector Protect/Unprotect
Verify
CE#
>0.4µS
WE#
>1µS
Sector Protect: 150 uS
Sector Unprotect: 15 mS
OE#
Notes:
Use standard microprocessor timings for this device for read and write cycles.
For Sector Protect, use A6=0, A1=1, A0=0. For Sector Unprotect, use A6=1, A1=1, A0=0.
Temporary Sector Unprotect
Parameter
Std
tVIDR
tRSP
Speed Option
-70R
-90
Unit
Min
500
Ns
Min
4
µs
Description
VID Rise and Fall Time
RESET# Setup Time for Temporary
Sector Unprotect
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Figure 13. Temporary Sector Unprotect Timing Diagram
VID
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
CE#
WE#
tRSP
RY/BY#
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FIGURE 12. TSOP
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ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
Storage Temperature
-65 to +125
°C
Plastic Packages
-65 to +125
°C
-55 to +125
°C
200
mA
-0.5 to +11.5
V
-0.5 to Vcc+0.5
V
-0.5 to +4.0
V
Ambient Temperature
With Power Applied
Output Short Circuit Current
1
A9, OE#, Reset#
Voltage with
Respect to Ground
All other pins
2
3
Vcc
Notes:
1.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
2.
Minimum DC input voltage on A9, OE#, RESET# pins is –0.5V. During voltage transitions, A9, OE#, RESET# pins may
undershoot Vss to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure below. Maximum DC
input voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns.
3.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods
of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc +
0.5 V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below.
4.
Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress
rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the
device to the maximum rating values for extended periods of time may adversely affect the device reliability.
RECOMMENDED OPERATING RANGES1
Parameter
Ambient Operating Temperature
Commercial Devices
Industrial Devices
Operating Supply Voltage
Vcc
Value
Unit
0 to 70
-40 to 85
°C
Regulated: 3.0 to 3.6
V
Full: 2.7 to 3.6
1.
Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc
+1.5V
Maximum Negative Overshoot
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Waveform
Waveform
ORDERING INFORMATION
EN29LV800
T
70R
T
I
P
PACKAGING CONTENT
(Blank) = Conventional
P = Pb Free
TEMPERATURE RANGE
(Blank) = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
PACKAGE
T = 48-pin TSOP
S = Small Outline Package
SPEED
70R = 70ns (Regulated)
90 = 90ns
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
BASE PART NUMBER
EN = EON Silicon Devices
29F = FLASH, 3V Read Program Erase
800 = 8 Megabit (1024K x 8 / 512 x 16)
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Revisions List
0.1 (2001.07.03):
Preliminary version
0.2 (2001.07.05):
“block” changed to “sector”
LACTHUP >= 200mA line removed from first page
Chip erase and Sector Erase command descriptions modified.
DQ7,DQ5,DQ3 status polling descriptions modified.
Table 12 Latchup characteristics modified
Changed P/E endurance to 100K everywhere
Changed Absolute Maximum Ratings
Unlock Bypass stuff added
0.3 (2001.08.23):
On Table 7. DC Characteristics, changed:
“Vcc=2.7-3.6V +/- 10%” to “Vcc=2.7-3.6V”
VOH(TTL) Min “2.4” changed to “0.85 x Vcc”
Table 8: input/output levels changed in notes.
0.4 (2001.09.26):
Added in the Automatic Sleep Mode in User Mode Definitions section.
Re-Wrote the Write Mode in User Mode Definitions section.
Corrected the address range (A0 – A18) in Table 1.
Corrected the address pin (A18) in the TSOP Connection Diagram.
Modified the Program/Erase time in Table 11 – Program/Erase Performance.
Eliminated the max time for tWHWH2 and updated tWHWH1 and tWHWH2 in Tables
9 and 10 -- Program/Erase AC Characteristics.
Eliminated tWHWH3 in Table 10 - Program/Erase AC Characteristics.
Eliminated the chip-erase time from the Features section.
Modified Test Specification Table for Read
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Modified the notes for Table 8 – AC Characteristics for Read Operation
Eliminated speed option –120 from Byte# Configuration Table.
Added A8 to the description of Auto Select Identification Mode.
Added notes for Flowcharts 2 and 4.
Changed Vcc from 7.0V to 4.0V in the Absolute Max Rating.
Changed address location of Manufacture and Device ID in Table 5 –
Command Definitions.
0.5 (2002.01.10)
Removed –55ns speed option
Added ‘Regulated’ functionality statement.
Updated all speed tables to reflect changes above.
0.6 (2002.01.29)
Updated Ordering information to add packaging type.
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