Cypress CY8CLED16 Ez-colorâ ¢ hb-led controller Datasheet

CY8CLED16
EZ-Color™ HB-LED Controller
Features
■
HB LED Controller
❐ Configurable Dimmers Support up to 16
Independent LED Channels
❐ 8 to 32 Bits of Resolution per Channel
❐ Dynamic Reconfiguration Enables LED Controller Plus Other
Features: CapSense, Battery Charging, and Motor Control
■
Visual Embedded Design
❐ LED-Based Drivers
• Binning compensation
• Temperature Feedback
• Optical Feedback
• DMX512
■
PrISM Modulation Technology
❐ Reduces Radiated EMI
❐ Reduces Low Frequency Blinking
■
Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 3.0 to 5.25V Operating Voltage
❐ Operating Voltages Down to 1.0V using
On-Chip Switch Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■
■
Advanced Peripherals (PSoC® Blocks)
❐ 16 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• Up to 4 Full-Duplex UARTs
• Multiple SPI Masters or Slaves
• Connectable to all GPIO Pins
❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Complex Peripherals by Combining Blocks
■
Flexible On-Chip Memory
❐ 32K Flash Program Storage 50,000 Erase/Write Cycles
❐ 2K SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■
Complete Development Tools
❐ Free Development Software
• PSoC Designer™
❐ Full-Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 KBytes Trace Memory
Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Source on all GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to Eight Analog Inputs on GPIO
❐ Configurable Interrupt on all GPIO
Cypress Semiconductor Corporation
Document Number: 001-13105 Rev. *C
•
198 Champion Court
EZ-Color HB LED Controller
Preliminary Data Sheet
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 15, 2010
[+] Feedback
CY8CLED16
Logic Block Diagram
Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Analog
Drivers
SYSTEM BUS
Global Digital Interconnect
SRAM
2K
Global Analog Interconnect
SROM
Flash 32K
PSoC CORE
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Digital
Block
Array
Digital
Clocks
Two
Multiply
Accums.
Analog
Block
Array
POR and LVD
Decimator
I 2C
System Resets
Analog
Input
Muxing
Internal
Voltage
Ref.
Switch
Mode
Pump
SYSTEM RESOURCES
Document Number: 001-13105 Rev. *C
Page 2 of 43
[+] Feedback
CY8CLED16
Contents
EZ-Color™ Functional Overview....................................... 4
Target Applications........................................................ 4
The PSoC Core ............................................................. 4
The Digital System ........................................................ 4
The Analog System ....................................................... 5
Additional System Resources ....................................... 6
EZ-Color Device Characteristics ................................... 6
Getting Started.................................................................... 6
Application Notes .......................................................... 6
Development Kits .......................................................... 6
Training ......................................................................... 6
Cypros Consultants ....................................................... 6
Solutions Library............................................................ 6
Technical Support ......................................................... 6
Development Tools ............................................................ 7
PSoC Designer Software Subsystems.......................... 7
In-Circuit Emulator......................................................... 7
Document Conventions ..................................................... 8
Acronyms Used ............................................................. 8
Units of Measure ........................................................... 8
Numeric Naming............................................................ 8
Pin Information ................................................................... 9
Pinouts .......................................................................... 9
Register Reference........................................................... 12
Register Conventions .................................................. 12
Register Mapping Tables ............................................ 12
Document Number: 001-13105 Rev. *C
Electrical Specifications ................................................... 15
Absolute Maximum Ratings.......................................... 16
Operating Temperature ................................................ 16
DC Electrical Characteristics........................................ 17
AC Electrical Characteristics ........................................ 27
Packaging Information...................................................... 36
Packaging Dimensions................................................. 36
Thermal Impedances.................................................... 38
Capacitance on Crystal Pins ........................................ 38
Solder Reflow Peak Temperature ................................ 38
Development Tool Selection ............................................ 39
Software ........................................................................39
Evaluation Tools........................................................... 39
Device Programmers.................................................... 40
Accessories (Emulation and Programming) ................. 40
Third Party Tools .......................................................... 40
Build a PSoC Emulator into Your Board....................... 40
Ordering Information......................................................... 41
Key Device Features .................................................... 41
Ordering Code Definitions ............................................ 41
Document History Page .................................................... 42
Sales, Solutions, and Legal Information ......................... 43
Worldwide Sales and Design Support.......................... 43
Products ....................................................................... 43
Page 3 of 43
[+] Feedback
CY8CLED16
EZ-Color™ Functional Overview
Cypress's EZ-Color family of devices offers the ideal control
solution for High Brightness LED applications requiring intelligent dimming control. EZ-Color devices combine the power and
flexibility of PSoC (Programmable System-on-Chip); with
Cypress's PrISM (precise illumination signal modulation)
modulation technology providing lighting designers a fully
customizable and integrated lighting solution platform.
The EZ-Color family supports a range of independent LED
channels from 4 channels at 32 bits of resolution each, up to 16
channels at 8 bits of resolution each. This enables lighting
designers the flexibility to choose the LED array size and color
quality. PSoC Designer software, with lighting specific drivers,
can significantly cut development time and simplify implementation of fixed color points through temperature, optical, and LED
binning compensation. EZ-Color's virtually limitless analog and
digital customization allow for simple integration of features in
addition to intelligent lighting, such as Battery Charging, Image
Stabilization, and Motor Control during the development
process. These features, along with Cypress' best-in-class
quality and design support, make EZ-Color the ideal choice for
intelligent HB LED control applications.
to 2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz ILO (internal low speed oscillator) is provided for the
Sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
Real Time Clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a System
Resource), provide the flexibility to integrate almost any timing
requirement into the EZ-Color device.
EZ-Color GPIOs provide connection to the CPU, digital and
analog resources of the device. Each pin’s drive mode may be
selected from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
The Digital System
The Digital System is composed of 16 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8, 16, 24, and 32-bit peripherals, which
are called user module references. Digital peripheral configurations include those listed below.
Target Applications
■
PrISM (8 to 32 bit)
■
LCD Backlight
■
PWMs (8 to 32 bit)
■
Large Signs
■
PWMs with Dead band (8 to 32 bit)
■
General Lighting
■
Counters (8 to 32 bit)
■
Architectural Lighting
■
Timers (8 to 32 bit)
■
Camera/Cell Phone Flash
■
UART 8 bit with selectable parity (up to 4)
■
Flashlights
■
SPI master and slave (up to 4 each)
The PSoC Core
■
I2C slave and multi-master (1 available as a System Resource)
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
GPIO (General Purpose I/O).
■
Cyclical Redundancy Checker/Generator (8 to 32 bit)
■
IrDA (up to 4)
■
Generators (8 to 32 bit)
The M8C CPU core is a powerful processor with speeds up to 48
MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 25 vectors,
to simplify programming of real time embedded events. Program
execution is timed and protected using the included Sleep and
Watch Dog Timers (WDT).
Memory encompasses 32 KB of Flash for program storage, 2 KB
of SRAM for data storage, and up to 2 KB of EEPROM emulated
using the Flash. Program Flash utilizes four protection levels on
blocks of 64 bytes, allowing customized software IP protection.
The EZ-Color family incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate
Document Number: 001-13105 Rev. *C
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by EZ-Color device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in Table 1, “EZ-Color Device Characteristics,” on page 6.
Page 4 of 43
[+] Feedback
CY8CLED16
Figure 1. Digital System Block Diagram
Port 5
Port 6
Port 3
Port 4
Port 1
Port 2
To System Bus
Digital Clocks
From Core
DCB02
4
DCB03
4
8
8
DBB10
DBB11
DCB12
4
DCB13
4
Row 2
DBB20
DBB21
DCB22
4
DCB23
4
Row Output
Configuration
Row Input
Configuration
Row 1
Correlators
■
Peak Detectors
■
Many other topologies possible
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
8
Row Output
Configuration
Row Input
Configuration
8
■
Figure 2. Analog System Block Diagram
Row Output
Configuration
Row Input
Configuration
Digital PSoC Block Array
DBB01
Modulators
Analog blocks are provided in columns of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
blocks, as shown in the figure below.
DIGITAL SYSTEM
DBB00
■
Port 0
To Analog
System
Row 0
DTMF Dialer
AGNDIn RefIn
Port 7
■
P2[3]
P2[6]
P2[4]
P2[1]
P2[2]
DBB30
DBB31
DCB32
4
DCB33
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
Row Output
Configuration
Row Input
Configuration
P2[0]
Row 3
Array Input Configuration
GOE[7:0]
GOO[7:0]
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
The Analog System
The Analog System is composed of 12 configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common EZ-Color analog functions (most
available as user modules) are listed below.
■
Analog-to-digital converters (up to 4, with 6- to 14-bit resolution,
selectable as Incremental, Delta Sigma, and SAR)
■
Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch)
■
Amplifiers (up to 4, with selectable gain to 48x)
■
Instrumentation amplifiers (up to 2, with selectable gain to 93x)
■
Comparators (up to 4, with 16 selectable thresholds)
■
DACs (up to 4, with 6- to 9-bit resolution)
■
Multiplying DACs (up to 4, with 6- to 9-bit resolution)
■
High current output drivers (four with 40 mA drive as a Core
Resource)
■
1.3V reference (as a System Resource)
Document Number: 001-13105 Rev. *C
Block Array
ACB00
ACB01
ACB02
ACB03
ASC10
ASD11
ASC12
ASD13
ASD20
ASC21
ASD22
ASC23
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Page 5 of 43
[+] Feedback
CY8CLED16
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Resources include a multiplier, decimator, switch mode pump,
low voltage detection, and power on reset. Statements
describing the merits of each system resource are presented
below.
■
■
■
The decimator provides a custom hardware filter for digital
signal, processing applications including the creation of Delta
Sigma ADCs.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
■
An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
Multiply accumulate (MAC) provides fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
■
An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
EZ-Color Device Characteristics
Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data
sheet is shown in the highlighted row of the table.
Analog
Blocks
SRAM
Size
1
4
8
0
2
4
256 Bytes
4K
No
56
1
4
48
2
2
6
1K
16K
Yes
Flash
Size
Digital
Blocks
16
4
Analog
Columns
Digital
Rows
2
CY8CLED04
Analog
Outputs
Digital
I/O
CY8CLED02
Part Number
Analog
Inputs
LED
Channels
CapSense
Table 1. EZ-Color Device Characteristics
CY8CLED08
8
44
2
8
12
4
4
12
256 Bytes
16K
No
CY8CLED16
16
44
4
16
12
4
4
12
2K
32K
No
Getting Started
The quickest way to understand the device is to read this data
sheet and then use the PSoC Designer Integrated Development
Environment (IDE). This data sheet is an overview of the
EZ-Color integrated circuit and presents specific pin, register,
and electrical specifications. For in depth information, along with
detailed programming information, see the PSoC Programmable
System-on-Chip Technical Reference Manual.
For up-to-date ordering, packaging, and electrical specification
information, see the latest device data sheets on the web at
http://www.cypress.com/ez-color.
Application Notes
A long list of application notes will assist you in every aspect of
your design effort. To view the application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Documentation tab.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com/store, click Lighting & Power Control to
view a current list of available items.
Document Number: 001-13105 Rev. *C
Training
Free technical training (on demand, webinars, and workshops)
is available online at www.cypress.com/training. The training
covers a wide variety of topics and skill levels to assist you in
your designs.
Cypros Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed designs. To contact or become a PSoC
Consultant go to www.cypress.com/cypros.
Solutions Library
Visit our growing library of solution focused designs at
www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files
that enable you to complete your designs quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at www.cypress.com/support. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Page 6 of 43
[+] Feedback
CY8CLED16
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
development
environment
for
the
Programmable
System-on-Chip (PSoC) devices. The PSoC Designer IDE runs
on Windows XP or Windows Vista.
This system provides design database management by project,
an integrated debugger with In-Circuit Emulator, in-system
programming support, and built-in support for third-party
assemblers and C compilers.
PSoC Designer also supports C language compilers developed
specifically for the devices in the PSoC family.
PSoC Designer Software Subsystems
System Level View
A drag-and-drop visual embedded system design environment
based on PSoC Designer. In the system level view you create a
model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state
based upon any or all other system devices. Based upon the
design, PSoC Designer automatically selects one or more PSoC
Mixed-Signal Controllers that match your system requirements.
PSoC Designer generates all embedded code, then compiles
and links it into a programming file for a specific PSoC device.
Chip Level View
The chip-level view is a more traditional Integrated Development
Environment (IDE) based on PSoC Designer. Choose a base
device to work with and then select different onboard analog and
digital components called user modules that use the PSoC
blocks. Examples of user modules are ADCs, DACs, Amplifiers,
and Filters. Configure the user modules for your chosen
application and connect them to each other and to the proper
pins. Then generate your project. This prepopulates your project
with APIs and libraries that you can use to program your
application.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
Hybrid Designs
You can begin in the system-level view, allow it to choose and
configure your user modules, routing, and generate code, then
switch to the chip-level view to gain complete control over
on-chip resources. All views of the project share a common code
editor, builder, and common debug, emulation, and programming
tools.
Document Number: 001-13105 Rev. *C
Code Generation Tools
PSoC Designer supports multiple third party C compilers and
assemblers. The code generation tools work seamlessly within
the PSoC Designer interface and have been tested with a full
range of debugging tools. The choice is yours.
Assemblers. The assemblers allow assembly code to merge
seamlessly with C code. Link libraries automatically use absolute
addressing or are compiled in relative mode, and linked with
other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all the features of C tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing you to test the program in a physical
system while providing an internal view of the PSoC device.
Debugger commands allow the designer to read and program
and read and write data memory, read and write I/O registers,
read and write CPU registers, set and clear breakpoints, and
provide program run, halt, and step control. The debugger also
allows the designer to create a trace buffer of registers and
memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality In-Circuit Emulator (ICE) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed (24
MHz) operation.
Page 7 of 43
[+] Feedback
CY8CLED16
Document Conventions
Units of Measure
Acronyms Used
A units of measure table is located in the Electrical Specifications
section. Table 7 on page 15 lists all the abbreviations used to
measure the devices.
The following table lists the acronyms that are used in this
document.
Acronym
Description
AC
alternating current
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CT
continuous time
DAC
digital-to-analog converter
DC
direct current
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
FSR
full scale range
GPIO
general purpose I/O
GUI
graphical user interface
HBM
human body model
ICE
in-circuit emulator
ILO
internal low speed oscillator
IMO
internal main oscillator
I/O
input/output
IPOR
imprecise power on reset
LSb
least-significant bit
LVD
low voltage detect
MSb
most-significant bit
PC
program counter
PLL
phase-locked loop
POR
power on reset
PPOR
precision power on reset
PSoC®
Programmable System-on-Chip
PWM
pulse width modulator
SC
switched capacitor
SLIMO
slow IMO
SMP
switch mode pump
SRAM
static random access memory
Document Number: 001-13105 Rev. *C
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’).
Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal.
Page 8 of 43
[+] Feedback
CY8CLED16
Pin Information
Pinouts
The CY8CLED16 device is available in three packages which are listed and illustrated in the following tables. Every port pin (labeled
with a “P”) is capable of Digital I/O. However, Vss, Vdd, SMP, and XRES are not capable of Digital I/O.
28-Pin Part Pinout
Table 2. 28-Pin Part Pinout (SSOP)
Pin
No.
1
2
3
4
5
6
7
8
9
Type
Digital Analog
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I/O
I
Power
10
11
12
13
I/O
I/O
I/O
I/O
14
15
I/O
I/O
I/O
I/O
20
21
22
23
24
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
SMP
P1[7]
P1[5]
P1[3]
P1[1]
Power
16
17
18
19
Pin
Name
Vss
P1[0]
P1[2]
P1[4]
P1[6]
XRES
Input
I
I
I
I/O
I/O
I
Power
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
Description
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
Switch Mode Pump (SMP) connection to
external components required.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
Figure 3. 28-Pin Device
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I,
A, I, P2[3]
P2[1]
SMP
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VREF
P2[4], External AGND
P2[2], A, I
P2[0], A, I
XRES
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK[1].
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA[1].
Optional External Clock Input (EXTCLK).
Active high external reset with internal pull
down.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VREF).
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
Note
1. These are the ISSP pins, which are not High Z at POR.
Document Number: 001-13105 Rev. *C
Page 9 of 43
[+] Feedback
CY8CLED16
48-Pin Part Pinouts
Table 3. 48-Pin Part Pinout (SSOP)
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Type
Digital Analog
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I
I/O
I
I/O
I/O
I/O
I/O
Power
14
15
16
17
18
19
20
21
22
23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
24
25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
Power
26
27
28
29
30
31
32
33
34
35
Pin
Name
Vss
P1[0]
Input
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
Power
P4[0]
P4[2]
P4[4]
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
Vdd
I
I
I
I/O
I/O
I
Description
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Direct switched capacitor block input.
Direct switched capacitor block input.
Switch Mode Pump (SMP) connection to
external components required.
I2C Serial Clock (SCL).
I2C Serial Data (SDA).
Figure 4. 48-Pin Device
A, I, P0[7]
A, IO, P0[5]
A, IO, P0[3]
A, I, P0[1]
P2[7]
P2[5]
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P5[1]
I2C SCL, P1[7]
I2C SDA, P1[5]
P1[3]
I2C SCL, XTALin, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
P0[0], A, I
P2[6], External VREF
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
P5[2]
P5[0]
P1[6]
P1[4], EXTCLK
P1[2]
P1[0], XTALout, I2C SDA
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK[1].
Ground connection.
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA[1].
Optional External Clock Input (EXTCLK).
Active high external reset with internal pull
down.
Direct switched capacitor block input.
Direct switched capacitor block input.
External Analog Ground (AGND).
External Voltage Reference (VREF).
Analog column mux input.
Analog column mux input and column output.
Analog column mux input and column output.
Analog column mux input.
Supply voltage.
LEGEND: A = Analog, I = Input, and O = Output.
Document Number: 001-13105 Rev. *C
Page 10 of 43
[+] Feedback
CY8CLED16
Table 4. 48-Pin Part Pinout (QFN)[2]
P4[1]
Power
SMP
Switch Mode Pump (SMP) connection to external
components required.
8
I/O
P3[7]
9
I/O
P3[5]
10
I/O
P3[3]
11
I/O
P3[1]
12
I/O
P5[3]
13
I/O
P5[1]
14
I/O
P1[7]
I2C Serial Clock (SCL).
15
I/O
P1[5]
I2C Serial Data (SDA).
16
I/O
P1[3]
17
I/O
P1[1]
18
Power
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK[1].
Vss
Ground connection.
19
I/O
P1[0]
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA[1].
20
I/O
P1[2]
21
I/O
P1[4]
22
I/O
P1[6]
23
I/O
P5[0]
24
I/O
P5[2]
25
I/O
P3[0]
26
I/O
P3[2]
27
I/O
P3[4]
28
I/O
29
1
2
3
4
5
6
MLF
7
8
9
10
11
12
(Top View)
36
35
34
33
32
31
30
29
28
27
26
25
P2[4], External AGND
P2[2], A, I
P2[0], A, I
P4[6]
P4[4]
P4[2]
P4[0]
XRES
P3[6]
P3[4]
P3[2]
P3[0]
Optional External Clock Input (EXTCLK).
P3[6]
Input
XRES
Active high external reset with internal pull down.
30
I/O
P4[0]
31
I/O
P4[2]
32
I/O
P4[4]
33
I/O
34
I/O
I
P2[0]
Direct switched capacitor block input.
35
I/O
I
P2[2]
Direct switched capacitor block input.
36
I/O
P2[4]
External Analog Ground (AGND).
37
I/O
P2[6]
External Voltage Reference (VREF).
38
I/O
I
P0[0]
Analog column mux input.
39
I/O
I/O
P0[2]
Analog column mux input and column output.
40
I/O
I/O
P0[4]
Analog column mux input and column output.
41
I/O
I
P0[6]
Analog column mux input.
42
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
P0[0], A, I
P2[6], External VREF
I/O
38
37
P4[3]
6
P5[0]
P5[2]
P4[5]
I/O
Vdd
P0[6], A, I
P0[4], A, IO
P0[2], A, IO
I/O
5
42
41
40
39
4
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
P4[7]
45
44
I/O
17
18
19
20
21
22
23
24
Direct switched capacitor block input.
3
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
P1[2]
EXTCLK, P1[4]
P1[6]
Direct switched capacitor block input.
P2[1]
15
16
P2[3]
I
I2C SDA, P1[5]
P1[3]
I
I/O
P2[5]
P2[7]
P0[1], A, I
I/O
2
48
47
46
1
7
Figure 5. 48-Pin Device
Description
43
Pin
Name
Analog
13
14
Type
Digital
P5[1]
I2C SCL, P1[7]
Pin
No.
P4[6]
Power
Vdd
Supply voltage.
43
I/O
I
P0[7]
Analog column mux input.
44
I/O
I/O
P0[5]
Analog column mux input and column output.
45
I/O
I/O
P0[3]
Analog column mux input and column output.
46
I/O
I
P0[1]
Analog column mux input.
47
I/O
P2[7]
48
I/O
P2[5]
LEGEND: A = Analog, I = Input, and O = Output.
Note
2. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
Document Number: 001-13105 Rev. *C
Page 11 of 43
[+] Feedback
CY8CLED16
Register Reference
Register Conventions
Register Mapping Tables
Abbreviations Used
This chapter lists the registers of the CY8CLED16 EZ-Color
device.
The register conventions specific to this section are listed in the
following table.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
The device has a total register address space of 512 bytes. The
register space is referred to as I/O space and is divided into two
banks. The XOI bit in the Flag register (CPU_F) determines
which bank the user is currently in. When the XOI bit is set the
user is in Bank 1.
Note In the following register mapping tables, blank fields are
reserved and should not be accessed.
Table 5. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2
PRT6DR
PRT6IE
PRT6GS
PRT6DM2
PRT7DR
PRT7IE
PRT7GS
PRT7DM2
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
Addr (0,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
W
RW
#
#
W
Name
DBB20DR0
DBB20DR1
DBB20DR2
DBB20CR0
DBB21DR0
DBB21DR1
DBB21DR2
DBB21CR0
DCB22DR0
DCB22DR1
DCB22DR2
DCB22CR0
DCB23DR0
DCB23DR1
DCB23DR2
DCB23CR0
DBB30DR0
DBB30DR1
DBB30DR2
DBB30CR0
DBB31DR0
DBB31DR1
DBB31DR2
DBB31CR0
DCB32DR0
DCB32DR1
DCB32DR2
DCB32CR0
DCB33DR0
DCB33DR1
DCB33DR2
DCB33CR0
AMX_IN
ARF_CR
CMP_CR0
ASY_CR
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
DCB02DR0
28
#
DCB02DR1
29
W
DCB02DR2
2A
RW
DCB02CR0
2B
#
DCB03DR0
2C
#
TMP_DR0
DCB03DR1
2D
W
TMP_DR1
Blank fields are Reserved and should not be accessed.
Document Number: 001-13105 Rev. *C
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
Access
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
RW
66
67
68
69
6A
6B
6C
6D
RW
RW
#
#
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC12CR0
ASC12CR1
ASC12CR2
ASC12CR3
ASD13CR0
ASD13CR1
ASD13CR2
ASD13CR3
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
ASD22CR0
ASD22CR1
ASD22CR2
ASD22CR3
ASC23CR0
ASC23CR1
ASC23CR2
ASC23CR3
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
MUL1_X
A8
MUL1_Y
A9
MUL1_DH
AA
MUL1_DL
AB
ACC1_DR1
AC
ACC1_DR0
AD
# Access is bit specific.
Acces
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
RW
RW
Acces
RW
RW
RW
RW
RW
RW
RW
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
E6
E7
E8
E9
EA
EB
EC
ED
RW
RW
W
W
R
R
RW
RW
Name
RDI2RI
RDI2SYN
RDI2IS
RDI2LT0
RDI2LT1
RDI2RO0
RDI2RO1
RDI3RI
RDI3SYN
RDI3IS
RDI3LT0
RDI3LT1
RDI3RO0
RDI3RO1
CUR_PP
STK_PP
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
Page 12 of 43
[+] Feedback
CY8CLED16
Table 5. Register Map Bank 0 Table: User Space (continued)
Name
Addr (0,Hex)
Access
Name
DCB03DR2
2E
RW
TMP_DR2
DCB03CR0
2F
#
TMP_DR3
DBB10DR0
30
#
ACB00CR3
DBB10DR1
31
W
ACB00CR0
DBB10DR2
32
RW
ACB00CR1
DBB10CR0
33
#
ACB00CR2
DBB11DR0
34
#
ACB01CR3
DBB11DR1
35
W
ACB01CR0
DBB11DR2
36
RW
ACB01CR1
DBB11CR0
37
#
ACB01CR2
DCB12DR0
38
#
ACB02CR3
DCB12DR1
39
W
ACB02CR0
DCB12DR2
3A
RW
ACB02CR1
DCB12CR0
3B
#
ACB02CR2
DCB13DR0
3C
#
ACB03CR3
DCB13DR1
3D
W
ACB03CR0
DCB13DR2
3E
RW
ACB03CR1
DCB13CR0
3F
#
ACB03CR2
Blank fields are Reserved and should not be accessed.
Addr (0,Hex)
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ACC1_DR3
ACC1_DR2
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
Addr (0,Hex)
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
RDI1RI
B8
RDI1SYN
B9
RDI1IS
BA
RDI1LT0
BB
RDI1LT1
BC
RDI1RO0
BD
RDI1RO1
BE
BF
# Access is bit specific.
Acces
Name
RW
ACC0_DR3
RW
ACC0_DR2
RW
RW
RW
RW
RW
RW
RW
CPU_F
RW
RW
RW
RW
RW
RW
RW
CPU_SCR1
CPU_SCR0
Addr (0,Hex)
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Acces
RW
RW
RL
#
#
Table 6. Register Map Bank 1 Table: Configuration Space
PRT0DM0
00
RW
DBB20FN
40
RW
ASC10CR0
80
Acces
s
RW
RDI2RI
C0
Acces
s
RW
PRT0DM1
01
RW
DBB20IN
41
RW
ASC10CR1
81
RW
RDI2SYN
C1
RW
PRT0IC0
02
RW
DBB20OU
42
RW
ASC10CR2
82
RW
RDI2IS
C2
RW
PRT0IC1
03
RW
ASC10CR3
83
RW
RDI2LT0
C3
RW
PRT1DM0
04
RW
DBB21FN
44
RW
ASD11CR0
84
RW
RDI2LT1
C4
RW
PRT1DM1
05
RW
DBB21IN
45
RW
ASD11CR1
85
RW
RDI2RO0
C5
RW
PRT1IC0
06
RW
DBB21OU
46
RW
ASD11CR2
86
RW
RDI2RO1
C6
RW
PRT1IC1
07
RW
ASD11CR3
87
RW
PRT2DM0
08
RW
DCB22FN
48
RW
ASC12CR0
88
RW
RDI3RI
C8
RW
PRT2DM1
09
RW
DCB22IN
49
RW
ASC12CR1
89
RW
RDI3SYN
C9
RW
PRT2IC0
0A
RW
DCB22OU
4A
RW
ASC12CR2
8A
RW
RDI3IS
CA
RW
PRT2IC1
0B
RW
ASC12CR3
8B
RW
RDI3LT0
CB
RW
PRT3DM0
0C
RW
DCB23FN
4C
RW
ASD13CR0
8C
RW
RDI3LT1
CC
RW
PRT3DM1
0D
RW
DCB23IN
4D
RW
ASD13CR1
8D
RW
RDI3RO0
CD
RW
PRT3IC0
0E
RW
DCB23OU
4E
RW
ASD13CR2
8E
RW
RDI3RO1
CE
RW
PRT3IC1
0F
RW
ASD13CR3
8F
RW
PRT4DM0
10
RW
DBB30FN
50
RW
ASD20CR0
90
RW
GDI_O_IN
D0
RW
PRT4DM1
11
RW
DBB30IN
51
RW
ASD20CR1
91
RW
GDI_E_IN
D1
RW
PRT4IC0
12
RW
DBB30OU
52
RW
ASD20CR2
92
RW
GDI_O_OU
D2
RW
PRT4IC1
13
RW
ASD20CR3
93
RW
GDI_E_OU
D3
RW
PRT5DM0
14
RW
DBB31FN
54
RW
ASC21CR0
94
RW
D4
Name
Addr(1,Hex)
Access
Name
Addr(1,Hex)
Access
43
47
4B
4F
53
Name
Addr(1,Hex)
Name
Addr(1,Hex)
C7
CF
PRT5DM1
15
RW
DBB31IN
55
RW
ASC21CR1
95
RW
D5
PRT5IC0
16
RW
DBB31OU
56
RW
ASC21CR2
96
RW
D6
PRT5IC1
17
RW
ASC21CR3
97
RW
D7
PRT6DM0
18
RW
DCB32FN
58
RW
ASD22CR0
98
RW
D8
PRT6DM1
19
RW
DCB32IN
59
RW
ASD22CR1
99
RW
D9
PRT6IC0
1A
RW
DCB32OU
5A
RW
ASD22CR2
9A
RW
DA
PRT6IC1
1B
RW
ASD22CR3
9B
RW
DB
PRT7DM0
1C
RW
DCB33FN
5C
RW
ASC23CR0
9C
RW
PRT7DM1
1D
RW
DCB33IN
5D
RW
ASC23CR1
9D
RW
OSC_GO_EN
DD
RW
PRT7IC0
1E
RW
DCB33OU
5E
RW
ASC23CR2
9E
RW
OSC_CR4
DE
RW
PRT7IC1
1F
RW
ASC23CR3
9F
RW
OSC_CR3
DF
RW
DBB00FN
20
RW
CLK_CR0
60
RW
A0
OSC_CR0
E0
RW
DBB00IN
21
RW
CLK_CR1
61
RW
A1
OSC_CR1
E1
RW
DBB00OU
22
RW
ABF_CR0
62
RW
A2
OSC_CR2
E2
RW
AMD_CR0
63
RW
A3
VLT_CR
E3
RW
VLT_CMP
E4
R
23
57
5B
5F
DBB01FN
24
RW
64
A4
DBB01IN
25
RW
65
A5
DBB01OU
26
RW
27
DC
E5
AMD_CR1
66
RW
A6
ALT_CR0
67
RW
A7
DEC_CR2
E6
E7
RW
DCB02FN
28
RW
ALT_CR1
68
RW
A8
IMO_TR
E8
W
DCB02IN
29
RW
CLK_CR2
69
RW
A9
ILO_TR
E9
W
Blank fields are Reserved and should not be accessed.
Document Number: 001-13105 Rev. *C
# Access is bit specific.
Page 13 of 43
[+] Feedback
CY8CLED16
Table 6. Register Map Bank 1 Table: Configuration Space (continued)
Name
Addr(1,Hex)
Access
Name
RW
Addr(1,Hex)
Access
Name
6A
Addr(1,Hex)
Acces
s
Name
ECO_TR
EB
W
2C
RW
TMP_DR0
6C
RW
AC
EC
DCB03IN
2D
RW
TMP_DR1
6D
RW
AD
ED
DCB03OU
2E
RW
TMP_DR2
6E
RW
AE
EE
TMP_DR3
6F
RW
AF
2F
AB
Acces
s
RW
DCB03FN
6B
BDG_TR
Addr(1,Hex)
2A
2B
AA
EA
DCB02OU
EF
DBB10FN
30
RW
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
DBB10IN
31
RW
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
DBB10OU
32
RW
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
33
DBB11FN
34
RW
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
DBB11IN
35
RW
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
DBB11OU
36
RW
ACB01CR1
76
RW
RDI0RO1
B6
RW
ACB01CR2
77
RW
37
B7
F6
CPU_F
F7
DCB12FN
38
RW
ACB02CR3
78
RW
RDI1RI
B8
RW
DCB12IN
39
RW
ACB02CR0
79
RW
RDI1SYN
B9
RW
DCB12OU
3A
RW
ACB02CR1
7A
RW
RDI1IS
BA
RW
ACB02CR2
7B
RW
RDI1LT0
BB
RW
FB
FC
3B
DCB13FN
3C
RW
ACB03CR3
7C
RW
RDI1LT1
BC
RW
DCB13IN
3D
RW
ACB03CR0
7D
RW
RDI1RO0
BD
RW
DCB13OU
3E
RW
ACB03CR1
7E
RW
RDI1RO1
BE
RW
ACB03CR2
7F
RW
3F
Blank fields are Reserved and should not be accessed.
Document Number: 001-13105 Rev. *C
BF
RL
F8
F9
FLS_PR1
FA
RW
FD
CPU_SCR1
FE
#
CPU_SCR0
FF
#
# Access is bit specific.
Page 14 of 43
[+] Feedback
CY8CLED16
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8CLED16 EZ-Color device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/ez-color.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Refer to Table 21 for the electrical specifications
on the internal main oscillator (IMO) using SLIMO mode.
Figure 6. Voltage versus CPU Frequency, and IMO Frequency Trim Options
5.25
4.75
Vdd Voltage
Vdd Voltage
lid ng
Va rati n
e io
Op Reg
4.75
SLIMO Mode = 0
5.25
3.60
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=0
3.00
3.00
93 kHz
12 MHz
24 MHz
93 kHz
6 MHz
12 MHz
24 MHz
IMO Frequency
CPU Frequency
The following table lists the units of measure that are used in this chapter.
Table 7. Units of Measure
Symbol
oC
dB
fF
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
microvolts root-mean-square
Document Number: 001-13105 Rev. *C
Symbol
μW
mA
ms
mV
nA
ns
nV
Ω
pA
pF
pp
ppm
ps
sps
σ
V
Unit of Measure
microwatts
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Page 15 of 43
[+] Feedback
CY8CLED16
Absolute Maximum Ratings
Symbol
TSTG
Description
Storage Temperature
Min
-55
Typ
25
Max
+100
TA
Vdd
VIO
Ambient Temperature with Power Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
–
–
–
VIOZ
DC Voltage Applied to Tri-state
IMIO
IMAIO
Maximum Current into any Port Pin
Maximum Current into any Port Pin
Configured as Analog Driver
Electro Static Discharge Voltage
Latch up Current
-40
-0.5
Vss 0.5
Vss 0.5
-25
-50
–
–
+85
+6.0
Vdd +
0.5
Vdd +
0.5
+50
+50
mA
mA
2000
–
–
–
–
200
V
mA
Min
-40
-40
Typ
–
–
Max
+85
+100
Units
oC
oC
ESD
LU
–
Units
oC
Notes
Higher storage temperatures will
reduce data retention time. Recommended storage temperature is
+25oC ± 25oC. Extended duration
storage temperatures above 65oC will
degrade reliability.
o
C
V
V
V
Human Body Model ESD.
Operating Temperature
Symbol
TA
TJ
Description
Ambient Temperature
Junction Temperature
Document Number: 001-13105 Rev. *C
Notes
The temperature rise from ambient to
junction is package specific. See
“Thermal Impedances per Package”
on page 38. The user must limit the
power consumption to comply with
this requirement.
Page 16 of 43
[+] Feedback
CY8CLED16
DC Electrical Characteristics
DC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 8. DC Chip Level Specifications
Symbol
Vdd
Description
Supply Voltage
Min
3.00
Typ
–
Max
5.25
Units
V
IDD
Supply Current
–
8
14
mA
IDD3
Supply Current
–
5
9
mA
IDDP
Supply current when IMO = 6 MHz using
SLIMO mode.
–
2
3
mA
ISB
Sleep (Mode) Current with POR, LVD,
Sleep Timer, WDT, and internal slow
oscillator active.
Sleep (Mode) Current with POR, LVD,
Sleep Timer, WDT, and internal slow
oscillator active.
Sleep (Mode) Current with POR, LVD,
Sleep Timer, WDT, internal slow oscillator,
and 32 kHz crystal oscillator active.
Sleep (Mode) Current with POR, LVD,
Sleep Timer, WDT, and 32 kHz crystal
oscillator active.
Reference Voltage (Bandgap)
–
3
10
μA
–
4
25
μA
–
4
12
μA
–
5
27
μA
1.28
1.3
1.32
V
ISBH
ISBXTL
ISBXTLH
VREF
Document Number: 001-13105 Rev. *C
Notes
See DC POR and LVD specifications, Table 3-15 on page 27.
Conditions are 5.0V, TA = 25 oC,
CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz, VC2 =
93.75 kHz, VC3 = 0.366 kHz.
Conditions are Vdd = 3.3V, TA = 25
oC, CPU = 3 MHz, SYSCLK doubler
disabled, VC1 = 1.5 MHz, VC2 =
93.75 kHz, VC3 = 0.366 kHz.
Conditions are Vdd = 3.3V, TA = 25
o
C, CPU = 0.75 MHz, SYSCLK
doubler disabled, VC1 = 0.375 MHz,
VC2 = 23.44 kHz, VC3 = 0.09 kHz.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, -40 oC
≤ TA ≤ 55 oC.
Conditions are with internal slow
speed oscillator, Vdd = 3.3V, 55 oC <
TA ≤ 85 oC.
Conditions are with properly loaded,
1 μW max, 32.768 kHz crystal. Vdd
= 3.3V, -40 oC ≤ TA ≤ 55 oC.
Conditions are with properly loaded,
1 μW max, 32.768 kHz crystal. Vdd
= 3.3V, 55 oC < TA ≤ 85 oC.
Trimmed for appropriate Vdd.
Page 17 of 43
[+] Feedback
CY8CLED16
DC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 9. DC GPIO Specifications
Symbol
RPU
RPD
VOH
Description
Pull up Resistor
Pull down Resistor
High Output Level
Min
4
4
Vdd 1.0
Typ
5.6
5.6
–
Max
8
8
–
Units
kΩ
kΩ
V
VOL
Low Output Level
–
–
0.75
V
IOH
High Level Source Current
10
–
–
mA
IOL
Low Level Sink Current
25
–
–
mA
VIL
VIH
VH
IIL
CIN
COUT
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
Capacitive Load on Pins as Output
–
2.1
–
–
–
–
–
–
60
1
3.5
3.5
0.8
V
V
mV
nA
pF
pF
Document Number: 001-13105 Rev. *C
–
–
10
10
Notes
IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])). 80 mA maximum
combined IOH budget.
IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total
loads, 4 on even port pins (for example,
P0[2], P1[4]), 4 on odd port pins (for
example, P0[3], P1[5])). 150 mA maximum
combined IOL budget.
VOH = Vdd-1.0V. See the limitations of the
total current in the Note for VOH.
VOL = 0.75V. See the limitations of the total
current in the Note for VOL.
Vdd = 3.0 to 5.25.
Vdd = 3.0 to 5.25.
Gross tested to 1 μA.
Package and pin dependent. Temp = 25oC.
Package and pin dependent. Temp = 25oC.
Page 18 of 43
[+] Feedback
CY8CLED16
DC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC
blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at
25°C and are for design guidance only.
Table 10. 5V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
TCVOSOA Average Input Offset Voltage Drift
Input Leakage Current (Port 0 Analog Pins)
IEBOA
CINOA
Input Capacitance (Port 0 Analog Pins)
Common Mode Voltage Range. All Cases, except
highest.
Power = High, Opamp Bias = High
CMRROA Common Mode Rejection Ratio
GOLOA
Open Loop Gain
VOHIGHO High Output Voltage Swing (internal signals)
VCMOA
Min
Typ
Max
Units
–
–
–
–
–
–
1.6
1.3
1.2
10
8
7.5
mV
mV
mV
7.0
200
4.5
35.0
–
9.5
μV/oC
pA
pF
0.0
0.5
–
–
Vdd
Vdd - 0.5
V
V
60
80
Vdd - .01
–
–
–
–
–
–
dB
dB
V
–
–
0.1
V
–
–
–
–
–
–
67
150
300
600
1200
2400
4600
80
200
400
800
1600
3200
6400
–
μA
μA
μA
μA
μA
μA
dB
Notes
Gross tested to 1 μA.
Package and pin
dependent. Temp = 25 oC.
A
VOLOWOA Low Output Voltage Swing (internal signals)
Supply Current (including associated AGND buffer)
ISOA
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
PSRROA Supply Voltage Rejection Ratio
Document Number: 001-13105 Rev. *C
Vss ≤ VIN ≤ (Vdd - 2.25) or
(Vdd - 1.25V) ≤ VIN ≤ Vdd.
Page 19 of 43
[+] Feedback
CY8CLED16
Table 11. 3.3V DC Operational Amplifier Specifications
Min
Typ
Max
Units
VOSOA
Symbol
Input Offset Voltage (absolute value)
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = High
High Power is 5 Volts Only
Description
–
–
1.65
1.32
10
8
mV
mV
TCVOSOA
Average Input Offset Voltage Drift
–
7.0
35.0
μV/oC
Notes
IEBOA
Input Leakage Current (Port 0 Analog Pins)
–
200
–
pA
Gross tested to 1 μA.
CINOA
Input Capacitance (Port 0 Analog Pins)
–
4.5
9.5
pF
Package and pin
dependent. Temp = 25
o
C.
VCMOA
Common Mode Voltage Range
0
–
Vdd
V
CMRROA
Common Mode Rejection Ratio
60
–
–
dB
GOLOA
Open Loop Gain
VOHIGHOA High Output Voltage Swing (internal signals)
80
–
–
dB
Vdd - .01
–
–
V
VOLOWOA
Low Output Voltage Swing (internal signals)
–
–
.01
V
ISOA
Supply Current (including associated AGND buffer)
Power = Low, Opamp Bias = Low
Power = Low, Opamp Bias = High
Power = Medium, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = Low
Power = High, Opamp Bias = High
–
–
–
–
–
–
150
300
600
1200
2400
–
200
400
800
1600
3200
–
μA
μA
μA
μA
μA
Supply Voltage Rejection Ratio
54
80
–
dB
PSRROA
Not Allowed
Vss ≤ VIN ≤ (Vdd - 2.25)
or (Vdd - 1.25V) ≤ VIN ≤
Vdd
DC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 12. DC Low Power Comparator Specifications
Symbol
VREFLPC
ISLPC
VOSLPC
Description
Low power comparator (LPC) reference voltage
range
LPC supply current
LPC voltage offset
Document Number: 001-13105 Rev. *C
Min
0.2
Typ
–
Max
Vdd - 1
Units
V
–
–
10
2.5
40
30
μA
mV
Notes
Page 20 of 43
[+] Feedback
CY8CLED16
DC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 13. 5V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Description
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
Power = High
Low Output Voltage Swing (Load = 32 ohms
to Vdd/2)
Power = Low
Power = High
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
Min
–
–
0.5
Typ
3
+6
–
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
–
–
–
–
1
1
W
W
0.5 x Vdd + 1.3
0.5 x Vdd + 1.3
–
–
–
–
V
V
–
–
–
–
0.5 x Vdd - 1.3
0.5 x Vdd - 1.3
V
V
–
–
40
1.1
2.6
64
2
5
–
mA
mA
dB
Min
–
–
0.5
Typ
3
+6
-
Max
12
–
Vdd - 1.0
Units
mV
μV/°C
V
–
–
–
–
10
10
W
W
0.5 x Vdd + 1.0
0.5 x Vdd + 1.0
–
–
–
–
V
V
–
–
–
–
0.5 x Vdd - 1.0
0.5 x Vdd - 1.0
V
V
–
60
0.8
2.0
64
1
5
–
mA
mA
dB
Notes
Table 14. 3.3V DC Analog Output Buffer Specifications
Symbol
VOSOB
TCVOSOB
VCMOB
ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Description
Input Offset Voltage (Absolute Value)
Average Input Offset Voltage Drift
Common-Mode Input Voltage Range
Output Resistance
Power = Low
Power = High
High Output Voltage Swing (Load = 1k ohms
to Vdd/2)
Power = Low
Power = High
Low Output Voltage Swing (Load = 1k ohms
to Vdd/2)
Power = Low
Power = High
Supply Current Including Bias Cell (No Load)
Power = Low
Power = High
Supply Voltage Rejection Ratio
Document Number: 001-13105 Rev. *C
Notes
Page 21 of 43
[+] Feedback
CY8CLED16
DC Switch Mode Pump Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 15. DC Switch Mode Pump (SMP) Specifications
Min
Typ
Max
Units
Notes
VPUMP 5V
Symbol
5V Output Voltage at Vdd from Pump
Description
4.75
5.0
5.25
V
Configuration of footnote.[3]
Average, neglecting ripple. SMP
trip voltage is set to 5.0V.
VPUMP 3V
3V Output Voltage at Vdd from Pump
3.00
3.25
3.60
V
Configuration of footnote.[3]
Average, neglecting ripple. SMP
trip voltage is set to 3.25V.
IPUMP
Available Output Current
VBAT = 1.5V, VPUMP = 3.25V
VBAT = 1.8V, VPUMP = 5.0V
8
5
–
–
–
–
mA
mA
VBAT5V
Input Voltage Range from Battery
1.8
–
5.0
V
Configuration of footnote.[3] SMP
trip voltage is set to 5.0V.
VBAT3V
Input Voltage Range from Battery
1.0
–
3.3
V
Configuration of footnote.[3] SMP
trip voltage is set to 3.25V.
VBATSTART
Minimum Input Voltage from Battery to Start
Pump
1.2
–
–
V
Configuration of footnote.[3] 0oC
≤ TA ≤ 100. 1.25V at TA = -40oC.
ΔVPUMP_Line
Line Regulation (over VBAT range)
–
5
–
%VO
Configuration of footnote.[3] VO is
the “Vdd Value for PUMP Trip”
specified by the VM[2:0] setting in
Table 19, “DC POR, SMP, and
LVD Specifications,” on page 25.
ΔVPUMP_Load
Load Regulation
–
5
–
%VO
Configuration of footnote.[3] VO is
the “Vdd Value for PUMP Trip”
specified by the VM[2:0] setting in
Table 19, “DC POR, SMP, and
LVD Specifications,” on page 25.
ΔVPUMP_Rippl Output Voltage Ripple (depends on
capacitor/load)
e
–
100
–
mVpp
Configuration of footnote.[3] Load
is 5 mA.
E3
Efficiency
35
50
–
%
Configuration of footnote.[3] Load
is 5 mA. SMP trip voltage is set to
3.25V.
FPUMP
Switching Frequency
–
1.4
–
MHz
DCPUMP
Switching Duty Cycle
–
50
–
%
Configuration of footnote.[3]
SMP trip voltage is set to 3.25V.
SMP trip voltage is set to 5.0V.
Note
3. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 7.
Document Number: 001-13105 Rev. *C
Page 22 of 43
[+] Feedback
CY8CLED16
Figure 7. Basic Switch Mode Pump Circuit
D1
Vdd
L1
V BAT
+
V PUMP
C1
SMP
Battery
EZ-Color
Vss
DC Analog Reference Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to
the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control
register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.
Reference control power is high.
Table 16. 5V DC Analog Reference Specifications
Symbol
Description
VBG5
Bandgap Voltage Reference 5V
–
AGND = Vdd/2[4]
–
–
AGND = 2 x BandGap[4]
AGND = P2[4] (P2[4] = Vdd/2)[4]
–
–
–
–
AGND = BandGap[4]
AGND = 1.6 x BandGap[4]
AGND Block to Block Variation (AGND = Vdd/2)[4]
RefHi = Vdd/2 + BandGap
–
–
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)
–
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
–
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
–
–
–
RefHi = 2 x BandGap
RefHi = 3.2 x BandGap
RefLo = Vdd/2 – BandGap
Document Number: 001-13105 Rev. *C
Min
1.28
Vdd/2 0.02
2.52
P2[4] 0.013
1.27
2.03
-0.034
Vdd/2 +
1.21
3.75
P2[6] +
2.478
P2[4] +
1.218
P2[4] +
P2[6] 0.058
2.50
4.02
Vdd/2 1.369
Typ
Max
1.30
1.32
Vdd/2 Vdd/2 +
0.02
2.60
2.72
P2[4] P2[4] +
0.013
1.3
1.34
2.08
2.13
0.000 0.034
Vdd/2 + Vdd/2 +
1.3
1.382
3.9
4.05
P2[6] + P2[6] +
2.6
2.722
P2[4] + P2[4] +
1.3
1.382
P2[4] + P2[4] +
P2[6] P2[6] +
0.058
2.60
2.70
4.16
4.29
Vdd/2 - Vdd/2 1.30
1.231
Units
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Page 23 of 43
[+] Feedback
CY8CLED16
Table 16. 5V DC Analog Reference Specifications (continued)
Symbol
Description
–
RefLo = BandGap
–
RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)
–
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
–
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V)
Min
1.20
2.489 P2[6]
P2[4] 1.368
P2[4] P2[6] 0.042
Typ
Max
1.30
1.40
2.6 - 2.711 P2[6]
P2[6]
P2[4] - P2[4] 1.30
1.232
P2[4] - P2[4] P2[6] P2[6] +
0.042
Units
V
V
V
V
Table 17. 3.3V DC Analog Reference Specifications
Symbol
VBG33
–
Description
Bandgap Voltage Reference 3.3V
AGND = Vdd/2[4]
–
–
AGND = 2 x BandGap[4]
AGND = P2[4] (P2[4] = Vdd/2)
–
–
–
–
–
–
–
–
AGND = BandGap[4]
AGND = 1.6 x BandGap[4]
AGND Block to Block Variation (AGND = Vdd/2)[4]
RefHi = Vdd/2 + BandGap
RefHi = 3 x BandGap
RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)
RefHi = P2[4] + BandGap (P2[4] = Vdd/2)
RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
–
–
–
–
–
–
–
RefHi = 2 x BandGap
RefHi = 3.2 x BandGap
RefLo = Vdd/2 - BandGap
RefLo = BandGap
RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)
RefLo = P2[4] – BandGap (P2[4] = Vdd/2)
RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V)
Min
Typ
1.28
1.30
Vdd/2 - Vdd/2
0.02
Not Allowed
P2[4] - P2[4]
0.009
1.27
1.30
2.03
2.08
-0.034 0.000
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] + P2[4] +
P2[6] - P2[6]
0.042
2.50
2.60
Not Allowed
Not Allowed
Not Allowed
Not Allowed
Not Allowed
P2[4] - P2[4] P2[6] - P2[6]
0.036
Max
1.32
Vdd/2
+ 0.02
Units
V
V
P2[4] +
0.009
1.34
2.13
0.034
V
V
V
mV
P2[4] + V
P2[6] +
0.042
2.70
V
P2[4] - V
P2[6] +
0.036
Note
4. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V.
Document Number: 001-13105 Rev. *C
Page 24 of 43
[+] Feedback
CY8CLED16
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 18. DC Analog PSoC Block Specifications
Symbol
RCT
CSC
Description
Resistor Unit Value (Continuous Time)
Capacitor Unit Value (Switched Capacitor)
Min
–
–
Typ
12.2
80
Max
–
–
Units
kΩ
fF
Notes
DC POR, SMP, and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 19. DC POR, SMP, and LVD Specifications
Symbol
Description
VPPOR0R
VPPOR1R
VPPOR2R
Vdd Value for PPOR Trip (positive ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPPOR0
VPPOR1
VPPOR2
Vdd Value for PPOR Trip (negative ramp)
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VPH0
VPH1
VPH2
Min
Typ
Max
Units
–
2.91
4.39
4.55
–
V
V
V
–
2.82
4.39
4.55
–
V
V
V
PPOR Hysteresis
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
–
–
92
0
0
–
–
–
mV
mV
mV
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.86
2.96
3.07
3.92
4.39
4.55
4.63
4.72
2.92
3.02
3.13
4.00
4.48
4.64
4.73
4.81
2.98[5]
3.08
3.20
4.08
4.57
4.74[6]
4.82
4.91
V
V
V
V
V
V
V
V
V
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
Vdd Value for SMP Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.96
3.03
3.18
4.11
4.55
4.63
4.72
4.90
3.02
3.10
3.25
4.19
4.64
4.73
4.82
5.00
3.08
3.16
3.32
4.28
4.74
4.82
4.91
5.10
V
V
V
V
V
V
V
V
V
Notes
Notes
5. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.
6. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
Document Number: 001-13105 Rev. *C
Page 25 of 43
[+] Feedback
CY8CLED16
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 20. DC Programming Specifications
Symbol
IDDP
VILP
VIHP
IILP
IIHP
VOLV
VOHV
FlashENPB
FlashENT
FlashDR
Description
Min
Supply Current During Programming or
–
Verify
Input Low Voltage During Programming or
–
Verify
Input High Voltage During Programming or
2.2
Verify
Input Current when Applying Vilp to P1[0] or
–
P1[1] During Programming or Verify
Input Current when Applying Vihp to P1[0] or
–
P1[1] During Programming or Verify
Output Low Voltage During Programming or
–
Verify
Output High Voltage During Programming or Vdd - 1.0
Verify
Flash Endurance (per block)
50,000[7]
[8]
Flash Endurance (total)
1,800,00
0
Flash Data Retention
10
Typ
10
Max
30
Units
mA
Notes
–
0.8
V
–
–
V
–
0.2
mA
Driving internal pull down resistor.
–
1.5
mA
Driving internal pull down resistor.
–
V
–
Vss +
0.75
Vdd
–
–
–
–
–
–
–
–
Years
V
Erase/write cycles per block.
Erase/write cycles.
Notes
7. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 3.0V to 3.6V and 4.75V
to 5.25V.
8. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block
ever sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-13105 Rev. *C
Page 26 of 43
[+] Feedback
CY8CLED16
AC Electrical Characteristics
AC Chip Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Note See the individual user module data sheets for information on maximum frequencies for user modules.
Table 21. AC Chip Level Specifications
Symbol
FIMO24
Description
Min
Internal Main Oscillator Frequency for 24 23.4
MHz
Typ
24
Max
Units
24.6[9,10,11] MHz
FIMO6
Internal Main Oscillator Frequency for 6 5.5
MHz
6
6.5[9,10,11]
MHz
FCPU1
FCPU2
F48M
CPU Frequency (5V Nominal)
CPU Frequency (3.3V Nominal)
Digital PSoC Block Frequency
24
12
48
24.6[9,10]
12.3[10,11]
49.2[9,10,12]
MHz
MHz
MHz
F24M
F32K1
F32K_U
Digital PSoC Block Frequency
0
Internal Low Speed Oscillator Frequency 15
Internal Low Speed Oscillator Untrimmed
5
Frequency
24
32
24.6[10,12]
64
–
MHz
kHz
kHz
DCILO
F32K2
Internal Low Speed Oscillator Duty Cycle
20
External Crystal Oscillator
–
50
32.768 –
FPLL
PLL Frequency
–
23.986 –
MHz
Jitter24M2
TPLLSLEW
TPLLSLEWL
24 MHz Period Jitter (PLL)
PLL Lock Time
PLL Lock Time for Low Gain Setting
–
0.5
0.5
–
–
–
600
10
50
ps
ms
ms
0.093
0.093
0
–
80
%
kHz
Notes
Trimmed for 5V or 3.3V operation
using factory trim values. See the
figure on page 19. SLIMO Mode =
0.
Trimmed for 5V or 3.3V operation
using factory trim values. See the
figure on page 19. SLIMO Mode =
1.
Refer to the AC Digital Block Specifications below.
After a reset and before the m8c
starts to run, the ILO is not
trimmed. See the System Resets
section of the PSoC Technical
Reference Manual for details on
timing this.
Accuracy is capacitor and crystal
dependent. 50% duty cycle.
A multiple (x732) of crystal
frequency.
OW
TOS
TOSACC
External Crystal Oscillator Startup to 1% –
External Crystal Oscillator Startup to 100 –
ppm
250
300
500
600
ms
ms
Jitter32k
TXRST
DC24M
32 kHz Period Jitter
External Reset Pulse Width
24 MHz Duty Cycle
100
–
50
–
60
ns
μs
%
–
10
40
The crystal oscillator frequency is
within 100 ppm of its final value by
the end of the Tosacc period.
Correct operation assumes a
properly loaded 1 μW maximum
drive level 32.768 kHz crystal. 3.0V
≤ Vdd ≤ 5.5V, -40 oC ≤ TA ≤ 85 oC.
Notes
9. 4.75V < Vdd < 5.25V.
10. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
11. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3V.
12. See the individual user module data sheets for information on maximum frequencies for user modules
Document Number: 001-13105 Rev. *C
Page 27 of 43
[+] Feedback
CY8CLED16
Table 21. AC Chip Level Specifications (continued)
Symbol
Step24M
Fout48M
Description
24 MHz Trim Step Size
48 MHz Output Frequency
Min
–
46.8
Typ
50
48.0
Max
–
49.2[9, 11]
Units
kHz
MHz
Jitter24M1
FMAX
24 MHz Period Jitter (IMO)
Maximum frequency of signal on row
input or row output.
Power Supply Slew Rate
–
–
600
–
12.3
ps
MHz
SRPOWER_
–
–
250
V/ms
–
16
100
ms
Notes
Trimmed. Utilizing factory trim
values.
Vdd slew rate during power up.
UP
TPOWERUP
Time from End of POR to CPU Executing
Code
Power up from 0V. See the System
Resets section of the PSoC
Technical Reference Manual.
Figure 8. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 9. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 10. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Figure 11. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter24M1
F 24M
Document Number: 001-13105 Rev. *C
Page 28 of 43
[+] Feedback
CY8CLED16
Figure 12. 32 kHz Period Jitter (ECO) Timing Diagram
Jitter32k
F 32K2
AC General Purpose I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 22. AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO Operating Frequency
Rise Time, Normal Strong Mode, Cload = 50
pF
Fall Time, Normal Strong Mode, Cload = 50
pF
Rise Time, Slow Strong Mode, Cload = 50 pF
Fall Time, Slow Strong Mode, Cload = 50 pF
Min
Typ
0
3
–
–
Max
12.3
18
Units
MHz
ns
Notes
Normal Strong Mode
Vdd = 4.75 to 5.25V, 10% - 90%
2
–
18
ns
Vdd = 4.75 to 5.25V, 10% - 90%
10
10
27
22
–
–
ns
ns
Vdd = 3 to 5.25V, 10% - 90%
Vdd = 3 to 5.25V, 10% - 90%
Figure 13. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
Document Number: 001-13105 Rev. *C
TFallF
TFallS
Page 29 of 43
[+] Feedback
CY8CLED16
AC Operational Amplifier Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.
Power = High and Opamp Bias = High is not supported at 3.3V.
Table 23. 5V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Power = High, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
μs
μs
μs
–
–
–
–
–
–
5.9
0.92
0.72
μs
μs
μs
0.15
1.7
6.5
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.01
0.5
4.0
–
–
–
–
–
–
V/μs
V/μs
V/μs
0.75
3.1
5.4
–
–
–
–
100
–
–
–
–
MHz
MHz
MHz
nV/rt-Hz
Notes
Table 24. 3.3V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
ENOA
Description
Rising Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain)
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Gain Bandwidth Product
Power = Low, Opamp Bias = Low
Power = Medium, Opamp Bias = High
Noise at 1 kHz (Power = Medium, Opamp Bias = High)
Document Number: 001-13105 Rev. *C
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
μs
μs
–
–
–
–
5.41
0.72
μs
μs
0.31
2.7
–
–
–
–
V/μs
V/μs
0.24
1.8
–
–
–
–
V/μs
V/μs
0.67
2.8
–
–
–
100
–
–
–
MHz
MHz
nV/rt-Hz
Notes
Page 30 of 43
[+] Feedback
CY8CLED16
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 14. Typical AGND Noise with P2[4] Bypass
dBV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 15. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 001-13105 Rev. *C
0.01
0.1
Freq (kHz)
1
10
100
Page 31 of 43
[+] Feedback
CY8CLED16
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters
apply to 5V at 25°C and are for design guidance only.
Table 25. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
μs
Notes
≥ 50 mV overdrive comparator
reference set within VREFLPC.
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 26. AC Digital Block Specifications
Function
All
Functions
Timer
Counter
Dead Band
Description
Min
Typ
Max
Units
Notes
Maximum Block Clocking Frequency (>
4.75V)
49.2
MHz
4.75V < Vdd < 5.25V.
Maximum Block Clocking Frequency (<
4.75V)
24.6
MHz
3.0V < Vdd < 4.75V.
Capture Pulse Width
50[13]
–
–
ns
Maximum Frequency, No Capture
–
–
49.2
MHz
Maximum Frequency, With Capture
–
–
24.6
MHz
Enable Pulse Width
50[13]
–
–
ns
Maximum Frequency, No Enable Input
–
–
49.2
MHz
Maximum Frequency, Enable Input
–
–
24.6
MHz
Asynchronous Restart Mode
20
–
–
ns
Synchronous Restart Mode
50[13]
–
–
ns
Disable Mode
50[13]
–
–
ns
4.75V < Vdd < 5.25V.
4.75V < Vdd < 5.25V.
Kill Pulse Width:
Maximum Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
(PRS Mode)
Maximum Input Clock Frequency
–
–
49.2
MHz
4.75V < Vdd < 5.25V.
CRCPRS
(CRC Mode)
Maximum Input Clock Frequency
–
–
24.6
MHz
SPIM
Maximum Input Clock Frequency
–
–
8.2
MHz
SPIS
Maximum Input Clock Frequency
–
–
4.1
ns
–
–
ns
Transmitter
Receiver
[13]
Width of SS_ Negated Between Transmissions
50
Maximum Input Clock Frequency
Vdd ≥ 4.75V, 2 Stop Bits
–
–
24.6
MHz
–
–
49.2
MHz
–
–
24.6
MHz
–
–
49.2
MHz
Maximum Input Clock Frequency
Vdd ≥ 4.75V, 2 Stop Bits
Maximum data rate at 4.1 MHz
due to 2 x over clocking.
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Maximum data rate at 6.15 MHz
due to 8 x over clocking.
Maximum data rate at 3.08 MHz
due to 8 x over clocking.
Maximum data rate at 6.15 MHz
due to 8 x over clocking.
Note
13. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-13105 Rev. *C
Page 32 of 43
[+] Feedback
CY8CLED16
AC Analog Output Buffer Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 27. 5V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising Settling Time to 0.1%, 1V Step, 100pF
Load
Power = Low
Power = High
TSOB
Falling Settling Time to 0.1%, 1V Step, 100pF
Load
Power = Low
Power = High
SRROB Rising Slew Rate (20% to 80%), 1V Step,
100pF Load
Power = Low
Power = High
SRFOB
Falling Slew Rate (80% to 20%), 1V Step,
100pF Load
Power = Low
Power = High
BWOB
Small Signal Bandwidth, 20mVpp, 3dB BW,
100pF Load
Power = Low
Power = High
BWOB
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF
Load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
4
4
μs
μs
–
–
–
–
3.4
3.4
μs
μs
0.5
0.5
–
–
–
–
V/μs
V/μs
0.55
0.55
–
–
–
–
V/μs
V/μs
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Notes
Table 28. 3.3V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising Settling Time to 0.1%, 1V Step, 100pF
Load
Power = Low
Power = High
TSOB
Falling Settling Time to 0.1%, 1V Step, 100pF
Load
Power = Low
Power = High
SRROB
Rising Slew Rate (20% to 80%), 1V Step,
100pF Load
Power = Low
Power = High
SRFOB
Falling Slew Rate (80% to 20%), 1V Step,
100pF Load
Power = Low
Power = High
BWOB
Small Signal Bandwidth, 20mVpp, 3dB BW,
100pF Load
Power = Low
Power = High
BWOB
Min
Typ
Max
Units
–
–
–
–
4.7
4.7
μs
μs
–
–
–
–
4
4
μs
μs
.36
.36
–
–
–
–
V/μs
V/μs
.4
.4
–
–
–
–
V/μs
V/μs
0.7
0.7
–
–
–
–
MHz
MHz
Power = Low
200
–
–
kHz
Power = High
200
–
–
kHz
Notes
Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load
Document Number: 001-13105 Rev. *C
Page 33 of 43
[+] Feedback
CY8CLED16
AC External Clock Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 29. 5V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High Period
20.6
–
5300
ns
–
Low Period
20.6
–
–
ns
–
Power Up IMO to Switch
150
–
–
μs
Notes
Table 30. 3.3V AC External Clock Specifications
Symbol
Description
Min
FOSCEXT
Frequency with CPU Clock Divide
by 1
0.093
–
12.3
MHz
Maximum CPU frequency is 12 MHz at 3.3V.
With the CPU clock divider set to 1, the
external clock must adhere to the maximum
frequency and duty cycle requirements.
FOSCEXT
Frequency with CPU Clock Divide
by 2 or Greater
0.186
–
24.6
MHz
If the frequency of the external clock is greater
than 12 MHz, the CPU clock divider must be
set to 2 or greater. In this case, the CPU clock
divider will ensure that the fifty percent duty
cycle requirement is met.
–
High Period with CPU Clock Divide 41.7
by 1
–
5300
ns
–
Low Period with CPU Clock Divide 41.7
by 1
–
–
ns
–
Power Up IMO to Switch
–
–
μs
150
Typ
Max
Units
Notes
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 31. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TRSCLK
Rise Time of SCLK
1
–
20
ns
TFSCLK
Fall Time of SCLK
1
–
20
ns
TSSCLK
Data Set up Time to Falling Edge of SCLK
40
–
–
ns
THSCLK
Data Hold Time from Falling Edge of SCLK 40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash Erase Time (Block)
–
10
–
ms
TWRITE
Flash Block Write Time
–
40
–
ms
TDSCLK
Data Out Delay from Falling Edge of SCLK –
–
45
ns
Vdd > 3.6
TDSCLK3
Data Out Delay from Falling Edge of SCLK –
–
50
ns
3.0 ≤ Vdd ≤ 3.6
ms
Erase all blocks and protection fields
at once.
TERASEALL Flash Erase Time (Bulk)
–
80
–
Note
14. For the full industrial range, the user must employ a Temperature Sensor User Module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
Document Number: 001-13105 Rev. *C
Page 34 of 43
[+] Feedback
CY8CLED16
Table 31. AC Programming Specifications (continued)
TPROGRAM_ Flash Block Erase + Flash Block Write Time
–
–
100[14] ms
0°C ≤ TJ ≤ 100°C
–
–
200[14] ms
-40°C ≤ TJ ≤ 0°C
HOT
TPROGRAM_ Flash Block Erase + Flash Block Write Time
COLD
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and
are for design guidance only.
Table 32. AC Characteristics of the I2C SDA and SCL Pins
Standard-Mode
Fast-Mode
Min
Max
Min
Max
0
100
0
400
FSCLI2C SCL Clock Frequency
THDSTAI Hold Time (repeated) START Condition. After 4.0
–
0.6
–
this period, the first clock pulse is generated.
2C
TLOWI2C LOW Period of the SCL Clock
4.7
–
1.3
–
THIGHI2 HIGH Period of the SCL Clock
4.0
–
0.6
–
Symbol
Description
Units
Notes
kHz
μs
μs
μs
C
TSUSTAI
2C
Set-up Time for a Repeated START Condition 4.7
–
0.6
–
μs
THDDATI
2C
Data Hold Time
0
–
0
–
μs
TSUDATI
Data Set-up Time
250
–
100[15]
–
ns
TSUSTOI
2C
Set-up Time for STOP Condition
4.0
–
0.6
–
μs
TBUFI2C
Bus Free Time Between a STOP and START 4.7
Condition
Pulse Width of spikes are suppressed by the –
input filter.
–
1.3
–
μs
–
0
50
ns
2C
TSPI2C
Figure 16. Definition for Timing for Fast-/Standard-Mode on the I2C Bus
SDA
TLOWI2C
TSPI2C
TSUDATI2C
THDSTAI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Note
15. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-13105 Rev. *C
Page 35 of 43
[+] Feedback
CY8CLED16
Packaging Information
This section illustrates the packaging specifications for the CY8CLED16 EZ-Color device, along with the thermal impedances for each
package and the typical package capacitance on crystal pins.
Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of
the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at
http://www.cypress.com/design/MR10161.
Packaging Dimensions
Figure 0-1. 28-Pin (210-Mil) SSOP
51-85079 *D
Document Number: 001-13105 Rev. *C
Page 36 of 43
[+] Feedback
CY8CLED16
Figure 17. 48-Pin (300-Mil) SSOP
51-85061 *C
51-85061-C
Figure 18. 48-Pin (7x7 mm) QFN (Punched)
SIDE VIEW
TOP VIEW
0.08
BOTTOM VIEW
C
1.00 MAX.
6.90
7.10
0.05 MAX.
5.1
0.80 MAX.
6.70
6.80
0.23±0.05
0.20 REF.
N
N
PIN1 ID
0.20 R.
1
2 0.45
1
2
0.80 DIA.
6.70
6.80
6.90
7.10
5.1
SOLDERABLE
EXPOSED
PAD
5.45
5.55
0.30-0.45
0°-12°
0.50
C
NOTES:
1.
SEATING
PLANE
5.45
5.55
0.42±0.18
(4X)
HATCH AREA IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.13g
4. ALL DIMENSIONS ARE IN MM [MIN/MAX]
5. PACKAGE CODE
PART #
DESCRIPTION
LF48A
LY48A
STANDARD
LEAD FREE
Document Number: 001-13105 Rev. *C
001-12919 *B
Page 37 of 43
[+] Feedback
CY8CLED16
Figure 19. 48-Pin (7x7x1.0 mm) QFN (Sawn)
TOP VIEW
SIDE VIEW
7.00±0.100
BOTTOM VIEW
0.900±0.100
48
0.25
36
1
5.100 REF
0.200 REF.
37
0.50 PITCH
+0.05
-0.07
PIN1 ID
R 0.20
37
PIN 1 DOT
1
36
LASER MARK
0.45
7.00±0.100
SOLDERABLE
EXPOSED
PAD
5.100 REF
12
25
13
24
25
C
0.08
NOTES:
HATCH AREA IS SOLDERABLE EXPOSED METAL.
12
0.40±0.10
13
24
SEATING PLANE
0.020 +0.025
-0.00
1.
5.500±0.100
5.500±0.100
2. REFERENCE JEDEC#: MO-220
3. PACKAGE WEIGHT: 0.13g
4. ALL DIMENSIONS ARE IN MILLIMETERS
001-13191 *E
Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at
http://www.amkor.com/products/notes_papers/MLFAppNote.pdf.
Important Note Pinned vias for thermal conduction are not required for the low-power device.
Thermal Impedances
Solder Reflow Peak Temperature
Table 33. Thermal Impedances per Package
Following is the minimum solder reflow peak temperature to
achieve good solderability.
Package
28 SSOP
48 SSOP
48 QFN[17]
Typical θJA [16]
94 oC/W
69 oC/W
28 oC/W
Capacitance on Crystal Pins
Table 35. Solder Reflow Peak Temperature
Package
Minimum Peak
Temperature[18]
Maximum Peak
Temperature
28 SSOP
240oC
260oC
48 SSOP
220oC
260oC
48 QFN
220oC
260oC
Table 34. Typical Package Capacitance on Crystal Pins
Package
28 SSOP
48 SSOP
48 QFN
Package Capacitance
2.8 pF
3.3 pF
1.8 pF
Notes
16. TJ = TA + POWER x θJA
17. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
18. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications
Document Number: 001-13105 Rev. *C
Page 38 of 43
[+] Feedback
CY8CLED16
Development Tool Selection
Software
CY3265-RGB EZ-Color Evaluation Kit
At the core of the PSoC development software suite is PSoC
Designer, used to generate PSoC firmware applications. PSoC
Designer is available free of charge at
http://www.cypress.com/psocdesigner and includes a free C
compiler.
The CY3265-RGB evaluation board demonstrates the ability of
the EZ-Color device to use real-time temperature feedback to
control three primary, high brightness LEDs and create accurate,
mixed-color output. There are three variations of the kit available,
depending on the LED manufacturer of the LEDs on the board:
CY3265C-RGB (Cree LEDs), CY3265N-RGB (Nichia LEDs), or
CY3265O-RGB (OSRAM LEDs). The kit includes:
PSoC Programmer
■
CY3265C-RGB Evaluation Board
PSoC Programmer is flexible and used on the bench in development. It is also suitable for factory programming. PSoC
Programmer works either as a standalone programming application or operates directly from PSoC Designer. PSoC
Programmer software is compatible with both PSoC ICE Cube
In-Circuit Emulator and PSoC MiniProg. It is available free of
charge at http://www.cypress.com/psocprogrammer.
■
Tools CD, which includes:
❐ PSoC Programmer
❐ PSoC Designer
❐ .NET Framework 2.0 (Windows XP 32 bit)
■
Kit Documents (Quick Start, Kit Guide, Release Note, Application Note, Data Sheets, Schematics, and Layouts) Firmware
Evaluation Tools
■
Blue PCA Enclosure/Case
All evaluation tools are sold at the Cypress Online Store.
■
12V 1A Power Supply
CY3261A-RGB EZ-Color RGB Kit
■
Retractable USB Cable (A to Mini-B)
The CY3261A-RGB board is a preprogrammed HB LED color
mix board with seven pre-set colors using the CY8CLED16
EZ-Color HB LED Controller. The board is accompanied by a
CD containing the color selector software application, PSoC
Designer, PSoC Programmer, and a suite of documents,
schematics, and firmware examples. The color selector software
application can be installed on a host PC and is used to control
the EZ-Color HB LED controller using the included USB cable.
The application enables you to select colors via a CIE 1931 chart
or by entering coordinates. The kit includes:
■
PSoC MiniProg Programmer
■
Quick Start Guide
PSoC Designer™
CY3210-MiniProg1
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
Training Board (CY8CLED16)
■
MiniEval Socket Programming and Evaluation Board
■
One mini-A to mini-B USB Cable
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
■
PSoC Designer CD-ROM
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
■
Design Files and Application Installation CD-ROM
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
To program and tune this kit via PSoC Designer you must use a
Mini Programmer Unit (CY3217 Kit) and a CY3240-I2CUSB kit.
CY3263-ColorLock Evaluation Board
■
Tools CD, which includes:
❐ PSoC Programmer
❐ .NET Framework 2.0 (for Windows 2000 and Windows XP)
❐ PSoC Designer
❐ ColorLock Express Pack
❐ CY3263-ColorLock EZ-Color Kit CD
❐ ColorLock Monitor Application
❐ Kit Documents (Quick Start, Kit Guide, Release Note, Application Note, Data Sheets, Schematics, and Layouts)
❐ Firmware
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit
includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
Retractable USB Cable (A to Mini-B)
■
PSoC Designer Software CD
■
PSoC MiniProg Programmer
■
Getting Started Guide
■
Power Supply Adapter
■
USB 2.0 Cable
Document Number: 001-13105 Rev. *C
Page 39 of 43
[+] Feedback
CY8CLED16
Device Programmers
CY3207ISSP In-System Serial Programmer (ISSP)
All device programmers are purchased from the Cypress Online
Store.
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
Modular Programmer Base
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
Three Programming Module Cards
■
USB 2.0 Cable
■
MiniProg Programming Unit
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
Accessories (Emulation and Programming)
Table 36. Emulation and Programming Accessories
Part No.
Flex-Pod Kit[19]
Pin Package
Foot Kit[20]
Adapter[21]
CY8CLED16-28PVXI
28 SSOP
CY3250-LED16
CY8CLED16-48PVXI
48 SSOP
CY3250-LED16
CY3250-28SSOP-FK Adapters can be found at
CY3250-48SSOP-FK http://www.emulation.com.
CY8CLED16-48LFXI
48 QFN
CY3250-LED16QFN
CY3250-48QFN-FK
Third Party Tools
Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and
production. Specific details for each of these tools can be found at http://www.cypress.com under Design Support >> Development
Kits/Boards.
Build a PSoC Emulator into Your Board
For details on emulating the circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device,
refer to application note AN2323 “Build a PSoC Emulator into Your Board”.
Notes
19. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
20. Foot kit includes surface mount feet that can be soldered to the target PCB.
21. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at
http://www.emulation.com.
Document Number: 001-13105 Rev. *C
Page 40 of 43
[+] Feedback
CY8CLED16
Ordering Information
Key Device Features
The following table lists the CY8CLED16 EZ-Color devices’ key package features and ordering codes.
RAM
(Bytes)
Switch Mode
Pump
Temperature
Range
Digital PSoC
Blocks
Analog PSoC
Blocks
Digital I/O
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
CY8CLED16-28PVXI
CY8CLED16-28PVXIT
32K
32K
2K
2K
Yes
Yes
-40C to +85C
-40C to +85C
16
16
12
12
24
24
12
12
4
4
Yes
Yes
CY8CLED16-48PVXI
CY8CLED16-48PVXIT
32K
32K
2K
2K
Yes
Yes
-40C to +85C
-40C to +85C
16
16
12
12
44
44
12
12
4
4
Yes
Yes
CY8CLED16-48LFXI
CY8CLED16-48LFXIT
32K
32K
2K
2K
Yes
Yes
-40C to +85C
-40C to +85C
16
16
12
12
44
44
12
12
4
4
Yes
Yes
CY8CLED16-48LTXI
CY8CLED16-48LTXIT
32K
32K
2K
2K
Yes
Yes
-40C to +85C
-40C to +85C
16
16
12
12
44
44
12
12
4
4
Yes
Yes
Package
Ordering
Code
Flash
(Bytes)
Table 37. Device Key Features and Ordering Information
28 Pin (210 Mil) SSOP
28 Pin (210 Mil) SSOP
(Tape and Reel)
48 Pin (300 Mil) SSOP
48 Pin (300 Mil) SSOP
(Tape and Reel)
48 Pin QFN (Punched)
48 Pin QFN
(Tape and Reel) (Punched)
48 Pin QFN (Sawn)
48 Pin QFN
(Tape and Reel) (Sawn)
Ordering Code Definitions
CY 8 C LED
xx - xx xxxx
Package Type:
Thermal Rating:
PX = PDIP Pb-Free
C = Commercial
SX = SOIC Pb-Free
I = Industrial
PVX = SSOP Pb-Free
E = Extended
LFX/LKX = QFN Pb-Free
AX = TQFP Pb-Free
Pin Count
Part Number
LED Family Code
Technology Code: C = CMOS
Marketing Code: 8 = Cypress PSoC
Company ID: CY = Cypress
Document Number: 001-13105 Rev. *C
Page 41 of 43
[+] Feedback
CY8CLED16
Document History Page
Document Title: CY8CLED16 EZ-Color™ HB LED Controller
Document Number: 001-13105
ECN No
Origin of
Change
Submission
Date
**
1148504
SFVTMP3
See ECN
*A
2763950
DPT
09/29/2009
Added 48QFN package diagram (Sawn).
Added Saw Marketing part number in ordering information.
*B
2794355
XBM
10/28/2009
Added “Contents” on page 3
Updated “Development Tools” on page 7.
Corrected FCPU1 and FCPU2 parameters in “AC Chip Level Specifications” on page 27.
*C
2850593
FRE
01/14/2010
Updated DC GPIO, AC Chip-Level, and AC Programming Specifications
as follows:
Replaced TRAMP (time) with SRPOWER_UP (slew rate) specification.
Added note to Flash Endurance specification.
Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL,
TPROGRAM_HOT, and TPROGRAM_COLD specifications.
Corrected the Pod Kit part numbers.
Updated Development Tool Selection.
Updated copyright and Sales, Solutions, and Legal Information URLs.
Updated 28-Pin SSOP 48-Pin QFN (Punched), 48-Pin QFN (Sawn)
package diagrams.
Removed Preliminary for Final status.
Revision
Document Number: 001-13105 Rev. *C
Description of Change
New document (revision **).
Page 42 of 43
[+] Feedback
CY8CLED16
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC® Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/go/memory
cypress.com/go/image
cypress.com/go/psoc
cypress.com/go/touch
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2008-2009, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products
for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-13105 Rev. *C
Revised January 15, 2010
Page 43 of 43
PSoC Designer™ and EZ-Color™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
[+] Feedback