LINER LTC2480CMS-PBF 16-bit î î£ adc with easy drive input current cancellation Datasheet

LTC2480
16-Bit ΔΣ ADC with Easy Drive
Input Current Cancellation
FEATURES
DESCRIPTION
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The LTC®2480 combines a 16-bit plus sign No Latency
ΔΣ™ analog-to-digital converter with patented Easy Drive™
technology. The patented sampling scheme eliminates
dynamic input current errors and the shortcomings of onchip buffering through automatic cancellation of differential
input current. This allows large external source impedances
and input signals, with rail-to-rail input range to be directly
digitized while maintaining exceptional DC accuracy.
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Easy Drive Technology Enables Rail-to-Rail Inputs
with Zero Differential Input Current
Directly Digitizes High Impedance Sensors with
Full Accuracy
Programmable Gain from 1 to 256
Integrated Temperature Sensor
GND to VCC Input/Reference Common Mode Range
Programmable 50Hz, 60Hz or Simultaneous
50Hz/60Hz Rejection Mode
2ppm (0.25LSB) INL, No Missing Codes
1ppm Offset and 15ppm Full-Scale Error
Selectable 2x Speed Mode (15Hz Using Internal
Oscillator)
No Latency: Digital Filter Settles in a Single Cycle
Single Supply 2.7V to 5.5V Operation
Internal Oscillator
Available in a Tiny (3mm × 3mm) 10-Lead
DFN Package and 10-Lead MSOP Package
APPLICATIONS
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Direct Sensor Digitizer
Weight Scales
Direct Temperature Measurement
Strain Gauge Transducers
Instrumentation
Industrial Process Control
DVMs and Meters
The LTC2480 includes on-chip programmable gain, a
temperature sensor and an oscillator. The LTC2480 can
be conﬁgured to provide a programmable gain from 1
to 256 in 8 steps, measure an external signal or internal
temperature sensor and reject line frequencies. 50Hz, 60Hz
or simultaneous 50Hz/60Hz line frequency rejection can
be selected as well as a 2x speed-up mode.
The LTC2480 allows a wide common mode input range
(0V to VCC) independent of the reference voltage. The
reference can be as low as 100mV or can be tied directly
to VCC. The LTC2480 includes an on-chip trimmed oscillator eliminating the need for external crystals or oscillators. Absolute accuracy and low drift are automatically
maintained through continuous, transparent, offset and
full-scale calibration.
L, LT, LTC and LTM, Linear Technology and the Linear logo are registered trademarks and
No Latency ΔΣ and Easy Drive are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Patents pending.
TYPICAL APPLICATION
+FS Error vs RSOURCE at IN+ and IN–
VCC
10k
IDIFF = 0
VIN+
1μF
SENSE
VREF
VCC
SDO
LTC2480
SCK
VIN–
10k
SDI
GND
fO
CS
4-WIRE
SPI INTERFACE
+FS ERROR (ppm)
1μF
80
VCC = 5V
= 5V
60 VREF
VIN+ = 3.75V
– = 1.25V
V
IN
40
fO = GND
T
20 A = 25°C
CIN = 1μF
0
–20
–40
2480 TA01
–60
–80
1
10
100
1k
RSOURCE (Ω)
10k
100k
2480 TA04
2480fc
1
LTC2480
ABSOLUTE MAXIMUM RATINGS (Notes 1, 2)
Supply Voltage (VCC) to GND ...................... –0.3V to 6V
Analog Input Voltage to GND ....... –0.3V to (VCC + 0.3V)
Reference Input Voltage to GND .. –0.3V to (VCC + 0.3V)
Digital Input Voltage to GND ........ –0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ...... –0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2480C ............................................... 0°C to 70°C
LTC2480I ............................................ –40°C to 85°C
LTC2480H ........................................ –40°C to 125°C
Storage Temperature Range.................. –65°C to 125°C
PIN CONFIGURATION
TOP VIEW
SDI
1
10 fO
VCC
2
9 SCK
VREF
3
IN+
4
7 SDO
IN–
5
6 CS
11
GND
TOP VIEW
SDI
VCC
VREF
IN+
IN–
8 GND
1
2
3
4
5
10
9
8
7
6
fO
SCK
GND
SDO
CS
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 120°C/W
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2480CDD#PBF
LTC2480CDD#TRPBF
LBJY
10-Lead (3mm × 3mm) Plastic DFN
0°C to 70°C
LTC2480IDD#PBF
LTC2480IDD#TRPBF
LBJY
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 85°C
LTC2480CMS#PBF
LTC2480CMS#TRPBF
LTCWB
10-Lead Plastic MSOP
0°C to 70°C
LTC2480IMS#PBF
LTC2480IMS#TRPBF
LTCWB
10-Lead Plastic MSOP
–40°C to 85°C
LTC2480HDD#PBF
LTC2480HDD#TRPBF
LBJY
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC2480HMS#PBF
LTC2480HMS#TRPBF
LTCWB
10-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/
2480fc
2
LTC2480
ELECTRICAL CHARACTERISTICS (NORMAL SPEED) The l denotes the speciﬁcations which
apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
Resolution (No Missing Codes)
0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
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Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
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2
1
10
Offset Error
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14)
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0.5
2.5
Offset Error Drift
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC
Positive Full-Scale Error
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF (H-Grade)
Positive Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
Negative Full-Scale Error
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF (H-Grade)
Negative Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
0.1
ppm of
VREF/°C
Total Unadjusted Error
5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
15
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise
5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN– = IN+ ≤ VCC (Note 13)
0.6
μVRMS
Internal PTAT Signal
TA = 27°C
420
mV
1.4
mV/°C
16
Bits
10
l
l
0.1
l
l
1
μV
ppm of VREF
ppm of VREF
ppm of
VREF/°C
25
40
l
Programmable Gain
ppm of VREF
ppm of VREF
nV/°C
25
40
Internal PTAT Temperature Coefﬁcient
UNITS
ppm of VREF
ppm of VREF
256
ELECTRICAL CHARACTERISTICS (2X SPEED) The l denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
MIN
TYP
MAX
Resolution (No Missing Codes)
0.1 ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5)
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Integral Nonlinearity
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
l
Offset Error
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 14)
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Offset Error Drift
2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC
Positive Full-Scale Error
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF (H-Grade)
Positive Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
Negative Full-Scale Error
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF (H-Grade)
Negative Full-Scale Error Drift
2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF , IN– = 0.25VREF
0.1
ppm of
VREF/°C
Output Noise
5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN– = IN+ ≤ VCC (Note 13)
0.84
μVRMS
Programmable Gain
(Note 15)
16
Bits
2
1
10
0.5
2
100
l
l
25
40
l
l
mV
ppm of VREF
ppm of VREF
ppm of
VREF/°C
25
40
1
ppm of VREF
ppm of VREF
nV/°C
0.1
l
UNITS
ppm of VREF
ppm of VREF
128
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LTC2480
CONVERTER CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Notes 3, 4)
PARAMETER
CONDITIONS
Input Common Mode Rejection DC
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5)
l
MIN
140
TYP
MAX
UNITS
dB
Input Common Mode Rejection
50Hz ±2%
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5)
l
140
dB
Input Common Mode Rejection
60Hz ±2%
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5)
l
140
dB
Input Normal Mode Rejection
50Hz ±2%
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2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 7)
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 7) (H-Grade) l
110
104
120
dB
dB
Input Normal Mode Rejection
60Hz ±2%
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2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 8)
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 8) (H-Grade) l
110
104
120
dB
dB
Input Normal Mode Rejection
50Hz/60Hz ±2%
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Notes 5, 9)
l
87
Reference Common Mode
Rejection DC
2.5V ≤ VREF ≤ VCC, GND ≤ IN– = IN+ ≤ VCC (Note 5)
l
120
Power Supply Rejection DC
dB
140
dB
VREF = 2.5V, IN– = IN+ = GND
120
dB
Power Supply Rejection, 50Hz ±2%
VREF = 2.5V, IN– = IN+ = GND (Notes 7, 9)
120
dB
Power Supply Rejection, 60Hz ±2%
= 2.5V, IN– = IN+ = GND (Notes 8, 9)
120
dB
VREF
ANALOG INPUT AND REFERENCE The l denotes the speciﬁcations which apply over the full operating
temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IN+
Absolute/Common Mode IN+ Voltage
CONDITIONS
MIN
GND – 0.3V
VCC + 0.3V
V
IN–
Absolute/Common Mode IN– Voltage
GND – 0.3V
VCC + 0.3V
V
FS
Full-Scale of the Differential Input (IN+ – IN–)
l
0.5VREF/GAIN
TYP
MAX
UNITS
V
LSB
Least Signiﬁcant Bit of the Output Code
l
FS/216
VIN
Input Differential Voltage Range (IN+ – IN–)
l
–FS
+FS
V
VREF
Reference Voltage Range
l
0.1
VCC
V
(IN+)
IN+ Sampling Capacitance
11
pF
CS (IN–)
IN– Sampling Capacitance
11
pF
CS
CS (VREF)
VREF Sampling Capacitance
IDC_LEAK (IN+)
IN+ DC Leakage Current
Sleep Mode, IN+ = GND
l
–10
1
10
nA
IDC_LEAK (IN–)
IN– DC Leakage Current
Sleep Mode, IN– = GND
l
–10
1
10
nA
Sleep Mode, VREF = VCC
l
–100
1
100
nA
IDC_LEAK (VREF)
VREF DC Leakage Current
11
pF
ANALOG INPUTS AND DIGITAL OUTPUTS
The l denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage CS, fO, SDI
2.7V ≤ VCC ≤ 5.5V
l
VIL
Low Level Input Voltage CS, fO, SDI
2.7V ≤ VCC ≤ 5.5V
l
VIH
High Level Input Voltage SCK
2.7V ≤ VCC ≤ 5.5V (Note 10)
l
VIL
Low Level Input Voltage SCK
2.7V ≤ VCC ≤ 5.5V (Note 10)
l
IIN
Digital Input Current CS, fO, SDI
0V ≤ VIN ≤ VCC
l
TYP
MAX
VCC – 0.5
V
0.5
VCC – 0.5
–10
UNITS
V
V
0.5
V
10
μA
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LTC2480
ANALOG INPUTS AND DIGITAL OUTPUTS
The l denotes the speciﬁcations which apply over the
full operating temperature range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
IIN
Digital Input Current SCK
CIN
Digital Input Capacitance CS, fO, SDI
CONDITIONS
0V ≤ VIN ≤ VCC (Note 10)
MIN
l
CIN
Digital Input Capacitance SCK
VOH
High Level Output Voltage SDO
IO = –800μA
l
VOL
Low Level Output Voltage SDO
IO = 1.6mA
l
VOH
High Level Output Voltage SCK
IO = –800μA
l
VOL
Low Level Output Voltage SCK
IO = 1.6mA
l
IOZ
Hi-Z Output Leakage SDO
TYP
–10
MAX
UNITS
10
μA
10
pF
10
pF
VCC – 0.5
V
0.4
V
0.4
V
10
μA
VCC – 0.5
l
V
–10
POWER REQUIREMENTS The l denotes the speciﬁcations which apply over the full operating temperature
range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
l
Supply Current
l
l
l
ICC
CONDITIONS
Conversion Mode (Note 12)
Sleep Mode (Note 12)
H-Grade
MIN
TYP
2.7
160
1
MAX
UNITS
5.5
V
250
2
20
μA
μA
μA
TIMING CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating temperature
range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
fEOSC
External Oscillator Frequency Range
(Note 15)
MAX
UNITS
l
tHEO
MIN
10
4000
kHz
External Oscillator High Period
l
0.125
100
μs
tLEO
External Oscillator Low Period
l
0.125
100
tCONV_1
Conversion Time for 1x Speed Mode
50Hz Mode
50Hz Mode (H-Grade)
60Hz Mode
60Hz Mode (H-Grade)
Simultaneous 50Hz/60Hz Mode
Simultaneous 50Hz/60Hz Mode (H-Grade)
External Oscillator
l
l
l
l
l
l
l
163.5
160.3
157.2
165.1
160.3
157.2
136.3
133.6
131.0
137.6
133.6
131.0
149.9
146.9
144.1
151.0
146.9
144.1
41036/fEOSC (in kHz)
ms
ms
ms
ms
ms
ms
ms
tCONV_2
Conversion Time for 2x Speed Mode
50Hz Mode
50Hz Mode (H-Grade)
60Hz Mode
60Hz Mode (H-Grade)
Simultaneous 50Hz/60Hz Mode
Simultaneous 50Hz/60Hz Mode (H-Grade)
External Oscillator
l
l
l
l
l
l
l
78.7
80.3
65.6
66.9
72.2
73.6
20556/fEOSC (in kHz)
ms
ms
ms
ms
ms
ms
ms
38.4
fEOSC/8
kHz
kHz
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
l
fESCK
External SCK Frequency Range
(Note 10)
l
45
TYP
81.9
82.7
68.2
68.9
75.1
75.6
μs
55
%
4000
kHz
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LTC2480
TIMING CHARACTERISTICS
The l denotes the speciﬁcations which apply over the full operating temperature
range, otherwise speciﬁcations are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
tLESCK
External SCK Low Period
(Note 10)
l
MIN
tHESCK
External SCK High Period
(Note 10)
l
125
tDOUT_ISCK
Internal SCK 24-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
l
l
0.61
(Note 10)
l
TYP
MAX
125
UNITS
ns
ns
0.625
0.64
192/fEOSC (in kHz)
ms
ms
24/fESCK (in kHz)
ms
tDOUT_ESCK
External SCK 24-Bit Data Output Time
t1
CS↓ to SDO Low
l
0
200
ns
t2
CS↑ to SDO High Z
l
0
200
ns
t3
CS↓ to SCK↓
Internal SCK Mode
l
0
200
t4
CS↓ to SCK↑
External SCK Mode
l
50
tKQMAX
SCK↓ to SDO Valid
tKQMIN
SDO Hold After SCK↓
t5
l
(Note 5)
200
l
15
50
ns
ns
ns
ns
SCK Set-Up Before CS↓
l
t6
SCK Hold After CS↓
l
t7
SDI Setup Before SCK↑
(Note 5)
l
100
ns
t8
SDI Hold After SCK↑
(Note 5)
l
100
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise speciﬁed.
VREFCM = VREF/2, FS = 0.5VREF/GAIN
VIN = IN+ – IN–, VIN(CM) = (IN+ + IN–)/2
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless otherwise speciﬁed.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is deﬁned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external
oscillator).
ns
50
ns
Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external
oscillator).
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =
280kHz ±2% (external oscillator).
Note 10: The SCK can be conﬁgured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as digital input and the
driving clock is fESCK. In internal SCK mode, the SCK pin is used as digital
output and the output clock signal during the data output is fISCK.
Note 11: The external oscillator is connected to the fO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: Refer to Applications Information section for performance vs
data rate graphs.
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LTC2480
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
2
25°C
0
85°C
–1
–2
1
–45°C, 25°C, 90°C
0
–1
–2
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
2
–0.75
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
12
8
4
0
VCC = 5V
VREF = 5V
VIN(CM) = 1.25V
fO = GND
85°C
25°C
TUE (ppm OF VREF)
TUE (ppm OF VREF)
8
–45°C
–4
–8
2
12
85°C
8
–45°C
0
–4
Noise Histogram (6.8sps)
12
12
NUMBER OF READINGS (%)
2
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
1.2
1.8
2480 G07
85°C
–45°C
–4
–12
–1.25
1.25
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
1.25
2480 G03
Long-Term ADC Readings
5
VCC = 5V, VREF = 5V, VIN = 0V, VIN(CM) = 2.5V
4 GAIN = 256, TA = 25°C, RMS NOISE = 0.60μV
10,000 CONSECUTIVE
READINGS
RMS = 0.59μV
VCC = 2.7V
AVERAGE = –0.19μV
VREF = 2.5V
10 VIN = 0V
GAIN = 256
8 TA = 25°C
3
6
4
2
1
0
–1
–2
–3
2
0
25°C
0
Noise Histogram (7.5sps)
14
–3 –2.4 –1.8 –1.2 –0.6 0 0.6
OUTPUT READING (μV)
4
2480 G02
14
4
1.25
2480 G06
–8
2480 G01
6
–0.25
0.25
0.75
INPUT VOLTAGE (V)
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
25°C
4
–12
–1.25
2.5
10,000 CONSECUTIVE
READINGS
RMS = 0.60μV
VCC = 5V
AVERAGE = –0.69μV
VREF = 5V
10 VIN = 0V
GAIN = 256
8 TA = 25°C
–0.75
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
–8
–12
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
NUMBER OF READINGS (%)
–1
2480 G05
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
–45°C, 25°C, 90°C
0
–3
–1.25
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
2480 G04
12
1
–2
–3
–1.25
2.5
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
2
INL (ppm OF VREF)
–45°C
3
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
TUE (ppm OF VREF)
1
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
ADC READING (μV)
INL (ppm OF VREF)
2
3
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
INL (ppm OF VREF)
3
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
–4
–5
0
–3 –2.4 –1.8 –1.2 –0.6 0 0.6
OUTPUT READING (μV)
1.2
1.8
2480 G08
0
10
30
40
20
TIME (HOURS)
50
60
2480 G09
2480fc
7
LTC2480
TYPICAL PERFORMANCE CHARACTERISTICS
RMS Noise
vs Input Differential Voltage
0.8
VCC = 5V
VREF = 5V
GAIN = 256
VIN(CM) = 2.5V
TA = 25°C
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
GAIN = 256
TA = 25°C
0.9
0.7
0.6
0.5
1.0
0.8
0.7
0.6
–1
0
2
1
3
5
4
OFFSET ERROR (ppm OF VREF)
0.6
0.8
0.7
0.6
0.5
0.5
3.5
3.9 4.3
VCC (V)
4.7
5.1
0
5.5
1
2
3
VREF (V)
0
–0.1
–0.2
0 15 30 45 60
TEMPERATURE (°C)
–0.1
–0.2
–1
75
90
2480 G16
0
1
3
2
VIN(CM) (V)
5
4
0.2
0.1
Offset Error vs VREF
0.3
REF+ = 2.5V
– = GND
REF
VIN = 0V
VIN(CM) = GND
GAIN = 256
TA = 25°C
0
VCC = 5V
REF– = GND
VIN = 0V
VIN(CM) = GND
GAIN = 256
TA = 25°C
0.2
0.1
0
–0.1
–0.1
–0.2
–0.3
2.7
6
2480 G15
OFFSET ERROR (ppm OF VREF)
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
–0.3
–45 –30 –15
0
Offset Error vs VCC
0.3
OFFSET ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
0.1
0.1
2480 G14
Offset Error vs Temperature
0.2
0.2
5
4
2480 G13
0.3
VCC = 5V
VREF = 5V
VIN = 0V
GAIN = 256
TA = 25°C
–0.3
0.4
3.1
90
Offset Error vs VIN(CM)
0.3
VCC = 5V
VIN = 0V
VIN(CM) = GND
GAIN = 256
TA = 25°C
0.9
0.7
75
2480 G12
RMS Noise vs VREF
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
GAIN = 256
TA = 25°C
0 15 30 45 60
TEMPERATURE (°C)
2480 G11
1.0
0.4
2.7
0.4
–45 –30 –15
6
VIN(CM) (V)
RMS NOISE (μV)
RMS NOISE (μV)
0.8
0.6
0.4
2.5
RMS Noise vs VCC
0.9
0.7
0.5
2480 G10
1.0
0.8
0.5
0.4
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5 2
INPUT DIFFERENTIAL VOLTAGE (V)
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
GAIN = 256
0.9
RMS NOISE (μV)
RMS NOISE (ppm OF VREF)
0.9
RMS Noise vs Temperature (TA)
RMS Noise vs VIN(CM)
1.0
RMS NOISE (μV)
1.0
–0.2
3.1
3.5
3.9 4.3
VCC (V)
4.7
5.1
5.5
2480 G17
–0.3
0
1
2
3
VREF (V)
4
5
2480 G18
2480fc
8
LTC2480
TYPICAL PERFORMANCE CHARACTERISTICS
Temperature Sensor
vs Temperature
5
VPTAT/VREF (V)
0.30
0.25
310
VCC = 5V
fO = GND
4
0.35
On-Chip Oscillator Frequency
vs Temperature
308
3
2
FREQUENCY (kHz)
VCC = 5V
VREF = 1.4V
fO = GND
TEMPERATURE ERROR (°C)
0.40
Temperature Sensor Error
vs Temperature
VREF = 1.4V
1
0
–1
–2
306
304
302
–3
–4
–30
0
30
60
TEMPERATURE (°C)
90
–5
–60
120
–30
30
60
0
TEMPERATURE (°C)
On-Chip Oscillator Frequency
vs VCC
304
302
2.5
3.0
3.5
4.0
VCC (V)
4.5
5.0
5.5
–20
–40
REJECTION (dB)
REJECTION (dB)
FREQUENCY (kHz)
306
300
–40
–60
–80
–120
–120
10
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
2480 G27
–140
200
CONVERSION CURRENT (μA)
VCC = 4.1V DC ±0.7V
= 2.5V
V
–20 INREF
+ = GND
– = GND
IN
–40 fO = GND
TA = 25°C
–60
–80
–100
–120
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
2480 G29
Conversion Current
vs Temperature
0
REJECTION (dB)
1M
2480 G28
PSRR vs Frequency at VCC
–140
30600
–80
–100
1
VCC = 4.1V DC ±1.4V
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
–60
–100
–140
180
90
PSRR vs Frequency at VCC
0
VCC = 4.1V DC
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
–20
75
2480 G26
PSRR vs Frequency at VCC
0
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
308
0 15 30 45 60
TEMPERATURE (°C)
2480 G25
2480 G24
310
300
–45 –30 –15
120
90
Sleep Mode Current
vs Temperature
2.0
fO = GND
CS = GND
SCK = NC
SDO = NC
SDI = GND
SLEEP MODE CURRENT (μA)
0.20
–60
VCC = 4.1V
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
VCC = 5V
160
140
VCC = 2.7V
120
fO = GND
1.8 CS = V
CC
1.6 SCK = NC
SDO = NC
1.4 SDI = GND
1.2
VCC = 5V
1.0
0.8
0.6
VCC = 2.7V
0.4
0.2
30650
30700
30750
FREQUENCY AT VCC (Hz)
30800
2480 G30
100
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2480 G31
0
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2480 G32
2480fc
9
LTC2480
TYPICAL PERFORMANCE CHARACTERISTICS
400
350
300
2
VCC = 5V
VCC = 3V
250
1
25°C, 90°C
0
–1
200
90°C
0
–45°C, 25°C
–1
–2
–3
–2.5 –2 –1.5 –1 –0.5 0 0.5 1 1.5
INPUT VOLTAGE (V)
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2480 G33
NUMBER OF READINGS (%)
90°C
0
–45°C, 25°C
–2
RMS = 0.86μV
10,000 CONSECUTIVE
AVERAGE = 0.184mV
14 READINGS
VCC = 5V
12 VREF = 5V
VIN = 0V
GAIN = 256
10
TA = 25°C
8
6
0.8
4
0.6
0.4
VCC = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
TA = 25°C
0.2
0
0
179
1.25
–0.25
0.25
0.75
INPUT VOLTAGE (V)
181.4
183.8
188.6
186.2
OUTPUT READING (μV)
2480 G36
240
VCC = 5V
VREF = 5V
VIN = 0V
FO = GND
TA = 25°C
230
OFFSET ERROR (μV)
OFFSET ERROR (μV)
194
1
3
2
VREF (V)
4
5
2480 G38
Offset Error vs Temperature
(2x Speed Mode)
200
196
0
2480 G37
Offset Error vs VIN(CM)
(2x Speed Mode)
198
1.25
1.0
2
–0.75
–0.25
0.25
0.75
INPUT VOLTAGE (V)
RMS Noise vs VREF
(2x Speed Mode)
16
1
–0.75
2480 G35
Noise Histogram
(2x Speed Mode)
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
–3
–1.25
–3
–1.25
2.5
2480 G34
Integral Nonlinearity (2x Speed
Mode; VCC = 2.7V, VREF = 2.5V)
–1
2
RMS NOISE (μV)
0
INL (ppm OF VREF)
1
–45°C
100
2
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
FO = GND
2
–2
150
3
3
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
FO = GND
INL (ppm OF VREF)
450
SUPPLY CURRENT (μA)
3
VREF = VCC
IN+ = GND
IN– = GND
SCK = NC
SDO = NC
SDI = GND
CS GND
FO = EXT OSC
TA = 25°C
INL (ppm OF VREF)
500
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 2.5V)
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 5V)
Conversion Current
vs Output Data Rate
192
190
188
186
220
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
FO = GND
210
200
190
180
184
170
182
180
–1
0
1
3
VIN(CM) (V)
2
4
5
6
2480 G39
160
–45 –30 –15
0 15 30 45 60
TEMPERATURE (°C)
75
90
2480 G40
2480fc
10
LTC2480
TYPICAL PERFORMANCE CHARACTERISTICS
Offset Error vs VREF
(2x Speed Mode)
250
VCC = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
230
OFFSET ERROR (μV)
OFFSET ERROR (μV)
200
0
240
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
150
100
PSRR vs Frequency at VCC
(2x Speed Mode)
220
–40
210
200
190
2
2.5
3
4
3.5
VCC (V)
4.5
5.5
5
160
–140
1
0
2
4
3
VREF (V)
–60
1M
2480 G43
0
VCC = 4.1V DC ±1.4V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
VCC = 4.1V DC ±0.7V
REF+ = 2.5V
REF– = GND
IN+ = GND
–40 IN– = GND
fO = GND
–60 TA = 25°C
–20
–80
–80
–100
–100
–120
–120
–140
10k 100k
1k
100
FREQUENCY AT VCC (Hz)
PSRR vs Frequency at VCC
(2x Speed Mode)
REJECTION (dB)
RREJECTION (dB)
–40
10
2480 G42
PSRR vs Frequency at VCC
(2x Speed Mode)
–20
1
5
2480 G41
0
–80
–120
170
0
–60
–100
180
50
VCC = 4.1V DC
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
–20
REJECTION (dB)
Offset Error vs VCC
(2x Speed Mode)
0 20 40 60 80 100 120 140 160 180 200 220
FREQUENCY AT VCC (Hz)
2480 G44
–140
30600
30650
30700
30750
FREQUENCY AT VCC (Hz)
30800
2480 G45
PIN FUNCTIONS
SDI (Pin 1): Serial Data Input. This pin is used to select
the GAIN, line frequency rejection, input, temperature
sensor and 2x speed mode. Data is shifted into the SDI
pin on the rising edge of serial clock (SCK).
VCC (Pin 2): Positive Supply Voltage. Bypass to GND (Pin 8)
with a 1μF tantalum capacitor in parallel with 0.1μF ceramic
capacitor as close to the part as possible.
VREF (Pin 3): Positive Reference Input. The voltage on
this pin can have any value between 0.1V and VCC. The
negative reference input is GND (Pin 8).
IN+ (Pin 4), IN– (Pin 5): Differential Analog Inputs. The
voltage on these pins can have any value between GND
– 0.3V and VCC + 0.3V. Within these limits the converter
bipolar input range (VIN = IN+ – IN–) extends from –0.5
• VREF/GAIN to 0.5 • VREF/GAIN. Outside this input range
the converter produces unique overrange and underrange
output codes.
CS (Pin 6): Active LOW Chip Select. A LOW on this pin
enables the digital input/output and wakes up the ADC.
Following each conversion the ADC automatically enters
the sleep mode and remains in this low power state as
2480fc
11
LTC2480
PIN FUNCTIONS
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the data output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 7): Three-State Digital Output. During the data
output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = VCC), the SDO pin
is in a high impedance state. During the conversion and
sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
data input/output period. In external serial clock operation
mode, SCK is used as the digital input for the external serial interface clock during the data output period. A weak
internal pull-up is automatically activated in internal serial
clock operation mode. The serial clock operation mode
is determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
GND (Pin 8): Ground. Shared pin for analog ground, digital
ground and reference ground. Should be connected directly
to a ground plane through a minimum impedance.
fO (Pin 10): Frequency Control Pin. Digital input that
controls the conversion clock. When fO is connected to
GND the converter uses its internal oscillator running at
307.2kHz. The conversion clock may also be overridden by
driving the fO pin with an external clock in order to change
the output rate or the digital ﬁlter rejection null.
SCK (Pin 9): Bidirectional Digital Clock Pin. In internal
serial clock operation mode, SCK is used as the digital
output for the internal serial interface clock during the
GND (Exposed Pad Pin 11): This pin is ground and should
be soldered to the PCB ground plane. For prototyping
purposes, this pin may remain ﬂoating.
FUNCTIONAL BLOCK DIAGRAM
2
3
4
5
VREF
VCC
IN+
IN+
IN–
3RD ORDER
$3 ADC
–
(1-256)
IN
REF–
GAIN
MUX
TEMP
SENSOR
SDI
REF+
SCK
SERIAL
INTERFACE
SD0
CS
FO
AUTOCALIBRATION
AND CONTROL
GND
1
9
7
6
10
INTERNAL
OSCILLATOR
8
2480 FD
TEST CIRCUITS
VCC
1.69k
SDO
SDO
1.69k
Hi-Z TO VOH
VOL TO VOH
VOH TO Hi-Z
CLOAD = 20pF
2480 TA02
CLOAD = 20pF
Hi-Z TO VOL
VOH TO VOL
VOL TO Hi-Z
2480 TA03
2480fc
12
LTC2480
TIMING DIAGRAMS
Timing Diagram Using Internal SCK
CS
t1
t2
SDO
tKQMIN
t3
tKQMAX
SCK
t7
t8
SDI
2480 TD1
SLEEP
DATA IN/OUT
CONVERSION
Timing Diagram Using External SCK
CS
t1
t2
SDO
t5
tKQMIN
t6
t4
tKQMAX
SCK
t7
t8
SDI
2480 TD2
SLEEP
DATA IN/OUT
CONVERSION
APPLICATIONS INFORMATION
CONVERTER OPERATION
CONVERT
Converter Operation Cycle
The LTC2480 is a low power, delta-sigma analog-to-digital converter with an easy to use 4-wire serial interface
and automatic differential input current cancellation.
Its operation is made up of three states. The converter
operating cycle begins with the conversion, followed by
the low power sleep state and ends with the data output
(see Figure 1). The 4-wire interface consists of serial data
output (SDO), serial clock (SCK), chip select (CS) and
serial data input (SDI).
Initially, the LTC2480 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
SLEEP
FALSE
CS = LOW
AND
SCK
TRUE
DATA OUTPUT
CONFIGURATION INPUT
2480 F01
Figure 1. LTC2480 State Transition Diagram
2480fc
13
LTC2480
APPLICATIONS INFORMATION
While in this sleep state, power consumption is reduced
by two orders of magnitude. The part remains in the sleep
state as long as CS is HIGH. The conversion result is held
indeﬁnitely in a static shift register while the converter is
in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the ﬁrst rising edge of SCK, the device returns to
the low power sleep mode and the conversion result is
still held in the internal static shift register. If CS remains
LOW after the ﬁrst rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data input and output state and
start a new conversion. The conversion result is shifted
out of the device through the serial data output pin (SDO)
on the falling edge of the serial clock (SCK) (see Figure 2).
The LTC2480 includes a serial data input pin (SDI) in
which data is latched by the device on the rising edge of
SCK (Figure 2). The bit stream applied to this pin can be
used to select various features of the LTC2480, including
an on-chip temperature sensor, programmable GAIN, line
frequency rejection and output data rate. Alternatively,
this pin may be tied to ground and the part will perform
conversions in a default state. In the default state (SDI
grounded) the device simply performs conversions on
the user applied input with a GAIN of 1 and simultaneous
rejection of 50Hz and 60Hz line frequencies.
Through timing control of the CS and SCK pins, the LTC2480
offers several ﬂexible modes of operation (internal or
external SCK and free-running conversion modes). These
various modes do not require programming conﬁguration
registers; moreover, they do not disturb the cyclic operation
described above. These modes of operation are described
in detail in the Serial Interface Timing Modes section.
Easy Drive Input Current Cancellation
The LTC2480 combines a high precision delta-sigma ADC
with an automatic differential input current cancellation
front end. A proprietary front-end passive sampling
network transparently removes the differential input
current. This enables external RC networks and high
impedance sensors to directly interface to the LTC2480
without external amplifiers. The remaining common
mode input current is eliminated by either balancing
the differential input impedances or setting the common
mode input equal to the common mode reference (see
the Automatic Input Current Cancellation section). This
unique architecture does not require on-chip buffers
enabling input signals to swing all the way to ground
and up to VCC. Furthermore, the cancellation does
not interfere with the transparent offset and full-scale
auto-calibration and the absolute accuracy (full-scale
+ offset + linearity) is maintained even with external
RC networks.
Accessing the Special Features of the LTC2480
The LTC2480 combines a high resolution, low noise ΔΣ
analog-to-digital converter with an on-chip selectable
temperature sensor, programmable gain, programmable
digital ﬁlter and output rate control. These special features
are selected through a single 8-bit serial input word during
the data input/output cycle (see Figure 2).
The LTC2480 powers up in a default mode commonly
used for most measurements. The device will remain in
this mode as long as the serial data input (SDI) is low.
In this default mode, the measured input is external, the
GAIN is 1, the digital ﬁlter simultaneously rejects 50Hz
and 60Hz line frequency noise, and the speed mode is 1x
(offset automatically, continuously calibrated).
A simple serial interface grants access to any or all special
functions contained within the LTC2480. In order to change
the mode of operation, an enable bit (EN) followed by up
to 7 bits of data are shifted into the device (see Table 1).
The ﬁrst 3 bits (GS2, GS1, GS0) control the GAIN of the
converter from 1 to 256. The 4th bit (IM) is used to select
the internal temperature sensor as the conversion input,
while the 5th and 6th bits (FA, FB) combine to determine
the line frequency rejection mode. The 7th bit (SPD) is
used to double the output rate by disabling the offset auto
calibration.
2480fc
14
LTC2480
APPLICATIONS INFORMATION
CS
SDO
Hi-Z
BIT 23
BIT 22
BIT 21
BIT 20
BIT 19
EOC
DMY
SIG
MSB
B16
BIT 18
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
LSB
GS2
GS1
GS0
IM
PREVIOUS
CONFIGURATION BITS
CONVERSION RESULT
SCK
SDI
EN
GS2
GS1
GS0
IM
FA
SLEEP
FB
SPD
DON’T CARE
DATA INPUT/OUTPUT
CONVERSION
2480 F02
Figure 2. Input/Output Data Timing
Table 1. Selecting Special Modes
Gain
EN GS2 GS1 GS0
0 X X X
0 0
0
1
0 1
0
1
1 0
0
1
1 1
0
1
0 0
1
1
0 1
1
1
1 0
1
1
1 1
1
1
0 0
0
1
0 1
0
1
1 0
0
1
1 1
0
1
0 0
1
1
0 1
1
1
1 0
1
1
1 1
1
1
1
1
Any Gain
1
1
1 X X X
1 X X X
1 X X X
1 X X X
Rejection
Mode
IM FA FB SPD
X
X X X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Any
0
0
Rejection
1
0
Mode
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
0
Any
1
0 Speed
0
1
1
0
1
0
0
X
1
0
1
X
1
1
0
X
1
1
1
X
Comments
Keep Previous Mode
External Input, Gain = 1, Autocalibration
External Input, Gain = 4, Autocalibration
External Input, Gain = 8, Autocalibration
External Input, Gain = 16, Autocalibration
External Input, Gain = 32, Autocalibration
External Input, Gain = 64, Autocalibration
External Input, Gain = 128, Autocalibration
External Input, Gain = 256, Autocalibration
External Input, Gain = 1, 2x Speed
External Input, Gain = 2, 2x Speed
External Input, Gain = 4, 2x Speed
External Input, Gain = 8, 2x Speed
External Input, Gain = 16, 2x Speed
External Input, Gain = 32, 2x Speed
External Input, Gain = 64, 2x Speed
External Input, Gain = 128, 2x Speed
External Input, Simultaneous 50Hz/60Hz Rejection
External Input, 50Hz Rejection
External Input, 60Hz Rejection
Reserved, Do Not Use
Temperature Input, 50Hz/60Hz Rejection, Gain = 1, Autocalibration
Temperature Input, 50Hz Rejection, Gain = 1, Autocalibration
Temperature Input, 60Hz Rejection, Gain = 1, Autocalibration
Reserved, Do Not Use
2480 TBL1
2480fc
15
LTC2480
APPLICATIONS INFORMATION
Table 2a. The LTC2480 Performance vs GAIN in Normal Speed Mode (VCC = 5V, VREF = 5V)
GAIN
1
4
8
16
32
64
128
256
Input Span
±2.5
±0.625
±0.312
±0.156
±78m
±39m
±19.5m
±9.76m
V
LSB
38.1
9.54
4.77
2.38
1.19
0.596
0.298
0.149
μV
65536
65536
65536
65536
65536
65536
32768
16384
Counts
Noise Free Resolution*
UNIT
Gain Error
5
5
5
5
5
5
5
8
Offset Error
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ppm of FS
μV
UNIT
Table 2b. The LTC2480 Performance vs GAIN in 2x Speed Mode (VCC = 5V, VREF = 5V)
GAIN
1
2
4
8
16
32
64
128
Input Span
±2.5
±1.25
±0.625
±0.312
±0.156
±78m
±39m
±19.5m
V
LSB
38.1
19.1
9.54
4.77
2.38
1.19
0.596
0.298
μV
Noise Free Resolution*
65536
65536
65536
65536
65536
65536
45875
22937
Gain Error
5
5
5
5
5
5
5
5
Offset Error
200
200
200
200
200
200
200
200
Counts
ppm of FS
μV
*The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger.
GAIN (GS2, GS1, GS0)
Rejection Mode (FA, FB)
The input referred gain of the LTC2480 is adjustable from
1 to 256. With a gain of 1, the differential input range is
±VREF/2 and the common mode input range is rail-to-rail.
As the GAIN is increased, the differential input range is reduced to ±VREF/2 • GAIN but the common mode input range
remains rail-to-rail. As the differential gain is increased,
low level voltages are digitized with greater resolution. At
a gain of 256, the LTC2480 digitizes an input signal range
of ±9.76mV with over 16,000 counts.
The LTC2480 includes a high accuracy on-chip oscillator with no required external components. Coupled with
a 4th order digital lowpass ﬁlter, the LTC2480 rejects
line frequency noise. In the default mode, the LTC2480
simultaneously rejects 50Hz and 60Hz by at least 87dB.
The LTC2480 can also be conﬁgured to selectively reject
50Hz or 60Hz to better than 110dB.
Temperature Sensor (IM)
The LTC2480 includes an on-chip temperature sensor.
The temperature sensor is selected by setting IM = 1 in
the serial input data stream. Conversions are performed
directly on the temperature sensor by the converter. While
operating in this mode, the device behaves as a temperature to bits converter. The digital reading is proportional
to the absolute temperature of the device. This feature
allows the converter to linearize temperature sensors or
continuously remove temperature effects from external
sensors. Several applications leveraging this feature are
presented in more detail in the applications section. While
operating in this mode, the gain is set to 1 and the speed
is set to normal independent of the control bits (GS2,
GS1, GS0 and SPD).
Speed Mode (SPD)
The LTC2480 continuously performs offset calibrations.
Every conversion cycle, two conversions are automatically
performed (default) and the results combined. This result
is free from offset and drift. In applications where the offset
is not critical, the autocalibration feature can be disabled
with the beneﬁt of twice the output rate.
Linearity, full-scale accuracy and full-scale drift are identical for both 2x and 1x speed modes. In both the 1x and
2x speed there is no latency. This enables input steps or
multiplexer channel changes to settle in a single conversion cycle easing system overhead and increasing the
effective conversion rate.
2480fc
16
LTC2480
APPLICATIONS INFORMATION
Output Data Format
The LTC2480 serial output data stream is 24 bits long.
The ﬁrst 3 bits represent status information indicating
the sign and conversion state. The next 17 bits are the
conversion result, MSB ﬁrst. The remaining 4 bits indicate
the conﬁguration state associated with the current conversion result. The third and fourth bit together are also
used to indicate an underrange condition (the differential
input voltage is below –FS) or an overrange condition (the
differential input voltage is above +FS).
In applications where the processor generates 32 clock
cycles, or to remain compatible with higher resolution
converters, the LTC2480’s digital interface will ignore
extra clock edges seen during the next conversion period
after the 24th and output “1” for the extra clock cycles.
Furthermore, CS may be pulled high prior to outputting
all 24 bits, aborting the data out transfer and initiating a
new conversion.
Bit 21 (third output bit) is the conversion result sign
indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0,
this bit is LOW.
Bit 20 (fourth output bit) is the most signiﬁcant bit (MSB) of
the result. This bit in conjunction with bit 21 also provides
the underrange or overrange indication. If both bit 21 and
bit 20 are HIGH, the differential input voltage is above +FS.
If both bit 21 and bit 20 are LOW, the differential input
voltage is below –FS.
The function of these bits is summarized in Table 3.
Table 3. LTC2480 Status Bits
INPUT RANGE
BIT 23
EOC
BIT 22
DMY
BIT 21
SIG
BIT 20
MSB
VIN ≥ 0.5 • VREF
0
0V ≤ VIN < 0.5 • VREF
0
0
1
1
0
1/0
0
–0.5 • VREF ≤ VIN < 0V
0
0
0
1
VIN < –0.5 • VREF
0
0
0
0
Bit 23 (ﬁrst output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bits 20-4 are the 16-bit plus sign conversion result MSB
ﬁrst.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 2). Whenever CS is HIGH,
Bits 3-0 are the corresponding conﬁguration bits for the
present conversion result. Bits 3-1 are the gain set bits
and bit 0 is IM (see Figure 2).
Table 4. LTC2480 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
VIN*
VIN* ≥ FS**
FS** – 1LSB
BIT 23
EOC
0
0
BIT 22
DMY
0
0
BIT 21
SIG
1
1
BIT 20
MSB
1
0
BIT 19
BIT 18
BIT 17
…
BIT 4
0
1
0
1
0
1
…
…
0
1
0.5 • FS**
0.5 • FS** – 1LSB
0
0
0
0
1
1
0
0
1
0
0
1
0
1
…
…
0
1
0
–1LSB
0
0
0
0
1/0***
0
0
1
0
1
0
1
0
1
…
…
0
1
–0.5 • FS**
–0.5 • FS** – 1LSB
0
0
0
0
0
0
1
1
1
0
0
1
0
1
…
…
0
1
…
…
0
1
–FS**
0
0
0
1
0
0
0
0
0
0
0
1
1
1
VIN* < –FS**
* The differential input voltage VIN = IN+ – IN–.
** The full-scale voltage FS = 0.5 • VREF .
*** The sign bit changes state during the 0 output code when the device is operating in the 2× speed mode .
2480fc
17
LTC2480
APPLICATIONS INFORMATION
In order to shift the conversion result out of the device,
CS must ﬁrst be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 23 (EOC) can be captured on the ﬁrst
rising edge of SCK. Bit 22 is shifted out of the device on
the ﬁrst falling edge of SCK. The ﬁnal data bit (bit 0) is
shifted out on the falling edge of the 23rd SCK and may
be latched on the rising edge of the 24th SCK pulse. On
the falling edge of the 24th SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (bit 23) for the next conversion cycle.
Table 4 summarizes the output data format.
As long as the voltage on the IN+ and IN– pins is maintained within the –0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 • VREF/GAIN
to +FS = 0.5 • VREF /GAIN. For differential input voltages
greater than +FS, the conversion result is clamped to the
value corresponding to the +FS + 1LSB. For differential
input voltages below –FS, the conversion result is clamped
to the value corresponding to –FS – 1LSB.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital ﬁlter
(commonly implemented as a SINC or Comb ﬁlter). For
high resolution, low frequency applications, this ﬁlter is
typically designed to reject line frequencies of 50Hz or 60Hz
plus their harmonics. The ﬁlter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2480 incorporates a highly accurate on-chip
oscillator. This eliminates the need for external frequency
setting components such as crystals or oscillators.
Frequency Rejection Selection (fO)
The LTC2480 internal oscillator provides better than 110dB
normal mode rejection at the line frequency and all its
harmonics (up to the 255th) for 50Hz ±2% or 60Hz ±2%,
or better than 87dB normal mode rejection from 48Hz to
62.4Hz. The rejection mode is selected by writing to the
on-chip conﬁguration register and the default mode at
POR is simultaneous 50Hz/60Hz rejection.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2480 can
operate with an external conversion clock. The converter
automatically detects the presence of an external clock
signal at the fO pin and turns off the internal oscillator.
The frequency fEOSC of the external signal must be at least
10kHz to be detected. The external clock signal duty cycle
is not signiﬁcant as long as the minimum and maximum
speciﬁcations for the high and low periods tHEO and tLEO
are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2480 provides better than 110dB
normal mode rejection in a frequency range of fEOSC/5120
±4% and its harmonics. The normal mode rejection as a
function of the input frequency deviation from fEOSC/5120
is shown in Figure 3.
–80
–85
NORMAL MODE REJECTION (dB)
SDO remains high impedance and any externally generated SCK clock pulses are ignored by the internal data
out shift register.
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
–12
–8
–4
0
4
8
12
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%)
2480 F03
Figure 3. LTC2480 Normal Mode Rejection When Using
an External Oscillator
Whenever an external clock is not present at the fO pin,
the converter automatically activates its internal oscillator and enters the internal conversion clock mode. The
LTC2480 operation will not be disturbed if the change of
conversion clock source occurs during the sleep state
or during the data output state while the converter uses
2480fc
18
LTC2480
APPLICATIONS INFORMATION
Table 5. LTC2480 State Duration
STATE
OPERATING MODE
CONVERT
Internal Oscillator
External Oscillator
DURATION
60Hz Rejection
133ms, Output Data Rate ≤ 7.5 Readings/s for 1x Speed Mode
67ms, Output Data Rate ≤ 15 Readings/s for 2x Speed Mode
50Hz Rejection
160ms, Output Data Rate ≤ 6.2 Readings/s for 1x Speed Mode
80ms, Output Data Rate ≤ 12.5 Readings/s for 2x Speed Mode
50Hz/60Hz Rejection
147ms, Output Data Rate ≤ 6.8 Readings/s for 1x Speed Mode
73.6ms, Output Data Rate ≤ 13.6 Readings/s for 2x Speed Mode
fO = External Oscillator
with Frequency fEOSC kHz
(fEOSC/5120 Rejection)
41036/fEOSCs, Output Data Rate ≤ fEOSC/41036 Readings/s for
1x Speed Mode
20556/fEOSCs, Output Data Rate ≤ fEOSC/20556 Readings/s for
2x Speed Mode
As Long As CS = HIGH, After a Conversion is Complete
SLEEP
DATA OUTPUT
Internal Serial Clock
fO = LOW/HIGH
(Internal Oscillator)
As Long As CS = LOW But Not Longer Than 0.62ms
(24 SCK Cycles)
fO = External Oscillator with
Frequency fEOSC kHz
As Long As CS = LOW But Not Longer Than 192/fEOSCms
(24 SCK Cycles)
External Serial Clock with
Frequency fSCK kHz
an external serial clock. If the change occurs during the
conversion state, the result of the conversion in progress
may be outside speciﬁcations but the following conversions will not be affected. If the change occurs during the
data output state and the converter is in the Internal SCK
mode, the serial clock duty cycle may be affected but the
serial data stream will remain valid.
Table 5 summarizes the duration of each state and the
achievable output data rate as a function of fO.
Ease of Use
The LTC2480 data output has no latency, ﬁlter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
The LTC2480 performs offset and full-scale calibrations
every conversion cycle. This calibration is transparent to
the user and has no effect on the cyclic operation described
above. The advantage of continuous calibration is extreme
stability of offset and full-scale readings with respect to
time, supply voltage change and temperature drift.
As Long As CS = LOW But Not Longer Than 24/fSCKms
(24 SCK Cycles)
Power-Up Sequence
The LTC2480 automatically enters an internal reset state
when the power supply voltage VCC drops below approximately 2V. This feature guarantees the integrity of
the conversion result and of the serial interface mode
selection.
When the VCC voltage rises above this critical threshold,
the converter creates an internal power-on-reset (POR)
signal with a duration of approximately 4ms. The POR
signal clears all internal registers. Following the POR signal,
the LTC2480 starts a normal conversion cycle and follows
the succession of states described in Figure 1. The ﬁrst
conversion result following POR is accurate within the
speciﬁcations of the device if the power supply voltage is
restored within the operating range (2.7V to 5.5V) before
the end of the POR time interval.
On-Chip Temperature Sensor
The LTC2480 contains an on-chip PTAT (proportional to
absolute temperature) signal that can be used as a temperature sensor. The internal PTAT has a typical value of 420mV
at 27°C and is proportional to the absolute temperature
2480fc
19
LTC2480
APPLICATIONS INFORMATION
value with a temperature coefﬁcient of 420/(27 + 273) =
1.40mV/°C (SLOPE), as shown in Figure 4. The internal
PTAT signal is used in a single-ended mode referenced
to device ground internally. The GAIN is automatically
set to one (independent of the values of GS0, GS1, GS2)
in order to preserve the PTAT property at the ADC output
code and avoid an out of range error. The 1x speed mode
with automatic offset calibration is automatically selected
for the internal PTAT signal measurement as well.
600
VPTAT (mV)
500
400
300
–30
0
30
60
TEMPERATURE (°C)
90
120
2480 F04
Figure 4. Internal PTAT Signal vs Temperature
When using the internal temperature sensor, if the output
code is normalized to RSDO = VPTAT/VREF , the temperature
is calculated using the following formula:
TK =
RSDO • VREF
in Kelvin
SLOPE
and
TC =
RSDO • VREF
– 273 in °C
SLOPE
where SLOPE is nominally 1.4mV/°C.
Since the PTAT signal can have an initial value variation
which results in errors in SLOPE, to achieve better temperature measurements, a one-time calibration is needed
to adjust the SLOPE value. The converter output of the
PTAT signal, R0SDO, is measured at a known temperature
T0 (in °C) and the SLOPE is calculated as:
R0SDO • VREF
T0 + 273
This calibrated SLOPE can be used to calculate the temperature.
SLOPE =
RSDO • VREF
– 273
SLOPE
R
= SDO • (T0 + 273) – 273
R0SDO
TC =
Reference Voltage Range
VCC = 5V
IM = 1
FO = GND
SLOPE = 1.40mV/°C
200
–60
If the same VREF source is used during calibration and
temperature measurement, the actual value of the VREF
is not needed to measure the temperature as shown in
the calculation below:
The LTC2480 external reference voltage range is 0.1V
to VCC. The converter output noise is determined by
the thermal noise of the front-end circuits, and as such,
its value in nanovolts is nearly constant with reference
voltage. Since the transition noise (600nV) is much less
than the quantization noise (VREF/217), a decrease in the
reference voltage will increase the converter resolution. A
reduced reference voltage will also improve the converter
performance when operated with an external conversion
clock (external fO signal) at substantially higher output
data rates (see the Output Data Rate section). VREF must
be ≥1.1V to use the internal temperature sensor.
The negative reference input to the converter is internally
tied to GND. GND (Pin 8) should be connected to a ground
plane through as short a trace as possible to minimize
voltage drop. The LTC2480 has an average operational
current of 160μA and for 0.1Ω parasitic resistance, the
voltage drop of 16μV causes a gain error of 3.2ppm for
VREF = 5V.
Input Voltage Range
The analog input is truly differential with an absolute/common mode range for the IN+ and IN– input pins extending
from GND – 0.3V to VCC + 0.3V. Outside these limits, the
ESD protection devices begin to turn on and the errors
due to input leakage current increase rapidly. Within these
limits, the LTC2480 converts the bipolar differential input
signal, VIN = IN+ – IN–, from –FS to +FS where FS = 0.5 •
VREF/GAIN. Outside this range, the converter indicates the
overrange or the underrange condition using distinct output
codes. Since the differential input current cancellation does
not rely on an on-chip buffer, current cancellation as well
as DC performance is maintained rail-to-rail.
2480fc
20
LTC2480
APPLICATIONS INFORMATION
Input signals applied to IN+ and IN– pins may extend by
300mV below ground and above VCC. In order to limit any
fault current, resistors of up to 5k may be added in series
with the IN+ and IN– pins without affecting the performance
of the devices. The effect of the series resistance on the
converter accuracy can be evaluated from the curves
presented in the Input Current/Reference Current sections.
In addition, series resistors will introduce a temperature
dependent offset error due to the input leakage current.
A 1nA input leakage current will develop a 1ppm offset
error on a 5k resistor if VREF = 5V. This error has a very
strong temperature dependency.
3- or 4-wire I/O, single cycle or continuous conversion. The
following sections describe each of these serial interface
timing modes in detail. In all these cases, the converter
can use the internal oscillator (fO = LOW or fO = HIGH)
or an external oscillator connected to the fO pin. Refer to
Table 6 for a summary.
Serial Interface Timing Modes
The serial clock mode is selected on the falling edge
of CS. To select the external serial clock mode, the
serial clock pin (SCK) must be LOW during each CS
falling edge.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift
out the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
The LTC2480’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several ﬂexible modes of
operation. These include internal/external serial clock,
Table 6. LTC2480 Interface Timing Modes
SCK SOURCE
CONVERSION
CYCLE CONTROL
DATA OUTPUT
CONTROL
CONNECTION
AND WAVEFORMS
External SCK, Single Cycle Conversion
External
CS and SCK
CS and SCK
Figures 5, 6
External SCK, 3-Wire I/O
External
SCK
SCK
Figure 7
Internal SCK, Single Cycle Conversion
Internal
CS↓
CS↓
Figures 8, 9
Internal SCK, 3-Wire I/O, Continuous Conversion
Internal
Continuous
Internal
Figure 10
CONFIGURATION
2.7V TO 5.5V
1μF
2
VCC
10
FO
INT/EXT CLOCK
LTC2480
REFERENCE
VOLTAGE
0.1V TO VCC
3
VREF
SDO
ANALOG
INPUT
TEST EOC
(OPTIONAL)
1
SDI
9
SCK
4
IN+
CS
5
IN–
GND
4-WIRE
SPI INTERFACE
7
6
8
CS
TEST EOC
BIT 23
BIT 22
EOC
SDO
Hi-Z
BIT 21
BIT 20
SIG
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
BIT 0
LSB
IM
Hi-Z
TEST EOC
Hi-Z
SCK
(EXTERNAL)
SDI*
DON’T CARE
EN
GS2
GS1
GS0
IM
FA
FB
SPD
DATA OUTPUT
CONVERSION
DON’T CARE
CONVERSION
2480 F05
SLEEP
SLEEP
Figure 5. External Serial Clock, Single Cycle Operation
2480fc
21
LTC2480
APPLICATIONS INFORMATION
2.7V TO 5.5V
1μF
2
VCC
10
FO
INT/EXT CLOCK
LTC2480
3
REFERENCE
VOLTAGE
0.1V TO VCC
VREF
1
SDI
9
SCK
ANALOG
INPUT
4
IN+
5
IN–
TEST EOC
(OPTIONAL)
4-WIRE
SPI INTERFACE
7
SDO
6
CS
8
GND
CS
BIT 0
TEST EOC
BIT 23
EOC
SDO
BIT 22
BIT 21
BIT 20
SIG
MSB
EOC
Hi-Z
Hi-Z
BIT 19
BIT 18
BIT 17
BIT 16
BIT 9
TEST EOC
BIT 8
Hi-Z
Hi-Z
SCK
(EXTERNAL)
SDI*
SLEEP
DON’T CARE
DATA
OUTPUT
EN
GS2
GS1
GS0
IM
FA
CONVERSION
FB
DON’T CARE
SPD
DATA OUTPUT
CONVERSION
2480 F06
SLEEP
SLEEP
Figure 6. External Serial Clock, Reduced Data Output Length
2.7V TO 5.5V
1μF
2
VCC
10
FO
INT/EXT CLOCK
LTC2480
REFERENCE
VOLTAGE
0.1V TO VCC
3
VREF
1
SDI
9
SCK
SDO
4
ANALOG
INPUT
IN+
CS
5
IN–
GND
BIT 21
BIT 20
BIT 19
SIG
MSB
3-WIRE
SPI INTERFACE
7
6
8
CS
BIT 23
BIT 22
EOC
SDO
BIT 18
BIT 17
BIT 16
BIT 4
BIT 0
LSB
IM
SCK
(EXTERNAL)
SDI*
DON’T CARE
CONVERSION
EN
GS2
GS1
GS0
IM
FA
FB
SPD
DATA OUTPUT
DON’T CARE
CONVERSION
2480 F07
Figure 7. External Serial Clock, CS = 0 Operation
2480fc
22
LTC2480
APPLICATIONS INFORMATION
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0
if the device is in the sleep state. Independent of CS, the
device automatically enters the low power sleep state once
the conversion is complete.
When the device is in the sleep state, its conversion result
is held in an internal static shift register. The device remains
in the sleep state until the ﬁrst rising edge of SCK is seen
while CS is LOW. The input data is then shifted in via the
SDI pin on the rising edge of SCK (including the ﬁrst rising
edge) and the output data is shifted out of the SDO pin on
each falling edge of SCK. This enables external circuitry
to latch the output on the rising edge of SCK. EOC can be
latched on the ﬁrst rising edge of SCK and the last bit of
the conversion result can be latched on the 24th rising
edge of SCK. On the 24th falling edge of SCK, the device
begins a new conversion. SDO goes HIGH (EOC = 1)
indicating a conversion is in progress. In applications
where the processor generates 32 clock cycles, or to
remain compatible with higher resolution converters, the
LTC2480’s digital interface will ignore extra clock edges
seen during the next conversion period after the 24th and
outputs “1” for the extra clock cycles.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time
in order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling CS HIGH anytime between the ﬁrst rising edge and
the 24th falling edge of SCK (see Figure 6). On the rising
edge of CS, the device aborts the data output state and
immediately initiates a new conversion. If the device has
not ﬁnished loading the last input bit SPD of SDI by the
time CS is pulled HIGH, the SDI information is discarded
and the previous conﬁguration is kept. This is useful for
systems not requiring all 24 bits of output data, aborting
an invalid conversion cycle or synchronizing the start of
a conversion.
External Serial Clock, 3-Wire I/O
This timing mode utilizes a 3-wire serial I/O interface. The
conversion result is shifted out of the device by an externally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or transmission over an isolation barrier.
The external serial clock mode is selected at the end of
the power-on reset (POR) cycle. The POR cycle is concluded typically 4ms after VCC exceeds approximately 2V.
The level applied to SCK at this time determines if SCK
is internal or external. SCK must be driven LOW prior to
the end of POR in order to enter the external serial clock
timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can
be continuously monitored at the SDO pin during the
convert and sleep states. EOC may be used as an interrupt
to an external controller indicating the conversion result
is ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge
of EOC, the conversion result is loaded into an internal
static shift register. The input data is then shifted in via
the SDI pin on the rising edge of SCK (including the ﬁrst
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. EOC can be latched on
the ﬁrst rising edge of SCK. On the 24th falling edge of
SCK, SDO goes HIGH (EOC = 1) indicating a new conversion has begun. In applications where the processor
generates 32 clock cycles, or to remain compatible
with higher resolution converters, the LTC2480’s digital
interface will ignore extra clock edges seen during the
next conversion period after the 24th and outputs “1”
for the extra clock cycles.
2480fc
23
LTC2480
APPLICATIONS INFORMATION
rising edge of SCK. In the internal SCK timing mode, SCK
goes HIGH and the device begins outputting data at time
tEOCtest after the falling edge of CS (if EOC = 0) or tEOCtest
after EOC goes LOW (if CS is LOW during the falling edge
of EOC). The value of tEOCtest is 12μs if the device is using
its internal oscillator. If fO is driven by an external oscillator
of frequency fEOSC, then tEOCtest is 3.6/fEOSC in seconds. If
CS is pulled HIGH before time tEOCtest, the device returns
to the sleep state and the conversion result is held in the
internal static shift register.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and control
the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode,
the serial clock pin (SCK) must be ﬂoating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is automatically selected if SCK is not externally driven.
If CS remains LOW longer than tEOCtest, the ﬁrst rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data I/O cycle concludes
after the 24th rising edge. The input data is shifted in via
the SDI pin on the rising edge of SCK (including the ﬁrst
rising edge) and the output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the ﬁrst rising edge of SCK and the
last bit of the conversion result on the 24th rising edge of
SCK. After the 24th rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC
= 0), the device will exit the low power mode during the
EOC test. In order to allow the device to return to the low
power sleep state, CS must be pulled HIGH before the ﬁrst
2.7V TO 5.5V
1μF
2
VCC
10
FO
INT/EXT CLOCK
VCC
LTC2480
REFERENCE
VOLTAGE
0.1V TO VCC
3
VREF
SDI
ANALOG
INPUT
<tEOCtest
4
IN+
5
IN–
4-WIRE
SPI INTERFACE
7
6
CS
GND
10k
9
SCK
SDO
TEST EOC
1
8
CS
BIT 23
BIT 22
EOC
SDO
Hi-Z
BIT 21
BIT 20
SIG
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
BIT 0
LSB
IM
Hi-Z
TEST EOC
Hi-Z
Hi-Z
SCK
(INTERNAL)
SDI*
DON’T CARE
EN
CONVERSION
GS2
GS1
GS0
IM
FA
FB
SPD
DATA OUTPUT
SLEEP
DON’T CARE
CONVERSION
2480 F08
SLEEP
Figure 8. Internal Serial Clock, Single Cycle Operation
2480fc
24
LTC2480
APPLICATIONS INFORMATION
CS remains LOW during the data output state. However,
the data output state may be aborted by pulling CS HIGH
anytime between the ﬁrst and 24th rising edge of SCK (see
Figure 9). On the rising edge of CS, the device aborts the
data output state and immediately initiates a new conversion. If the device has not ﬁnished loading the last input
bit SPD of SDI by the time CS is pulled HIGH, the SDI
information is discarded and the previous conﬁguration
is still kept. This is useful for systems not requiring all 24
bits of output data, aborting an invalid conversion cycle,
or synchronizing the start of a conversion. If CS is pulled
HIGH while the converter is driving SCK LOW, the internal
pull-up is not available to restore SCK to a logic HIGH state.
This will cause the device to exit the internal serial clock
mode on the next falling edge of CS. This can be avoided
by adding an external 10k pull-up resistor to the SCK pin
or by never pulling CS HIGH when SCK is LOW.
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a LOW signal, the
LTC2480’s internal pull-up remains disabled. Hence, SCK
remains LOW. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes HIGH
once the external driver goes Hi-Z. On the next CS falling
edge, the device will remain in the internal SCK timing
mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conversion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period deﬁned above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Whenever SCK is LOW, the LTC2480’s internal pull-up at
pin SCK is disabled. Normally, SCK is not externally driven
if the device is in the internal SCK timing mode. However,
2.7V TO 5.5V
1μF
2
VCC
10
FO
INT/EXT CLOCK
VCC
LTC2480
REFERENCE
VOLTAGE
0.1V TO VCC
3
VREF
SDI
>tEOCtest
ANALOG
INPUT
4
IN+
5
IN–
4-WIRE
SPI INTERFACE
7
6
CS
GND
10k
9
SCK
SDO
TEST EOC
(OPTIONAL)
1
8
<tEOCtest
CS
TEST EOC
BIT 0
BIT 23
EOC
SDO
Hi-Z
BIT 22
EOC
Hi-Z
Hi-Z
BIT 21
BIT 20
SIG
MSB
BIT 19
BIT 18
BIT 17
BIT 16
Hi-Z
BIT 8
TEST EOC
Hi-Z
SCK
(INTERNAL)
SDI*
SLEEP
DON’T CARE
DATA
OUTPUT
EN
CONVERSION
GS2
GS1
GS0
IM
FA
FB
DATA OUTPUT
SLEEP
SPD
DON’T CARE
CONVERSION
2480 F09
SLEEP
Figure 9. Internal Serial Clock, Reduce Data Output Length
2480fc
25
LTC2480
APPLICATIONS INFORMATION
Internal Serial Clock, 3-Wire I/O,
Continuous Conversion
period) then immediately begins outputting data. The
data input/output cycle begins on the ﬁrst rising edge of
SCK and ends after the 24th rising edge. The input data
is then shifted in via the SDI pin on the rising edge of
SCK (including the ﬁrst rising edge) and the output data
is shifted out of the SDO pin on each falling edge of SCK.
The internally generated serial clock is output to the SCK
pin. This signal may be used to shift the conversion result
into external circuitry. EOC can be latched on the ﬁrst rising edge of SCK and the last bit of the conversion result
can be latched on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1) indicating a
new conversion is in progress. SCK remains HIGH during
the conversion.
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated serial clock (SCK) signal, see Figure 10. CS may be
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the internal
serial clock timing mode is automatically selected if SCK
is not externally driven LOW (if SCK is loaded such that
the internal pull-up cannot pull the pin HIGH, the external
SCK mode will be selected).
Preserving the Converter Accuracy
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has ﬁnished and the device has entered
the low power sleep state. The part remains in the sleep
state a minimum amount of time (1/2 the internal SCK
The LTC2480 is designed to reduce as much as possible
the conversion result sensitivity to device decoupling, PCB
layout, anti-aliasing circuits, line frequency perturbations
and so on. Nevertheless, in order to preserve the 24-bit
accuracy capability of this part, some simple precautions
are required.
2.7V TO 5.5V
1μF
2
VCC
10
FO
INT/EXT CLOCK
VCC
LTC2480
REFERENCE
VOLTAGE
0.1V TO VCC
3
VREF
SDI
4
IN+
5
IN–
3-WIRE
SPI INTERFACE
7
6
CS
GND
10k
9
SCK
SDO
ANALOG
INPUT
1
8
CS
BIT 23
SDO
BIT 22
EOC
BIT 21
BIT 20
SIG
MSB
BIT 19
BIT 18
BIT 17
BIT 16
BIT 4
BIT 0
LSB
IM
SCK
(INTERNAL)
SDI*
DON’T CARE
CONVERSION
EN
GS2
GS1
GS0
IM
FA
FB
SPD
DON’T CARE
DATA OUTPUT
CONVERSION
2480 F10
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
2480fc
26
LTC2480
APPLICATIONS INFORMATION
Digital Signal Levels
The LTC2480’s digital interface is easy to use. Its digital
inputs (SDI, fO, CS and SCK in External SCK mode of
operation) accept standard CMOS logic levels and the
internal hysteresis receivers can tolerate edge transition
times as slow as 100μs. However, some considerations
are required to take advantage of the exceptional accuracy
and low supply current of this converter.
The digital output signals (SDO and SCK in Internal SCK
mode of operation) are less of a concern because they are
not generally active during the conversion state.
While a digital input signal is in the range 0.5V to
(VCC – 0.5V), the CMOS input receiver draws additional
current from the power supply. It should be noted that,
when any one of the digital input signals (SDI, fO, CS and
SCK in External SCK mode of operation) is within this range,
the power supply current may increase even if the signal in
question is at a valid logic level. For micropower operation,
it is recommended to drive all digital input signals to full
CMOS levels [VIL < 0.4V and VOH > (VCC – 0.4V)].
During the conversion period, the undershoot and/or
overshoot of a fast digital signal connected to the pins can
severely disturb the analog to digital conversion process.
Undershoot and overshoot occur because of the impedance mismatch of the circuit board trace at the converter
pin when the transition time of an external control signal
is less than twice the propagation delay from the driver
to the LTC2480. For reference, on a regular FR-4 board,
signal propagation velocity is approximately 183ps/inch
for internal traces and 170ps/inch for surface traces.
Thus, a driver generating a control signal with a minimum
transition time of 1ns must be connected to the converter
pin through a trace shorter than 2.5 inches. This problem
becomes particularly difﬁcult when shared control lines are
used and multiple reﬂections may occur. The solution is
to carefully terminate all transmission lines close to their
characteristic impedance.
Parallel termination near the LTC2480 pin will eliminate
this problem but will increase the driver power dissipation. A series resistor between 27Ω and 56Ω placed near
the driver output pin will also eliminate this problem
without additional power dissipation. The actual resistor
value depends upon the trace impedance and connection
topology.
An alternate solution is to reduce the edge rate of the control
signals. It should be noted that using very slow edges will
increase the converter power supply current during the
transition time. The differential input architecture reduces
the converter’s sensitivity to ground currents.
Particular attention must be given to the connection of
the fO signal when the LTC2480 is used with an external
conversion clock. This clock is active during the conversion time and the normal mode rejection provided by the
internal digital ﬁlter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals can result in DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals can result in a DC offset error. Such perturbations can occur due to asymmetric capacitive coupling
between the fO signal trace and the converter input and/or
reference connection traces. An immediate solution is to
maintain maximum possible separation between the fO
signal trace and the input/reference signals. When the fO
signal is parallel terminated near the converter, substantial
AC current is ﬂowing in the loop formed by the fO connection trace, the termination and the ground return path.
Thus, perturbation signals may be inductively coupled into
the converter input and/or reference. In this situation, the
user must reduce to a minimum the loop area for the fO
signal as well as the loop area for the differential input
and reference connections. Even when fO is not driven,
other nearby signals pose similar EMI threats which will
be minimized by following good layout practices.
2480fc
27
LTC2480
APPLICATIONS INFORMATION
Driving the Input and Reference
period is 2.5/fEOSC and, for a settling error of less than
1ppm, τ ≤ 0.178/fEOSC.
The input and reference pins of the LTC2480 converter
are directly connected to a network of sampling capacitors. Depending upon the relation between the differential
input voltage and the differential reference voltage, these
capacitors are switching between these four pins transferring small amounts of charge in the process. A simpliﬁed
equivalent circuit is shown in Figure 11.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kΩ with no external bypass capacitor or up
to 500Ω with 0.001μF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization of the sensor is possible.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, VREF+ or GND) can
be considered to form, together with RSW and CEQ (see
Figure 11), a ﬁrst order passive network with a time
constant τ = (RS + RSW) • CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy
if the sampling period is at least 14 times greater than the
input circuit time constant τ. The sampling process on
the four input analog pins is quasi-independent so each
time constant should be considered by itself and, under
worst-case circumstances, the errors may add.
For many applications, the sensor output impedance
combined with external bypass capacitors produces RC
time constants much greater than the 580ns required for
1ppm accuracy. For example, a 10kΩ bridge driving a 0.1μF
bypass capacitor has a time constant an order of magnitude
greater than the required maximum. Historically, settling
issues were solved using buffers. These buffers led to
increased noise, reduced DC performance (Offset/Drift),
limited input/output swing (cannot digitize signals near
ground or VCC), added system cost and increased power.
The LTC2480 uses a proprietary switching algorithm that
forces the average differential input current to zero independent of external settling errors. This allows accurate direct
digitization of high impedance sensors without the need
of buffers. Additional errors resulting from mismatched
leakage currents must also be taken into account.
When using the internal oscillator, the LTC2480’s front-end
switched-capacitor network is clocked at 123kHz corresponding to an 8.1μs sampling period. Thus, for settling
errors of less than 1ppm, the driving source impedance
should be chosen such that τ ≤ 8.1μs/14 = 580ns. When an
external oscillator of frequency fEOSC is used, the sampling
IREF+
VCC
RSW (TYP)
10k
ILEAK
+
VREF
I IN
ILEAK
VCC
IIN+
I REF
ILEAK
VIN+
RSW (TYP)
10k
CEQ
12pF
(TYP)
VCC
ILEAK
AVG
1.5 v VREF
VIN(CM)
VREF(CM)
0.5 v REQ
VINCM VREFCM
0.5 v REQ
VIN 2
VREF v REQ
0.5 • VREF • DT
REQ
1.5VREF
VREF(CM) – VIN(CM)
0.5 • REQ
2
–
VIN
VREF • REQ
¥V
´
VREFCM ¦ REF µ
§ 2 ¶
VINCM
IN
¥ IN IN ´
¦
µ
2
§
¶
REQ 2.71M7 INTERNAL OSCILLATOR 60Hz MODE
REQ 2.98M7 INTERNAL OSCILLATOR 50Hz AND 60Hz MODE
ILEAK
IREF–
AVG
VIN IN
RSW (TYP)
10k
VIN–
I IN –
where:
ILEAK
IIN–
AVG
VCC
ILEAK
REQ 0.833 v 1012 / f EOSC EXTERNAL OSCILLATOR
RSW (TYP)
10k
2480 F11
GND
ILEAK
DT IS THE DENSITY OF A DIGITAL TRANSITION AT THE MODULATOR OUTPUT
WHERE REF– IS INTERNALLY TIED TO GND
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 • fEOSC EXTERNAL OSCILLATOR
Figure 11. LTC2480 Equivalent Analog Input Circuit
2480fc
28
LTC2480
APPLICATIONS INFORMATION
RSOURCE
VINCM + 0.5VIN
IN+
CEXT
CPAR
20pF
LTC2480
RSOURCE
VINCM – 0.5VIN
IN–
CEXT
CPAR
20pF
2480 F12
Figure 12. An RC Network at IN+ and IN–
+FS ERROR (ppm)
80
VCC = 5V
= 5V
60 VREF
VIN+ = 3.75V
– = 1.25V
40 VIN
FO = GND
20 TA = 25°C
CEXT = 0pF
CEXT = 100pF
0
CEXT = 1nF, 0.1μF, 1μF
–20
–40
–60
–80
1
10
100
1k
RSOURCE (Ω)
10k
100k
2480 F13
Figure 13. +FS Error vs RSOURCE at IN+ or IN–
–FS ERROR (ppm)
80
VCC = 5V
= 5V
60 VREF
VIN+ = 1.25V
–
40 VIN = 3.75V
FO = GND
20 TA = 25°C
CEXT = 1nF, 0.1μF, 1μF
0
CEXT = 100pF
–20
CEXT = 0pF
–40
–60
–80
1
10
100
1k
RSOURCE (Ω)
10k
100k
2480 F14
Figure 14. –FS Error vs RSOURCE at IN+ or IN–
The switching algorithm forces the average input current
on the positive input (IIN+) to be equal to the average input
current on the negative input (IIN–). Over the complete
conversion cycle, the average differential input current
(IIN+ – IIN–) is zero. While the differential input current
is zero, the common mode input current (IIN++ IIN–)/2 is
proportional to the difference between the common mode
input voltage (VINCM) and the common mode reference
voltage (VREFCM).
In applications where the input common mode voltage
is equal to the reference common mode voltage, as in
the case of a balance bridge type application, both the
differential and common mode input current are zero.
The accuracy of the converter is unaffected by settling
errors. Mismatches in source impedances between IN+
and IN– also do not affect the accuracy.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between VINCM and VREFCM. For a reference
common mode of 2.5V and an input common mode of
1.5V, the common mode input current is approximately
0.74μA (in simultaneous 50Hz/60Hz rejection mode). This
common mode input current has no effect on the accuracy
if the external source impedances tied to IN+ and IN– are
matched. Mismatches in these source impedances lead
to a ﬁxed offset error but do not affect the linearity or fullscale reading. A 1% mismatch in 1k source resistances
leads to a 15ppm shift (74μV) in offset voltage.
In applications where the common mode input voltage
varies as a function of input signal level (single-ended
input, RTDs, half bridges, current sensors, etc.), the
common mode input current varies proportionally with
input voltage. For the case of balanced input impedances,
the common mode input current effects are rejected by the
large CMRR of the LTC2480 leading to little degradation in
accuracy. Mismatches in source impedances lead to gain
errors proportional to the difference between the common
mode input voltage and the common mode reference
voltage. 1% mismatches in 1k source resistances lead to
worst-case gain errors on the order of 15ppm or 1LSB
(for 1V differences in reference and input common mode
2480fc
29
LTC2480
APPLICATIONS INFORMATION
voltage). Table 7 summarizes the effects of mismatched
source impedance and differences in reference/input
common mode voltages.
Table 7. Suggested Input Conﬁguration for LTC2480
BALANCED INPUT
RESISTANCES
UNBALANCED INPUT
RESISTANCES
Constant
VIN(CM) – VREF(CM)
CEXT > 1nF at Both
IN+ and IN–. Can Take
Large Source Resistance
with Negligible Error
CEXT > 1nF at Both IN+
and IN–. Can Take Large
Source Resistance.
Unbalanced Resistance
Results in an Offset
Varying
VIN(CM) – VREF(CM)
CEXT > 1nF at Both IN+
and IN–. Can Take Large
Source Resistance with
Negligible Error
Minimize IN+ and IN–
Capacitors and Avoid
Large Source Impedance
(<5kΩ Recommended)
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a speciﬁcation can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current and offset
will be insigniﬁcant (about 1% of their respective values
over the entire temperature and voltage range). Even for
the most stringent applications, a one-time calibration
operation may be sufﬁcient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1μV typical and 10μV maximum offset voltage.
Reference Current
In a similar fashion, the LTC2480 samples the differential
reference pins VREF+ and GND transferring small amount
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can
be analyzed in two distinct situations.
For relatively small values of the external reference capacitors (CREF < 1nF), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
values for CREF will deteriorate the converter offset and
gain performance without signiﬁcant beneﬁts of reference
ﬁltering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 1nF) may be
required as reference ﬁlters in certain conﬁgurations. Such
capacitors will average the reference sampling charge and
the external source resistance will see a quasi constant
reference differential impedance.
In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator for 60Hz mode, the typical differential reference
resistance is 1MΩ which generates a full-scale (VREF/2)
gain error of 0.51ppm for each ohm of source resistance
driving the VREF pin. For 50Hz/60Hz mode, the related
difference resistance is 1.1MΩ and the resulting full-scale
error is 0.46ppm for each ohm of source resistance driving the VREF pin. For 50Hz mode, the related difference
resistance is 1.2MΩ and the resulting full-scale error is
0.42ppm for each ohm of source resistance driving the
VREF pin. When fO is driven by an external oscillator with a
frequency fEOSC (external conversion clock operation), the
typical differential reference resistance is 0.30 • 1012/fEOSC
Ω and each ohm of source resistance driving the VREF pin
will result in 1.67 • 10–6 • fEOSCppm gain error. The typical
+FS and –FS errors for various combinations of source
resistance seen by the VREF pin and external capacitance
connected to that pin are shown in Figures 15-18.
In addition to this gain error, the converter INL performance is degraded by the reference source impedance.
The INL is caused by the input dependent terms
–VIN2/(VREF • REQ) – (0.5 • VREF • DT)/REQ in the reference
pin current as expressed in Figure 11. When using internal
oscillator and 60Hz mode, every 100Ω of reference source
resistance translates into about 0.67ppm additional INL
error. When using internal oscillator and 50Hz/60Hz mode,
every 100Ω of reference source resistance translates into
about 0.61ppm additional INL error. When using internal
oscillator and 50Hz mode, every 100Ω of reference source
resistance translates into about 0.56ppm additional INL
error. When fO is driven by an external oscillator with a
frequency fEOSC, every 100Ω of source resistance driving
2480fc
30
LTC2480
APPLICATIONS INFORMATION
90
60
50
0
CREF = 0.01μF
CREF = 0.001μF
CREF = 100pF
CREF = 0pF
40
30
20
–20
–30
–40
–50
VCC = 5V
–60 VREF = 5V
V + = 1.25V
–70 VIN– = 3.75V
IN
–80 FO = GND
TA = 25°C
–90
10
0
10
0
–10
10
0
CREF = 0.01μF
CREF = 0.001μF
CREF = 100pF
CREF = 0pF
–10
–FS ERROR (ppm)
70
+FS ERROR (ppm)
10
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
80
1k
100
RSOURCE (Ω)
10k
100k
1k
100
RSOURCE (Ω)
10k
2480 F16
2480 F15
Figure 15. +FS Error vs RSOURCE at VREF (Small CREF)
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
+FS ERROR (ppm)
400
300
0
CREF = 1μF, 10μF
–100
CREF = 0.1μF
200
CREF = 0.01μF
100
0
CREF = 0.01μF
–200
CREF = 1μF, 10μF
–300
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
FO = GND
TA = 25°C
–400
0
200
600
400
RSOURCE (Ω)
800
1000
2480 F17
Figure 17. +FS Error vs RSOURCE at VREF (Large CREF)
10
INL (ppm OF VREF)
Figure 16. –FS Error vs RSOURCE at VREF (Small CREF)
–FS ERROR (ppm)
500
VCC = 5V
8 VREF = 5V
VIN(CM) = 2.5V
6 T = 25°C
A
4 CREF = 10μF
R = 500Ω
0
R = 100Ω
–2
–4
–6
–8
–0.3
0.1
–0.1
VIN/VREF (V)
0.3
–500
0
200
CREF = 0.1μF
600
400
RSOURCE (Ω)
800
1000
2480 F18
Figure 18. –FS Error vs RSOURCE at VREF (Large CREF)
VREF translates into about 2.18 • 10–6 • fEOSCppm additional INL error. Figure 19 shows the typical INL error due
to the source resistance driving the VREF pin when large
CREF values are used. The user is advised to minimize the
source impedance driving the VREF pin.
R = 1k
2
–10
–0.5
100k
0.5
2480 F19
Figure 19. INL vs Differential Input Voltage and
Reference Source Resistance for CREF > 1μF
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (VREFCM – VINCM) and a 5V reference,
each Ohm of reference source resistance introduces an
extra (VREFCM – VINCM)/(VREF • REQ) full-scale gain error,
which is 0.074ppm when using internal oscillator and 60Hz
mode. When using internal oscillator and 50Hz/60Hz mode,
the extra full-scale gain error is 0.067ppm. When using
2480fc
31
LTC2480
APPLICATIONS INFORMATION
internal oscillator and 50Hz mode, the extra gain error is
0.061ppm. If an external clock is used, the corresponding
extra gain error is 0.24 • 10–6 • fEOSCppm.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a speciﬁcation can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by VREF+
and GND, the expected drift of the dynamic current gain
error will be insigniﬁcant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufﬁcient.
In addition to the reference sampling charge, the reference pins ESD protection diodes have a temperature
dependent leakage current. This leakage current, nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05μV typical and 0.5μV
maximum full-scale error.
3500
40
TA = 85°C
20
10
0
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line fre0
–500
2500
–1000
TA = 85°C
2000
1500
10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2480 F20
Figure 20. Offset Error vs Output Data
Rate and Temperature
TA = 85°C
–2000
TA = 25°C
1000
0
–10
TA = 25°C
–1500
–2500
500
TA = 25°C
0
An increase in fEOSC over the nominal 307.2kHz will
translate into a proportional increase in the maximum
output data rate. The increase in output rate is nevertheless accompanied by three potential effects, which must
be carefully considered.
VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
3000
30
When using its internal oscillator, the LTC2480 produces
up to 7.5 samples per second (sps) with a notch frequency
of 60Hz, 6.25sps with a notch frequency of 50Hz and
6.82sps with the 50Hz/60Hz rejection mode. The actual
output data rate will depend upon the length of the sleep
and data output phases which are controlled by the user
and which can be made insigniﬁcantly short. When operated with an external conversion clock (fO connected to
an external oscillator), the LTC2480 output data rate can
be increased as desired. The duration of the conversion
phase is 41036/fEOSC. If fEOSC = 307.2kHz, the converter
behaves as if the internal oscillator is used and the notch
is set at 60Hz.
–FS ERROR (ppm OF VREF)
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
FO = EXT CLOCK
+FS ERROR (ppm OF VREF)
OFFSET ERROR (ppm OF VREF)
50
Output Data Rate
–3000
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2480 F21
Figure 21. +FS Error vs Output Data
Rate and Temperature
–3500
VIN(CM) = VREF(CM)
VCC = VREF = 5V
FO = EXT CLOCK
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2480 F22
Figure 22. –FS Error vs Output Data
Rate and Temperature
2480fc
32
LTC2480
APPLICATIONS INFORMATION
quency. In many applications, the subsequent performance
degradation can be substantially reduced by relying upon
the LTC2480’s exceptional common mode rejection and by
carefully eliminating common mode to differential mode
conversion sources in the input circuit. The user should
avoid single-ended input ﬁlters and should maintain a
very high degree of matching and symmetry in the circuits
driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
through the input and the reference pins. If large external
input and/or reference capacitors (CIN, CREF) are used, the
previous section provides formulae for evaluating the effect
of the source resistance upon the converter performance for
any value of fEOSC. If small external input and/or reference
capacitors (CIN, CREF) are used, the effect of the external
source resistance upon the LTC2480 typical performance
can be inferred from Figures 13, 14, 15 and 16 in which
the horizontal axis is scaled by 307200/fEOSC.
Third, an increase in the frequency of the external oscillator
above 1MHz (a more than 3× increase in the output data
rate) will start to decrease the effectiveness of the internal
autocalibration circuits. This will result in a progressive
degradation in the converter accuracy and linearity. Typical
measured performance curves for output data rates up to
100 readings per second are shown in Figures 20 to 27. In
order to obtain the highest possible level of accuracy from
this converter at output data rates above 20 readings per
22
24
20
22
20
RESOLUTION (BITS)
20
18
16
12
10
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
FO = EXT CLOCK
RES = LOG 2 (VREF/NOISERMS)
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2480 F23
18
TA = 85°C
TA = 25°C
16
14
VIN(CM) = VREF(CM)
12 VCC = VREF = 5V
FO = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
Figure 23. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
2480 F24
Figure 24. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
VIN(CM) = VREF(CM)
VIN = 0V
15 FO = EXT CLOCK
TA = 25°C
10
VCC = VREF = 5V
5
0
–5
VCC = 5V, VREF = 2.5V
–10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2480 F25
Figure 25. Offset Error vs Output
Data Rate and Reference Voltage
22
24
VCC = VREF = 5V
22
20
20
VCC = 5V, VREF = 2.5V
18
16
14 VIN(CM) = VREF(CM)
VIN = 0V
FO = EXT CLOCK
12 T = 25°C
A
RES = LOG 2 (VREF/NOISERMS)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2480 F26
Figure 26. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Reference Voltage
RESOLUTION (BITS)
14
RESOLUTION (BITS)
RESOLUTION (BITS)
TA = 85°C
OFFSET ERROR (ppm OF VREF)
TA = 25°C
18
VCC = VREF = 5V
16
VCC = 5V, VREF = 2.5V
VIN(CM) = VREF(CM)
14
VIN = 0V
REF– = GND
12 FO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/INLMAX)
10
0 10 20 30 40 50 60 70 80 90 100
OUTPUT DATA RATE (READINGS/SEC)
2480 F27
Figure 27. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Reference Voltage
2480fc
33
LTC2480
APPLICATIONS INFORMATION
The combined effect of the internal SINC4 digital ﬁlter and
of the analog and digital autocalibration circuits determines
the LTC2480 input bandwidth. When the internal oscillator
is used with the notch set at 60Hz, the 3dB input bandwidth
is 3.63Hz. When the internal oscillator is used with the
notch set at 50Hz, the 3dB input bandwidth is 3.02Hz.
If an external conversion clock generator of frequency
fEOSC is connected to the fO pin, the 3dB input bandwidth
is 11.8 • 10–6 • fEOSC.
Due to the complex ﬁltering and calibration algorithms
utilized, the converter input bandwidth is not modeled
very accurately by a ﬁrst order ﬁlter with the pole located
at the 3dB frequency. When the internal oscillator is used,
the shape of the LTC2480 input bandwidth is shown in
Figure 28. When an external oscillator of frequency fEOSC
is used, the shape of the LTC2480 input bandwidth can
be derived from Figure 28, 60Hz mode curve in which the
horizontal axis is scaled by fEOSC/307200.
The conversion noise (600nVRMS typical for VREF = 5V)
can be modeled by a white noise source connected to a
noise free converter. The noise spectral density is 47nV√Hz
for an inﬁnite bandwidth source and 64nV√Hz for a single
0.5MHz pole source. From these numbers, it is clear that
particular attention must be given to the design of external
ampliﬁcation circuits. Such circuits face the simultaneous
requirements of very low bandwidth (just a few Hz) in
order to reduce the output referred noise and relatively
high bandwidth (at least 500kHz) necessary to drive the
input switched-capacitor network. A possible solution is
a high gain, low bandwidth ampliﬁer stage followed by a
high bandwidth unity-gain buffer.
When external ampliﬁers are driving the LTC2480, the
ADC input referred system noise calculation can be
simpliﬁed by Figure 29. The noise of an ampliﬁer driving
the LTC2480 input pin can be modeled as a band limited
white noise source. Its bandwidth can be approximated
by the bandwidth of a single pole lowpass ﬁlter with a
INPUT SIGNAL ATTENUATION (dB)
Input Bandwidth
0
–1
50Hz AND
60Hz MODE
–2
50Hz MODE
–3
60Hz MODE
–4
–5
–6
1
3
0
4
5
2
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2480 F28
Figure 28. Input Signal Bandwidth Using the Internal Oscillator
100
INPUT REFERRED NOISE
EQUIVALENT BANDWIDTH (Hz)
second, the user is advised to maximize the power supply
voltage used and to limit the maximum ambient operating
temperature. In certain circumstances, a reduction of the
differential reference voltage may be beneﬁcial.
10
60Hz MODE
50Hz MODE
1
0.1
0.1
1
10 100 1k 10k 100k 1M
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz) 2480 F29
Figure 29. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
corner frequency fi. The ampliﬁer noise spectral density
is ni. From Figure 29, using fi as the x-axis selector, we
can ﬁnd on the y-axis the noise equivalent bandwidth freqi
of the input driving ampliﬁer. This bandwidth includes
the band limiting effects of the ADC internal calibration
and ﬁltering. The noise of the driving ampliﬁer referred
to the converter input and including all these effects can
be calculated as N = ni • √freqi. The total system noise
(referred to the LTC2480 input) can now be obtained by
summing as square root of sum of squares the three ADC
input referred noise sources: the LTC2480 internal noise,
the noise of the IN+ driving ampliﬁer and the noise of the
IN– driving ampliﬁer.
2480fc
34
LTC2480
APPLICATIONS INFORMATION
If the fO pin is driven by an external oscillator of frequency
fEOSC, Figure 29 can still be used for noise calculation if
the x-axis is scaled by fEOSC/307200. For large values of
the ratio fEOSC/307200, the Figure 29 plot accuracy begins
to decrease, but at the same time the LTC2480 noise ﬂoor
rises and the noise contribution of the driving ampliﬁers
lose signiﬁcance.
Normal Mode Rejection and Anti-aliasing
The SINC4 digital ﬁlter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2480’s autocalibration circuits further simplify the
anti-aliasing requirements by additional normal mode
signal ﬁltering both in the analog and digital domain.
Independent of the operating mode, fS = 256 • fN = 2048
• fOUT(MAX) where fN is the notch frequency and fOUT(MAX)
is the maximum output data rate. In the internal oscillator mode with a 50Hz notch setting, fS = 12800Hz, with
50Hz/60Hz rejection, fS = 13960Hz and with a 60Hz notch
setting fS = 15360Hz. In the external oscillator mode, fS =
0
0
–10
–10
INPUT NORMAL MODE REJECTION (dB)
INPUT NORMAL MODE REJECTION (dB)
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital ﬁltering. Combined
with a large oversampling ratio, the LTC2480 signiﬁcantly
simpliﬁes anti-aliasing ﬁlter requirements. Additionally,
the input current cancellation feature of the LTC2480 al-
lows external lowpass ﬁltering without degrading the DC
performance of the device.
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS11fS12fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2480 F30
INPUT NORMAL MODE REJECTION (dB)
0
fN = fEOSC/5120
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (Hz)
8fN
2480 F32
Figure 32. Input Normal Mode Rejection at DC
2480 F31
Figure 31. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch Mode or External Oscillator
0
INPUT NORMAL MODE REJECTION (dB)
Figure 30. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch Mode
0 fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
250fN 252fN 254fN 256fN 258fN 260fN 262fN
INPUT SIGNAL FREQUENCY (Hz)
2480 F33
Figure 33. Input Normal Mode Rejection at fS = 256fN
2480fc
35
LTC2480
APPLICATIONS INFORMATION
fEOSC/20. The performance of the normal mode rejection
is shown in Figures 30 and 31.
the LTC2480 for the 50Hz rejection mode and 50Hz/60Hz
rejection mode are shown in Figures 35 and 36.
In 1x speed mode, the regions of low rejection occurring
at integer multiples of fS have a very narrow bandwidth.
Magniﬁed details of the normal mode rejection curves
are shown in Figure 32 (rejection near DC) and Figure 33
(rejection at fS = 256fN) where fN represents the notch
frequency. These curves have been derived for the external oscillator mode but they can be used in all operating
modes by appropriately selecting the fN value.
As a result of these remarkable normal mode speciﬁcations, minimal (if any) anti-alias ﬁltering is required in front
of the LTC2480. If passive RC components are placed in
front of the LTC2480, the input dynamic current should
be considered (see Input Current section). In this case,
the differential input current cancellation feature of the
LTC2480 allows external RC networks without signiﬁcant
degradation in DC performance.
The user can expect to achieve this level of performance
using the internal oscillator as it is demonstrated by
Figures 34, 35 and 36. Typical measured values of the
normal mode rejection of the LTC2480 operating with an
internal oscillator and a 60Hz notch setting are shown in
Figure 34 superimposed over the theoretical calculated
curve. Similarly, the measured normal mode rejection of
Traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. The proprietary
architecture used for the LTC2480 third order modulator
resolves this problem and guarantees a predictable stable
behavior at input signal levels of up to 150% of full-scale.
In many industrial applications, it is not uncommon to have
NORMAL MODE REJECTION (dB)
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
–20
–40
–60
–80
–100
–120
NORMAL MODE REJECTION (dB)
0
0
–40
15
30
45
60
75
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–80
–100
–120
0
MEASURED DATA
CALCULATED DATA
–20
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
0
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
2480 F35
2480 F34
Figure 35. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (50Hz Notch)
Figure 34. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (60Hz Notch)
MEASURED DATA
CALCULATED DATA
–20
–40
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
–60
–80
–100
–120
0
20
40
60
80
100
120
140
INPUT FREQUENCY (Hz)
160
180
200
220
0
NORMAL MODE REJECTION (dB)
NORMAL MODE REJECTION (dB)
0
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
–40
–60
–80
–100
–120
0
15
30
45
60
75
90 105 120 135 150 165 180 195 210 225 240
INPUT FREQUENCY (Hz)
2480 F36
Figure 36. Input Normal Mode Rejection vs Input Frequency
with Input Perturbation of 100% Full-Scale (50Hz/60Hz Mode)
2480 F37
Figure 37. Measured Input Normal Mode Rejection
vs Input Frequency with Input Perturbation of 150%
Full-Scale (60Hz Notch)
2480fc
36
LTC2480
APPLICATIONS INFORMATION
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
–20
–40
–60
–80
–20
–40
–60
–80
–100
–100
–120
0
INPUT NORMAL REJECTION (dB)
NORMAL MODE REJECTION (dB)
0
0
–120
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
INPUT FREQUENCY (Hz)
0
fN
2fN 3fN 4fN 5fN 6fN 7fN
INPUT SIGNAL FREQUENCY (fN)
2480 F39
2480 F38
Figure 39. Input Normal Mode
Rejection 2x Speed Mode
–20
–20
–40
–60
–80
–100
MEASURED DATA
VCC = 5V
CALCULATED DATA VREF = 5V
VINCM = 2.5V
VIN(P-P) = 5V
FO = GND
TA = 25oC
–40
–60
–80
–100
–120
248 250 252 254 256 258 260 262 264
INPUT SIGNAL FREQUENCY (fN)
–120
–80
NO AVERAGE
–90
–100
–110
WITH
RUNNING
AVERAGE
–120
–130
–140
0
25
50 75 100 125 150 175 200 225
INPUT FREQUENCY (Hz)
2480 F48
Figure 40. Input Normal Mode
Rejection 2x Speed Mode
–70
NORMAL MODE REJECTION (dB)
0
NORMAL MODE REJECTION (dB)
INPUT NORMAL REJECTION (dB)
Figure 38. Measured Input Normal Mode Rejection
vs Input Frequency with Input Perturbation of 150%
Full-Scale (50Hz Notch)
0
8fN
2480 F41
Figure 41. Input Normal Mode
Rejection vs Input Frequency,
2x Speed Mode and 50Hz/60Hz Mode
to measure microvolt level signals superimposed over volt
level perturbations and the LTC2480 is eminently suited
for such tasks. When the perturbation is differential, the
speciﬁcation of interest is the normal mode rejection for
large input signal levels. With a reference voltage VREF = 5V,
the LTC2480 has a full-scale differential input range of
5V peak-to-peak. Figures 37 and 38 show measurement
results for the LTC2480 normal mode rejection ratio with a
7.5V peak-to-peak (150% of full-scale) input signal superimposed over the more traditional normal mode rejection
ratio results obtained with a 5V peak-to-peak (full-scale)
input signal. In Figure 37, the LTC2480 uses the internal
oscillator with the notch set at 60Hz (fO = LOW) and in
Figure 38 it uses the internal oscillator with the notch set
at 50Hz. It is clear that the LTC2480 rejection performance
is maintained with no compromises in this extreme situation. When operating with large input signal levels, the
60
62
54 56
58
48 50
52
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
2480 F42
Figure 42. Input Normal Mode
Rejection 2x Speed Mode
user must observe that such signals do not violate the
device absolute maximum ratings.
Using the 2x speed mode of the LTC2480, the device
bypasses the digital offset calibration operation to double
the output data rate. The superior normal mode rejection
is maintained as shown in Figures 30 and 31. However,
the magniﬁed details near DC and fS = 256fN are different,
see Figures 39 and 40. In 2x speed mode, the bandwidth is
11.4Hz for the 50Hz rejection mode, 13.6Hz for the 60Hz
rejection mode and 12.4Hz for the 50Hz/60Hz rejection
mode. Typical measured values of the normal mode rejection of the LTC2480 operating with the internal oscillator
and 2x speed mode is shown in Figure 41.
When the LTC2480 is conﬁgured in 2x speed mode, by
performing a running average, a SINC1 notch is combined
with the SINC4 digital ﬁlter, yielding the normal mode
2480fc
37
LTC2480
APPLICATIONS INFORMATION
rejection identical as that for the 1x speed mode. The
averaging operation still keeps the output rate with the
following algorithm:
Result 1 = average (sample 0, sample 1)
Result 2 = average (sample 1, sample 2)
……
Result n = average (sample n – 1, sample n)
The main advantage of the running average is that it
achieves simultaneous 50Hz/60Hz rejection at twice the
effective output rate, as shown in Figure 42. The raw output
data provides a better than 70dB rejection over 48Hz to
62.4Hz, which covers both 50Hz ±2% and 60Hz ±2%. With
running average on, the rejection is better than 87dB for
both 50Hz ±2% and 60Hz ±2%.
Complete Thermocouple Measurement System with
Cold Junction Compensation
The LTC2480 is ideal for direct digitization of thermocouples and other low voltage output sensors. The input
has a typical offset error of 500nV (2.5μV max) offset
drift of 10nV/°C and a noise level of 600nVRMS. The input
span may be optimized for various sensors by setting the
gain of the PGA. Using an external 5V reference with a
PGA gain of 64 gives a ±78mV input range—perfect for
thermocouples.
Figure 44 (last page of this data sheet) is a complete type
K thermocouple meter. The only signal conditioning is a
simple surge protection network. In any thermocouple
meter, the cold junction temperature sensor must be at
the same temperature as the junction between the thermocouple materials and the copper printed circuit board
traces. The tiny LTC2480 can be tucked neatly underneath
an Omega MPJ-K-F thermocouple socket ensuring close
thermal coupling.
The LTC2480’s 1.4mV/°C PTAT circuit measures the
cold junction temperature. Once the thermocouple voltage and cold junction temperature are known, there are
many ways of calculating the thermocouple temperature
including a straight-line approximation, lookup tables or
a polynomial curve ﬁt. Calibration is performed by applying an accurate 500mV to the ADC input derived from an
LT®1236 reference and measuring the local temperature
with an accurate thermometer as shown in Figure 43. In
calibration mode, the up and down buttons are used to
adjust the local temperature reading until it matches an
accurate thermometer. Both the voltage and temperature
calibration are easily automated.
The complete microcontroller code for this application is
available on the LTC2480 product Web page at:
http://www.linear.com
It can be used as a template for may different instruments
and it illustrates how to generate calibration coefﬁcients
for the onboard temperature sensor. Extensive comments
detail the operation of the program. The read_LTC2480()
function controls the operation of the LTC2480 and is
listed below for reference.
5V
ISOTHERMAL
C8
1μF
LT1236
2
+
G1
NC1M4V0
IN OUT
TRIM
GND
4
6
5
R2
2k
R7
8k
R8
1k
4
IN+
IN–
5
3
2
REF
VCC
CS
SCK
LTC2480 SDO
SDI
GND GND FO
8
C7
0.1μF
6
9
7
1
10
11
2480 F43
TYPE K
THERMOCOUPLE
JACK
(OMEGA MPJ-K-F)
26.3C
Figure 43. Calibration Setup
2480fc
38
LTC2480
APPLICATIONS INFORMATION
/*** read_LTC2480() ************************************************************
This is the function that actually does all the work of talking to the LTC2480.
The spi_read() function performs an 8 bit bidirectional transfer on the SPI bus.
Data changes state on falling clock edges and is valid on rising edges, as
determined by the setup_spi() line in the initialize() function.
A good starting point when porting to other processors is to write your own
spi_write function. Note that each processor has its own way of configuring
the SPI port, and different compilers may or may not have built-in functions
for the SPI port. Also, since the state of the LTC2480ʼs SDO line indicates
when a conversion is complete you need to be able to read the state of this line
through the processorʼs serial data input. Most processors will let you read
this pin as if it were a general purpose I/O line, but there may be some that
donʼt.
When in doubt, you can always write a “bit bang” function for troubleshooting
purposes.
The “fourbytes” structure allows byte access to the 32 bit return value:
struct fourbytes
{
int8 te0;
int8 te1;
int8 te2;
int8 te3;
};
//
//
//
//
//
//
Define structure of four consecutive bytes
To allow byte access to a 32 bit int or float.
The make32() function in this compiler will
also work, but a union of 4 bytes and a 32 bit int
is probably more portable.
Also note that the lower 4 bits are the configuration word from the previous
conversion. The 4 LSBs are cleared so that
they donʼt affect any subsequent mathematical operations. While you can do a
right shift by 4, there is no point if you are going to convert to floating point
numbers - just adjust your scaling constants appropriately.
*******************************************************************************/
signed int32 read_LTC2480(char config)
{
union
// adc_code.bits32
all 32 bits
{
// adc_code.by.te0
byte 0
signed int32 bits32;
// adc_code.by.te1
byte 1
struct fourbytes by;
// adc_code.by.te2
byte 2
} adc_code;
// adc_code.by.te3
byte 3
output_low(CS);
while(input(PIN_C4)) {}
// Enable LTC2480 SPI interface
// Wait for end of conversion. The longest
// you will ever wait is one whole conversion period
// Now is the time to switch any multiplexers because the conversion is finished
// and you have the whole data output time for things to settle.
adc_code.by.te3
adc_code.by.te2
adc_code.by.te1
adc_code.by.te0
=
=
=
=
0;
spi_read(config);
spi_read(0);
spi_read(0);
output_high(CS);
// Set upper byte to zero.
// Read first byte, send config byte
// Read 2nd byte, send speed bit
// Read 3rd byte. ʻ0ʼ argument is necessary
// to act as SPI master!! (compiler
// and processor specific.)
// Disable LTC2480 SPI interface
// Clear configuration bits and subtract offset. This results in
// a 2ʼs complement 32 bit integer with the LTC2480ʼs MSB in the 2^20 position
adc_code.by.te0 = adc_code.by.te0 & 0xF0;
adc_code.bits32 = adc_code.bits32 - 0x00200000;
return adc_code.bits32;
} // End of read_LTC2480()
2480fc
39
LTC2480
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev B)
R = 0.125
TYP
6
0.40 p 0.10
10
0.70 p0.05
3.55 p0.05
1.65 p0.05
2.15 p0.05 (2 SIDES)
3.00 p0.10
(4 SIDES)
PACKAGE
OUTLINE
1.65 p 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD) DFN REV B 0309
5
0.25 p 0.05
0.50 BSC
0.75 p0.05
0.200 REF
0.25 p 0.05
1
0.50
BSC
2.38 p0.05
(2 SIDES)
2.38 p0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION
OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT
STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661 Rev E)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
10 9 8 7 6
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.497 ± 0.076
(.0196 ± .003)
REF
0° – 6° TYP
GAUGE PLANE
1 2 3 4 5
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
0.86
(.034)
REF
1.10
(.043)
MAX
0.18
(.007)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.1016 ± 0.0508
(.004 ± .002)
MSOP (MS) 0307 REV E
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
2480fc
40
LTC2480
REVISION HISTORY
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
11/09
Revised Tables 3 and 4.
17
C
04/10
Added H-Grade to Absolute Maximum Ratings, Order Information, Electrical Characteristics (Normal Speed),
Electrical Characteristics (2x Speed), Converter Characteristics, Power Requirements, and Timing Characteristics.
2-5
2480fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
41
LTC2480
TYPICAL APPLICATION
5V
PIC16F73
C8
1μF
C7
0.1μF
18
17
16
15
14
13
12
11
28
27
26
25
24
23
22
21
7
6
5
4
3
2
ISOTHERMAL
R2
2k
4
IN+
IN–
TYPE K
THERMOCOUPLE
JACK
(OMEGA MPJ-K-F)
5
3
REF
2
VCC
CS
SCK
LTC2480 SDO
SDI
GND GND fO
8
6
9
7
1
10
11
5V
D7
D6
2 s 16 CHARACTER
D5
LCD DISPLAY
D4
(OPTREX DMC162488
EN
OR SIMILAR)
RW
CONTRAST
GND D0 D1 D2 D3 RS
VCC
5V
1
3
R6
5k
2
5V
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
RA5
RA4
RA3
RA2
RA1
RA0
VDD
OSC1
OSC2
MCLR
20
5V
C6
0.1μF
9
Y1
6MHz
10
R1
1 10k
D1
BAT54
5V
9
VSS
19
VSS
2480 F44
CALIBRATE
2
1
R3
10k
DOWN
R4
10k
R5
10k
UP
Figure 44. Complete Type K Thermocouple Meter
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5μV Offset, 1.6μVP-P Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460
Micropower Series Reference
0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400
24-Bit, No Latency ΔΣ ADC in SO-8
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2401/LTC2402
1-/2-Channel, 24-Bit, No Latency ΔΣ ADCs in MSOP
0.6ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency ΔΣ ADCs
with Differential Inputs
0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200μA
LTC2410
24-Bit, No Latency ΔΣ ADC with Differential Inputs
0.8μVRMS Noise, 2ppm INL
LTC2411/LTC2411-1 24-Bit, No Latency ΔΣ ADCs with Differential Inputs in MSOP 1.45μVRMS Noise, 4ppm INL,
Simultaneous 50Hz/60Hz Rejection (LTC2411-1)
24-Bit, No Latency ΔΣ ADC with Differential Inputs
LTC2413
LTC2415/LTC2415-1 24-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate
Simultaneous 50Hz/60Hz Rejection, 800nVRMS Noise
Pin-Compatible with the LTC2410
LTC2414/LTC2418
8-/16-Channel 24-Bit, No Latency ΔΣ ADCs
0.2ppm Noise, 2ppm INL, 3ppm Total Unadjusted Errors 200μA
LTC2420
20-Bit, No Latency ΔΣ ADC in SO-8
1.2ppm Noise, 8ppm INL, Pin-Compatible with LTC2400
LTC2430/LTC2431
20-Bit, No Latency ΔΣ ADCs with Differential Inputs
2.8μV Noise, SSOP-16/MSOP Package
LTC2435/LTC2435-1 20-Bit, No Latency ΔΣ ADCs with 15Hz Output Rate
3ppm INL, Simultaneous 50Hz/60Hz Rejection
LTC2440
High Speed, Low Noise 24-Bit ΔΣ ADC
3.5kHz Output Rate, 200nV Noise, 24.6 ENOBs
LTC2482
16-Bit ΔΣ ADC with Easy Drive Inputs
Pin-Compatible with LTC2480/LTC2484
LTC2484
24-Bit ΔΣ ADC with Easy Drive Inputs
Pin-Compatible with LTC2480/LTC2482
2480fc
42 Linear Technology Corporation
LT 0410 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005

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