Ordering number : EN8265A
LC709006A
CMOS IC
I/O-Expander for Microcontroller
http://onsemi.com
Overview
The LC709006A is a peripheral IC dedicated for expanding the capability of the microcontroller (MCU) I/O ports.
It interfaces with the microcontroller through synchronous serial communication. Communication with the extended
I/O ports is accomplished through 24-bit parallel I/O. The extended port features include the capabilities to specify the
I/O direction on a bit basis, to specify the output type (CMOS or N-channel open drain), and to specify the I/O
voltage level on a port basis according to the power level of the peripheral equipment. These features make allow the
LC709004A to be used in a wide variety of applications.
Features
• 4-/5-wire synchronous serial transmission and reception, and 24-bit parallel I/O
• Wide operating voltage range (2.0V to 6.0V)
• Multifunction I/O ports
- I/O direction specification: Bit units
- CMOS or Nch-OD output type specification: Bit units
- Output voltage adjustment: Port (8 bits) units
• Output current: 12mA max. (capable of driving a green LED directly)
• Data transmission and reception: Can control reception of input data and transmission of output data in parallel.
• Cascaded configuration: Ports can be expanded in units of 24 bits × n (n is the number of LSI chips).
• Packaging from: MFP36SDJ (375mil): lead-free type
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.2
N0712HKIM B8-8713 No.8265-1/14
LC709006A
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = VSS P0= VSSP2 = 0V
Ratings
Parameter
Maximum supply voltage
Input voltage
Symbol
Pin/Remarks
VDD max
VDD, VDDP0,
VI
VDDP1, VDDP2
RES, CS, DIN,
CLK
Output voltage
VO
DOUT
Input/output voltage
VIO(1)
Port 0
VIO(2)
Port 1
VIO(3)
Port 2
IOPH(1)
Ports 0 to 2
Conditions
VDD=VDDP0=
VDDP1=VDDP2
VDD[V]
min
typ
Unit
max
-0.3
+7.0
-0.3
VDD+0.3
-0.3
VDD+0.3
VDDP0
-0.3
V
+0.3
-0.3
VDDP1
+0.3
-0.3
VDDP2
+0.3
High level output current
Peak output current
Mean output current
(Note 1)
Total output current
IOPH(2)
DOUT
IOMH(1)
Ports 0 to 2
IOMH(2)
DOUT
IOP0H
Port 0
CMOS output
applicable pin
-13
CMOS output
-3
selected Per 1
applicable pin
Total of all
applicable pins
IOP1H
Port 1
Total of all
applicable pins
IOP2H
Port 2
Total of all
applicable pins
IOAH
DOUT, ports 0 to 1
-7
selected Per 1
Total of all
applicable pins
-6
mA
-32
-32
-32
-105
Low level output current
Peak output current
IOPL(1)
Ports 0 to 2
Per 1 applicable
16
IOPL(2)
DOUT
pin
13
Mean output current
IOML(1)
ports 0 to 2
Per 1 applicable
7
(Note 1)
IOML(2)
DOUT
pin
6
Total output current
IOP0L
Port 0
Total of all
32
applicable pins
IOP1L
Port 1
mA
Total of all
32
applicable pins
IOP2L
Port 2
Total of all
32
applicable pins
IOAL
DOUT, ports 0 to 2
Total of all
105
applicable pins
Power dissipation
Pd max
MFP36SDJ
Ta=-30 to +70°C
330
Ta=-40 to +85°C
250
mW
Operating temperature
Topr
-40
85
Storage temperature
Tstg
-55
125
°C
Note 1: The mean output current is a mean value measured over 100ms.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.8265-2/14
LC709006A
Allowable Operating Conditions at Ta = -40 to +85°C, VSS = VSS P0= VSSP2 = 0V
Specification (Note 3)
Parameter
Symbol
Pin/Remarks
Operating supply voltage
VDD(1)
VDD
VDD(2)
VDDP0
Conditions
VDD[V]
min
typ
Unit
max
2.0
6.0
VDD-3.0
VDD
VDD
VDD+3.0
Supply voltage must
be within VDD (1)'s
specification.
VDD(3)
VDDP1, VDDP2
Supply voltage must
be within VDD (1)'s
specification.
High level input voltage
Low level input voltage
VIH(1)
DIN, ports 0 to 2
4.5 to 6.0
0.3VDD+0.7
VDDPx
VIH(2)
DIN, ports 0 to 2
2.0 to 6.0
0.3VDD+0.7
VDDPx
VIH(3)
RES, CS, CLK
4.5 to 6.0
0.4VDD+0.7
VDD
VIH(4)
RES, CS, CLK
2.0 to 6.0
0.4VDD+0.7
VDD
VIL(1)
DIN, ports 0 to 2
4.5 to 6.0
VSS
0.2VDD+0.1
VIL(2)
DIN, ports 0 to 2
2.0 to 6.0
VSS
0.2VDD+0.1
VIL(3)
RES, CS, CLK
4.5 to 6.0
VSS
0.1VDD+0.2
VIL(4)
RES, CS, CLK
2.0 to 6.0
VSS
0.1VDD+0.2
V
Note 3: VDDPx denote the power supply pin (VDDP0,VDDP1,VDDP2) for port pins.
No.8265-3/14
LC709006A
Electrical Characteristics at Ta = -40 to +85°C, VSS = VSS P0= VSSP2 = 0V
(Note 3)
Parameter
High level input
Symbol
IIH
current
Pin/Remarks
RES, CS, CLK,
Ports 0 to 2
Conditions
VIN=VDD
(including output Tr.
VDD[V]
VDDPx[V]
Specification
min
typ
max
2.0 to 6.0
10
off leakage current)
Lower level input
IIL
current
RES, CS, CLK,
Ports 0 to 2
VIN=VSS
(including output Tr.
Unit
μA
2.0 to 6.0
-10
off leakage current)
High level output
VOH(1)
IOH=-2mA
2.0 to 6.0
4.5 to 6.0
VDDPx-0.5
voltage
VOH(2)
IOH=-5mA
2.0 to 6.0
4.5 to 6.0
VDDPx-1.0
VOH(3)
IOH=-1mA
2.0 to 6.0
2.0 to 6.0
VDDPx-0.5
IOH=-2mA
2.0 to 6.0
4.5 to 6.0
VDDPx-0.5
VOH(5)
IOH=-5mA
2.0 to 6.0
4.5 to 6.0
VDDPx-1.0
VOH(6)
IOH=-1mA
2.0 to 6.0
2.0 to 6.0
VDDPx-0.5
IOH=-5mA
4.5 to 6.0
VDDPx-0.5
VOH(8)
IOH=-10mA
4.5 to 6.0
VDDPx-1.0
VOH(9)
IOH=-2mA
2.0 to 6.0
IOL=5mA
4.5 to 6.0
2.0 to 6.0
VOH(4)
VOH(7)
Ports 0
Ports 1
DOUT
V
VOL(1)
voltage
VOL(2)
IOL=12mA
4.5 to 6.0
2.0 to 6.0
1
VOL(3)
IOL=2mA
2.0 to 6.0
2.0 to 6.0
0.4
0.4
VOL(4)
Ports 0
VDDPx-0.5
Lower level output
IOL=5mA
4.5 to 6.0
4.5 to 6.0
VOL(5)
IOL=12mA
4.5 to 6.0
4.5 to 6.0
1
VOL(6)
IOL=2mA
2.0 to 6.0
2.0 to 6.0
0.4
IOL=5mA
4.5 to 6.0
VOL(8)
IOL=10mA
4.5 to 6.0
1
VOL(9)
IOL=2mA
2.0 to 6.0
0.4
VOH=VSS
4.5 to 6.0
VOL(7)
Ports 1,2
0.4
DOUT
Pull-up resistance
Rpu(1)
CS
Voltage hysteresis
VHIS
RES, CS, CLK
Consumption current
IDDSP
VDD=VDDP0=
VDDP1=VDDP2
(operation stopped)
2.0 to 6.0
0.4
100
230
650
0.1VDD
kΩ
V
RES=CS=VDD
CLK=DIN=VDD or VSS
DOUT=open
2.0 to 6.0
20
μA
P0 to P2=open or VDD
or VSS (Note 2)
Pin capacity
CP
All pins
Other than test pin
VIN=VSS
f=1MHz
2.0 to 6.0
10
pF
Ta=25°C
Note 2: The consumption current does not include the current flowing into the port's output transistor.
Note 3: VDDPx denote the power supply pin (VDDP0,VDDP1,VDDP2) for port pins.
No.8265-4/14
LC709006A
Switching I/O Characteristics at Ta=-40 to +85°C, VDD=VDDP0=VDDP1=VDDP2, VSS=VSSP0=VSSP1=VSSP2, VSS=0V
Specification
Parameter
Clock setup time
Symbol
TsCLK
Pin/Remarks
CS, CLK
Conditions
VDD[V]
min
typ
Unit
max
•Specified with
respect to falling
edge of CS.
2.0 to 6.0
100
2.0 to 6.0
100
2.0 to 6.0
100
2.0 to 6.0
200
4.5 to 6.0
250
•See Fig. 9.
Chip select low level setup
TslCS
CS, CLK
time
•Specified with
respect to falling
edge of CS.
•See Fig. 9.
Chip select low level hold
ThlCS
CS, CLK
time
•Specified with
respect to falling
edge of CS.
•See Fig. 9.
Clock hold time
ThCLK
CS, CLK
•Specified with
respect to falling
edge of CS.
•See Fig. 9.
Clock low level pulse width
Clock high level pulse
TwlCLK
TwhCLK
CLK
CLK
•See Fig. 9.
•See Fig. 9.
width
2.0 to 6.0
200
2.0 to 6.0
100
2.0 to 6.0
200
2.0 to 6.0
150
4.5 to 6.0
30
2.0 to 6.0
50
•Specified with
4.5 to 6.0
50
respect to falling
edge of CLK.
2.7 to 6.0
150
300
ThhCS
CS, RES
•See Fig. 9.
TwlCS
CS, RES
•See Fig. 9.
Reset low level pulse width
TwlRES
CS, RES
•See Fig. 9.
Data setup time
TsDIN
DIN
•Specified with
time
width
respect to falling
edge of CLK.
•See Fig. 9.
Serial data output delay
ThDIN
TdD0UT
DIN
DOUT
time
(Note 4)
Port data output delay time
Port data input setup time
TdPOUT
TsPIN
Port 0 to 2
Port 0 to 2
•See Fig. 9.
2.0 to 6.0
4.5 to 6.0
200
respect to falling
edge of CLK.
2.7 to 6.0
400
•See Fig. 9.
2.0 to 6.0
800
•Specified with
4.5 to 6.0
200
respect to rising
edge of CS.
2.7 to 6.0
400
•See Fig. 9.
2.0 to 6.0
800
•Specified with
4.5 to 6.0
30
2.0 to 6.0
50
•Specified with
4.5 to 6.0
50
respect to rising
edge of CLK.
2.7 to 6.0
150
•See Fig. 9.
2.0 to 6.0
300
•See Fig. 9.
ThPIN
Port 0 to 2
ns
•Specified with
respect to rising
edge of CLK.
Port data input hold time
250
500
•See Fig. 9.
Data hold time
4.5 to 6.0
1000
CS, RES
Chip select low level pulse
1000
2.0 to 6.0
setup time
Chip select high level hold
500
2.0 to 6.0
2.7 to 6.0
TshCS
Chip select high level
2.7 to 6.0
Note 4: The input data of P00 will be out from DOUT terminal at the first negative edge of CLK signal. Because of this,
Serial data output delay time of the first clock will be the time measured from the negative edge of the CLK or
the time at the input data (P00) is settled.
No.8265-5/14
LC709006A
Package Dimensions
unit : mm (typ)
3263
15.2
0.65
7.9
19
10.5
36
1
0.8
0.3
18
0.25
0.1
(2.25)
2.45max
(0.8)
SANYO : MFP36SDJ(375mil)
Pin Assignment
VSSP0
DOUT
DIN
CLK
CS
VDD
RES
VSS
P27
P26
P25
P24
P23
P22
P21
P20
VSSP2
VDDP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
LC709006A
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VDDP0
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
VDDP1
Top view
No.8265-6/14
LC709006A
Block Diagram
DIN
DOUT
Control logic
Serial/parallel converter/shift register
CLK
CS
VDD
VSS
I/O control/output register
RES
VDDP0
VDDP2
P00
Port0 I/O buffer
Port 2 I/O buffer
P27
P07
P20
VSSP0
VSSP2
P17
P10
VDDP1
Port 1 I/O buffer
Pin Description
Pin Name
VSS
VSSP0
I/O
-
Description
I/O Type
Reset Time
• - power supply pin
• VSS is the power supply pin for blocks other than I/O ports (P00 to P27).
• VSSP0 is the power supply pin for port pins P00 to P07.
VSSP2
• VSSP2 is the power supply pin for port pins P10 to P17 and P20 to P27.
VDD
VDDP0
-
• + power supply pin
• VDD is the power supply pin for blocks other than I/O ports (P00 to P27).
• VDDP0 is the power supply pin for port pins P00 to P07.
VDDP1
VDDP2
• VDDP1 is the power supply pin for port pins P10 to P17.
• VDDP2 is the power supply pin for port pins P20 to P27.
(Notes)
• VDDP0 must not be set higher than VDD l (VDDP0≤VDD).
• VDDP1 must not be set lower than VDD (VDDP1≥VDD).
• VDDP2 must not be set lower than VDD (VDDP2≥VDD).
Port 0
I/O
P00 to P07
• 8-bit I/O port
Output:
• I/O specifiable in 1 bit units.
CMOS/Nch-OD
• CMOS/Nch-open drain specifiable in 1 bit units.
Input: TTL
Hi-Z
• Output voltage variable in 1 port units according to VDDP0 voltage.
Port 1
I/O
P10 to P17
• 8-bit I/O port
Output:
• I/O specifiable in 1 bit units.
CMOS/Nch-OD
• CMOS/Nch-open drain specifiable in 1 bit units.
Input: TTL
Hi-Z
• Output voltage variable in 1 port units according to VDDP1 voltage.
Port 2
P20 to P27
I/O
• 8-bit I/O port
Output:
• I/O specifiable in 1 bit units.
CMOS/Nch-OD
• CMOS/Nch-open drain specifiable in 1 bit units.
Input: TTL
Hi-Z
• Output voltage variable in 1 port units according to VDDP2 voltage.
Continued on next page.
No.8265-7/14
LC709006A
Continued from preceding page.
Pin Name
I/O
I/O Type
Description
DIN
I
• Serial data input pin
DOUT
O
• Serial data output pin
Output: CMOS
• Serial clock input pin
Input: TTL
• Port data is placed on DOUT on the falling edge of this clock.
Schmidt
CLK
I
Reset Time
Input: TTL
High
• The data from DIN is latched on the negative-to-positive transition of this clock.
CS
RES
I
I
• Chip select input pin
Input: TTL
• Setting this pin to the low level enables serial data to be input or output.
Schmidt
• Device's system reset input pin
Input: TTL
• Setting this pin to the low level initializes the internal control circuit and registers and
Schmidt
puts DOUT in the high level and all data port pins (P00 to P27) into the Hi-Z state.
Port Output Types and I/O States
The output type and I/O states of the LC709006A's ports can be selected by configuring the data direction register
(DDR) and data register (DTR). Port data can be taken into the LC709006A only when DDR is set to 0 (Nch-open
drain) and DTR is set to 1 (Nch-Tr OFF). The ports are held high for the other settings of DDR and DTR.
Port
Port Name
DDR
DTR
Output Type
P00 to P07
Input
Output
Hi-Z
0
1
Nch-open drain
Enabled
0
0
Nch-open drain
Disabled (High)
Low
1
1
CMOS
Disabled (High)
High
1
0
CMOS
Disabled (High)
Low
P10 to P17
P20 to P27
Port Output Circuit
Nch-open drain
CMOS
VDDP0 to 2
Principles of Operation
The LC709006A accomplishes data transmission and reception to and from the MCU through synchronous serial
communication and performs I/O operations on the extended ports in parallel mode. Its communication modes (MCU to
LC709006A by serial to parallel conversion and LC709006A to MCU by parallel to serial conversion) include the
initial communication modes (modes 0 and 1) in which the LC709006A initializes itself and the data communication
mode in which the LC709006A sends and receives port data. The initial communication modes are used for various
communication control purposes for the first time in system operation after a power-on or system reset. In these modes,
the LC709006A sets up the I/O mode and output type of the ports. The data communication mode is used for
communication control after the end of the initial communication modes. In this mode, the LC709006A carries out
actual port I/O operations. The port I/O mode and output type settings are stored in the data direction register (DDR).
The data output state settings ("High" output, "Hi-Z" output, or "Low" output) are stored in the data register (DTR).
The LC709006A's operating modes are summarized below, followed by detailed mode descriptions.
Communication Mode
Description
Mode 0
Sets the output type of all ports to "N-ch-open drain."
Mode 1
Sets the I/O direction of the ports and the their output type to CMOS or "Nch-open-drain" on a bit basis.
Initial communication mode
Data communication mode
Sends and receives port data.
No.8265-8/14
LC709006A
(1) Initial communication modes
• Mode 0
1) Setting the RES pin to the low level initializes the system, sets the DOUT pin to the high level, and sets the DDR
register of all ports to 0 and the DTR register to 1. The output type of the ports is set to Nch-open drain and their
I/O state (Nch-Tr=OFF) to the "Hi-Z" (input mode) state.
2) When the RES pin is set high (reset) and the CS pin is set and held low for a certain period (TwlCS), the DDR is
fixed at 0. Subsequently, the LC709006A is placed in the data communication mode.
RES
CS
CLK
DIN
DOUT
DDR
DTR
Hi-Z
P00 to P27
* DDR and DTR denote the state of the internal registers.
Fig. 1
• Mode 1
1) When the RES pin is set to the low level, the LC709006A initializes the system, sets the DOUT pin to the high
level, and sets the DDR register of all ports to 0 and the DTR register to 1. The output type of the ports is set to
Nch-open drain and their I/O state (Nch-Tr=OFF) to the "Hi-Z" (input mode) state.
2) When the RES pins is set high (reset) and the CS pin is set low, the LC709006A gets ready for serial
communication.
3) The input data at P00 is sent directly to the DOUT pin on the first falling edge of the transmission clock signal
CLK. The data at pins P01 to P27 is loaded into the shift register on the rising edge of the next clock.
4) Subsequently, the ports' input data, which is loaded into the shift register on the falling edge of CLK, is placed at
the DOUT pin sequentially (P00→P07, P20→P27) in synchronization with the falling edges of CLK, starting at
port pin P00. In parallel with this operation, when data to be placed at the ports is supplied to the DIN pin
sequentially starting at the port pin P00 (P00→P07, P10→P17, P20→P27), it is loaded into the internal shift
register in synchronization with the rising edges of CLK.
5) When the CS pin is set high after the rising edge of the 24th clock, the data loaded in the shift register is loaded
into the DDR register which determines the I/O mode and output type of the data (serial data is loaded into the
DDR register after a reset is effected). Subsequently, the LC709006A controls serial data transmission and
reception in the data communication mode.
RES
CS
CLK
DIN
DOUT
0
1
6
7
8
9
14
15
16
17
22
P00_DR
P01_DR
P06_DR
P07_DR
P10_DR
P11_DR
P16_DR
P17_DR
P20_DR
P21_DR
P26_DR
P00_DI
P01_DI
P06_DI
P07_DI
P10_DI
P11_DI
P16_DI
P17_DI
P20_DI
P21_DI
P26_DI
23
P27_DR
P27_DI
DDR
DTR
P00 to P27
Hi-Z
Hi-Z
Hi-Z
Hi-Z
* PXX_DR denotes the input data to the port DDR identified by PXX.
* PXX_DI denotes the input data from the port pin identified by PXX.
Fig. 2
No.8265-9/14
LC709006A
(2) Data communication mode
1) When the CS pin is set low with the RES pin held high, the LC709006A gets ready for serial communication.
(Subsequently, processing in steps 2) and 3) are identical to steps 2) and 3) in paragraph (1)-2).
2) The input data at P00 is sent directly to the DOUT pin on the first falling edge of the CLK signal. Data at pins
P01 to P27 is loaded into the shift register on the next rising edge of the clock.
3) Subsequently, the ports' input data, which is loaded into the shift register on the falling edge of CLK, is placed at
the DOUT pin sequentially (P00→P07, P10→P17, P20→P27) in synchronization with the falling edges of CLK,
starting at port pin P00. In parallel with this operation, when data to be placed at the ports is supplied to the DIN
pin sequentially starting at the port pin P00 (P00→P07, P10→P17, P20→P27), it is loaded into the internal shift
register in synchronization with the rising edges of CLK.
4) When the CS pin is set high after the rising edge of the 24th clock, the data loaded in the shift register is loaded
into the DDR register which determines the output state of the ports and the states of all port pins (P00 to P27) are
then changed (output) according to the conditions established in the DDR and DTR registers. Serial data that
occurs following the initial communication mode processing is always loaded into the DTR register.
RES
CS
CLK
0
DIN
DOUT
P27_DI(Previous Data)
6
7
8
17
22
23
P00_DO
P01_DO
1
P06_DO
P07_DO
P10_DO
P11_DO
9
14
P16_DO
15
P17_DO
16
P20_DO
P21_DO
P26_DO
P27_DO
P00_DI
P01_DI
P06_DI
P07_DI
P10_DI
P11_DI
P16_DI
P17_DI
P20_DI
P21_DI
P26_DI
P27_DI
DDR
DTR
P00 to P27
Hi-Z
Hi-Z
Hi-Z
Hi-Z
P00-P27_OUT
* PXX_DO denotes the output data to the port pin identified by PXX.
Fig. 3
5) Subsequently, the state of all port pins (P00 to P27) is updated each time the set of steps 1) to 4) described in
paragraph (2) are performed.
RES
CS
CLK
7
8
P01_DO
P06_DO
P07_DO
P10_DO
P11_DO
P16_DO
P17_DO
P20_DO
P21_DO
P26_DO
P00_DI
P01_DI
P06_DI
P07_DI
P10_DI
P11_DI
P16_DI
P17_DI
P20_DI
P21_DI
P26_DI
0
DIN
DOUT
6
P00_DO
P27_DI(Previous Data)
1
9
14
15
16
17
22
23
P27_DO
P27_DI
DDR
DTR
P00 to P27
P00-P27_OUT(Previous Data)
P00-P27_OUT(Previous Data)
P00-P27_OUT(Previous Data)
P00-P27_OUT(Previous Data)
P00-P27_OUT
Fig. 4
Note: Connect a Pull-up resister (about 100kΩ) to CS using MCU VDD.
No.8265-10/14
LC709006A
Application Examples
(1) Example of a cascade configuration
Two or more LC709006A LSI chips can be cascaded to realize port expansion beyond 24 bits. Port expansion,
however, need to be made in units of 24 bits × n (n denotes the number of LSI chips).
VDD
Microcontroller(MCU)
Serial CS Output(CS)
Serial Clock Output(SCK)
LC709006
LC709006
CS
CS
CLK
Serial Data Output(SDO)
LC709006
CS
CLK
CLK
DIN
DOUT
DIN
DOUT
DIN
DOUT
RES
(LSI=1)
RES
(LSI=2)
RES
(LSI=n)
System Reset(RES)
Serial Data Input(SDI)
System Reset
Fig. 5
(2) Variable port power level example
When controlling the level of I/O ports according to the power voltage level of the peripheral equipment, the user
can connect the output from the power supply of the peripheral equipment directly to the power supply pins for the
I/O ports. The LC709006A dispenses with the need to add an external level shifter circuit.
Note the following when configuring the LC709006A in this way:
Note 5:
• VDDP0: The voltage level of VDDP0 must not be higher than that of VDD (VDDP0≤VDD).
• VDDP1: The voltage level of VDDP1 must not be lower than that of VDD (VDDP1≥VDD).
• VDDP2: The voltage level of VDDP2 must not be lower than that of VDD (VDDP2≥VDD).
• The input level of all ports (P00 to P27) is dependent on the VDD power source; it depends on none of the power
sources VDDP0 to VDDP2.
* Be sure to check the electrical characteristics of the LC709006A.
3.3V
0.1μF
VDD
2.5V
VDD
VDDP0
P00 to P07
Microcontroller(MCU)
2.5V parallel data I/O
2.5V peripheral
RES, CE,
3.3V serial send/receive CLK, DIN, DOUT
5V
VDDP1
LC709006
P10 to P17
VSS
5V parallel data I/O
5V peripheral
5V
VDDP2
P20 to P27
Nch-open drain display
data output
LED display
VSS, VSSP0, VSSP2
Fig. 6
No.8265-11/14
LC709006A
Example of Placing Bypass Capacitors between VDD and VSS Terminals
2.5V
C1
5.0V
VSSP0
VSSP0
VDDP0
5.0V
C1
3.3V
VDD
C1
VSS
LC709006
VDD
VSS
VSSP2
LC709006
VSSP2
5.0V
5.0V
VDDP2
VDDP0
5.0V
VDDP2
VDDP1
5.0V
C1
VDDP1
C1
(a) The case of using single voltage
(VDD= VDDP0= VDDP1= VDDP2)
(b) The case of using variable voltage
Fig. 7
In the case of using single voltage source as showing in the Fig.7 (a), you must connect a bypass capacitor (C1, about
0.1μF) between VDD and VSS. When connecting the capacitor (C1) and VDD-VSS, use a thick wire, and try to make
its length as short as possible: moreover, try to make the impedance of VDD-C1 and VSS-C1 equal.
In addition, when using several voltage sources as showing in the Fig.7 (b), it is suggested to connect the bypass
capacitor to each set of the voltage terminals.
VDD
RRES
RES
CRES
Note:
The values of CRES and RRES must be determined so
that a reset period of 1μs or longer is set up after the
operating voltage goes beyond its lower-limit value and
the reset can be released after the operating power
voltage is completely reached.
Fig. 8: Reset Circuit
No.8265-12/14
LC709006A
CS
CLK
TsCLK
TslCS TwlCLK TwhCLK
ThlCS
ThCLK
CS
RES
TshCS
TwlRES
ThhCS
TwlCS
CLK
DIN
TsDIN
ThDIN
CLK
DOUT
TdDOUT
CS
P00 to P27
TdPOUT
CS
CLK
P00 to P27
TsPIN
ThPIN
Fig. 9: Serial I/O and Parallel Data I/O Timing Diagram
No.8265-13/14
LC709006A
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PS No.8265-14/14