TI1 DS90UR916Q 5 - 65 mhz 24-bit color fpd-link ii deserializer with image enhancement Datasheet

DS90UR916Q
5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image
Enhancement
General Description
Features
The DS90UR916Q FPD-Link II deserializer operates with the
DS90UR905Q FPD-Link II serializer to deliver 24-bit digital
video data over a single differential pair. The DS90UR916Q
provides features designed to enhance image quality at the
display. The high speed serial bus scheme of FPD-Link II
greatly eases system design by eliminating skew problems
between clock and data, reduces the number of connector
pins, reduces the interconnect size, weight, and cost, and
overall eases PCB layout. In addition, internal DC balanced
decoding is used to support AC-coupled interconnects.
The DS90UR916Q Des (deserializer) recovers the data
(RGB) and control signals and extracts the clock from the serial stream. The Des locks to the incoming serial data stream
without the use of a training sequence or special SYNC patterns, and does not require a reference clock. A link status
(LOCK) output signal is provided. The DS90UR916Q is ideally suited for 24-bit color applications. White balance lookup
tables and adaptive Hi-FRC dithering provide the user a costeffective means to enhance display image quality.
Serial transmission is optimized with user selectable receiver
equalization. EMI is minimized by the use of low voltage differential signaling, output slew control, and the Des may be
configured to generate Spread Spectrum Clock and Data on
its parallel outputs.
The DS90UR916Qis offered in a 60-pin LLP package. It is
specified over the automotive AEC-Q100 grade 2 temperature range of -40°C to +105°C.
■ 5 – 65 MHz PCLK support (140 Mbps – 1.82 Gbps)
■ RGB888 + VS, HS, DE support
■ Image enhancement - White balance LUTs and Adaptive
■
■
■
■
■
■
■
■
■
■
■
■
■
Hi-FRC dithering
AC coupled STP interconnect cable up to 10 meters
@ Speed link BIST mode and reporting pin
I2C compatible Serial Control Bus
Power down mode minimizes power dissipation
1.8V or 3.3V compatible LVCMOS I/O interface
Automotive grade product: AEC-Q100 Grade 2 qualified
>8 kV HBM and ISO 10605 ESD Rating
FAST random data lock; no reference clock required
Adjustable input receiver equalization
LOCK (real time link status) reporting pin
EMI minimization on output parallel bus (SSCG)
Output Slew control (OS)
Backward compatible mode for operation with older
generation devices
Applications
■ Automotive Display for Navigation
■ Automotive Display for Entertainment
Applications Diagram
30115627
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2012 Texas Instruments Incorporated
301156 SNOSB46D
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DS90UR916Q 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement
February 22, 2012
DS90UR916Q
Block Diagrams
30115629
Ordering Information
NSID
Package Description
Quantity
SPEC
Package ID
DS90UR916QSQ
60–pin LLP, 9.0 X 9.0 X 0.8 mm, 0.5 mm pitch
1000
NOPB
SQA60B
DS90UR916QSQX
60–pin LLP, 9.0 X 9.0 X 0.8 mm, 0.5 mm pitch
2000
NOPB
SQA60B
DS90UR916QSQE
60–pin LLP, 9.0 X 9.0 X 0.8 mm, 0.5 mm pitch
250
NOPB
SQA60B
Note: Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market,
including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades
defined in the AEC Q100 standard. Automotive Grade products are identified with the letter Q. For more information go to
http://www.national.com/automotive.
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2
DS90UR916Q
DS90UR916Q Pin Diagram
30115620
Deserializer - DS90UR916Q — Top View
3
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DS90UR916Q
DS90UR916Q Deserializer Pin Descriptions
Pin Name
Pin #
I/O, Type
Description
LVCMOS Parallel Interface
R[7:0]
33, 34, 35,
36, 37, 39,
40, 41
I, STRAP, RED Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
O, LVCMOS In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 5). These
pins are inputs during power-up (See STRAP Inputs).
G[7:0]
20, 21, 22,
23, 25, 26,
27, 28
I, STRAP, GREEN Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
O, LVCMOS In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 5). These
pins are inputs during power-up (See STRAP Inputs).
B[7:0]
9, 10, 11,
12, 14, 17,
18, 19
I, STRAP, BLUE Parallel Interface Data Output Pins (MSB = 7, LSB = 0)
O, LVCMOS In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 5). These
pins are inputs during power-up (See STRAP Inputs).
HS
8
O, LVCMOS Horizontal Sync Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 5). Video
control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to
2 transitions per 130 PCLKs.
VS
7
O, LVCMOS Vertical Sync Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 5). Video
control signal is limited to 1 transition per 130 PCLKs. Thus, the minimum pulse width is 130
PCLKs.
DE
6
O, LVCMOS Data Enable Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 5). Video
control signal pulse width must be 3 PCLKs or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00). The signal is limited to
2 transitions per 130 PCLKs.
PCLK
5
O, LVCMOS Pixel Clock Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 5). Strobe
edge set by RFB function.
LOCK
32
O, LVCMOS LOCK Status Output
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, RGB[7:0], HS,
VS, DE and PCLK output states are controlled by OSS_SEL (See Table 5). May be used
as Link Status or to flag when Video Data is active (ON/OFF).
PASS
42
O, LVCMOS PASS Output (BIST Mode)
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
Control and Configuration — STRAP PINS
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pins are read upon
power-up and set device configuration. Pin Number listed along with shared RGB Output name in square brackets.
CONFIG[1:0]
10 [B6],
9 [B7]
STRAP
Operating Modes — Pin or Register Control
I, LVCMOS These pins determine the DS90UR916’s operating mode and interfacing device.
w/ pull-down CONFIG[1:0] = 00: Interfacing to DS90UR905, Control Signal Filter DISABLED
CONFIG[1:0] = 01: Interfacing to DS90UR905, Control Signal Filter ENABLED
CONFIG[1:0] = 10: Interfacing to DS90UR241
CONFIG[1:0] = 11: Interfacing to DS90C241
LF_MODE
12 [B4]
STRAP
SSCG Low Frequency Mode — Pin or Register Control
I, LVCMOS Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE
w/ pull-down (X).
LF_MODE = 1, SSCG in low frequency mode (PCLK = 5-20 MHz)
LF_MODE = 0, SSCG in high frequency mode (PCLK = 20-65 MHz)
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I/O, Type
DS90UR916Q
Pin Name
Pin #
Description
OS_PCLK
11 [B5]
STRAP
PCLK Output Slew Select — Pin or Register Control
I, LVCMOS OS_PCLK = 1, increased PCLK slew
w/ pull-down OS_PCLK = 0, normal (default)
OS_DATA
14 [B3]
STRAP
Data Output Slew Select — Pin or Register Control
I, LVCMOS OS_DATA = 1, increased DATA slew
w/ pull-down OS_DATA = 0, normal (default)
OP_LOW
42 PASS
OSS_SEL
17 [B2]
STRAP
Output Sleep State Select — Pin or Register Control
I, LVCMOS NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW =1
w/ pull-down OSS_SEL is used in conjunction with PDB to determine the state of the outputs when
inactive. (See Table 5).
RFB
18 [B1]
STRAP
Pixel Clock Output Strobe Edge Select — Pin or Register Control
I, LVCMOS RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
w/ pull-down RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
EQ[3:0]
20 [G7],
21 [G6],
22 [G5],
23 [G4]
STRAP
Receiver Input Equalization — Pin or Register Control
I, LVCMOS (See Table 2).
w/ pull-down
OSC_SEL[2:0]
26 [G2],
27 [G1],
28 [G0]
STRAP
Oscillator Select — Pin or Register Control
I, LVCMOS (See Table 6 and Table 7).
w/ pull-down
SSC[3:0]
34 [R6],
35 [R5],
36 [R4],
37 R[3]
STRAP
Spread Spectrum Clock Generation (SSCG) Range Select — Pin or Register Control
I, LVCMOS (See Table 3 and Table 4).
w/ pull-down
MAP_SEL[1:0]
40 [R1],
41 [R0]
STRAP
Bit Mapping Backward Compatibility / DS90UR241 Options — Pin or Register Control
I, LVCMOS Normal setting to b'00. See (Table 8).
w/ pull-down
STRAP
Outputs held Low when LOCK = 1 — Pin or Register Control
I, LVCMOS NOTE: IT IS NOT RECOMMENDED TO USE ANY OTHER STRAP OPTIONS WITH THIS
w/ pull-down STRAP FUNCTION
OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH
NOTE: Before the device is powered up, the outputs are in tri-state.
See Figure 20 and Figure 21.
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default).
Control and Configuration
PDB
59
I, LVCMOS Power Down Mode Input
w/ pull-down PDB = 1, Des is enabled (normal operation).
Refer to “Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by Table
5. Control Registers are RESET.
ID[x]
56
I, Analog
SCL
3
I, LVCMOS
Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to VDDIO.
SDA
2
I/O,
LVCMOS
Open Drain
Serial Control Bus Data Input / Output - Optional
SDA requires an external pull-up resistor to VDDIO.
BISTEN
44
I, LVCMOS BIST Enable Input — Optional
w/ pull-down BISTEN = 1, BIST is enabled
BISTEN = 0, BIST is disabled
RES
47
I, LVCMOS Reserved - tie LOW
w/ pull-down
Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 9)
5
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DS90UR916Q
Pin Name
NC
Pin #
I/O, Type
1, 15, 16,
30, 31, 45,
46, 60
Description
Not Connected
Leave pin open (float)
FPD-Link II Serial Interface
RIN+
49
I, LVDS
True Input. The input must be AC Coupled with a 100 nF capacitor.
RIN-
50
I, LVDS
Inverting Input. The input must be AC Coupled with a 100 nF capacitor.
CMF
51
I, Analog
Common-Mode Filter
VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
CMLOUTP
52
O, LVDS
Test Monitor Pin — EQ Waveform
NC or connect to test point. Requires Serial Bus Control to enable.
CMLOUTN
53
O, LVDS
Test Monitor Pin — EQ Waveform
NC or connect to test point. Requires Serial Bus Control to enable.
VDDL
29
Power
Logic Power, 1.8 V ±5%
VDDIR
48
Power
Input Power, 1.8 V ±5%
VDDR
43, 55
Power
RX High Speed Logic Power, 1.8 V ±5%
VDDSC
4, 58
Power
SSCG Power, 1.8 V ±5%
VDDPR
57
Power
PLL Power, 1.8 V ±5%
VDDCMLO
54
Power
RX High Speed Logic Power, 1.8 V ±5%
13, 24, 38
Power
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (VDDIO)
DAP
Ground
DAP is the large metal contact at the bottom side, located at the center of the LLP package.
Connected to the ground plane (GND) with at least 9 vias.
Power and Ground
VDDIO
GND
NOTE: 1 = HIGH, 0 = LOW
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
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6
θJC(based on 9 thermal vias)
ESD Rating (HBM)
2.8 °C/W
ESD Rating (MM)
Recommended Operating
Conditions
Supply Voltage (VDDn)
LVCMOS Supply
Voltage (VDDIO)
OR
LVCMOS Supply
Voltage (VDDIO)
Operating Free Air
Temperature (TA)
PCLK Clock Frequency
Supply Noise (Note 10)
1/θJA mW / °C
24.6 °C/W
ESD Rating (CDM)
For soldering specifications:
see product folder at www.national.com and
www.national.com/ms/MS/MS-SOLDERING.pdf
470mW
θJA(based on 9 thermal vias)
≥±8 kV
≥±1 kV
≥±250 V
ESD Rating (ISO10605), RD = 2kΩ, CS = 150pF or RD =
2kΩ, CS = 330pF or RD = 330Ω, CS = 150pF
Air Discharge (RIN+, RIN−)
≥±30 kV
Contact Discharge (RIN+, RIN−)
≥±10 kV
Contact Discharge (RIN+, RIN−)
−0.3V to +2.5V
−0.3V to +4.0V
−0.3V to +(VDDIO + 0.3V)
−0.3V to (VDD + 0.3V)
+150°C
−65°C to +150°C
Min
1.71
1.71
Nom
1.8
1.8
Max
1.89
1.89
Units
V
V
3.0
3.3
3.6
V
−40
5
+25
+105
65
50
°C
MHz
mVP-P
≥±10 kV
ESD Rating (ISO10605), RD = 330Ω, CS = 330pF
Air Discharge (RIN+, RIN−)
≥±15 kV
Deserializer DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
VDDIO
V
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Input Current
VOH
VOL
VIN = 0V or VDDIO
GND
0.8
V
+15
μA
−15
±1
IOH = −2 mA, OS_PCLK/DATA = L
R[7:0], G
[7:0], B[7:0],
HS, VS, DE,
PCLK, LOCK,
PASS
2.4
VDDIO
Low Level Output Voltage
IOL = +2 mA, OS_PCLK/DATA = L
R[7:0], G
[7:0], B[7:0],
HS, VS, DE,
PCLK, LOCK,
PASS
GND
Output Short Circuit Current
VDDIO = 3.3V
VOUT = 0V, OS_PCLK/DATA = L/H
PCLK
36
mA
Output Short Circuit Current
VDDIO = 3.3V
VOUT = 0V, OS_PCLK/DATA = L/H
Des Outputs
37
mA
TRI-STATE® Output
Current
PDB = 0V, OSS_SEL = 0V,
VOUT = 0V or VDDIO
Outputs
High Level Output Voltage
IOS
IOZ
2.2
PDB,
BISTEN
V
0.4
V
−15
+15
µA
1.235
VDDIO
V
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
IIN
Input Current
PDB,
BISTEN
VIN = 0V or VDDIO
GND
−15
7
±1
0.595
V
+15
μA
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DS90UR916Q
ESD Rating (IEC 61000–4–2), RD = 330Ω, CS = 150pF
Air Discharge (RIN+, RIN−)
≥±25 kV
If Military/Aerospace specified devices are required,
please contact the Texas Instruments Sales Office/
Distributors for availability and specifications.
Supply Voltage – VDDn (1.8V)
Supply Voltage – VDDIO
LVCMOS I/O Voltage
Receiver Input Voltage
Junction Temperature
Storage Temperature
60L LLP Package
Maximum Power Dissipation
Capacity at 25°C
Derate above 25C
≥±10 kV
Contact Discharge (RIN+, RIN−)
Absolute Maximum Ratings (Note 1)
DS90UR916Q
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
R[7:0], G
[7:0], B[7:0],
HS, VS, DE,
PCLK, LOCK,
PASS
VDDIO−
0.45
VDDIO
Max
Units
VOH
High Level Output Voltage
IOH = −2 mA, OS_PCLK/DATA = L
VOL
Low Level Output Voltage
IOL = +2 mA, OS_PCLK/DATA = L
Output Short Circuit Current
VDDIO = 1.8V
VOUT = 0V, OS_PCLK/DATA = L/H
PCLK
18
mA
Output Short Circuit Current
VDDIO = 1.8V
VOUT = 0V, OS_PCLK/DATA = L/H
Des Outputs
18
mA
TRI-STATE Output Current
PDB = 0V, OSS_SEL = 0V,
VOUT = 0V or VDDIO
Outputs
IOS
IOZ
GND
V
0.45
-15
+15
V
µA
LVDS RECEIVER DC SPECIFICATIONS
VTH
Differential Input Threshold
High Voltage
VTL
Differential Input Threshold
Low Voltage
VCM
Common Mode Voltage,
Internal VBIAS
IIN
Input Current
RT
Internal Termination
Resistor
+50
mV
−50
mV
VCM = +1.2V (Internal VBIAS)
RIN+, RINVIN = 0V or VDDIO
1.2
-15
80
100
V
+15
µA
120
Ω
CML DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
VOD
Differential Output Voltage
RL = 100Ω
VOS
Offset Voltage
Single-ended
RL = 100Ω
RT
Internal Termination
Resistor
CMLOUTP,
CMLOUTN
80
542
mV
1.4
V
100
120
Ω
93
110
mA
33
45
mA
62
75
mA
40
3000
µA
5
50
µA
10
100
µA
SUPPLY CURRENT
IDD1
IDDIO1
IDDZ
IDDIOZ
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Deserializer
Supply Current
(includes load current)
Checker Board Pattern,
OS_PCLK/DATA = H,
EQ = 001,
SSCG=ON,CMLOUTP/N
enabled
CL = 4pF, Figure 1
Deserializer Supply Current PDB = 0V, All other
Power Down
LVCMOS Inputs = 0V
VDD= 1.89V
All VDD pins
VDDIO=1.89V
VDDIO = 3.6V
VDD= 1.89V
VDDIO=1.89V
VDDIO = 3.6V
8
VDDIO
All VDD pins
VDDIO
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
tRCP
PCLK Output Period
tRDC
PCLK Output Duty Cycle
tCLH
tCHL
tROS
tROH
LVCMOS
Low-to-High
Transition Time, Figure 2
LVCMOS
High-to-Low
Transition Time, Figure 2
Typ
Max
Units
15.38
T
200
ns
PCLK
43
50
57
%
SSCG=ON, 5–20MHz
35
59
65
%
SSCG=ON, 20–65MHz
40
53
60
%
VDDIO = 1.8V
CL = 4 pF (lumped load)
PCLK/RGB[7:0], HS,
VS, DE
VDDIO = 1.8V
CL = 4 pF (lumped load)
VDDIO = 1.71 to 1.89V or
3.0 to 3.6V
CL = 4 pF (lumped load)
RGB[7:0], HS, VS, DE
tDD
Des Delay - Latency, Figure 3
tDPJ
Des Period Jitter
Des Cycle-to-Cycle Jitter
Des Input Jitter Tolerance,
Figure 8
2.0
ns
1.6
ns
1.5
ns
0.27
0.45
T
0.4
0.55
T
VDDIO = 3.3V
CL = 4 pF (lumped load)
Data Valid after PCLK – Hold
Time, Figure 6
Deserializer Lock Time,
Figure 5
ns
PCLK/RGB[7:0], HS,
VS, DE
RGB[7:0], HS, VS, DE
Horizontal Blanking Time
2.1
VDDIO = 3.3V
CL = 4 pF (lumped load)
VDDIO = 1.71 to 1.89V or
3.0 to 3.6V
CL = 4 pF (lumped load)
tDDLT
tRJIT
Pin/Freq.
SSCG=OFF, 5–65MHz
Min
PCLK
Data Valid before PCLK – Set
Up Time, Figure 6
tHBLANK
tDCCJ
Conditions
HS
tRCP
6
SSC[3:0] = 0000 (OFF),
(Note 6)
PCLK = 5 MHz
SSC[3:0] = 0000 (OFF),
(Note 6)
PCLK = 65MHz
SSC[3:0] = ON,
(Note 6)
PCLK = 5MHz
SSC[3:0] = ON,
(Note 6)
PCLK = 65MHz
139*T
140 * T
ns
SSC[3:0] = OFF,
(Note 8, Note 11)
PCLK = 5 MHz
975
1700
ps
PCLK = 10 MHz
500
1000
ps
PCLK = 65 MHz
550
1250
ps
PCLK = 5 MHz
675
1150
ps
PCLK = 10 MHz
375
900
ps
PCLK = 65 MHz
500
1150
ps
for jitter freq < 2MHz
0.9
UI
0.5
UI
SSC[3:0] = OFF,
(Note 9, Note 11)
EQ = OFF,
SSCG = OFF,
PCLK = 65MHz
for jitter freq > 6MHz
3
ms
4
ms
30
ms
6
ms
BIST Mode
tPASS
BIST PASS Valid Time,
BISTEN = 1, Figure 9
1
10
ns
SSCG Mode
fDEV
fMOD
Spread Spectrum
Clocking Deviation
Frequency
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
±0.5
±2
%
Spread Spectrum
Clocking Modulation
Frequency
PCLK = 5 to 65 MHz,
SSC[3:0] = ON
8
100
kHz
9
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DS90UR916Q
Deserializer Switching Characteristics
DS90UR916Q
Recommended Timing for the Serial Control Bus
Over +3.3V supply and temperature ranges unless otherwise specified.
Symbol
Parameter
fSCL
SCL Clock Frequency
tLOW
SCL Low Period
Conditions
Max
Units
>0
100
kHz
Fast Mode
>0
400
kHz
Standard Mode
4.7
us
Fast Mode
1.3
us
Standard Mode
4.0
us
Standard Mode
Min
Typ
tHIGH
SCL High Period
Fast Mode
0.6
us
tHD;STA
Hold time for a start or a
repeated start condition,
Figure 10
Standard Mode
4.0
us
0.6
us
Set Up time for a start or a
repeated start condition,
Figure 10
Standard Mode
4.7
us
0.6
us
Data Hold Time,
Figure 10
Standard Mode
0
3.45
us
Fast Mode
0
0.9
us
Data Set Up Time,
Figure 10
Standard Mode
250
ns
Fast Mode
100
ns
tSU;STO
Set Up Time for STOP
Condition, Figure 10
Standard Mode
4.0
us
Fast Mode
0.6
us
tBUF
Bus Free Time
Between STOP and START,
Figure 10
Standard Mode
4.7
us
1.3
us
SCL & SDA Rise Time,
Figure 10
Standard Mode
1000
ns
Fast Mode
300
ns
SCL & SDA Fall Time,
Figure 10
Standard Mode
300
ns
Fast mode
300
ns
tSU:STA
tHD;DAT
tSU;DAT
tr
tf
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Fast Mode
Fast Mode
Fast Mode
10
Over 3.3V supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
VIH
Input High Level
SDA and SCL
2.2
VIL
Input Low Level Voltage
SDA and SCL
GND
VHY
Input Hysteresis
Typ
Max
Units
VDDIO
V
0.8
>50
VOL
SDA, IOL = 1.25mA
Iin
SDA or SCL, Vin = VDDIO or GND
V
mV
0
0.4
V
-15
+15
µA
SDA, RPU = X, Cb ≤ 400pF
tR
SDA RiseTime – READ
40
ns
tF
SDA Fall Time – READ
25
ns
tSU;DAT
Set Up Time — READ
520
ns
tHD;DAT
Hold Up Time — READ
55
ns
tSP
Input Filter
Cin
Input Capacitance
SDA or SCL
50
ns
<5
pF
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 5: When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data transfer require tPLD
Note 6: tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK.
Note 7: UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*PCLK). The UI scales with PCLK frequency.
Note 8: tDPJ is the maximum amount the period is allowed to deviate over many samples.
Note 9: tDCCJ is the maximum amount of jitter between adjacent clock cycles.
Note 10: Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with amplitude = 100
mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise
frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the noise frequency is less than 400 kHz.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: Specification is guaranteed by design and is not tested in production.
11
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DS90UR916Q
DC and AC Serial Control Bus Characteristics
DS90UR916Q
AC Timing Diagrams and Test Circuits
30115632
FIGURE 1. Checkerboard Data Pattern
30115605
FIGURE 2. Deserializer LVCMOS Transition Times
30115611
FIGURE 3. Deserializer Delay – Latency
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DS90UR916Q
30115613
FIGURE 4. Deserializer Disable Time (OSS_SEL = 0)
30115614
FIGURE 5. Deserializer PLL Lock Times and PDB TRI-STATE Delay
30115635
FIGURE 6. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = Off
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DS90UR916Q
30115634
FIGURE 7. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = On
30115616
FIGURE 8. Receiver Input Jitter Tolerance
30115652
FIGURE 9. BIST PASS Waveform
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DS90UR916Q
30115636
FIGURE 10. Serial Control Bus Timing Diagram
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DS90UR916Q
The DS90UR905 / DS90UR916Q chipset can operate in 24bit color depth (with VS,HS,DE encoded in the DCA bit) or in
18-bit color depth (with VS, HS, DE encoded in DCA or
mapped into the high-speed data bits). In 18–bit color applications, the three video signals maybe sent encoded via the
DCA bit (restrictions apply) or sent as “data bits” along with
three additional general purpose signals.
Functional Description
The DS90UR905 / DS90UR916Q chipset transmits and receives 27-bits of data (24-high speed color bits and 3 low
speed video control signals) over a single serial FPD-Link II
pair operating at 140Mbps to 1.82Gbps. The serial stream also contains an embedded clock, video control signals and the
DC-balance information which enhances signal quality and
supports AC coupling. The pair is intended for use with each
other but is backward compatible with previous generations
of FPD-Link II as well.
The Des can attain lock to a data stream without the use of a
separate reference clock source, which greatly simplifies system complexity and overall cost. The Des also synchronizes
to the Ser regardless of the data pattern, delivering true automatic “plug and lock” performance. It can lock to the incoming serial stream without the need of special training patterns
or sync characters. The Des recovers the clock and data by
extracting the embedded clock information, validating and
then deserializing the incoming data stream providing a parallel LVCMOS video bus to the display. White balance LUTs
and dithering features are provided to enable display image
enhancement.
Data Transfer
The DS90UR905 / DS90UR916Q chipset will transmit and
receive a pixel of data in the following format: C1 and C0 represent the embedded clock in the serial stream. C1 is always
HIGH and C0 is always LOW. b[23:0] contain the scrambled
RGB data. DCB is the DC-Balanced control bit. DCB is used
to minimize the short and long-term DC bias on the signal
lines. This bit determines if the data is unmodified or inverted.
DCA is used to validate data integrity in the embedded data
stream and can also contain encoded control (VS,HS,DE).
Both DCA and DCB coding schemes are generated by the
Ser and decoded by the Des automatically. Figure 11 illustrates the serial stream per PCLK cycle.
30115637
FIGURE 11. FPD-Link II Serial Stream (905/916)
Des OPERATING MODES AND BACKWARD
COMPATIBILITY (CONFIG[1:0])
The DS90UR916Q is also backward compatible with previous
generations of FPD-Link II. Configuration modes are provided
for backwards compatibility with the DS90C124 FPD-Link II
Generation 1, and also the DS90UR124 FPD-Link II Generation 2 chipset by setting the respective mode with the CONFIG[1:0] pins or control register as shown in Table 1. The
selection also determines whether the Video Control Signal
filter feature is enabled or disabled in Normal mode.
When the DS90UR916 deserializer is configured to operate
in backward compatible modes the image enhancement features (white balance and FRC dithering) are not available.
Video Control Signal Filter
When operating the devices in Normal Mode, the Video Control Signals (DE, HS, VS) have the following restrictions:
• Normal Mode with Control Signal Filter Enabled:
DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, the transition pulse must be 3 PCLK or longer.
• Normal Mode with Control Signal Filter Disabled:
DE and HS — Only 2 transitions per 130 clock cycles are
transmitted, no restriction on minimum transition pulse.
• VS — Only 1 transition per 130 clock cycles are
transmitted, minimum pulse width is 130 clock cycles.
Video Control Signals are defined as low frequency signals
with limited transitions. Glitches of a control signal can cause
a visual display error. This feature allows for the chipset to
validate and filter out any high frequency noise on the control
signals. See Figure 12.
TABLE 1. DS90UR916Q Des Modes
CON
FIG1
CON Mode
FIG0
Des Device
L
L
Normal Mode, Control
Signal Filter disabled
DS90UR905
L
H
Normal Mode, Control
Signal Filter enabled
DS90UR905
H
L
Backwards Compatible
GEN2
DS90UR241
H
H
Backwards Compatible
GEN1
DS90C241
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30115642
FIGURE 12. Video Control Signal Filter Waveform
DESERIALIZER Functional Description
The Des converts a single input serial data stream to a wide
parallel output bus, and also provides a signal check for the
chipset Built In Self Test (BIST) mode. Several image enhancement features are provided (Note that these features
are not available when operating in backward compatible
modes). White balance LUTs allow the user to define and target the color temperature of the display. Adaptive Hi-FRC
dithering enables the presentation of “true-color” images on
an 18–bit color display. The device can be configured via external pins and strap pins or through the optional serial control
bus. The Des features enhance signal quality on the link by
supporting: an equalizer input and also the FPD-Link II data
coding that provides randomization, scrambling, and DC balancing of the data. The Des includes multiple features to
reduce EMI associated with display data transmission. This
includes the randomization and scrambling of the data and
also the output spread spectrum clock generation (SSCG)
support. The Des features power saving features with a power
down mode, and optional LVCMOS (1.8 V) interface compatibility.
By default, the LUT data may not be reloaded after initialization at power-on.
An option does exist to allow LUT reloading after power-on
and initial LUT loading (as described above). This option may
only be used after enabling the white balance reload feature
via the associated serial bus control register. In this mode the
LUTs may be reloaded by the master controller via I2C. This
provides the user with the flexibility to refresh LUTs periodically , or upon system requirements to change to a new set
of LUT values. The host controller loads the updated LUT
values via the serial bus interface. There is no need to disable
the white balance feature while reloading the LUT data. Refreshing the white balance to the new set of LUT data will be
seamless - no interruption of displayed data.
It is important to note that initial loading of LUT values requires
that all 3 LUTs be loaded sequentially. When reloading, partial
LUT updates may be made. Refer to Applications Information
— Using Image Enhancement Features for a detailed description of the LUT loading and reloading procedures.
Image Enhancement Features
White Balance
The White Balance feature enables similar display appearance when using LCD’s from different vendors. It compensates for native color temperature of the display, and adjusts
relative intensities of R, G, B to maintain specified color temperature. Programmable control registers are used to define
the contents of three LUTs (8-bit color value for Red, Green
and Blue) for the White Balance Feature. The LUTs map input
RGB values to new output RGB values. There are three LUTs,
one LUT for each color. Each LUT contains 256 entries, 8-bits
per entry with a total size of 6144 bits (3 x 256 x 8). All entries
are readable and writable. Calibrated values are loaded into
registers through the I2C interface (deserializer is a slave device). This feature may also be applied to lower color depth
applications such as 18–bit (666) and 16–bit (565). White balance is enabled and configured via serial bus register control.
LUT contents. The user must define and load the contents of
the LUT for each color (R,G,B). Regardless of the color depth
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DS90UR916Q
being driven (888, 666, 656), the user must always provide
contents for 3 complete LUTs - 256 colors x 8 bits x 3 tables.
Unused bits - LSBs -shall be set to “0” by the user.
When 24-bit (888) input data is being driven to a 24-bit display, each LUT (R, G and B) must contain 256 unique 8-bit
entries. The 8-bit white balanced data is then available at the
output of the DS90UR916 deserailizer, and driven to the display.
When 18-bit (666) input data is being driven to an 18-bit display, the white balance feature may be used in one of two
ways. First, simply load each LUT with 256, 8-bit entries. Each
8-bit entry is a 6-bit value (6 MSBs) with the 2 LSBs set to
“00”. Thus as total of 64 unique 6-bit white balance output
values are available for each color (R, G and B). The 6-bit
white balanced data is available at the output of the
DS90UR916 deserializer, and driven directly to the display.
Alternatively, with 6-bit input data the user may choose to load
complete 8-bit values into each LUT. This mode of operation
provides the user with finer resolution at the LUT output to
more closely achieve the desired white point of the calibrated
display. Although 8-bit data is loaded, only 64 unique 8-bit
white balance output values are available for each color (R,
G and B). The result is 8-bit white balanced data. Before driving to the output of the deserializer, the 8-bit data must be
reduced to 6-bit with an FRC dithering function. To operate in
this mode, the user must configure the DS90UR916 to enable
the FRC2 function.
Examples of the three types of LUT configurations described
are shown in Figure 13.
Enabling white balance.The user must load all 3 LUTs prior
to enabling the white balance feature. The following sequence
must be followed by the user.
To initialize white balance after power-on:
1. Load contents of all 3 LUTs . This requires a sequential
loading of LUTs - first RED, second GREEN, third BLUE. 256,
8-bit entries must be loaded to each LUT. Page registers must
be set to select each LUT.
2. Enable white balance
DS90UR916Q
30115670
FIGURE 13. White Balance LUT Configurations
lows the white balance block and is intended to be used when
fine adjustment of color temperature is required on an 18-bit
color display, or when a 24-bit source drives an 18-bit display
with a white balance LUT calibrated for 24-bit source data.
For proper operation of the FRC dithering feature, the user
must provide a description of the display timing control signals. The timing mode, “sync mode” (HS, VS) or “DE only”
must be specified, along with the active polarity of the timing
control signals. All this information is entered to DS90UR916
control registers via the serial bus interface.
Adaptive Hi-FRC dithering consists of several components.
Initially, the incoming 8-bit data is expanded to 9-bit data. This
allows the effective dithered result to support a total of 16.7
million colors. The incoming 9-bit data is evaluated, and one
of four possible algorithms is selected. The majority of incoming data sequences are supported by the default dithering
algorithm. Certain incoming data patterns (black/white pixel,
full on/off sub-pixel) require special algorithms designed to
eliminate visual artifacts associated with these specific gray
level transitions. Three algorithms are defined to support
these critical transitions.
An example of the default dithering algorithm is illustrated in
Figure 14. The “1” or “0” value shown in the table describes
whether the 6-bit value is increased by 1 (“1”) or left unchanged (“0”). In this case, the 3 truncated LSBs are “001”.
Adaptive Hi-FRC Dithering
The Adaptive FRC Dithering Feature delivers product-differentiating image quality. It reduces 24-bit RGB (8 bits per subpixel) to 18-bit RGB (6 bits per sub-pixel), smoothing color
gradients, and allowing the flexibility to use lower cost 18-bit
displays. FRC (Frame Rate Control) dithering is a method to
emulate “missing” colors on a lower color depth LCD display
by changing the pixel color slightly with every frame. FRC is
achieved by controlling on and off pixels over multiple frames
(Temporal). Static dithering regulates the number of on and
off pixels in a small defined pixel group (Spatial). The FRC
module includes both Temporal and Spatial methods and also
Hi-FRC. Conventional FRC can display only 16,194,277 colors with 6-bit RGB source. “Hi-FRC” enables full (16,777,216)
color on an 18-bit LCD panel. The “adaptive” FRC module
also includes input pixel detection to apply specific Spatial
dithering methods for smoother gray level transitions. When
enabled, the lower LSBs of each RGB output are not active;
only 18 bit data (6 bits per R,G and B) are driven to the display.
This feature is enabled via serial bus register control.
Two FRC functional blocks are available, and may be independently enabled. FRC1 precedes the white balance LUT,
and is intended to be used when 24-bit data is being driven
to an 18-bit display with a white balance LUT that is calibrated
for an 18-bit data source. The second FRC block, FRC2, fol-
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DS90UR916Q
30115671
FIGURE 14. Default FRC Algorithm
Receiver Differential Input Threshold and Input Jitter Tolerance define the acceptable data eye opening. A differential
probe should be used to measure across a 100Ohm termination resistor between the CMLOUTP/N pins. Figure 15
illustrates the eye opening.
Signal Quality Enhancers
Des — Input Equalizer Gain (EQ)
The Des can enable receiver input equalization of the serial
stream to increase the eye opening to the Des input. Note this
function cannot be seen at the RxIN+/- input but can be observed at the serial test port (CMLOUTP/N) enabled via the
Serial Bus control registers. The equalization feature may be
controlled by the external pin or by register.
TABLE 2. Receiver Equalization Configuration Table
INPUTS
EQ3
EQ2
L
L
Effect
EQ1
EQ0
L
L
H
L
H
H
~3 dB
L
H
L
H
~4.5 dB
L
H
H
H
~6 dB
H
L
L
H
~7.5 dB
H
L
H
H
~9 dB
H
H
L
H
~10.5 dB
H
H
H
H
~12 dB
X
X
X
L
OFF*
~1.5 dB
30115672
FIGURE 15. CMLOUT Eye Opening
EMI Reduction Features
Output Slew (OS_PCLK/DATA)
The parallel bus outputs (RGB[7:0], VS, HS, DE and PCLK)
of the Des feature a selectable output slew. The DATA ((RGB
[7:0], VS, HS, DE) are controlled by strap pin or register bit
OS_DATA. The PCLK is controlled by strap pin or register bit
OS_PCLK. When the OS_PCLK/DATA = HIGH, the maximum slew rate is selected. When the OS_PCLK/DATA =
LOW, the minimum slew rate is selected. Use the higher slew
* Default Setting is EQ = Off
The quality of the equalized signal may be assessed by monitoring the differential eye opening at the CMLOUTP/N. The
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DS90UR916Q
rate setting when driving longer traces or a heavier capacitive
load.
SSCG Generation — Optional
The Des provides an internally generated spread spectrum
clock (SSCG) to modulate its outputs. Both clock and data
outputs are modulated. This will aid to lower system EMI.
Output SSCG deviations to ±2.0% (4% total) at up to 35kHz
modulations nominally are available. See Table 3. This feature may be controlled by external STRAP pins or by register.
Common Mode Filter Pin (CMF) — Optional
The Des provides access to the center tap of the internal termination. A capacitor may be placed on this pin for additional
common-mode filtering of the differential pair. This can be
useful in high noise environments for additional noise rejection capability. A 0.1µF capacitor may be connected to this
pin to Ground.
TABLE 3. SSCG Configuration (LF_MODE = L) — Des Output
SSC[3:0] Inputs
LF_MODE = L (20 - 65 MHz)
Result
SSC3
SSC2
SSC1
SSC0
fdev (%)
fmod (kHz)
L
L
L
L
L
L
L
Off
Off
H
±0.5
L
L
H
L
±1.0
L
L
H
H
±1.5
L
H
L
L
±2.0
L
H
L
H
±0.5
L
H
H
L
±1.0
L
H
H
H
±1.5
H
L
L
L
±2.0
H
L
L
H
±0.5
H
L
H
L
±1.0
H
L
H
H
±1.5
H
H
L
L
±2.0
H
H
L
H
±0.5
H
H
H
L
±1.0
H
H
H
H
±1.5
PCLK/2168
PCLK/1300
PCLK/868
PCLK/650
TABLE 4. SSCG Configuration (LF_MODE = H) — Des Output
SSC[3:0] Inputs
LH_MODE = H (5 - 20 MHz)
Result
SSC3
SSC2
SSC1
SSC0
fdev (%)
fmod (kHz)
L
L
L
L
Off
Off
L
L
L
H
±0.5
L
L
H
L
±1.0
L
L
H
H
±1.5
L
H
L
L
±2.0
L
H
L
H
±0.5
L
H
H
L
±1.0
L
H
H
H
±1.5
H
L
L
L
±2.0
H
L
L
H
±0.5
H
L
H
L
±1.0
H
L
H
H
±1.5
H
H
L
L
±2.0
H
H
L
H
±0.5
H
H
H
L
±1.0
H
H
H
H
±1.5
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20
PCLK/620
PCLK/370
PCLK/258
PCLK/192
Stop Stream SLEEP Feature
The Des will enter a low power SLEEP state when the input
serial stream is stopped. A STOP condition is detected when
the embedded clock bits are not present. When the serial
stream starts again, the Des will then lock to the incoming
signal and recover the data. Note – in STOP STREAM
SLEEP, the optional Serial Bus Control Registers values are
RETAINED.
CLOCK-DATA RECOVERY STATUS FLAG (LOCK) and
OUTPUT STATE SELECT (OSS_SEL)
When PDB is driven HIGH, the CDR PLL begins locking to
the serial input and LOCK goes from TRI-STATE to LOW
(depending on the value of the OSS_SEL setting). After the
DS90UR916Q completes its lock sequence to the input serial
data, the LOCK output is driven HIGH, indicating valid data
and clock recovered from the serial input is available on the
parallel bus and PCLK outputs. The PCLK output is held at
its current state at the change from OSC_CLK (if this is enabled via OSC_SEL) to the recovered clock (or vice versa).
If there is a loss of clock from the input serial stream, LOCK
is driven Low and the state of the RGB/VS/HS/DE outputs are
based on the OSS_SEL setting (STRAP PIN configuration or
register).
30115633
FIGURE 16. SSCG Waveform
1.8V or 3.3V VDDIO Operation
The Des parallel bus and Serial Bus Interface can operate
with 1.8 V or 3.3 V levels (VDDIO) for target (Display) compatibility. The 1.8 V levels will offer a lower noise (EMI) and also
a system power savings.
Power Saving Features
PowerDown Feature (PDB)
The Des has a PDB input pin to ENABLE or POWER DOWN
the device. This pin can be controlled by the system to save
power, disabling the Des when the display is not needed. An
auto detect mode is also available. In this mode, the PDB pin
is tied High and the Des will enter POWER DOWN when the
serial stream stops. When the serial stream starts up again,
the Des will lock to the input stream and assert the LOCK pin
and output valid data. In POWER DOWN mode, the Data and
PCLK output states are determined by the OSS_SEL status.
Oscillator Output — Optional
The Des provides an optional PCLK output when the input
clock (serial stream) has been lost. This is based on an internal oscillator. The frequency of the oscillator may be selected.
This feature may be controlled by the external pin or by register. See Table 6 and Table 7.
TABLE 5. OSS_SEL and PDB Configuration — Des Outputs
INPUTS
Serial
Input
OUTPUTS
PDB
OSS_SEL
PCLK
RGB/HS/VS/DE
LOCK
PASS
X
L
X
Z
Z
Z
Z
Static
H
L
L
L
L
L
Static
H
H
Z
Z*
L
L
Active
H
X
Active
Active
H
H
*NOTE — If pin is strapped HIGH, output will be pulled up
TABLE 6. OSC (Oscillator) Mode — Des Output
INPUTS
OUTPUTS
Embedded PCLK
PCLK
RGB/HS/VS/DE
LOCK
PASS
NOTE *
OSC
Output
L
L
L
Present
Toggling
Active
H
H
* NOTE — Absent and OSC_SEL ≠ 000
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DS90UR916Q
Note – in POWER DOWN, the optional Serial Bus Control
Registers are RESET.
DS90UR916Q
30115640
FIGURE 17. Des Outputs with Output State Select Low (OSS_SEL = H)
30115653
FIGURE 18. Des Outputs with Output State Select High (OSS_SEL = L)
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22
DS90UR916Q
TABLE 7. OSC_SEL (Oscillator) Configuration
OSC_SEL[2:0] INPUTS
PCLK Oscillator Output
OSC_SEL2
OSC_SEL1
OSC_SEL0
L
L
L
Off – Feature Disabled – Default
L
L
H
50 MHz ±40%
L
H
L
25 MHz ±40%
L
H
H
16.7 MHz ±40%
H
L
L
12.5 MHz ±40%
H
L
H
10 MHz ±40%
H
H
L
8.3 MHz ±40%
H
H
H
6.3 MHz ±40%
30115654
FIGURE 19. Des Outputs with Output State High and PCLK Output Oscillator Option Enabled
2) OSS_SEL function is not available when O/P_LOW is tied
H.
Outputs RGB[7:0], HSYNC, VSYNC, DE, and PCLK are in
TRI-STATE before PDB toggles HIGH because the OP_LOW
strap value has not been recognized until the DS90UR916
powers up. Figure 20 shows the user controlled release of
OP_LOW and automatic reset of OP_LOW set on the falling
edge of LOCK. Figure 21 shows the user controlled release
of OP_LOW and manual reset of OP_LOW set. Note manual
reset of OP_LOW can only occur when LOCK is H.
OP_LOW — Optional
The OP_ LOW feature is used to hold the LVCMOS outputs
(except the LOCK output) at a LOW state. This feature is enabled by setting the OP_LOW strap pin = HIGH, followed by
the rising edge of PDB. The user must toggle the OP_LOW
Set/Reset register bit to release the outputs to the normal
toggling state. Note that the release of the outputs can only
occur when LOCK is HIGH. When the OP_LOW feature is
enabled, anytime LOCK = LOW, the LVCMOS outputs will
toggle to a LOW state again. The OP_ LOW strap pin feature
is assigned to output PASS pin 42.
Restrictions on other straps:
1) Other straps should not be used in order to keep RGB[7:0],
HS, VS, DE, and PCLK at a true LOW state. Other features
should be selected thru I2C.
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DS90UR916Q
30115665
FIGURE 20. OP_LOW Auto Set
30115666
FIGURE 21. OP_LOW Manual Set/Reset
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24
Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature supports the testing of the high-speed serial link. This is useful in
the prototype stage, equipment production, in-system test
and also for system diagnostics. In the BIST mode only a input
clock is required along with control to the Ser and Des BISTEN input pins. The Ser outputs a test pattern (PRBS7) and
drives the link at speed. The Des detects the PRBS7 pattern
and monitors it for errors. A PASS output pin toggles to flag
any payloads that are received with 1 to 24 errors. Upon completion of the test, the result of the test is held on the PASS
output until reset (new BIST test or Power Down). A high on
PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of
the test is controlled by the pulse width applied to the Des
BISTEN pin. During the BIST duration the deserializer data
outputs toggle with a checkerboard pattern.
Inter-operability is supported between this FPD-Link II device
and all FPD-Link II generations (Gen 1/2/3) — see respective
datasheets for details on entering BIST mode and control.
Sample BIST Sequence
See Figure 22 for the BIST mode flow diagram.
Step 1: Place the DS90UR905 Ser in BIST Mode by setting
Ser BISTEN = H. For the DS90UR905 Ser or DS99R421
FPD-Link II Ser BIST Mode is enabled via the BISTEN pin.
For the DS90C241 Ser or DS90UR241 Ser, BIST mode is
enetered by setting all the input data of the device to Low
state. A PCLK is required for all the Ser options. When the
Des detects the BIST mode pattern and command (DCA and
DCB code) the RGB and control signal outputs are shut off.
Step 2: Place the DS90UR916Q Des in BIST mode by setting
the BISTEN = H. The Des is now in the BIST mode and checks
the incoming serial payloads for errors. If an error in the payload (1 to 24) is detected, the PASS pin will switch low for one
half of the clock period. During the BIST test, the PASS output
can be monitored and counted to determine the payload error
rate.
Step 3: To Stop the BIST mode, the Des BISTEN pin is set
Low. The Des stops checking the data and the final test result
is held on the PASS pin. If the test ran error free, the PASS
output will be High. If there was one or more errors detected,
the PASS output will be Low. The PASS output state is held
until a new BIST is run, the device is RESET, or Powered
Down. The BIST duration is user controlled by the duration of
the BISTEN signal.
Step 4: To return the link to normal operation, the Ser BISTEN
input is set Low. The Link returns to normal operation.
Figure 23 shows the waveform diagram of a typical BIST test
for two cases. Case 1 is error free, and Case 2 shows one
with multiple errors. In most cases it is difficult to generate
errors due to the robustness of the link (differential data transmission etc.), thus they may be introduced by greatly extending the cable length, faulting the interconnect, reducing signal
condition enhancements (De-Emphasis, VODSEL, or Rx
Equalization).
Control Signal Filter — Optional
The Des provides an optional Control Signal (VS, HS, DE)
filter that monitors the three video control signals and eliminates any pulses that are 1 or 2 PCLKs wide. Control signals
must be 3 pixel clocks wide (in its HIGH or LOW state, regardless of which state is active). This is set by the CONFIG
[1:0] or by the Control Register. This feature may be controlled
by the external pin or by Register.
Low Frequency Optimization (LF_Mode)
This feature may be controlled by the external pin or by Register.
Des — Map Select
This feature may be controlled by the external pin or by Register.
TABLE 8. Map Select Configuration
INPUTS
Effect
MAPSEL1
MAPSEL0
L
L
Bit 4, Bit 5 on LSB
DEFAULT
L
H
LSB 0 or 1
H
H or L
LSB 0
Strap Input Pins
Configuration of the device maybe done via configuration input pins and the STRAP input pins, or via the Serial Control
Bus. The STRAP input pins share select parallel bus output
pins. They are used to load in configuration values during the
initial power up sequence of the device. Only a pull-up on the
pin is required when a HIGH is desired. By default the pad
has an internal pull down, and will bias Low by itself. The recommended value of the pull up is 10 kΩ to VDDIO; open (NC)
for Low, no pull-down is required (internal pull-down). If using
the Serial Control Bus, no pull ups are required.
Optional Serial Bus Control
Please see the following section on the optional Serial Bus
Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode
for details.
25
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DS90UR916Q
Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is strobed on.
If RFB is High, output data is strobed on the Rising edge of
the PCLK. If RFB is Low, data is strobed on the Falling edge
of the PCLK. This allows for inter-operability with downstream
devices. The Des output does not need to use the same edge
as the Ser input. This feature may be controlled by the external pin or by register.
DS90UR916Q
BER Calculations
It is possible to calculate the approximate Bit Error Rate
(BER). The following is required:
• Pixel Clock Frequency (MHz)
• BIST Duration (seconds)
• BIST test Result (PASS)
The BER is less than or equal to one over the product of 24
times the PCLK rate times the test duration. If we assume a
65MHz PCLK, a 10 minute (600 second) test, and a PASS,
the BERT is ≤ 1.07 X 10E-12
The BIST mode runs a check on the data payload bits. The
LOCK pin also provides a link status. It the recovery of the C0
and C1 bits does not reconstruct the expected clock signal,
the LOCK pin will switch Low. The combination of the LOCK
and At-Speed BIST PASS pin provides a powerful tool for
system evaluation and performance monitoring.
30115643
FIGURE 22. BIST Mode Flow Diagram
30115664
FIGURE 23. BIST Waveforms
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26
The DS90UR916 may also be configured by the use of a serial
control bus that is I2C protocol compatible. By default, the I2C
reg_0x00'h is set to 00'h and all configuration is set by control/
strap pins. A write of 01'h to reg_0x00'h will enable/allow configuration by registers; this will override the control/strap pins.
Multiple devices may share the serial control bus since multiple addresses are supported. See Figure 24.
30115641
FIGURE 24. Serial Control Bus Connection
30115651
FIGURE 25. START and STOP Conditions
To communicate with a remote device, the host controller
(master) sends the slave address and listens for a response
from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is addressed correctly,
it Acknowledges (ACKs) the master by driving the SDA bus
low. If the address doesn't match a device's slave address, it
Not-acknowledges (NACKs) the master by letting SDA be
pulled High. ACKs also occur on the bus when data is being
transmitted. When the master is writing data, the slave ACKs
after every data byte is successfully received. When the master is reading data, the master ACKs after every data byte is
received to let the slave know it wants to receive another data
byte. When the master wants to stop reading, it NACKs after
the last data byte and creates a stop condition on the bus. All
communication on the bus begins with either a Start condition
or a Repeated Start condition. All communication on the bus
ends with a Stop condition. A READ is shown in Figure 26
and a WRITE is shown in Figure 27.
If the Serial Bus is not required, the three pins may be left
open (NC).
TABLE 9. ID[x] Resistor Value – DS90UR916Q Des
Resistor
RID* kΩ
(5% tol)
Address
7'b
Address
8'b
0 appended
(WRITE)
0.47
7b' 111 0001 (h'71)
8b' 1110 0010 (h'E2)
2.7
7b' 111 0010 (h'72)
8b' 1110 0100 (h'E4)
8.2
7b' 111 0011 (h'73)
8b' 1110 0110 (h'E6)
Open
7b' 111 0110 (h'76)
8b' 1110 1100 (h'EC)
*Note: RID ≠ 0 ohm, do not connect directly to VSS (GND),
this is not a valid address.
27
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DS90UR916Q
The serial bus is comprised of three pins. The SCL is a Serial
Bus Clock Input. The SDA is the Serial Bus Data Input / Output signal. Both SCL and SDA signals require an external pull
up resistor to VDDIO. For most applications a 4.7 k pull up resistor to VDDIO may be used. The resistor value may be
adjusted for capacitive loading and data rate requirements.
The signals are either pulled High, or driven Low.
The third pin is the ID[X] pin. This pin sets one of four possible
device addresses. Two different connections are possible.
The pin may be pulled to VDD (1.8V, NOT VDDIO)) with a 10
kΩ resistor; or a 10 kΩ pull up resistor (to VDD 1.8V, NOT
VDDIO)) and a pull down resistor of the recommended value
to set other three possible addresses may be used. See Table
9. Do not tie ID[x] directly to VSS.
The Serial Bus protocol is controlled by START, START-Repeated, and STOP phases. A START occurs when SCL
transitions Low while SDA is High. A STOP occurs when SDA
transition High while SCL is also HIGH. See Figure 25
Optional Serial Bus Control
DS90UR916Q
30115638
FIGURE 26. Serial Control Bus — READ
30115639
FIGURE 27. Serial Control Bus — WRITE
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28
DS90UR916Q
TABLE 10. DESERIALIZER — Serial Bus Control Registers
PAGE
0
0
ADD ADD
Register Name
(dec) (hex)
0
1
0
1
Des Config 1
Slave ID
Default
Function
(bin)
Bit(s)
R/W
7
R/W
0
LFMODE
0: 20 to 65 MHz Operation
1: 5 to 20 MHz Operation
6
R/W
0
OS_PCLK
0: Normal PCLK Output Slew
1: Increased PCLK Slew
5
R/W
0
OS_DATA
0: Normal DATA OUTPUT Slew
1: Increased Data Slew
4
R/W
0
RFB
0: Data strobed on Falling edge of PCLK
1: Data strobed on Rising edge of PCLK
3:2
R/W
00
CONFIG
00: Normal Mode, Control Signal Filter
Disabled
01: Normal Mode, Control Signal Filter
Enabled
10: Backwards Compatible
(DS90UR241)
11: Backwards Compatible (DS90C241)
1
R/W
0
SLEEP
Note – not the same function as
PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings
retained.
0
R/W
0
REG Control
0: Configurations set from control pins /
STRAP pins
1: Configurations set from registers
(except I2C_ID)
7
R/W
0
6:0
R/W
1110000 ID[X]
29
Description
0: Address from ID[X] Pin
1: Address from Register
Serial Bus Device ID, Four IDs are:
7b '1110 001 (h'71)
7b '1110 010 (h'72)
7b '1110 011 (h'73)
7b '1110 110 (h'76)
All other addresses are Reserved.
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DS90UR916Q
PAGE
0
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ADD ADD
Register Name
(dec) (hex)
2
2
Des Features 1
Default
Function
(bin)
Bit(s)
R/W
7
R/W
0
OP_LOW
Release/Set
0: set outputs state LOW (except LOCK)
1: release output LOW state, outputs
toggling normally
Note: This register only works during
LOCK = 1.
6
R/W
0
OSS_SEL
Output Sleep State Select
0:PCLK/RGB[7:0]/HS/VS/DE = L, LOCK
= Normal, PASS = H
1:PCLK/RGB[7:0]/HS/VS/DE = TriState, LOCK = Normal, PASS = H
5:4
R/W
00
MAP_SEL
Special for Backwards Compatible Mode
with DS90UR241)
00: bit 4, 5 on LSB
01: LSB zero or one
10: LSB zero
11: LSB zero
3
R/W
0
OP_LOW strap
bypass
0: strap will determine whether OP_LOW
feature is ON or OFF
1: Turns OFF OP_LOW feature
2:0
R/W
00
OSC_SEL
000: OFF
001: 50 MHz ±40%
010: 25 MHz ±40%
011: 16.7 MHz ±40%
100: 12.5 MHz ±40%
101: 10 MHz ±40%
110: 8.3 MHz ±40%
111: 6.3 MHz ±40%
30
Description
0
0
ADD ADD
Register Name
(dec) (hex)
3
4
3
4
Des Features 2
CMLOUT
Config
Default
Function
(bin)
Bit(s)
R/W
7:5
R/W
000
4
R/W
0
3:0
R/W
0000
7
R/W
0
6:0
R/W
Description
EQ Gain
000: ~1.625 dB
001: ~3.25 dB
010: ~4.87 dB
011: ~6.5 dB
100: ~8.125 dB
101: ~9.75 dB
110: ~11.375 dB
111: ~13 dB
EQ Enable
0: EQ = disabled
1: EQ = enabled
SSC
IF LF_MODE = 0, then:
000: SSCG OFF
0001: fdev = ±0.5%, fmod = PCLK/2168
0010: fdev = ±1.0%, fmod = PCLK/2168
0011: fdev = ±1.5%, fmod = PCLK/2168
0100: fdev = ±2.0%, fmod = PCLK/2168
0101: fdev = ±0.5%, fmod = PCLK/1300
0110: fdev = ±1.0%, fmod = PCLK/1300
0111: fdev = ±1.5%, fmod = PCLK/1300
1000: fdev = ±2.0%, fmod = PCLK/1300
1001: fdev = ±0.5%, fmod = PCLK/868
1010: fdev = ±1.0%, fmod = PCLK/868
1011: fdev = ±1.5%, fmod = PCLK/868
1100: fdev = ±2.0%, fmod = PCLK/868
1101: fdev = ±0.5%, fmod = PCLK/650
1110: fdev = ±1.0%, fmod = PCLK/650
1111: fdev = ±1.5%, fmod = PCLK/650
IF LF_MODE = 1, then:
000: SSCG OFF
0001: fdev = ±0.5%, fmod = PCLK/620
0010: fdev = ±1.0%, fmod = PCLK/620
0011: fdev = ±1.5%, fmod = PCLK/620
0100: fdev = ±2.0%, fmod = PCLK/620
0101: fdev = ±0.5%, fmod = PCLK/370
0110: fdev = ±1.0%, fmod = PCLK/370
0111: fdev = ±1.5%, fmod = PCLK/370
1000: fdev = ±2.0%, fmod = PCLK/370
1001: fdev = ±0.5%, fmod = PCLK/258
1010: fdev = ±1.0%, fmod = PCLK/258
1011: fdev = ±1.5%, fmod = PCLK/258
1100: fdev = ±2.0%, fmod = PCLK/258
1101: fdev = ±0.5%, fmod = PCLK/192
1110: fdev = ±1.0%, fmod = PCLK/192
1111: fdev = ±1.5%, fmod = PCLK/192
Repeater Enable 0: Output CMLOUTP/N = disabled
1: Output CMLOUTP/N = enabled
0000000 Reserved
31
DS90UR916Q
PAGE
Reserved
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DS90UR916Q
PAGE
0
ADD ADD
Register Name
(dec) (hex)
21
15
FRC
Configuration
R/W
7
R/W
0
Timing mode
select
Select display timing mode
0: DE only mode
1: Sync mode (VS, HS)
6
R/W
0
VS Polarity
0: Active HIGH
1: Active LOW
5
R/W
0
HS Polarity
0: Active HIGH
1: Active LOW
4
R/W
0
DE Polarity
0: Active HIGH
1: Active LOW
3
R/W
0
FRC2 enable
0: FRC2 disabled
1: FRC2 enabled
2
R/W
0
FRC1 enable
0: FRC1 disabled
1: FRC1 enabled
0
Reserved
Reserved
[1:0]
0
22
16
White Balance
Configuration
Default
Function
(bin)
Bit(s)
Description
[7:6]
R/W
0
Page Setting
00: Configuration Registers
01: Red LUT
10: Green LUT
11: Blue LUT
5
R/W
0
White Balance
Enable
0: WB disabled
1: WB enabled
4
R/W
0
Reload Enable
0: Reload disabled
1: Reload enabled
0
Reserved
Reserved
1
0255
00 FF
White Balance
Red LUT
[FF:0]
[3:0]
R/W
N/A
Red LUT
256 8–bit entries to be applied to the Red
subpixel data
2
0255
00 FF
White Balance
Green LUT
[FF:0]
R/W
N/A
Green LUT
256 8–bit entries to be applied to the
Green subpixel data
3
0255
00 FF
White Balance
Blue LUT
[FF:0]
R/W
N/A
Blue LUT
256 8–bit entries to be applied to the Blue
subpixel data
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32
DISPLAY APPLICATION
The DS90UR905/916Q chipset is intended for interface between a host (graphics processor) and a Display. It supports
an 24-bit color depth (RGB888) and up to 1024 X 768 display
formats. In a RGB888 application, 24 color bits (R[7:0], G[7:0],
B[7:0]), Pixel Clock (PCLK) and three control bits (VS, HS and
DE) are supported across the serial link with PCLK rates from
5 to 65 MHz. The chipset may also be used in 18-bit color
applications. In this application three to six general purpose
signals may also be sent from host to display.
The Des is expected to be located close to its target device.
The interconnect between the Des and the target device is
typically in the 1 to 3 inch separation range. The input capacitance of the target device is expected to be in the 5 to 10 pF
range. Care should be taken on the PCLK output trace as this
signal is edge sensitive and strobes the data. It is also assumed that the fanout of the Des is one. If additional loads
need to be driven, a logic buffer or mux device is recommended.
33
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DS90UR916Q
TYPICAL APPLICATION CONNECTION
Figure 28 shows a typical application of the DS90UR916Q
Des using serial bus control mode for a 65 MHz 24-bit Color
Display Application. The LVDS inputs utilize 100 nF coupling
capacitors to the line and the Receiver provides internal termination. Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1 µF capacitors and two 4.7
µF capacitors should be used for local device bypassing. System GPO (General Purpose Output) signals control the PDB
and the BISTEN pins. In this application the RRFB pin is tied
Low to strobe the data on the falling edge of the PCLK.
The DS90UR916 will most often be used in serial bus control
mode as this is required to enable the image enhancement
features of the device. The schematic illustrates the proper
connection of SDA and SCL to the pull-up resistors as well as
the external resistor network to the ID[x] pin..
The interface to the target display is with 3.3V LVCMOS levels, thus the VDDIO pin is connected to the 3.3 V rail. A delay
cap is placed on the PDB signal to delay the enabling of the
device until power is stable.
Applications Information
DS90UR916Q
30115645
FIGURE 28. DS90UR916Q Typical Connection Diagram — Pin Control
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34
TRANSMISSION MEDIA
The Ser/Des chipset is intended to be used in a point-to-point
configuration, through a PCB trace, or through twisted pair
cable. The Ser and Des provide internal terminations providing a clean signaling environment. The interconnect for LVDS
should present a differential impedance of 100 Ohms. Use
cables and connectors that have matched differential
impedance to minimize impedance discontinuities. Shielded
or un-shielded cables may be used depending upon the noise
environment and application requirements.
LIVE LINK INSERTION
The Ser and Des devices support live pluggable applications.
The automatic receiver lock to random data “plug & go” hot
insertion capability allows the DS90UR916Q to attain lock to
the active data stream during a live insertion event.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the LVDS Ser/Des devices should be designed to provide low-noise power feed to
the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted
stray noise pickup, feedback and interference. Power system
performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This
arrangement provides plane capacitance for the PCB power
system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value
and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and
tantalum electrolytic types. RF capacitors may use values in
the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be
in the 2.2 uF to 10 uF range. Voltage rating of the tantalum
capacitors should be at least 5X the power supply voltage
being used.
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power
and ground pins directly to the power and ground planes with
LVDS INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
• Minimize the number of Vias
• Use differential connectors when operating above
500Mbps line speed
• Maintain balance of the traces
• Minimize skew within the pair
• Terminate as close to the TX outputs and RX inputs as
possible
Additional general guidance can be found in the LVDS
Owner’s Manual - available in PDF format from the National
web site at: www.national.com/lvds
35
www.ti.com
DS90UR916Q
bypass capacitors connected to the plane with via on both
ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the
path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces
the parasitic inductance of the capacitor. The user must pay
attention to the resonance frequency of these external bypass
capacitors, usually in the range of 20-30 MHz. To provide effective bypassing, multiple capacitors are often used to
achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common
practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for
different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit.
Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to
sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane.
Locate LVCMOS signals away from the LVDS lines to prevent
coupling from the LVCMOS lines to the LVDS lines. Closelycoupled differential lines of 100 Ohms are typically recommended for LVDS interconnect. The closely coupled lines
help to ensure that coupled noise will appear as commonmode and thus is rejected by the receivers. The tightly coupled lines will also radiate less.
Information on the LLP style package is provided in National
Application Note: AN-1187.
POWER UP REQUIREMENTS AND PDB PIN
At power-on, the PDB pin must be LOW. The transition to the
HIGH state (normal operating mode) may only occur after all
power supplies are stable and above the minimum recommended operating voltage. All other LVCMOS inputs must
also remain LOW prior to power supplies stabilized at the
recommended operating voltages. Active driving of inputs
and the transition of PDB to the HIGH state should be delayed
1usec after power supplies are stabilized.
DS90UR916Q
USING IMAGE ENHANCEMENT FEATURES
The DS90UR916Q offers two FRC dithering blocks and one
White Balance lookup table. Depending upon the color depth
of the source data, display and LUT contents, these blocks
may be independently enabled or disabled in various combinations. Refer to Table 11 below for recommendations.
To reload LUT contents, after the initial load at power-up,
the following procedure must be followed.
1. Enable RELOAD
2. Set appropriate page register (RED, GREEN or BLUE)
3. Load new LUT values (any sequence, any order, any
number)
4. Load appropriate R, G or B 255 value to clear page
register
5. Set appropriate page register (RED, GREEN or BLUE)
6. Load new LUT values (any sequence, any order, any
number)
7. Load appropriate R, G or B 255 value to clear page
register
8. Set appropriate page register (RED, GREEN or BLUE)
9. Load new LUT values (any sequence, any order, any
number)
10. Load appropriate R, G or B 255 value to clear page
register
11. Disable RELOAD
TABLE 11. Enabling Image Enhancement Features
Source White Balance LUT Display
FRC1
FRC2
24-bit
24-bit
24-bit
Disabled Disabled
24-bit
24-bit
18-bit
Disabled Enabled
24-bit
18-bit
18-bit
Enabled Disabled
18-bit
24-bit
24-bit
Disabled Disabled
18-bit
24-bit
18-bit
Disabled Enabled
18-bit
18-bit
18-bit
Disabled Disabled
If the white balance feature is to be used all 3 LUTs must be
fully loaded after initial power-up. LUTs must be loaded sequentially — first Red, second Green, third Blue — and all 256
values must be loaded into each LUT. After power-up the
following procedure must be followed.
1. Power-on (reload = disable by default)
2. Enable WB
3. Set page Register RED
4. Initial RED LUT load (all 256 bytes) '916 will self clear
page register
5. Set page Register GREEN
6. Initial GREEN LUT load (all 256 bytes)'916 will self clear
page register
7. Set page Register BLUE
8. Initial BLUE LUT load (all 256 bytes) '916 will self clear
page register
Once all LUTs are loaded, ‘916 will enable the WB output
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ALTERNATE COLOR / DATA MAPPING
Color Mapped data Pin names are provided to specify a recommended mapping for 24-bit Color Applications. Seven [7]
is assumed to be the MSB, and Zero [0] is assumed to be the
LSB. While this is recommended it is not required. When connecting to earlier generations of FPD-Link II Ser and Des
devices, a color mapping review is recommended to ensure
the correct connectivity is obtained. Table 12 provides examples for interfacing to 18-bit applications with or without the
video control signals embedded. The DS90UR916Q Des also
provides additional flexibility with the MAP_SEL feature as
well.
36
18-bit
RGB
18-bit
RGB
18-bit
RGB
24-bit
RGB
905 Pin
Name
916 Pin
Name
24-bit
RGB
18-bit
RGB
18-bit
RGB
18-bit
RGB
0
LSB R0
GP0
RO
RO
R0
R0
GP0
LSB R0
0
0
R1
GP1
R1
R1
R1
R1
GP1
R1
0
R0
R2
R0
R2
R2
R2
R2
R0
R2
R0
R1
R3
R1
R3
R3
R3
R3
R1
R3
R1
R2
R4
R2
R4
R4
R4
R4
R2
R4
R2
R3
MSB R5
R3
R5
R5
R5
R5
R3
MSB R5
R3
R4
LSB G0
R4
R6
R6
R6
R6
R4
LSB G0
R4
R5
G1
R5
R7
R7
R7
R7
R5
G1
R5
0
G2
GP2
G0
G0
G0
G0
GP2
G2
0
0
G3
GP3
G1
G1
G1
G1
GP3
G3
0
G0
G4
G0
G2
G2
G2
G2
G0
G4
G0
G1
MSB G5
G1
G3
G3
G3
G3
G1
MSB G5
G1
G2
LSB B0
G2
G4
G4
G4
G4
G2
LSB0
G2
G3
B1
G3
G5
G5
G5
G5
G3
B1
G3
G4
B2
G4
G6
G6
G6
G6
G4
B2
G4
G5
B3
G5
G7
G7
G7
G7
G5
B3
G5
0
B4
GP4
B0
B0
B0
B0
GP4
B4
0
0
MSB B5
GP5
B1
B1
B1
B1
GP5
MSB B5
0
B0
HS
B0
B2
B2
B2
B2
B0
HS
B0
B1
VS
B1
B3
B3
B3
B3
B1
VS
B1
B2
DE
B2
B4
B4
B4
B4
B2
DE
B2
B3
GP0
B3
B5
B5
B5
B5
B3
GP0
B3
B4
GP1
B4
B6
B6
B6
B6
B4
GP1
B4
B5
GP2
B5
B7
B7
B7
B7
B5
GP2
B5
HS
GND
HS
HS
HS
HS
HS
HS
GND
HS
VS
GND
VS
VS
VS
VS
VS
VS
GND
VS
DE
GND
DE
DE
DE
DE
DE
DE
GND
905 Pin
Name
916 Pin
Name
Scenario Scenario Scenario Scenario
4
3
2
1
Scenario Scenario Scenario Scenario
1
2
3
4
Scenario 2 supports an 18-bit RGB color mapping, 3 embedded video control signals, and up to six general purpose
signals. This scenario is NOT supported when FRC or white
balance are enabled on the DS90UR916.
Scenario 1
Scenario 1 supports the 24-bit RGB color mapping, along with
the 3 embedded video control signals. This is the native mode
for the chipset. FRC and white balance may be enabled with
this scenario.
Scenario 4
Scenario 4 supports an 18-bit RGB color mapping and 3 embedded video control signals. All LSBs are set to “0”. FRC and
white balance may be enabled with this scenario.
Scenario 3
Scenario 3 supports an 18-bit RGB color mapping, 3 un-embedded video control signals, and up to three general purpose
signals. This scenario is NOT supported when FRC or white
balance are enabled on the DS90UR916.
Scenario 2
37
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DS90UR916Q
TABLE 12. Alternate Color / Data Mapping — See Text Below
DS90UR916Q
Physical Dimensions inches (millimeters) unless otherwise noted
60–pin LLP Package (9.0 mm x 9.0 mm x 0.8 mm, 0.5 mm pitch)
NS Package Number SQA60B
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38
DS90UR916Q
Notes
39
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DS90UR916Q 5 - 65 MHz 24-bit Color FPD-Link II Deserializer with Image Enhancement
Notes
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