ICST ICS9DB202CFLF Two 0.7v current mode differential hcsl output pairs, 1 differential clock input Datasheet

ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS™
JITTER ATTENUATOR
GENERAL DESCRIPTION
Features
The ICS9DB202 is a high perfromance 1-to-2 Differential-to-HCSL Jitter Attenuator designed for use
HiPerClockS™ in PCI Express™ systems. In some PCI Express™
systems, such as those found in desktop PCs, the
PCI Express™ clocks are generated from a low
bandwidth, high phase noise PLL frequency synthesizer. In these
systems, a jitter-attenuating device may be necessary in order
to reduce high frequency random and deterministic jitter components from the PLL synthesizer and from the system board.
The ICS9DB202 has two PLL bandwidth modes. In low bandwidth mode, the PLL loop bandwidth is 500kHz. This setting offers the best jitter attenuation and is still high enough to pass a
triangular input spread spectrum profile. In high bandwidth mode,
the PLL bandwidth is at 1MHz and allows the PLL to pass more
spread spectrum modulation.
• Two 0.7V current mode differential HCSL output pairs
ICS
• 1 differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 140MHz
• Output skew: 110ps (maximum)
• Cycle-to-cycle jitter: 110ps (maximum)
• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz):
2.42ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
For serdes which have x10 reference multipliers instead of x12.5
multipliers, each of the two PCI Express™ outputs (PCIEX0:1)
can be set for 125MHz instead of 100MHz by configuring the
appropriate frequency select pins (FS0:1).
• Industrial temperature information available upon request
PIN ASSIGNMENT
PLL_BW
CLK
nCLK
FS0
VDD
GND
PCIEXT0
PCIEXC0
VDD
nOE0
BLOCK DIAGRAM
IREF
Current
Set
+
1 HiZ
0 Enabled
nOE0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDDA
BYPASS
IREF
FS1
VDD
GND
PCIEXT1
PCIEXC1
VDD
nOE1
ICS9DB202
nCLK
CLK
Phase
Detector
0
Loop
Filter
0 ÷4
1 ÷5
VCO
1
20-Lead TSSOP
6.50mm x 4.40mm x 0.92
package body
PCIEXT0
G Package
nPCIEXC0
Top View
ICS9DB202
20-Lead, 209-MIL SSOP
5.30mm x 7.20mm x 1.75mm
body package
F Package
Top View
FS0
÷5
Internal Feedback
0
0 ÷5
1 ÷4
PCIEXT1
nPCIEXC1
1
FS1
BYPASS
nOE1
9DB202CG
1 HiZ
0 Enabled
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1
REV. A OCTOBER 6, 2004
ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS™
JITTER ATTENUATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
PLL_BW
Input
Type
2
CLK
Input
3
nCLK
Input
4
FS0
Input
Description
Pullup
Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup/
Inver ting differential clock input. VDD/2 default when left floating.
Pulldown
Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
5, 9, 12, 16
VDD
Power
Core supply pins.
6, 15
GND
PCIEXT0,
PCIEXC0
Power
Power supply ground.
Output
Differential output pairs. HCSL interface levels.
7, 8
10, 11
nOE0, nOE1
Input
17
PCIEXC1,
PCIEXT1
FS1
18
IREF
Input
19
BYPASS
Power
20
VDDA
Power
13, 14
Pulldown
Output
Input
Output enable. When HIGH, forces outputs to HiZ state.
When LOW, enables outputs. LVCMOS/LVTTL interface levels.
Differential output pairs. HCSL interface levels.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
A fixed precision resistor (475Ω) from this pin to ground provides a
reference current used for differential current-mode PCIEX clock outputs.
BYPASS pin. When HIGH. bypass mode, when LOW, PLL mode.
Pulldown
LVCMOS/LVTTL interface levels.
Analog supply pin. Requires 24Ω series resistor.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
Test Conditions
Minimum
Typical
Maximum
Units
4
pF
RPULLUP
Input Pullup Resistor
51
KΩ
RPULLDOWN
Input Pulldown Resistor
51
KΩ
TABLE 3A. RATIO OF OUTPUT FREQUENCY
INPUT FREQUENCY FUNCTION TABLE, FS0
TO
TABLE 3B. RATIO OF OUTPUT FREQUENCY
INPUT FREQUENCY FUNCTION TABLE, FS1
Inputs
Outputs
Inputs
Outputs
FS0
PCIEX0
FS1
PCIEX1
0
5/4
0
1
1
1
1
5/4
TABLE 3D. OUTPUT ENABLE
FUNCTION TABLE, NOE0
TABLE 3E. OUTPUT ENABLE
FUNCTION TABLE, NOE1
TO
TABLE 3C. BYPASS TABLE
Inputs
BYPASS
0
1
Mode
PLL Mode
Bypass Mode
(output = inputs)
TABLE 3F. PLL BANDWIDTH TABLE
Inputs
Outputs
Inputs
Outputs
Inputs
nOE0
PCIEX0
nOE1
PCIEX1
PLL_BW
0
Enabled
0
Enabled
0
500kHz
1
HiZ
1
HiZ
1
1MHz
9DB202CG
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2
Bandwidth
REV. A OCTOBER 6, 2004
ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS™
JITTER ATTENUATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
20 Lead TSSOP
20 Lead SSOP
73.2°C/W (0 lfpm)
80.8°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω
Symbol
Parameter
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
Test Conditions
3.135
3.3
3.465
V
3.135
3.3
VDDA
Analog Supply Voltage
3.465
V
IDD
Power Supply Current
112
mA
IDDA
Analog Supply Current
22
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
IIL
Input High Current
Input Low Current
Test Conditions
BYPASS,
nOE0, nOE1, FS1
FS0, PLL_BW
BYPASS,
nOE0, nOE1, FS1
FS0, PLL_BW
Minimum
Maximum
Units
2
Typical
VDD + 0.3
mV
-0.3
0.8
mV
150
µA
VDD = VIN = 3.465V
5
VDD = 3.465V, VIN = 0V
-5
µA
-150
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω
Symbol
Parameter
IIH
Input High Current
CLK, nCLK
VDD = VIN = 3.465V
Test Conditions
IIL
Input Low Current
CLK, nCLK
VDD = 3.465V, VIN = 0V
V PP
Peak-to-Peak Input Voltage
Minimum
Typical
0.15
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
VCMR
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
9DB202CG
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3
Maximum
Units
150
µA
150
µA
1.3
V
VDD - 0.85
V
REV. A OCTOBER 6, 2004
ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS™
JITTER ATTENUATOR
TABLE 4D. HCSL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω
Symbol
Parameter
IOH
Output Current
Test Conditions
Minimum
Typical
Maximum
Units
12
14
16
mA
65
V
VOH
Output High Voltage
VOL
Output Low Voltage
IOZ
High Impedance Leakage Current
-10
10
µA
VOX
Output Crossover Voltage
250
550
mV
Maximum
Units
140
MHz
680
V
TABLE 5. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = 0°C TO 70°C, RREF = 475Ω
Symbol
Parameter
fMAX
Output Frequency
tsk(o)
Output Skew; NOTE 1, 2
tjit(cc)
tjit(Ø)
tR / tF
Cycle-to-Cycle Jitter
RMS Phase Jitter
(Random); NOTE 3
Output Rise/Fall Time
Test Conditions
Minimum
Typical
110
ps
Outputs @ Different Frequencies
50
110
ps
Outputs @ Same Frequencies
50
ps
Integration Range: 1.5MHz - 22MHz
20% to 80%
2.42
300
o dc
Output Duty Cycle
48
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot following this section.
9DB202CG
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4
ps
1100
ps
52
%
REV. A OCTOBER 6, 2004
ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS™
JITTER ATTENUATOR
TYPICAL PHASE NOISE AT 100MHZ
➤
0
-10
PCI Express™ Filter
-20
-40
100MHz
-50
-60
RMS Phase Jitter (Random)
1.5MHz to 22MHz = 2.42ps (typical)
-70
-80
-90
-100
Raw Phase Noise Data
-110
-120
➤
NOISE POWER dBc
Hz
-30
-130
-140
➤
-150
-160
Phase Noise Result by adding
PCI Express™ Filter to raw data
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
The illustrated phase noise plot was taken using a low phase
noise signal generator, the noise floor of the signal generator is
less than that of the device under test.
Using this configuration allows one to see the true spectral purity
or phase noise performance of the PLL in the device under test.
9DB202CG
Due to the tracking ability of a PLL, it will track the input signal
up to its loop bandwidth. Therefore, if the input phase noise is
greater than that of the PLL, it will increase the output phase
noise performance of the device. It is recommended that the
phase noise performance of the input is verified in order to
achieve the above phase noise performance.
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5
REV. A OCTOBER 6, 2004
ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS™
JITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
3.3V±5%
VDD
nCLK
SCOPE
VDD,
VDDA
V
Qx
HCSL
V
Cross Points
PP
CMR
CLK
GND
GND
0V
3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PCIEXC0,
PCIEXC1
PCIEXCx
PCIEXTy
PCIEXT0,
PCIEXT1
tcycle
➤
➤
PCIEXCx
➤
n
tcycle n+1
➤
t jit(cc) = tcycle n –tcycle n+1
PCIEXTy
1000 Cycles
t sk(o)
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
PCIEXC0,
PCIEXC1
80%
80%
PCIEXT0,
PCIEXT1
VSW I N G
Clock
Outputs
20%
20%
tR
Pulse Width
t
PERIOD
tF
odc =
t PW
t PERIOD
HCSL OUTPUT RISE/FALL TIME
9DB202CG
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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6
REV. A OCTOBER 6, 2004
ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS™
JITTER ATTENUATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS9DB202 provides separate
power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 1 illustrates how a 24Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VDDA pin.
3.3V
VDD
.01µF
24Ω
V DDA
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
9DB202CG
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7
REV. A OCTOBER 6, 2004
ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS™
JITTER ATTENUATOR
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3D show interface examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
3.3V LVPECL DRIVER
BY
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
BY
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
Receiv er
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
3.3V LVPECL DRIVER
9DB202CG
nCLK
Zo = 50 Ohm
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN
3.3V LVDS DRIVER
BY
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8
BY
REV. A OCTOBER 6, 2004
ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS™
JITTER ATTENUATOR
RELIABILITY INFORMATION
TABLE 6A.
θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP PACKAGE
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98°C/W
66.6°C/W
88°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 6B.
θJAVS. AIR FLOW TABLE FOR 20 LEAD SSOP PACKAGE
θJA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
80.8°C/W
200
73.2°C/W
500
69.2°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS9DB202 is: 2471
9DB202CG
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9
REV. A OCTOBER 6, 2004
ICS9DB202
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
PCI EXPRESS™
JITTER ATTENUATOR
FOR
20 LEAD TSSOP
PACKAGE OUTLINE - F SUFFIX
TABLE 6B. PACKAGE DIMENSIONS
TABLE 6A. PACKAGE DIMENSIONS
SYMBOL
Millimeters
Millimeters
Minimum
N
SYMBOL
Maximum
Minimum
20
N
Maximum
20
A
--
1.20
A
--
2.0
A1
0.05
0.15
A1
0.05
--
A2
0.80
1.05
A2
1.65
1.85
b
0.19
0.30
b
0.22
0.38
c
0.09
0.20
D
6.40
6.60
c
0.09
0.25
D
6.90
7.50
E
7.40
8.20
E1
5.0
5.60
E
E1
6.40 BASIC
4.30
e
L
4.50
0.65 BASIC
0.45
0.75
e
0.55
0.95
0°
8°
α
0°
8°
L
aaa
--
0.10
α
Reference Document: JEDEC Publication 95, MO-153
9DB202CG
20 LEAD SSOP
FOR
0.65 BASIC
Reference Document: JEDEC Publication 95, MO-150
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10
REV. A OCTOBER 6, 2004
ICS9DB202
Integrated
Circuit
Systems, Inc.
PCI EXPRESS™
JITTER ATTENUATOR
TABLE 7. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS9DB202CG
ICS9DB202CG
20 Lead TSSOP
72 per Tube
0°C to 70°C
ICS9DB202CGT
ICS9DB202CG
20 Lead TSSOP on Tape and Reel
2500
0°C to 70°C
ICS9DB202CGLF
ICS9DB202CGL
72 per Tube
0°C to 70°C
ICS9DB202CGLFT
ICS9DB202CGL
2500
0°C to 70°C
ICS9DB202CF
ICS9DB202CF
20 Lead "Lead-Free" TSSOP
20 Lead "Lead-Free" TSSOP on
Tape and Reel
20 Lead SSOP
64 per Tube
0°C to 70°C
ICS9DB202CFT
ICS9DB202CF
20 Lead SSOP on Tape and Reel
1000
0°C to 70°C
ICS9DB202CFLF
ICS9DB202CFLF
64 per Tube
0°C to 70°C
ICS9DB202CFLFT
ICS9DB202CFLF
20 Lead "Lead-Free" SSOP
20 Lead "Lead-Free" SSOP on
Tape and Reel
1000
0°C to 70°C
The aforementioned trademarks, HiPerClockS™ and PCI Express™ iare trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
9DB202CG
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11
REV. A OCTOBER 6, 2004
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