LINER LTC6800 Rail-to-rail, input and output, instrumentation amplifier Datasheet

LTC6800
Rail-to-Rail,
Input and Output,
Instrumentation Amplifier
Features
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Description
116dB CMRR Independent of Gain
Maximum Offset Voltage: 100µV
Maximum Offset Voltage Drift: 250nV/°C
–40°C to 125°C Operation
Rail-to-Rail Input Range
Rail-to-Rail Output Swing
Supply Operation: 2.7V to 5.5V
Available in MS8 and 3mm × 3mm × 0.8mm
DFN Packages
The LTC®6800 is a precision instrumentation amplifier.
The CMRR is typically 116dB with a single 5V supply and is
independent of gain. The input offset voltage is guaranteed
below 100µV with a temperature drift of less than 250nV/°C.
The LTC6800 is easy to use; the gain is adjustable with
two external resistors, like a traditional op amp.
The LTC6800 uses charge balanced sampled data techniques to convert a differential input voltage into a single
ended signal that is in turn amplified by a zero-drift
operational amplifier.
Applications
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The differential inputs operate from rail-to-rail and the
single ended output swings from rail-to-rail. The LTC6800
is available in an MS8 surface mount package. For space
limited applications, the LTC6800 is available in a 3mm ×
3mm × 0.8mm dual fine pitch leadless package (DFN).
Thermocouple Amplifiers
Electronic Scales
Medical Instrumentation
Strain Gauge Amplifiers
High Resolution Data Acquisition
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical Application
Typical Input Referred Offset vs Input
Common Mode Voltage (VS = 3V)
High Side Power Supply Current Sense
15
1.5mΩ
VS = 3V
VREF = 0V
TA = 25°C
10
2
3
–
8
7
LTC6800
+
4
5
6
10k
0.1µF
5
OUT
100mV/A
OF LOAD
CURRENT
ILOAD
VOS (µV)
VREGULATOR
LOAD
0
G = 1000
G = 100
–5
G = 10
–10
150Ω
G=1
6800 TA01
–15
0
1
1.5
2
2.5
0.5
INPUT COMMON MODE VOLTAGE (V)
3
6800 TA02
6800fb
LTC6800
Absolute Maximum Ratings
(Note 1)
Total Supply Voltage (V+ to V –)................................5.5V
Input Current......................................................... ±10mA
| V+IN – VREF |.............................................................5.5V
| V–IN – VREF |............................................................5.5V
Output Short-Circuit Duration........................... Indefinite
Operating Temperature Range
(Note 7).................................................. –40°C to 125°C
Storage Temperature Range
DD Package........................................ –65°C to 125°C
MS8 Package...................................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
Pin Configuration
TOP VIEW
NC
1
8 V+
–IN
2
7 OUT
+IN
3
V–
4
9
TOP VIEW
NC 1
–IN 2
+IN 3
4
V–
6 RG
5 REF
8
7
6
5
V+
OUT
RG
REF
MS8 PACKAGE
8-LEAD PLASTIC MSOP
DD PACKAGE
8-LEAD (3mm s 3mm) PLASTIC DFN
TJMAX = 150°C, θJA = 200°C/W
TJMAX = 125°C, θJA = 160°C/W
UNDERSIDE METAL INTERNALLY CONNECTED TO V–
(PCB CONNECTION OPTIONAL)
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC6800HDD#PBF
LTC6800HDD#TRPBF
LAEP
8-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LTC6800HMS8#PBF
LTC6800HMS8#TRPBF
LTADE
8-Lead Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
6800fb
LTC6800
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 3V, V– = 0V, REF = 200mV. Output voltage swing is referenced
to V–. All other specifications reference the OUT pin to the REF pin.
PARAMETER
CONDITIONS
Input Offset Voltage (Note 2)
VCM = 200mV
Average Input Offset Drift (Note 2)
TA = –40°C to 85°C
TA = 85°C to 125°C
l
l
Common Mode Rejection Ratio
(Notes 4, 5)
A V = 1, VCM = 0V to 3V
l
Integrated Input Bias Current (Note 3)
VCM = 1.2V
4
10
nA
Integrated Input Offset Current (Note 3)
VCM = 1.2V
1
3
nA
Input Noise Voltage
DC to 10Hz
2.5
µVP-P
Power Supply Rejection Ratio (Note 6)
VS = 2.7V to 5.5V
l
110
116
dB
Output Voltage Swing High
RL = 2k to V –
RL = 10k to V –
l
l
2.85
2.95
2.94
2.98
V
V
Output Voltage Swing Low
MIN
TYP
–1
85
AV = 1
Gain Nonlinearity
AV = 1
Supply Current
No Load
l
UNITS
±100
µV
±250
–2.5
nV/°C
µV/°C
113
l
Gain Error
MAX
dB
20
mV
0.1
%
100
ppm
1.2
mA
Internal Op Amp Gain Bandwidth
200
kHz
Slew Rate
0.2
V/µs
3
kHz
Internal Sampling Frequency
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
V+ = 5V, V– = 0V, REF = 200mV. Output voltage swing is referenced to V–. All other specifications reference the OUT pin to the REF pin.
PARAMETER
CONDITIONS
Input Offset Voltage (Note 2)
VCM = 200mV
Average Input Offset Drift (Note 2)
TA = –40°C to 85°C
TA = 85°C to 125°C
l
l
Common Mode Rejection Ratio
(Notes 4, 5)
A V = 1, VCM = 0V to 5V
l
Integrated Input Bias Current (Note 3)
VCM = 1.2V
Integrated Input Offset Current (Note 3)
VCM = 1.2V
Power Supply Rejection Ratio (Note 6)
VS = 2.7V to 5.5V
Output Voltage Swing High
= 2k to V –
RL
RL = 10k to V –
Output Voltage Swing Low
MIN
TYP
–1
85
MAX
UNITS
±100
µV
±250
–2.5
nV/°C
µV/°C
116
dB
4
10
nA
1
3
nA
l
110
116
dB
l
l
4.85
4.95
4.94
4.98
V
V
20
l
mV
Gain Error
AV = 1
0.1
%
Gain Nonlinearity
AV = 1
100
ppm
Supply Current
No Load
1.3
mA
l
Internal Op Amp Gain Bandwidth
200
kHz
Slew Rate
0.2
V/µs
3
kHz
Internal Sampling Frequency
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: These parameters are guaranteed by design. Thermocouple effects
preclude measurement of these voltage levels in high speed automatic
test systems. VOS is measured to a limit determined by test equipment
capability.
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LTC6800
Electrical Characteristics
Note 3: If the total source resistance is less than 10k, no DC errors result
from the input bias currents or the mismatch of the input bias currents or
the mismatch of the resistances connected to –IN and +IN.
Note 4: The CMRR with a voltage gain, A V, larger than 10 is 120dB (typ).
Note 5: At temperatures above 70°C, the common mode rejection ratio
lowers when the common mode input voltage is within 100mV of the
supply rails.
Note 6: The power supply rejection ratio (PSRR) measurement accuracy
depends on the proximity of the power supply bypass capacitor to the
device under test. Because of this, the PSRR is 100% tested to relaxed
limits at final test. However, their values are guaranteed by design to meet
the data sheet limits.
Note 7: The LTC6800H is guaranteed functional over the operating
temperature range of –40°C to 125°C. Specifications over the –40°C to
125°C range (denoted by l) are assured by design and characterization
but are not tested or QA sampled at these temperatures.
Typical Performance Characteristics
Input Offset Voltage vs Input
Common Mode Voltage
5
0
G = 1000
G = 100
–5
G = 10
–10
0
G=1
G = 10
–10
0
1.0
1.5
2.0
2.5
0.5
INPUT COMMON MODE VOLTAGE (V)
–15
3.0
60
INPUT OFFSET VOLTAGE (µV)
10
5
0
TA = 70°C
–5
TA = 25°C
–10
–15
TA = –55°C
0
2
3
4
1
INPUT COMMON MODE VOLTAGE (V)
0
6800 G01
VS = 5V
15 VREF = 0V
G = 10
5
6800 G04
2
3
4
1
INPUT COMMON MODE VOLTAGE (V)
10
5
0
TA = 70°C
–5
TA = 25°C
–10
–20
5
TA = –55°C
60
VS = 3V
VREF = 0V
G = 10
20
0
TA = 85°C
–20
–40
TA = 125°C
0
1.0
1.5
2.0
2.5
0.5
INPUT COMMON MODE VOLTAGE (V)
0
2053 G02
Input Offset Voltage vs Input
Common Mode Voltage,
85°C ≤ TA ≤ 125°C
40
–60
VS = 3V
15 VREF = 0V
G = 10
–15
G=1
20
INPUT OFFSET VOLTAGE (µV)
G = 100
–5
Input Offset Voltage vs Input
Common Mode Voltage
–20
G = 1000
5
INPUT OFFSET VOLTAGE (µV)
–15
20
VS = 5V
VREF = 0V
10 TA = 25°C
INPUT OFFSET VOLTAGE (µV)
10
Input Offset Voltage vs Input
Common Mode Voltage
15
VS = 3V
VREF = 0V
TA = 25°C
INPUT OFFSET VOLTAGE (µV)
INPUT OFFSET VOLTAGE (µV)
15
Input Offset Voltage vs Input
Common Mode Voltage
3.0
6800 G05
1.0
1.5
2.0
2.5
0.5
INPUT COMMON MODE VOLTAGE (V)
3.0
6800 G03
Input Offset Voltage vs Input
Common Mode Voltage,
85°C ≤ TA ≤ 125°C
VS = 5V
VREF = 0V
G = 10
40
20
0
TA = 85°C
–20
–40
–60
TA = 125°C
0
2
3
4
1
INPUT COMMON MODE VOLTAGE (V)
5
6800 G06
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LTC6800
Typical Performance Characteristics
RS = 10k
–20
RS = 15k
RS
+
SMALL CIN
–40
–
RS = 20k
RS
0
1.0
1.5
2.0
2.5
0.5
INPUT COMMON MODE VOLTAGE (V)
3.0
ADDITIONAL OFFSET ERROR (µV)
0
–10
100
50
R+
–100
R+ = 500Ω, R– = 0Ω
+
BIG CIN
–150
–200
R+ = 0Ω, R– = 500Ω
R+ = 100Ω, R– = 0Ω
–50
R–
0
R+ = 1k, R– = 0Ω
–
1.0
1.5
2.0
2.5
0.5
INPUT COMMON MODE VOLTAGE (V)
2
3
4
1
INPUT COMMON MODE VOLTAGE (V)
5
3.0
6800 G13
–20
–30
RS = 10k
RS = 5k
+
–
1.0
1.5
2.0
2.5
0.5
INPUT COMMON MODE VOLTAGE (V)
VS = 5V
VREF = 0V
TA = 25°C
G = 10
100
+
R+ = 1k, R– = 0Ω
RS = 10k
RS = 5k
30
RS = 1k
10
RS = 500Ω
–10
RS
–30
+
BIG CIN
–50
VS = 5V
VREF = 0V
R+ = R– = RS
CIN > 1µF
G = 10
TA = 25°C
–
RS
0
2
3
4
1
INPUT COMMON MODE VOLTAGE (V)
5
6800 G12
40
20
0
VS = 3V
–20
VS = 5V
–40
–60
–
1
6800 G09
60
R+ = 500Ω, R– = 0Ω
BIG CIN
0
3.0
Offset Voltage vs Temperature
R+ = 0Ω, R– = 500Ω
R+ = 0Ω, R– = 100Ω
–50
R–
R+ = 15k, R– = 0k
1.0
1.5
2.0
2.5
0.5
INPUT COMMON MODE VOLTAGE (V)
80
R+ = 100Ω, R– = 0Ω
–150
0
6800 G11
0
R+
–
R–
50
–70
3.0
R+ = 0Ω, R– = 1k
50
–100
+
SMALL CIN
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN > 1µF)
RS
0
R+ = 5k, R– = 0k
R+ = 10k, R– = 0k
+
R
–10
6800 G08
RS = 15k
BIG CIN
150
–200
0
70
RS
–30
R+ = 0k, R– = 15k
R+ = 0k, R– = 10k
R+ = 0k, R– = 5k
10
–50
Additional Input Offset Due to
Input RS Mismatch vs Input
Common Mode (CIN > 1µF)
R+ = 0Ω, R– = 1k
20
–40
–10
–20
VS = 3V
VREF = 0V
CIN < 100pF
G = 10
TA = 25°C
30
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN > 1µF)
6800 G10
R+ = 0Ω, R– = 100Ω
0
0
200
VS = 3V
VREF = 0V
TA = 25°C
G = 10
–
RS
0
–40
5
+
VS = 3V
V
= 0V
30 REF
R+ = R– = RS
C > 1µF
20 GIN= 10
TA = 25°C
10
Additional Input Offset Due to
Input RS Mismatch vs Input
Common Mode (CIN > 1µF)
150
RS
–20 SMALL CIN
40
VS = 5V
RIN+ = 0k, RIN– = 20k
30 VREF = 0V
CIN < 100pF
RIN+ = 0k, RIN– = 15k
20 G = 10
RIN+ = 0k, RIN– = 10k
TA = 25°C
RIN+ = 10k, RIN– = 0k
10
200
RS = 5k
6800 G07
Additional Input Offset Due to
Input RS Mismatch vs Input
Common Mode (CIN < 100pF)
RIN+ = 15k, RIN– = 0k
RIN+ = 20k, RIN– = 0k
R+
–20
+
SMALL CIN
–30
–
R–
–40
0
2
3
4
1
INPUT COMMON MODE VOLTAGE (V)
RS = 10k
–10
Additional Input Offset Due to
Input RS Mismatch vs Input
Common Mode (CIN < 100pF)
40
RS = 15k
0
–30
50
RS = 20k
ADDITIONAL OFFSET ERROR (µV)
RS = 0k
0
40
ADDITIONAL OFFSET ERROR (µV)
RS = 5k
VS = 5V
VREF = 0V
+
–
20 RIN = RIN = RS
CIN < 100pF
G = 10
10 TA = 25°C
INPUT OFFSET VOLTAGE (µV)
20
30
ADDITIONAL OFFSET ERROR (µV)
40
–60
ADDITIONAL OFFSET ERROR (µV)
VS = 3V
VREF = 0V
R+ = R– = RS
CIN < 100pF
G = 10
TA = 25°C
ADDITIONAL OFFSET ERROR (µV)
ADDITIONAL OFFSET ERROR (µV)
60
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN < 100pF)
ADDITIONAL OFFSET ERROR (µV)
Additional Input Offset Due to
Input RS vs Input Common Mode
(CIN < 100pF)
2
4
3
INPUT COMMON MODE VOLTAGE (V)
5
6800 G14
–80
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
6800 G15
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LTC6800
Typical Performance Characteristics
VOS vs VREF
VIN+ = VIN– = REF
G = 10
TA = 25°C
6
0
VS = 5V
VS = 3V
–10
2
0
–2
–4
2
VREF (V)
3
–10
–2.4 –1.9 –1.4 –0.9 –0.4 0.1 0.6
OUTPUT VOLTAGE (V)
4
6800 G16
INPUT REFERRED NOISE DENSITY (nV/•Hz)
130
R+ = R– = 1k
CMRR (db)
110
R+ = R– = 10k
100
R+ = 10k, R– = 0Ω
R+ = 0Ω, R– = 10k
90
R+
80
70
R–
+
–
1
10
100
FREQUENCY (Hz)
1000
300
250
VS = 3V
100
50
0
1
10
4.5
0
–1
–2
TA = 25°C
–1
1
TIME (s)
2
3.5
3.0
3
5
0
–1
–2
6800 G22
–3
–1
1
TIME (s)
3
5
6800 G21
Supply Current vs Supply Voltage
VS = 5V, SOURCING
0.95
VS = 3V, SOURCING
1.5
VS = 3V, SINKING
VS = 5V, SINKING
1
0.1
OUTPUT CURRENT (mA)
–5
1.00
2.0
0
0.01
2.6
6800 G18
VS = 3V
TA = 25°C
6800 G20
2.5
1.0
0.6
–0.4
1.6
OUTPUT VOLTAGE (V)
1
–3
10000
4.0
0.5
–3
100
1000
FREQUENCY (Hz)
–1.4
Input Referred Noise
in 10Hz Bandwidth
VS = 5V
150
5.0
VS = 5V
TA = 25°C
–5
1.6
6800 G17
Output Voltage Swing
vs Output Current
1
–3
–4
3
6800 G19
OUTPUT VOLTAGE SWING (V)
INPUT REFFERED NOISE VOLTAGE (µV)
2
1.1
G = 10
TA = 25°C
200
Input Referred Noise
in 10Hz Bandwidth
3
–2
Input Voltage Noise Density
vs Frequency
CMRR vs Frequency
VS = 3V, 5V
VIN = 1VP-P
120 TA = 25°C
0
–10
–2.4
INPUT REFFERED NOISE VOLTAGE (µV)
1
2
–8
–8
0
VS = ±2.5V
8 VREF = 0V
G = 10
6
RL = 10k
4 TA = 25°C
–6
–6
–20
–30
4
SUPPLY CURRENT (mA)
VOS (µV)
10
10
VS = ±2.5V
VREF = 0V
G=1
RL = 10k
TA = 25°C
8
NONLINEARITY (ppm)
20
Gain Nonlinearity, G = 10
Gain Nonlinearity, G = 1
10
NONLINEARITY (ppm)
30
0.90
0.85
TA = 85°C
TA = 125°C
0.80
0.75
0.70
TA = –55°C
TA = 0°C
0.65
10
6800 G23
0.60
2.5
3.5
4.5
SUPPLY VOLTAGE (V)
5.5
6
6800 G24
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LTC6800
Typical Performance Characteristics
Low Gain Settling Time
vs Settling Accuracy
6
SETTLING TIME (ms)
SETTLING TIME (ms)
7
5
4
3
2
3.40
VS = 5V
dVOUT = 1V
30 0.1% ACCURACY
TA = 25°C
25
3.35
20
15
10
0.01
0.001
SETTLING ACCURACY (%)
0.1
0
3.30
1
10
6800 G25
100
GAIN (V/V)
1000
10000
TA = 125°C
3.25
TA = 85°C
3.20
3.15
5
1
0
0.0001
35
VS = 5V
dVOUT = 1V
G < 100
TA = 25°C
CLOCK FREQUENCY (kHz)
8
Internal Clock Frequency
vs Supply Voltage
Settling Time vs Gain
TA = 25°C
3.10
2.5
6800 G26
TA = –55°C
3.5
4.5
SUPPLY VOLTAGE (V)
5.5
6
6800 G27
Pin Functions
NC (Pin 1): Not Connected.
–IN (Pin 2): Inverting Input.
+IN (Pin 3): Noninverting Input.
V– (Pin 4): Negative Supply.
RG (Pin 6): Inverting Input of Internal Op Amp. See
Figure 1.
OUT (Pin 7): Amplifier Output. See Figure 1.
V+ (Pin 8): Positive Supply.
REF (Pin 5): Voltage Reference (VREF) for Amplifier
Output.
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LTC6800
Block Diagram
8
+IN
+
3
–IN
V+
CS
OUT
CH
7
–
2
REF
5
V–
RG
6
4
6800 BD
Applications Information
Theory of Operation
The LTC6800 uses an internal capacitor (CS) to sample
a differential input signal riding on a DC common mode
voltage (see the Block Diagram). This capacitor’s charge is
transferred to a second internal hold capacitor (CH) translating the common mode of the input differential signal to
that of the REF pin. The resulting signal is amplified by a
zero-drift op amp in the noninverting configuration. The
RG pin is the negative input of this op amp and allows
external programmability of the DC gain. Simple filtering
can be realized by using an external capacitor across the
feedback resistor.
Input Voltage Range
The input common mode voltage range of the LTC6800
is rail-to-rail. However, the following equation limits the
size of the differential input voltage:
V– ≤ (V+IN – V–IN) + VREF ≤ V+ – 1.3
Where V+IN and V–IN are the voltages of the +IN and –IN
pins, respectively, VREF is the voltage at the REF pin and
V+ is the positive supply voltage.
For example, with a 3V single supply and a 0V to 100mV
differential input voltage, VREF must be between 0V and
1.6V.
Settling Time
The sampling rate is 3kHz and the input sampling period
during which CS is charged to the input differential voltage
VIN is approximately 150µs. First assume that on each
input sampling period, CS is charged fully to VIN. Since
CS = CH (= 1000pF), a change in the input will settle to
N bits of accuracy at the op amp noninverting input after
N clock cycles or 333µs(N). The settling time at the OUT
pin is also affected by the settling of the internal op amp.
Since the gain bandwidth of the internal op amp is typically
200kHz, the settling time is dominated by the switched
capacitor front end for gains below 100 (see the Typical
Performance Characteristics section).
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LTC6800
Applications Information
UNITY GAIN
UNITY GAIN
5V
V+IN
+
VIN
V–IN
–
3
2
5V
8
+
7
–
NONUNITY GAIN
5
6
V+IN
VOUT
+
VIN
V–IN
–
3
2
5V
8
+
7
–
4
5
6
V+IN
VOUT
+
VIN
V–IN
–
3
2
5V
8
+
7
–
4
5
6 R2
4
VREF
0V < V+IN < 5V
0V < V–IN < 5V
0V < VIN < 3.7V
VOUT = VIN
NONUNITY GAIN
V+IN
VOUT
+
VIN
V–IN
–
3
2
8
+
–
VOUT = VIN + VREF
VOUT = 1 +
R2
R1
VIN + VREF
VOUT
R1
VREF
VREF
0V < V–IN < 5V AND |V–IN – VREF| < 5.5V
0V < V+IN < 5V AND |V+IN – VREF| < 5.5V
0V < VIN + VREF < 3.7V
5
4
R1
0V < V–IN < 5V AND |V–IN – VREF| < 5.5V
0V < V+IN < 5V AND |V+IN – VREF| < 5.5V
0V < VIN + VREF < 3.7V
7
6 R2
0V < V–IN < 5V AND |V–IN – VREF| < 5.5V
0V < V+IN < 5V AND |V+IN – VREF| < 5.5V
0V < VIN + VREF < 3.7V
VOUT = 1 +
R2
R1
(VIN + VREF)
6800 F01
Figure 1
Input Current
Whenever the differential input VIN changes, CH must be
charged up to the new input voltage via CS. This results
in an input charging current during each input sampling
period. Eventually, CH and CS will reach VIN and, ideally,
the input current would go to zero for DC inputs.
In reality, there are additional parasitic capacitors which
disturb the charge on CS every cycle even if VIN is a DC
voltage. For example, the parasitic bottom plate capacitor
on CS must be charged from the voltage on the REF pin
to the voltage on the –IN pin every cycle. The resulting
input charging current decays exponentially during each
input sampling period with a time constant equal to RSCS.
If the voltage disturbance due to these currents settles
before the end of the sampling period, there will be no
errors due to source resistance or the source resistance
mismatch between –IN and +IN. With RS less than 10k,
no DC errors occur due to this input current.
In the Typical Performance Characteristics section of this
data sheet, there are curves showing the additional error
from nonzero source resistance in the inputs. If there are
no large capacitors across the inputs, the amplifier is
less sensitive to source resistance and source resistance
mismatch. When large capacitors are placed across the
inputs, the input charging currents previously described
result in larger DC errors, especially with source resistor
mismatches.
Power Supply Bypassing
The LTC6800 uses a sampled data technique and, therefore,
contains some clocked digital circuitry. It is, therefore,
sensitive to supply bypassing. A 0.1µF ceramic capacitor
must be connected between Pin 8 (V+) and Pin 4 (V–) with
leads as short as possible.
6800fb
LTC6800
Typical Applications
Precision ÷2
5V
0.1µF
3
VIN
+
8
7
LTC6800
2
–
5
4
VOUT
6
V
VOUT = IN
2
1k
0.1µF
6800 TA03
Precision Doubler (General Purpose)
2.5V
3
VIN
+
0.1µF
8
7
LTC6800
2
–
5
4
6
VOUT
VOUT = 2VIN
0.1µF
0.1µF
–2.5V
6800 TA04
Precision Inversion (General Purpose)
2.5V
3
+
0.1µF
8
7
LTC6800
VIN
2
–
4
5
6
VOUT
VOUT = –VIN
0.1µF
–2.5V
6800 TA05
6800fb
10
LTC6800
Package Description
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698 Rev C)
0.70 p0.05
3.5 p0.05
1.65 p0.05
2.10 p0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 p 0.05
0.50
BSC
2.38 p0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
PIN 1
TOP MARK
(NOTE 6)
0.200 REF
3.00 p0.10
(4 SIDES)
R = 0.125
TYP
5
0.40 p 0.10
8
1.65 p 0.10
(2 SIDES)
0.75 p0.05
4
0.25 p 0.05
1
(DD8) DFN 0509 REV C
0.50 BSC
2.38 p0.10
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
6800fb
11
LTC6800
Package Description
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660 Rev F)
3.00 p 0.102
(.118 p .004)
(NOTE 3)
0.889 p 0.127
(.035 p .005)
5.23
(.206)
MIN
0.254
(.010)
7 6 5
0.52
(.0205)
REF
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
DETAIL “A”
0o – 6o TYP
GAUGE PLANE
3.20 – 3.45
(.126 – .136)
0.53 p 0.152
(.021 p .006)
DETAIL “A”
0.42 p 0.038
(.0165 p .0015)
TYP
8
0.65
(.0256)
BSC
1
1.10
(.043)
MAX
2 3
4
0.86
(.034)
REF
0.18
(.007)
RECOMMENDED SOLDER PAD LAYOUT
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.1016 p 0.0508
(.004 p .002)
MSOP (MS8) 0307 REV F
6800fb
12
LTC6800
Revision History
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
7/10
Corrected text in the Absolute Maximum Ratings section
2
Updated Pin 6 and Pin 7 text in the Pin Functions section
7
Replaced Figure 1
9
6800fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
13
LTC6800
Typical Application
Differential Bridge Amplifier
3V
0.1µF
R < 10k
2
3
8
–
7
LTC6800
+
4
5
6
OUT
R2 10k
0.1µF
R1
10Ω
GAIN = 1 + R2
R1
6800 TA06
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6800fb
14 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LT 0710 REV B • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2002
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